JP5433500B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device.

The solid-state imaging device includes a light receiving unit in which M × N pixel units P _{1,1 to} P _{M, N} each having a photodiode and a charge storage unit are two-dimensionally arranged in M rows and N columns, and each pixel of the light receiving unit Row selection for storing charges generated in the photodiode in a certain period for the portion P _{m, n} in the charge storage portion and outputting data corresponding to the stored charge amount of each pixel portion P _{m, n} for each row And a reading unit that inputs data output from each pixel unit P _{m, n of} the light receiving unit and outputs data corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m, n} , and In some cases, an AD conversion unit that AD converts the data output from the reading unit and outputs a digital value may be provided.

Such a solid-state imaging device can detect and image the intensity of light reaching each pixel unit P _{m, n} of the light receiving unit. In recent years, it has been attempted to perform not only imaging but also optical communication using such a solid-state imaging device. For example, the solid-state imaging device of the invention disclosed in Patent Document 1 has a plurality of means for reading data from each pixel unit, and imaging is performed by reading data for each pixel unit by the first reading unit. In addition, an optical signal can be received by adding and outputting current signals generated from photodiodes of one or more specific pixel portions by the second readout means.

Japanese Patent No. 3995959

  In the solid-state imaging device of the invention disclosed in Patent Document 1, since the data read by the first reading unit is image data, the data reading speed by the first reading unit is, for example, several tens of fps (frame per second). is there. On the other hand, since the data read by the second reading means is communication data, the data reading speed by the second reading means is, for example, several tens of kbps (kilo bit per second).

  The present inventor has found that the following problems occur in a solid-state imaging device that performs such imaging and optical communication. The solid-state imaging device of the invention disclosed in Patent Document 1 is intended to be used even when the optical signal source may move. In this case, the position of the optical signal source is specified based on the image data read by the first reading means, and the data from the pixel portion at the specified position in the image is used as communication data by the second reading means. Read out.

  When tracking the position of the optical signal source in this way, a certain pixel unit has read image data by the first reading means before a certain time t, but after that time t by the second reading means. Communication data is read out. Alternatively, a certain pixel unit has not read data by either the first reading unit or the second reading unit before a certain time t, but after that time t, the second reading unit receives communication data. Will be read. That is, in the pixel portion, the charge accumulation time before time t is longer than the charge accumulation time after time t. However, since the communication data read by the second reading means first immediately after time t corresponds to the amount of charge accumulated over a long period of time immediately before time t, it becomes an incorrect value. There is. With this, the solid-state imaging device cannot accurately receive the optical signal from the optical signal source.

  The present invention has been made in order to solve the above-described problems, and is capable of accurately receiving an optical signal from an optical signal source even when tracking the position of the optical signal source. An object of the present invention is to provide a solid-state imaging device.

The solid-state imaging device according to the present invention provides: (1) a photodiode that generates an amount of electric charge according to the amount of incident light, a charge accumulating unit that accumulates the electric charge, and data that corresponds to the amount of accumulated electric charge in the electric charge accumulating unit M × N pixel portions P _{1,1 to} P _{M, N} each having a first switch for switching and a second switch for outputting data corresponding to the amount of stored charge in the charge storage portion, A light receiving unit arranged two-dimensionally in M rows and N columns, and (2) any one of the m1 rows in the light receiving unit is selected, and a control signal is output to each pixel unit P _{m1, n of} the m1 row. As a result, the junction capacitance portion of the photodiode is discharged, the charge generated in the photodiode is accumulated in the charge accumulation portion, and the first switch is closed, so that the data corresponding to the accumulated charge amount in the charge accumulation portion is read signal line L1. the first row selection unit to output to _n , (3) By selecting one of the m2 rows different from the m1 row in the light receiving unit and outputting a control signal to each pixel unit P _{m2, n of} the m2 row, the junction capacitance portion of the photodiode is discharged. A second row selection unit that accumulates charges generated by the photodiode in the charge accumulation unit and outputs data corresponding to the accumulated charge amount in the charge accumulation unit to the read signal line L2 _n by closing the second switch; 4) The third row for discharging the junction capacitance portion of the photodiode by selecting any m3 row in the light receiving portion and outputting a control signal to each pixel portion P _{m3, n of the m3} row. The selection unit is connected to (5) N readout signal lines L1 _{1 to} L1 _N, and the readout signal line L1 from each pixel unit P _{m1, n} in the m1st row in the light receiving unit selected by the first row selection unit. _The data output to _n is input and the m1st A first readout section for outputting data corresponding to the amount of electric charge generated in the photodiodes of each pixel section P _{m1, n in} the row; and (6) N readout signal lines L2 _{1 to} L2 _N connected to the first readout section. Data output from the pixel unit P _{m2, n} in the m2th row to the readout signal line L2 _n in the light receiving unit selected by the 2-row selection unit is input, and each pixel unit P _{m2, n in} the m2th row is input. A second reading unit that outputs data according to the amount of charge generated in the photodiode, and (7) a first row selection unit, a first reading unit, a second row selection unit, and a second reading unit, It is characterized by operating in parallel with each other. However, M and N are integers of 2 or more, m1 and m2 are integers of 1 to M and different from each other, m3 is an integer of 1 to M, and n is an integer of 1 to N. is there.

In the solid-state imaging device of the present invention, any one of the m1 rows in the light receiving unit is selected by the first row selection unit, and the junction capacitance portion of the photodiode is discharged in each pixel unit P _{m1, n} of the m1 row. Then, the charge generated in the photodiode is stored in the charge storage unit, and the first switch is closed, so that data corresponding to the amount of charge stored in the charge storage unit is output to the read signal line L1 _n . In the first readout unit connected to each readout signal line L1 _n , the data output from each pixel unit P _{m1, n} in the m1st row in the light receiving unit selected by the first row selection unit to the readout signal line L1 _n Is input, and data corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m1, n in} the m1th row is output.

On the other hand, any m2th row in the light receiving unit is selected by the second row selection unit, and the junction capacitance portion of the photodiode is discharged in each pixel unit _{Pm2, n} of the m2th row, and is generated in the photodiode. The stored charge is stored in the charge storage section, and the second switch is closed to output data corresponding to the amount of stored charge in the charge storage section to the read signal line L2 _n . In the second reading unit which is connected to the read signal line L2 _n, the m2 row pixel portion P _m2, data outputted from the _n to the read signal line L2 _n of the light-receiving unit selected by the second row selecting section Is input, and data corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m2, n in} the m2nd row is output.

  Different rows are selected in the light receiving unit by the first row selection unit and the second row selection unit. The first row selection unit and the first readout unit, and the second row selection unit and the second readout unit operate in parallel with each other. Thereby, for example, image data is obtained by the first row selection unit and the first reading unit, and communication data is obtained by the second row selection unit and the second reading unit.

In addition, any m3th row in the light receiving unit is selected by the third row selection unit, and the junction capacitance portion of the photodiode is discharged in each pixel unit _{Pm3, n} of the m3th row.

In the solid-state imaging device of the present invention, (a) the first row selection unit includes M latch circuits, and each pixel in the m1 row when the data held in the m1st latch circuit is a significant value. A control signal is output to the unit P _{m1, n} , and (b) the second row selection unit includes M latch circuits, and the data held in the m-th latch circuit among them is a significant value. A control signal is output to each pixel unit P _{m2, n in} the m2nd row, (c) the third row selection unit includes M latch circuits, and the data held in the m3th latch circuit among them is It is preferable to output a control signal to each pixel unit P _{m3, n} in the m3rd row when it is a significant value.

  In the solid-state imaging device according to the present invention, M latch circuits of the first row selection unit, the second row selection unit, and the third row selection unit are cascaded in the row order to form a shift register. It is preferable that each latch circuit holds data by serially inputting M-bit data to the first-stage latch circuit in FIG.

  In the solid-state imaging device according to the present invention, (a) the first row selection unit has a fixed time interval with respect to a plurality of rows corresponding to the latch circuits whose retention data is significant among the M latch circuits included in the first row selection unit. (B) The second row selection unit outputs a predetermined time for a plurality of rows corresponding to the latch circuits whose retention data is significant among the M latch circuits included in the second row selection unit. It is preferable to output the control signals sequentially at intervals.

  The solid-state imaging device of the present invention can accurately receive the optical signal from the optical signal source even when tracking the position of the optical signal source.

It is a figure which shows schematic structure of the solid-state imaging device 1 of this embodiment. It is a figure which shows the structure of the 1st read-out part 40 and the 2nd read-out part 50 of the solid-state imaging device 1 of this embodiment. Pixel portions P _m of the solid-state imaging device 1 of the present _embodiment, a diagram showing a circuit configuration of the _n and the holding portion 41 _n. It is a figure which shows the circuit structure of the difference calculating part 43 of the solid-state imaging device 1 of this embodiment. It is a figure which shows the structure of the 1st line selection part 20, the 2nd line selection part 30, and the 3rd line selection part 70 of the solid-state imaging device 1 of this embodiment. It is a diagram illustrating a configuration of a control signal generating circuit 21 _m in the first row selecting section 20 of the solid-state imaging device 1 of the present embodiment. It is a diagram illustrating a configuration of a control signal generating circuit 31 _m in the second row selecting section 30 of the solid-state imaging device 1 of the present embodiment. It is a figure explaining the pixel part in the light-receiving part 10 from which data is read by each of the 1st read-out part 40 and the 2nd read-out part 50 in the case of operation of each of a comparative example and an example. It is a timing chart in the case of operation of a comparative example. It is a timing chart in the case of operation of an example. It is a figure explaining the pixel part in the light-receiving part 10 from which the data is read by each of the 1st read-out part 40 and the 2nd read-out part 50 in the case of operation | movement of another Example. It is a timing chart in the case of operation of other examples.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 is a diagram illustrating a schematic configuration of a solid-state imaging device 1 of the present embodiment. The solid-state imaging device 1 shown in this figure includes a light receiving unit 10, a first row selecting unit 20, a second row selecting unit 30, a third row selecting unit 70, a first reading unit 40, a second reading unit 50, and a control unit. 60.

The light receiving unit 10 includes M × N pixel units P _{1,1 to} P _{M, N.} The M × N pixel portions P _{1,1 to} P _{M, N} have a common configuration and are two-dimensionally arranged in M rows and N columns. Each pixel unit P _{m, n} is located in the m-th row and the n-th column. Here, M and N are integers of 2 or more, m is an integer of 1 to M, and n is an integer of 1 to N.

Each pixel unit P _{m, n} includes a photodiode that generates an amount of charge corresponding to the amount of incident light, and a charge storage unit that stores the charge. Each pixel unit P _{m, n} discharges the junction capacitance unit of the photodiode based on various control signals received from the first row selection unit 20 or the second row selection unit 30 via the control signal line, Charges generated by the diode can be stored in the charge storage portion, and data corresponding to the amount of charge stored in the charge storage portion can be output to the read signal line L1 _n or the read signal line L2 _n .

The first row selection unit 20 selects any one of the m1 rows in the light receiving unit 10 and outputs a control signal to each pixel unit P _{m1, n in} the m1 row, so that the junction capacitance of the photodiode is obtained. The charge is generated in the charge storage part, and data corresponding to the amount of charge stored in the charge storage part is output to the read signal line L1 _n .

The second row selection unit 30 selects any m2th row in the light receiving unit 10 and outputs a control signal to each pixel unit _{Pm2, n in} the m2th row, so that the junction capacitance of the photodiode is obtained. The charge is generated in the charge storage part, and data corresponding to the amount of charge stored in the charge storage part is output to the read signal line L2 _n .

The third row selection unit 70 selects any m3th row in the light receiving unit 10 and outputs a control signal to each pixel unit _{Pm3, n in} the m3th row, so that the junction capacitance of the photodiode is obtained. The portion is discharged, and the charge generated by the photodiode is accumulated in the charge accumulation portion.

  Here, m1 and m2 are integers which are 1 or more and M or less and different from each other. m3 is an integer of 1 or more and M or less. The first row selection unit 20 and the second row selection unit 30 select different rows in the light receiving unit 10. The number of rows selected by each of the first row selection unit 20 and the second row selection unit 30 is arbitrary, but data output is sequentially performed for each row. The number of rows selected by the third row selection unit 70 is also arbitrary.

The first readout unit 40 is connected to _N readout signal lines L1 _{1 to} L1 _N, and receives readout signals from each pixel unit P _{m1, n} in the m1st row in the light receiving unit 10 selected by the first row selection unit 20. Data output to the line L1 _n is input, and data corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m1, n in} the m1th row is output.

The second readout unit 50 is connected to _N readout signal lines L2 _{1 to} L2 _N, and the readout signal is output from each pixel unit P _{m2, n} in the m2nd row in the light receiving unit 10 selected by the second row selection unit 30. Data output to the line L2 _n is input, and data corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m2, n in} the m2nd row is output.

  The control unit 60 controls the operations of the first row selection unit 20, the second row selection unit 30, the third row selection unit 70, the first readout unit 40, and the second readout unit 50, so that the solid-state imaging device 1. Control overall operation. Controlled by the control unit 60, the first row selection unit 20 and the first reading unit 40, and the second row selection unit 30 and the second reading unit 50 can operate in parallel with each other.

FIG. 2 is a diagram illustrating a configuration of the first reading unit 40 and the second reading unit 50 of the solid-state imaging device 1 of the present embodiment. In this figure, in the light receiving unit 10, the pixel unit P _{m, n in the m-} th row and the n-th column among the M × N pixel units P _{1,1 to} P _{M, N} is representatively shown. In each of the first reading unit 40 and the second reading unit 50, components related to the pixel unit P _{m, n} are shown.

The first reading unit 40 includes N holding units 41 _{1 to} 41 _N , a first column selection unit 42, and a difference calculation unit 43. The N holding portions 41 _{1 to} 41 _N have a common configuration. Each holding unit 41 _n is connected to the M pixel units P _{1, n to} P _{M, n} in the n-th column in the light receiving unit 10 via the readout signal line L1 _n. Data output from the pixel portion P _{m1, n of the} selected m1th row to the readout signal line L1 _n can be input, the data can be held, and the held data can be output. Each holding unit 41 _n preferably inputs and holds data of a signal component on which a noise component is superimposed, and preferably inputs and holds data of only a noise component.

The N holding units 41 _{1 to} 41 _N sample and hold data at the same timing based on various control signals received from the first column selection unit 42, and sequentially output the held data. Can do. The difference calculation unit 43 receives the data sequentially output from each of the _N holding units 41 _{1 to} 41 _N, and subtracts only the noise component data from the signal component data on which the noise component is superimposed. Output data according to. The difference calculation unit 43 may output data corresponding to the signal component as analog data, or may have an AD conversion function and output digital data. In this way, the first readout unit 40 can output data corresponding to the amount of charge generated in the photodiodes of the pixel units P _{m1, n in} the m1th row.

The second reading unit 50 includes N holding units 51 _{1 to} 51 _N , a second column selection unit 52, and a difference calculation unit 53. The N holding portions 51 _{1 to} 51 _N have a common configuration. Each holding unit 51 _n is connected to the M pixel units P _{1, n to} P _{M, n} in the n-th column in the light receiving unit 10 via the readout signal line L 2 _n. Data output from the selected pixel portion P _{m2, n of} the m2nd row to the readout signal line L2 _n can be input, the data can be held, and the held data can be output. Each holding unit 51 _n preferably inputs and holds data of a signal component on which a noise component is superimposed, and preferably inputs and holds data of only a noise component.

The N holding units 51 _{1 to} 51 _N sample and hold data at the same timing based on various control signals received from the second column selection unit 52, and sequentially output the held data. Can do. The difference calculation unit 53 receives the data sequentially output from each of the _N holding units 51 _{1 to} 51 _N, and subtracts only the noise component data from the signal component data on which the noise component is superimposed to obtain the signal component. Output data according to. The difference calculation unit 53 may output data corresponding to the signal component as analog data, or may have an AD conversion function and output digital data. In this way, the second readout unit 50 can output data corresponding to the amount of electric charge generated in the photodiodes of the pixel units P _{m2, n in} the m2nd row.

FIG. 3 is a diagram illustrating a circuit configuration of the pixel unit P _{m, n} and the holding unit 41 _n of the solid-state imaging device 1 of the present embodiment. In this Figure, M × N pixel units P _{1, 1} to P M in the light receiving unit _10, the pixel portion P _m of the m-th row n-th column among the _{N, n} is shown as a representative, also, the In one reading unit 40, a holding unit 41n related to the pixel unit Pm _{, n} is shown. The configuration of the holding unit 51 _{n is the same as} the configuration of the holding unit 41 _n .

Each pixel unit P _{m, n} is of an APS (Active Pixel Sensor) type, and includes a photodiode PD and six MOS transistors T1, T2, T3, T4 ₁ , T4 ₂ , T5. As shown in this figure, the transistor T1, the transistor T2, and the photodiode PD are connected in series, the reference voltage is input to the drain terminal of the transistor T1, and the anode terminal of the photodiode PD is grounded. ing. A connection point between the transistor T1 and the transistor T2 is connected to the gate terminal of the transistor T3 through the transistor T5.

A reference voltage is input to the drain terminal of the transistor T3. The source terminal of the transistor T3 is connected to the respective drain terminals of the transistors T4 ₁ and T4 ₂ . Each pixel portion P _m, the source terminal of the transistor T4 ₁ of _n is connected to the read signal line L1 _n. Each pixel portion P _m, the source terminal of the transistor T4 ₂ of _n is connected to the read signal line L2 _n. A constant current source is connected to each of the read signal line L1 _n and the read signal line L2 _n .

The gate terminal of the transfer transistor T2 of each pixel unit P _{m, n} is connected to the control signal line LT _m, and a Trans (m) signal output from the first row selection unit 20 or the second row selection unit 30 is received. Entered. The gate terminal of the reset transistor T1 of each pixel unit P _{m, n} is connected to the control signal line LR _m, and the Reset (m) signal output from the first row selection unit 20 or the second row selection unit 30 is received. Entered. The gate terminal of the holding transistor T5 of each pixel unit P _{m, n} is connected to the control signal line LH _m, and the Hold (m) signal output from the first row selecting unit 20 or the second row selecting unit 30 is received. Entered.

The gate terminal of the transistor T4 ₁ for output selection in each pixel portion P _{m, n} is connected to the control signal line LA1 _m, Address1 _(m) signal output from the first row selecting section 20 is input. The gate terminal of the transistor T4 ₂ for output selection in each pixel portion P _{m, n} is connected to the control signal line LA2 _m, Address2 _(m) signal output from the second row selecting section 30 is inputted. These control signals (Reset (m) signal, Trans (m) signal, Hold (m) signal, Address1 (m) signal, Address2 (m) signal) are N pixel portions P _{m, 1 in} the m-th row. ˜P _{m, N} are input in common.

The control signal line LT _m , the control signal line LR _m, and the control signal line LH _m are provided for each row, and the junction capacitance portion and the charge storage portion of the photodiode PD in each pixel portion P _{m, n} in the m-th row. Control signals (Reset (m) signal, Trans (m) signal, Hold (m) signal) for instructing each discharge and charge accumulation by the charge accumulation unit are sent. The Reset (m) signal is output from the Reset1 (m) signal output from the first row selection unit 20, the Reset2 (m) signal output from the second row selection unit 30, and the third row selection unit 70. And a logical OR of the Reset3 (m) signal. The Trans (m) signal is output from the Trans1 (m) signal output from the first row selection unit 20, the Trans2 (m) signal output from the second row selection unit 30, and the third row selection unit 70. This is the logical OR of the Trans3 (m) signal. The Hold (m) signal is a logical sum of the Hold1 (m) signal output from the first row selection unit 20 and the Hold2 (m) signal output from the second row selection unit 30.

The control signal line LA1 _m and the control signal line LA2 _m are provided for each row, and instruct data output to the read signal line L1 _n or the read signal line L2 _n in each pixel unit P _{m, n} of the m-th row. Control signals (Address1 (m) signal, Address2 (m) signal). Each control signal line LA1 _m is connected to the first row selection unit 20. Each control signal line LA2 _m is connected to the second row selection unit 30. Address1 (m) signal and the Address2 (m) signal not simultaneously become high level and never turned on simultaneously with transistor T4 ₁ and the transistor T4 _2.

  When the Reset (m) signal, Trans (m) signal, and Hold (m) signal are at a high level, the junction capacitance portion of the photodiode PD is discharged, and the diffusion region (charge) connected to the gate terminal of the transistor T3. The storage part) is discharged. When the Trans (m) signal is at a low level, the charge generated in the photodiode PD is accumulated in the junction capacitor portion. When the Reset (m) signal is at a low level and the Trans (m) signal and the Hold (m) signal are at a high level, the charge accumulated in the junction capacitance portion of the photodiode PD is the gate terminal of the transistor T3. Is transferred to and accumulated in a diffusion region (charge accumulating portion) connected to.

When the Address1 (m) signal is at a high level, data corresponding to the amount of charge accumulated in the diffusion region (charge accumulation unit) connected to the gate terminal of the transistor T3 (signal component data on which a noise component is superimposed) ) is output via the transistor T4 ₁ to read signal line L1 _n, is input to the holding portion 41 _n of the first reading unit 40. That is, the transistor T4 ₁ acts as a first switch for outputting the data corresponding to the accumulated charge amount in the charge storage unit to the read signal line L1 _n. Note that the charge storage section when in a discharged state, the data of the noise component only is outputted to the read signal line L1 _n, the transistors T4 _1.

When the Address2 (m) signal is at high level, data corresponding to the amount of charge accumulated in the diffusion region (charge accumulation unit) connected to the gate terminal of the transistor T3 (data of the signal component on which the noise component is superimposed) ) is output via the transistor T4 ₂ to read the signal line L2 _n, is input to the holding portion 51 _n of the second reading section 50. That is, the transistor T4 ₂ acts as a second switch for outputting the data corresponding to the accumulated charge amount in the charge storage unit to the read signal line L2 _n. Note that the charge storage section when in a discharged state, the data of the noise component only is outputted to the read signal line L2 _n via the transistor T4 _2.

Each holding unit 41 _n includes two capacitive elements C ₁ and C ₂ and four switches SW ₁₁ , SW ₁₂ , SW ₂₁ , and SW ₂₂ . In the holding section 41 _n, the switch _{SW 11} and the switch _{SW 12} is provided between the in series connected to the read signal line L1 _n and the wiring Hline_s1, one terminal of the capacitance _{C 1,} the switch _{SW 11} and the switch is connected to the connection point between the SW _12, the other end of the capacitive element C ₁ is grounded. The switch _{SW 21} and the switch _{SW 22} is provided between the in series connected to the read signal line L1 _n and the wiring Hline_n1, one terminal of the capacitance _{C 2} is between the switch _{SW 21} and the switch _{SW 22} is connected to the connection point, the other end of the capacitive element C ₂ is grounded.

In the holding unit 41 _n , the switch SW ₁₁ opens and closes according to the level of the set_s1 signal supplied from the first column selection unit 42. The switch SW ₂₁ opens and closes according to the level of the set_n1 signal supplied from the first column selection unit 42. The set_s1 signal and the set_n1 signal are input in common to the _N holding units 41 _{1 to} 41 _N. The switches SW ₁₂ and SW ₂₂ open and close according to the level of the hshift1 (n) signal supplied from the first column selection unit 42.

In the holding unit 41 _n , the noise component output from the pixel unit P _{m, n} to the readout signal line L1 _n when the set_n1 signal changes from the high level to the low level and the switch SW ₂₁ is opened is thereafter capacitance. It is held as a voltage value out_n1 (n) by the element C _2. set_s1 signal in the pixel portion P _m, the signal components noise components are output to the read signal line L1 _n from _n is superimposed when the switch SW ₁₁ is opened in turn from a high level to a low level, thereafter, the capacitor It is held as a voltage value out_s1 (n) by C _1. When hshift1 (n) signal becomes a high level, the switch SW ₁₂ is closed, is output to the voltage value out_s1 (n) is the wiring Hline_s1 that has been held by the capacitor element C _1, The switch SW ₂₂ is closed , voltage value out_n1 that has been held by the capacitor element C ₂ (n) is output to the wiring Hline_n1. A difference between the voltage value out_s1 (n) and the voltage value out_n1 (n) represents a voltage value corresponding to the amount of charge generated in the photodiode PD of the pixel portion Pm _{, n} .

FIG. 4 is a diagram illustrating a circuit configuration of the difference calculation unit 43 of the solid-state imaging device 1 of the present embodiment. The configuration of the difference calculation unit 53 is the same as the configuration of the difference calculation unit 43. As shown in this figure, the difference calculation unit 43 includes amplifiers A _{1 to} A ₃ , switches SW ₁ and SW ₂ , and resistors R _{1 to} R ₄ . Inverting input terminal of the amplifier A ₃ is connected to the output terminal of the buffer amplifier A ₁ via a resistor R _1, and is connected to its own output terminal via the resistor R _3. The non-inverting input terminal of the amplifier A ₃ is connected to the output terminal of the buffer amplifier A ₂ via the resistor R _2, and is connected to the ground potential via the resistor R _4. Input terminal of the buffer amplifier _{A 1} is connected to the N holding portion ₄₁ 1 to 41 _N via the wiring Hline_s1, it is connected to the ground potential via the switch SW _1. Input terminal of the buffer amplifier _{A 2} is connected to the N holding portion ₄₁ 1 to 41 _N via the wiring Hline_n1, it is connected to the ground potential via the switch SW _2.

The switches SW ₁ and SW ₂ of the difference calculation unit 43 are controlled by the hreset1 signal supplied from the first column selection unit 42 to open and close. When the switch SW ₁ is closed, the voltage value input to the input terminal of the buffer amplifier A ₁ is reset. When the switch SW ₂ is closed, the voltage value input to the input terminal of the buffer amplifier A ₂ is reset. When the switch _SW 1, SW ₂ is open, the wiring from one of the holding portions 41 _n of the N holding portion ₄₁ 1 _{~41 N} Hline_s1, the voltage value outputted to the Hline_n1 out_s1 (n), out_n1 (n) is input to the input terminals of the buffer amplifiers A ₁ and A ₂ . Assuming that the amplification factors of the buffer amplifiers A ₁ and A ₂ are 1, and the resistance values of the _four resistors R _{1 to} R ₄ are equal to each other, the voltage value output from the output terminal of the difference calculation unit 43 is The difference between the voltage values input through the wiring Hline_s1 and the wiring Hline_n1 is represented, and the noise component is removed.

FIG. 5 is a diagram illustrating a configuration of the first row selection unit 20, the second row selection unit 30, and the third row selection unit 70 of the solid-state imaging device 1 according to the present embodiment. As shown in this figure, the first row selection unit 20 includes M control signal generation circuits 21 _{1 to} 21 _M that constitute the first shift register, and M pieces that constitute the second shift register. Latch circuits 22 _{1 to} 22 _M are included. The second row selection unit 30 includes M control signal generation circuits 31 _{1 to} 31 _M constituting the first shift register and M latch circuits 32 _{1 to} 32 _M constituting the second shift register. Including. In addition, the third row selection unit 70 includes M latch circuits 72 _{1 to} 72 _M , M logical product circuits 73 _{1 to} 73 _M , and M logical product circuits 74 ₁ to 74 that constitute the shift register. _M is included.

Each of the _M control signal generation circuits 21 _{1 to} 21 _M included in the first row selection unit 20 has a common configuration and is connected in cascade. That is, the input terminal I of each control signal generation circuit 21 _m is connected to the output terminal O of the control signal generation circuit 21 _m−1 in the previous stage (here, m is an integer of 2 or more and M or less). Input terminal I of the control signal generating circuit 21 ₁ of the first stage, since a high level at a certain timing clock VCLK1 instructs to enter a low vshift1 (0) signal. Each control signal generation circuit 21 _m operates in synchronization with the clock VCLK1, inputs the basic control signal 1, and when the data row_sel1_data [m] held by the corresponding latch circuit 22 _m is at a high level, At a predetermined timing, the Reset1 (m) signal, Trans1 (m) signal, Hold1 (m) signal, and Address1 (m) signal are output as a high level.

Each of the M latch circuits 22 _{1 to} 22 _M is a D flip-flop and is connected in cascade. That is, the input terminal D of each latch circuit 22 _m is connected to the output terminal Q of the preceding latch circuit 22 _m−1 (here, m is an integer from 2 to M). Input terminal D of the latch circuit 22 ₁ of the first stage, the M-bit data Row_sel1_data: inputting [M 1] to serial. Each latch circuit 22 _m can hold data row_sel1_data [m] by operating in synchronization with the clock row_sel1_clk. Each latch circuit 22 _m supplies the stored data row_sel1_data [m] to the corresponding control signal generation circuit 21 _m .

  The first row selection unit 20 is provided with a vshift1 (0) signal, a clock VCLK1, a basic control signal 1, M-bit data row_sel1_data [M: 1] and a clock row_sel1_clk from the control unit 60.

Each of the _M control signal generation circuits 31 _{1 to} 31 _M included in the second row selection unit 30 has a common configuration and is connected in cascade. That is, the input terminal I of each control signal generation circuit 31 _m is connected to the output terminal O of the control signal generation circuit 31 _m−1 in the previous stage (here, m is an integer of 2 or more and M or less). Input terminal I of the control signal generating circuit 31 ₁ of the first stage, since a high level at a certain timing clock VCLK2 instructs to enter a low vshift2 (0) signal. When the control signal generating circuit 31 _m operates in synchronization with a clock VCLK2, enter the basic control signal 2, the data row_sel2_data held by the corresponding latch circuit 32 _m [m] is at a high level, At a predetermined timing, the Reset2 (m) signal, Trans2 (m) signal, Hold2 (m) signal, and Address2 (m) signal are output as a high level.

Each of the M latch circuits 32 _{1 to} 32 _M is a D flip-flop and is connected in cascade. That is, the input terminal D of each latch circuit 32 _m is connected to the output terminal Q of the preceding latch circuit 32 _m−1 (here, m is an integer of 2 or more and M or less). Input terminal D of the latch circuit 32 ₁ of the first stage, the M-bit data Row_sel2_data: inputting [M 1] to serial. Each latch circuit 32 _m can hold data row_sel2_data [m] by operating in synchronization with the clock row_sel2_clk. Each latch circuit 32 _m gives the stored data row_sel2_data [m] to the corresponding control signal generation circuit 31 _m .

  The second row selection unit 30 is provided with a vshift2 (0) signal, a clock VCLK2, a basic control signal 2, M-bit data row_sel2_data [M: 1] and a clock row_sel2_clk from the control unit 60.

Each of the _M latch circuits 72 _{1 to} 72 _M included in the third row selection unit 70 is a D flip-flop, and is connected in cascade. That is, the input terminal D of each latch circuit 72 _m is connected to the output terminal Q of the preceding latch circuit 72 _m−1 (here, m is an integer of 2 or more and M or less). Input terminal D of the latch circuit 72 ₁ of the first stage, the M-bit data Row_sel3_data: inputting [M 1] to serial. Each latch circuit 72 _m can hold data row_sel3_data [m] by operating in synchronization with the clock row_sel3_clk.

Each AND circuit 73 _m included in the third row selection unit 70 inputs the data row_sel3_data [m] output from the latch circuit 72 _m and also inputs the data of the Trans3 signal. Output data as Trans3 (m). Each AND circuit 74 _m receives the data row_sel3_data [m] output from the latch circuit 72 _m and also inputs the data of the Reset3 signal, and outputs the data of these ANDs as Reset3 (m). .

  The third row selection unit 70 is provided with a Trans3 signal, a Reset3 signal, M-bit data row_sel3_data [M: 1], and a clock row_sel3_clk from the control unit 60.

When the row_sel3_data [m3] stored in the mth latch circuit 72 _m3 among the _M latch circuits 72 _{1 to} 72 _M is at a high level, the third row selection unit 70 selects each pixel in the m3th row. A control signal (Reset3 (m3) signal, Trans3 (m3) signal) can be output as a high level to the part P _{m3, n} at a predetermined timing.

FIG. 6 is a diagram illustrating a configuration of the control signal generation circuit 21 _m of the first row selection unit 20 of the solid-state imaging device 1 of the present embodiment. Each control signal generation circuit 21 _m includes a D flip-flop 210, a logical inversion circuit 211, logical product circuits 212 to 217, logical sum circuits 218 and 219, and a logical product circuit 221. Each control signal generating circuit 21 _m, as the basic control signal 1 described in FIG. 5, All_reset1 signal, Reset1 signal, Trans1 signal, and inputs the Hold1 signal and Address1 signal.

The D flip-flop 210 of each control signal generation circuit 21 _m receives the vshift1 (m−1) signal output from the control signal generation circuit 21 _m−1 in the previous stage, and stores the data at a timing indicated by the clock VCLK1. Hold and output the held data.

The AND circuit 212 of each control signal generation circuit 21 _m receives the data row_sel1_data [m] output from the corresponding latch circuit 22 _m and also receives the data output from the D flip-flop 210. Output the logical product of.

The AND circuit 213 of each control signal generation circuit 21 _m inputs data obtained by logically inverting the data row_sel1_data [m] output from the corresponding latch circuit 22 _m by the logic inverting circuit 211 and generates the control signal for the previous stage. Data of the vshift1 (m-1) signal output from the circuit 21 _m-1 is also input, and data of these logical products is output.

OR circuit 218 of the control signal generating circuit 21 _m, type AND circuit 212 and AND circuit 213 the respective data, and outputs the data of the logical OR as vshift1 (m) signal.

The logical product circuit 214 of each control signal generation circuit 21 _m receives the data row_sel1_data [m] output from the corresponding latch circuit 22 _m and also receives the data of the Reset1 signal, and the data of these logical products. Is output as a Reset1 (m) signal.

The logical product circuit 215 of each control signal generation circuit 21 _m inputs the data row_sel1_data [m] output from the corresponding latch circuit 22 _m and also inputs the data of the Trans1 signal, and the data of these logical products. Is output as Trans1 (m) signal.

The logical product circuit 221 of each control signal generation circuit 21 _m inputs the data row_sel1_data [m] output from the corresponding latch circuit 22 _m and also receives the data of the All_reset1 signal, and the data of these logical products. Is output.

The logical sum circuit 219 of each control signal generation circuit 21 _m inputs the output data of the logical product circuit 221 and also receives the output data of the logical product circuit 212 and outputs the logical sum data.

The logical product circuit 216 of each control signal generation circuit 21 _m inputs the output data of the logical sum circuit 219 and also inputs the data of the Hold1 signal, and outputs the data of these logical products as the Hold1 (m) signal. To do.

The logical product circuit 217 of each control signal generation circuit 21 _m inputs the data of the Address1 signal and also inputs the output data of the logical product circuit 212 and outputs the data of these logical products as the Address1 (m) signal. To do.

Figure 7 is a diagram showing a control signal generation circuit 31 _m configuration of the second row selecting section 30 of the solid-state imaging device 1 of the present embodiment. Each control signal generation circuit 31 _m includes a D flip-flop 310, a logical inversion circuit 311, logical product circuits 312 to 317, logical sum circuits 318 and 319, and a logical product circuit 321. Each control signal generating circuit 31 _m, as the basic control signal 2 explained in Fig. 5, All_reset2 signal, Reset2 signal, Trans2 signal, and inputs the Hold2 signal and Address2 signal.

The D flip-flop 310 of each control signal generation circuit 31 _m receives the vshift2 (m−1) signal output from the control signal generation circuit 31 _m−1 in the previous stage, and stores the data at a timing indicated by the clock VCLK 2. Hold and output the held data.

A logical product circuit 312 of each control signal generation circuit 31 _m inputs data row_sel2_data [m] output from the corresponding latch circuit 32 _m and also inputs data output from the D flip-flop 310. Output the logical product of.

The logical product circuit 313 of each control signal generation circuit 31 _m inputs data obtained by logically inverting the data row_sel2_data [m] output from the corresponding latch circuit 32 _m by the logical inverting circuit 311 and generates the control signal for the previous stage. The data of the vshift2 (m-1) signal output from the circuit 31 _m-1 is also input, and the data of these logical products is output.

OR circuit 318 of the control signal generating circuit 31 _m, type the AND circuit 312 and AND circuit 313 the respective data, and outputs the data of the logical OR as vshift2 (m) signal.

AND circuit 314 of each control signal generating circuit 31 _m inputs the data row_sel2_data [m] output from the corresponding latch circuit 32 _m, and also input data Reset2 signal, data of logical product Is output as a Reset2 (m) signal.

The logical product circuit 315 of each control signal generation circuit 31 _m receives the data row_sel2_data [m] output from the corresponding latch circuit 32 _m and also receives the data of the Trans2 signal, and the data of these logical products. Is output as a Trans2 (m) signal.

AND circuit 321 of each control signal generating circuit 31 _m inputs the data row_sel2_data [m] output from the corresponding latch circuit 32 _m, and also input data All_reset2 signal, data of logical product Is output.

The logical sum circuit 319 of each control signal generation circuit 31 _m receives the output data of the logical product circuit 321 and also receives the output data of the logical product circuit 312 and outputs the logical sum data.

AND circuit 316 of each control signal generating circuit 31 _m inputs the output data of the OR circuit 319, and also input data Hold2 signal, outputs the data of logical product as Hold2 (m) signal To do.

AND circuit 317 of each control signal generating circuit 31 _m inputs the data of the Address2 signal, and also input the output data of the AND circuit 312, outputs data of logical product as Address2 (m) signal To do.

  The data row_sel1_data [m1] is set to the high level corresponding to the m1st row to be selected by the first row selection unit 20. The data row_sel2_data [m2] is set to the high level corresponding to the m2th row to be selected by the second row selection unit 30. Further, the data row_sel3_data [m3] is set to the high level corresponding to the m3th row to be selected by the third row selection unit 70. In order to make the m1st row selected by the first row selection unit 20 and the m2th row selected by the second row selection unit 30 different from each other, for each m value, data row_sel1_data [m] and data row_sel2_data [m ] Must not be at a high level, and at least one of them must be at a low level.

In the first row selection unit 20 having the configuration shown in FIG. 6, the data row_sel1_data [m1] held in the mth latch circuit 22 _m1 among the _M latch circuits 22 _{1 to} 22 _M is at a high level ( at this time, data row_sel2_data [m1] is always low level) when the control signal generating circuit 21 _m1 corresponding to this, the m1 row control signals to the pixel portion P _{m1, n} of (Reset1 (m1 ) Signal, Trans1 (m1) signal, Hold1 (m1) signal) can be output as high level at a predetermined timing, and Address1 (m1) signal can also be output as high level at a predetermined timing. .

Further, in the first row selection unit 20, the control signal generation circuit corresponding to the latch circuit whose retained data row_sel1_data [m] is at the low level among the _M latch circuits 22 _{1 to} 22 _M receives the vshift1 signal reached from the previous stage. Can be immediately output to the subsequent stage. That is, of the M latch circuits 22 _{1 to} 22 _M , only the latch circuit whose holding data row_sel1_data [m] is at a high level constitutes a substantial shift register. Therefore, the first row selection unit 20 performs a fixed time interval (period of the clock VCLK1) with respect to the row corresponding to the latch circuit whose holding data row_sel1_data [m] is high level among the _M latch circuits 22 _{1 to} 22 _M. ) Can sequentially output control signals.

In the second row selection unit 30 having the configuration shown in FIG. 7, the data row_sel2_data [m2] held in the mth latch circuit 32 _m2 among the _M latch circuits 32 _{1 to} 32 _M is at a high level ( at this time, data row_sel1_data [m2] is always low level) when the control signal generating circuit 31 _m2 corresponding to this, the m2 row control signals to the pixel portion P _{m2, n} of (Reset2 (m2 ) Signal, Trans2 (m2) signal, Hold2 (m2) signal) can be output as high level at a predetermined timing, and Address2 (m2) signal can also be output as high level at a predetermined timing. .

Further, in the second row selection unit 30, the control signal generation circuit corresponding to the latch circuit whose retained data row_sel2_data [m] is at the low level among the _M latch circuits 32 _{1 to} 32 _M receives the vshift2 signal reached from the previous stage. Can be immediately output to the subsequent stage. That is, of the M latch circuits 32 _{1 to} 32 _M , only the latch circuit whose retained data row_sel2_data [m] is at a high level constitutes a substantial shift register. Therefore, the second row selection unit 30 sets a fixed time interval (the period of the clock VCLK2) with respect to the row corresponding to the latch circuit whose holding data row_sel2_data [m] is high level among the _M latch circuits 32 _{1 to} 32 _M. ) Can sequentially output control signals.

As described above, when the row_sel1_data [m1] stored in the mth latch circuit 22 _m1 among the _M latch circuits 22 _{1 to} 22 _M is at the high level, the first row selection unit 20 The Reset 1 (m 1) signal, Trans 1 (m 1) signal, Hold 1 (m 1) signal, and Address 1 (m 1) can be output as a high level at a predetermined timing to each pixel unit P _{m1, n in the m} 1 row. When the data row_sel2_data [m2] held in the _m-th latch circuit 32 _m2 among the _M latch circuits 32 _{1 to} 32 _M is at a high level, the second row selection unit 30 selects each pixel in the m2-th row. The Reset 2 (m 2) signal, Trans 2 (m 2) signal, Hold 2 (m 2) signal, and Address 2 (m 2) signal can be output to the part P _{m2, n} as a high level at a predetermined timing. Further, the third row selection unit 70 selects the m3th row when the data row_sel3_data [m3] held in the mth latch circuit 72 _m3 among the _M latch circuits 72 _{1 to} 72 _M is at a high level. The Reset3 (m3) signal and the Trans3 (m3) signal can be output as a high level at a predetermined timing to each pixel unit Pm3 _{, n} .

Next, an example (FIGS. 8 and 10) of the operation of the solid-state imaging device 1 of the present embodiment will be described in comparison with the comparative example (FIGS. 8 and 9). In the comparative example, each of the first row selection unit and the second row selection unit is configured to perform a photo for each pixel unit P _{m3, n in} any m3 row different from the m1 row and the m2 row in the light receiving unit 10. The junction capacitance part of the diode is not discharged. In any of the examples and comparative examples, M = N = 8 for the sake of simplicity of explanation.

FIG. 8 is a diagram illustrating a pixel unit in the light receiving unit 10 from which data is read out by each of the first reading unit 40 and the second reading unit 50 in the case of the operation of the comparative example. In the comparative example, before a certain time t, as shown in FIG. 5A, the communication data of the pixel portions P _5,3 and the pixel portions P _5,4 of the light receiving unit 10 are stored in the first row selection unit. And read out by the first reading unit (region A in FIG. 5A), the pixel unit P _3,2 to the pixel unit P _3,5 , the pixel unit P _4,2 to the pixel unit P _{4 of the} light receiving unit 10. _{, 5} , pixel portion P _6,2 to pixel portion P _6,5 and pixel portion P _7,2 to pixel portion P _{7,5, the} respective image data are read by the second row selection portion and the second reading portion (same as above). Region B in FIG.

In the comparative example, after the time t, the communication data of the pixel units P _{4, 4} and the pixel units P _{4, 5} of the light receiving unit 10 are selected as the first row, as shown in FIG. And the first readout unit (region A in FIG. 2B), the pixel unit P _2,3 to the pixel unit P _2,6 , the pixel unit P _3,3 to the pixel unit P of the light receiving unit 10. ₃ , ₆ , the pixel part P _5,3 to the pixel part P _5,6 and the pixel part P _6,3 to the pixel part P _6,6 are read out by the second row selection part and the second readout part ( Region B in FIG.

  That is, in the comparative example, the regions A and B of the pixel portion of the light receiving unit 10 read by the first reading unit or the second reading unit with respect to a certain time t are one pixel in the row direction and the column direction, respectively. Just shift.

  FIG. 9 is a timing chart in the case of the operation of the comparative example. In the figure, in order from the top, the operations of the pixel units in the eighth to first rows in the light receiving unit 10, the data input operation of the holding unit 41 of the first reading unit 40, and the data output from the first reading unit 40 are shown. An operation, a data input operation of the holding unit 51 of the second reading unit 50, and a data output operation from the second reading unit 50 are shown.

In the figure, “turn 1” indicates that the transistor T2 and the transistor T5 are turned on in the pixel portion, whereby the charge of the junction capacitance portion of the photodiode PD is diffused (connected to the gate terminal of the transistor T3). Represents transfer to a region (charge storage unit). "Rolling 2" represents the transfer of transistor T4 ₁ or the transistor T4 ₂ By the ON state, the data corresponding to the accumulated charge amount in the charge accumulating portion to the holding portion 41 or the memory 51 in the pixel unit. “Initialization” means that the transistor T1 and the transistor T2 are turned on in the pixel portion to discharge and initialize the junction capacitance portion of the photodiode PD. “Accumulation” represents that the charge generated in the photodiode PD is accumulated in the junction capacitor portion by turning off the transistor T1 in the pixel portion.

As shown in this figure, in the comparative example, the communication data of the pixel unit P _4,4 and the pixel unit P _{4,5 that} are first read by the first reading unit 40 immediately after time t are the last communication data immediately before time t. Since this corresponds to the amount of charge accumulated over a long period of time, it may be an incorrect value. Therefore, the optical signal from the optical signal source cannot be received accurately.

On the other hand, in this comparative example, the second row of the pixel unit P _2,3 to P _{2, 6} each image data read by the first to the second reading section 50 immediately after time t, at time t immediately before from the original last Since this corresponds to the amount of charge accumulated over a long period of time, it may be an incorrect value. In addition, the image data of the pixel portions P _{5,3 to} P _{5,6 in} the fifth row that is first read out by the second reading unit 50 immediately after time t lasts for a shorter period last than just before time t. Since it corresponds to the amount of accumulated charge, it may be an incorrect value. However, since these data are not communication data but image data, there may be no problem even if the data is incorrect, or the erroneous data can be interpolated using data in adjacent rows. So it is not a big problem.

  In the case of the operation of the embodiment, the pixel unit in the light receiving unit 10 from which data is read out by each of the first reading unit 40 and the second reading unit 50 is the same as that shown in FIG. However, in the embodiment, the junction of the photodiode PD of each pixel unit in the fourth row of the light receiving unit 10 from which data is read by the first row selecting unit and the first reading unit by the third row selecting unit 70 after time t. The capacitor unit is initialized at a time before the data read cycle of the first reading unit from time t. As a result, the data of each pixel unit in the fourth row of the light receiving unit 10 is read at regular time intervals after the initialization immediately before the time t.

  FIG. 10 is a timing chart in the case of the operation of the embodiment. In the figure, in order from the top, the operations of the pixel units in the eighth to first rows in the light receiving unit 10, the data input operation of the holding unit 41 of the first reading unit 40, and the data output from the first reading unit 40 are shown. An operation, a data input operation of the holding unit 51 of the second reading unit 50, and a data output operation from the second reading unit 50 are shown. “Rotation 1”, “Rotation 2”, “Initialization”, and “Storage” in FIG. 9 are the same as those in FIG.

As shown in this figure, in the embodiment, the communication data of the pixel unit P _4,4 and the pixel unit P _{4,5 that} are first read by the first reading unit 40 immediately after the time t are the time before the time t. This corresponds to the amount of charge accumulated over the same period after t. Therefore, the optical signal from the optical signal source can be accurately received. Thus, the solid-state imaging device 1 of the present embodiment can accurately receive the optical signal from the optical signal source even when tracking the position of the optical signal source.

On the other hand, also in this embodiment, the pixel unit P _2,3 to P _{2, 6} each image data of the second row to be read by the first to the second reading section 50 immediately after time t, the last original time t immediately before Since this corresponds to the amount of charge accumulated over a longer period, it may be an incorrect value. In addition, the image data of the pixel portions P _{5,3 to} P _{5,6 in} the fifth row that is first read out by the second reading unit 50 immediately after time t lasts for a shorter period last than just before time t. Since it corresponds to the amount of accumulated charge, it may be an incorrect value. However, since these data are not communication data but image data, there may be no problem even if the data is incorrect, or the erroneous data can be interpolated using data in adjacent rows. So it is not a big problem.

  Note that the solid-state imaging device 1 of the present embodiment can operate in various modes. For example, the first row selection unit 20 may select odd-numbered rows in the light-receiving unit 10, and the second row selection unit 30 may select even-numbered rows in the light-receiving unit 10. In this case, the position of the optical signal source is specified based on the image data of the even-numbered rows read by the second row selecting unit 30 and the second reading unit 50, and any one of the specified positions in the image is present. The first row selection unit 20 and the first reading unit 40 read out data from the odd-numbered pixel units as communication data. In this case, the third row selection unit 70 initializes the junction capacitance portion of the photodiode PD of each pixel unit in the m3th row from which data is to be newly written prior to the start of reading.

  Further, the solid-state imaging device 1 of the present embodiment can also operate as shown in FIGS. 11 and 12.

FIG. 11 is a diagram illustrating a pixel unit in the light receiving unit 10 from which data is read out by each of the first reading unit 40 and the second reading unit 50 in the case of the operation of another embodiment. In this embodiment, before a certain time t ₁ , the communication data of the pixel portions P ₅ and ₃ and the pixel portions P ₅ and ₄ of the light receiving portion 10 are selected as the first row as shown in FIG. And the first reading unit (region A in FIG. 5A), the communication data of the pixel unit P _6,6 and the pixel unit P _{6,7 of} the light receiving unit 10 are the second row selection unit and It is read by the second reading unit (region B in FIG. 4A).

From time t ₁ to time t ₂ , as shown in FIG. 5B, the communication data of the pixel unit P _4,2 and the pixel unit P _4,3 of the light receiving unit 10 are transmitted to the first row selection unit and the first row selection unit, respectively. 1 is read by the reading unit (region A in FIG. 2B), and the communication data of the pixel unit P _6,6 and the pixel unit P _{6,7 of} the light receiving unit 10 are the second row selecting unit and the second reading unit. Read by the unit (region B in FIG. 2B). Then, after time t ₂ , as shown in FIG. 5C, the communication data of the pixel portions P ₄ and ₂ and the pixel portions P ₄ and ₃ of the light receiving portion 10 are sent to the first row selection portion and the first readout. (Region A in FIG. 3C), the communication data of the pixel portions P _7,6 and the pixel portions P _{7,7 of} the light receiving portion 10 are transmitted by the second row selection portion and the second reading portion, respectively. It is read out (region B in FIG. 4C).

  That is, in this embodiment, there are two optical signal sources that can move independently from each other, and the optical signal data from one optical signal source is read by the first row selection unit and the first reading unit. The optical signal data from the other optical signal source is read by the second row selection unit and the second reading unit.

  FIG. 12 is a timing chart in the case of the operation of another embodiment. In the figure, in order from the top, the operations of the pixel units in the eighth to first rows in the light receiving unit 10, the data input operation of the holding unit 41 of the first reading unit 40, and the data output from the first reading unit 40 are shown. An operation, a data input operation of the holding unit 51 of the second reading unit 50, and a data output operation from the second reading unit 50 are shown. “Rotation 1”, “Rotation 2”, “Initialization”, and “Storage” in FIG. 9 are the same as those in FIG. As shown in this figure, the data reading of the first reading unit and the data reading of the second reading unit have the same period but different phases.

Although the line to be read the data by the first row selecting section and the first reading unit is changed by the time t ₁ as a boundary, the pixel portion P _{4, 2} and the pixel read initially in the first reading unit immediately after the time t ₁ part P _4,3 each communication data is equivalent to the amount of charge accumulated over the time t ₁ the same period after the time t ₁ before. Although the line to be read out the data by the second row selecting section and the second reading unit is changed by the time t ₂ as a boundary, the pixel portion P _{7, 6} to be read first to the second reading unit immediately after the time t ₂ The communication data of each of the pixel portions P ₇ and ₇ corresponds to the amount of charge accumulated over the same period before time t _{2 as} before time t ₂ . Therefore, the optical signals from the two optical signal sources can be accurately received. As described above, the solid-state imaging device 1 according to the present embodiment can accurately receive the optical signal from each optical signal source even when tracking the positions of the two optical signal sources.

1 ... solid-state imaging device, 10 ... receiving unit, 20 ... first row selecting section, ₂₁ 1 through 21 M _... control signal generating circuit, ₂₂ 1 through 22 M _... latch circuit, 30 ... second row selecting section, ₃₁ 1 ~ 31 _M ... Control signal generation circuit, 32 _{1 to} 32 _M ... Latch circuit, 40... First reading unit, 41 _{1 to} 41 _N ... Holding unit, 42 ... First column selection unit, 43. 2 reading unit, 51 _{1 to} 51 _N ... holding unit, 52 ... first column selection unit, 53 ... difference calculation unit, 60 ... control unit, 70 ... third row selection unit, 72 _{1 to} 72 _M ... latch circuit, P _1,1 ~P _{M, N} ... pixel _{portion, L1 1 ~L1 N, L2 1} ~L2 N ... read signal _{line, LT 1 ~LT M, LR 1} ~LR M, LH 1 ~LH M, LA1 1 ~LA1 _M , LA2 _{1 to} LA2 _M ... Control signal lines.

Claims (4)

A photodiode that generates an amount of charge corresponding to the amount of incident light, a charge storage unit that stores the charge, a first switch that outputs data corresponding to the amount of charge stored in the charge storage unit, and the charge storage M × N pixel units P _{1,1 to} P _{M, N} each having a second switch for outputting data corresponding to the amount of stored charge in the unit are two-dimensionally arranged in M rows and N columns A light receiver;
Any one of the m1 rows in the light receiving unit is selected, and a control signal is output to each pixel unit P _{m1, n in} the m1 row, thereby discharging the junction capacitance portion of the photodiode, and A first row selection unit that accumulates charges generated by a diode in the charge accumulation unit and closes the first switch to output data corresponding to the accumulated charge amount in the charge accumulation unit to the read signal line L1 _n ;
By selecting one of the m2 rows that is different from the m1 row in the light receiving unit and outputting a control signal to each pixel unit P _{m2, n of} the m2 row, the junction capacitance portion of the photodiode is The second charge is discharged, the charge generated in the photodiode is accumulated in the charge accumulation unit, and the second switch is closed to output data corresponding to the accumulated charge amount in the charge accumulation unit to the read signal line L2 _n . A row selection section;
A third row that discharges the junction capacitance portion of the photodiode by selecting any m3 row in the light receiving portion and outputting a control signal to each pixel portion P _{m3, n of the m3} row. A selection section;
Is connected to the N number of read signal line L1 ₁ ~L1 _N, output from each pixel portion P _{m1, n} of the m1 row in a selected light receiving unit to the read signal line L1 _n by the first row selecting section A first reading unit that inputs data and outputs data corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m1, n in} the m1st row;
Is connected to the N number of read signal line L2 ₁ ~L2 _N, output from each pixel portion P _{m2, n} of the m2 row in a selected light receiving unit to the read signal line L2 _n by the second row selecting section A second readout unit that inputs data and outputs data corresponding to the amount of charge generated in the photodiode of each pixel unit P _{m2, n in} the m2nd row;
With
The first row selection unit and the first readout unit and the second row selection unit and the second readout unit operate in parallel with each other;
Solid-state imaging device (where M and N are integers of 2 or more, m1 and m2 are integers of 1 to M and different from each other, m3 is an integer of 1 to M, and n is 1 to N) Integer). The first row selection unit includes M latch circuits, and when the data held in the m1st latch circuit is a significant value, the control is performed on each pixel unit P _{m1, n} in the m1st row. Output signal,
The second row selection unit includes M latch circuits, and when the data held in the m2nd latch circuit is a significant value, the control is performed on each pixel unit _{Pm2, n} in the m2th row. Output signal,
The third row selection unit includes M latch circuits, and when the data held in the m3th latch circuit is a significant value, the control is performed on each pixel unit _{Pm3, n} in the m3th row. Output signal,
The solid-state imaging device according to claim 1. M latch circuits of each of the first row selection unit, the second row selection unit, and the third row selection unit are cascaded in row order to form a shift register, and the first stage latch circuit in the shift register Each latch circuit holds data by serially inputting M-bit data to
The solid-state imaging device according to claim 2. The first row selection unit sequentially outputs the control signal at a predetermined time interval to a plurality of rows corresponding to a latch circuit having retained data having a significant value among M latch circuits included in the first row selection unit,
The second row selection unit sequentially outputs the control signal at a predetermined time interval to a plurality of rows corresponding to a latch circuit whose retained data is a significant value among the M latch circuits included in the second row selection unit.
The solid-state imaging device according to claim 2.

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