TWI531239B - Solid-state imaging device - Google Patents

Description

Solid state camera

The present invention relates to a solid-state imaging device.

The solid-state imaging device includes a light receiving unit that two-dimensionally arrays M×N pixel portions P _1,1 to P _M,N each including a photodiode and a charge storage portion in M rows and N rows, and a column selection unit. In the pixel portion P _{m,n of} the light receiving portion, the charge generated in the photodiode is stored in the charge storage portion for a certain period of time, and the stored charge corresponding to each pixel portion P _m,n is outputted column by column. amounts of data; and a readout portion that inputs from each pixel unit P _m light _unit, the data _n output of, and outputting each of the pixel portions P _m, to produce _n of the photodiode in the charge amount corresponding to the data; Further, the present invention further includes an AD conversion unit that performs AD (Analog to Digital) conversion on the data output from the reading unit and outputs a digital value.

Such a solid-state imaging device can detect the intensity of light reaching the respective pixel portions P _{m, n} of the light receiving portion and perform imaging. Moreover, in recent years, not only imaging using such a solid-state imaging device but also attempting to perform optical communication has been attempted. For example, the solid-state imaging device of the invention disclosed in Patent Document 1 includes a plurality of means for reading data from each pixel portion, and the first reading means for reading data for each pixel portion can be imaged by using the first reading means. The optical signal can be received by accumulating and outputting a current signal generated from a photodiode of one or more specific pixel portions by the second reading means.

Prior technical literature Patent literature

Patent Document 1: Japanese Patent No. 3995959

In the solid-state imaging device of the invention disclosed in Patent Document 1, since the data read by the first reading means is image data, the speed of data reading by the first reading means is, for example, several tens of fps ( Frame per second, frame / second). On the other hand, since the data read by the second reading means is communication data, the data reading speed of the second reading means is, for example, tens of kbps (kilo bit per second). .

The inventors have found that the following problems occur in such a solid-state imaging device that performs imaging and optical communication. The solid-state imaging device of the invention disclosed in Patent Document 1 is also intended to be used in the case where there is a possibility that the optical signal source moves. In this case, the position of the optical signal source is specified based on the image data read by the first reading means, and the pixel from the specific position in the image is set by the second reading means. The information of the Ministry is read as communication data.

When the position of the optical signal source is tracked as such, a certain pixel portion reads the image data by the first reading means before a certain time t, and reads the communication material by the second reading means after the time t. . Alternatively, the certain pixel portion does not read the data by any of the first reading means and the second reading means before a certain time t, and the communication data is read by the second reading means after the time t. That is, in the pixel portion, the charge storage time before time t is longer than the charge storage time after time t. However, since the communication data read by the second reading means immediately after the time t corresponds to the amount of electric charge stored for a long period of time before the time t, there is a case where the value is an error. Therefore, the solid-state imaging device cannot correctly receive the optical signal from the optical signal source.

The present invention has been made to solve the above problems, and an object of the invention is to provide a solid-state imaging device for optical communication that can accurately receive an optical signal from an optical signal source even when the position of the optical signal source is tracked.

A solid-state imaging device according to the present invention includes: (1) a light receiving unit that two-dimensionally arranges M×N pixel portions P _1,1 to P _M,N in M rows and N rows _, and the pixel portion P ₁ Each of ₁ to P _M,N includes a photodiode that generates a charge corresponding to the amount of incident light, a charge storage portion that stores the charge, and a first switch that outputs data corresponding to the amount of stored charge in the charge storage portion. And a second switch for outputting data corresponding to the amount of stored charge in the charge storage unit; (2) a first column selecting unit that selects any m1th column of the light receiving unit and each of the m1th column The pixel portion P _m1,n outputs a control signal, thereby discharging the junction capacitance portion of the photodiode, storing the charge generated in the photodiode in the charge storage portion, and closing the first switch to correspond to The data of the stored charge amount in the charge storage unit is output to the read signal line L1 _n ; and (3) the second column selection unit selects any m2th column different from the m1th column in the light receiving unit, and the m2th column column of each pixel portion P _{m2, n} outputs a control signal, whereby the engagement of the photodiode discharges the capacitor portion, so that the photodiode The generated charges stored in the charge storage portion, and the second switch is turned off by the charge amount corresponding to the charge storage portion of the information stored in the L2 _n outputs the readout signal line; (4) a first reading portion, It is connected to the N read signal lines L1 ₁ to L1 _N , and is input to the read signal line L1 _n from each of the pixel portions P _{m1 and n} of the m1th column among the light receiving units selected by the first column selecting unit. And outputting data corresponding to the amount of charge generated in the photodiode of each pixel portion P _m1,n of the m1th column; and (5) the second readout portion, and the N readout signals The lines L2 ₁ to L2 _{N are} connected, and the data output from the pixel portions P _{m2 and n} of the m2th column of the light receiving unit selected by the second column selecting unit to the read signal line L2 _{n are} input and output. The amount of charge generated in the photodiode of each pixel portion P _m2,n of the m2 column corresponds to the amount of charge. Further, the solid-state imaging device according to the present invention is characterized in that any m3th column in the light receiving portion is selected, and a control signal is outputted to each of the pixel portions _{Pm3, n of} the m3th column, thereby coupling capacitance of the photodiode In the partial discharge, the first column selection unit and the first reading unit and the second column selection unit and the second reading unit operate in parallel with each other. In the above, M and N are integers of 2 or more, and m1 and m2 are integers of 1 or more and M or less, and m3 is an integer of 1 or more and M or less, and n is an integer of 1 or more and N or less.

In the solid-state imaging device of the present invention, the first column selection unit selects any m1th column of the light receiving unit, and the junction capacitance of the photodiode is made in each of the pixel portions _{Pm1 and n} of the m1th column. In the partial discharge, the charge generated in the photodiode is stored in the charge storage portion, and the data corresponding to the stored charge amount in the charge storage portion is output to the read signal line L1 _n by turning off the first switch. The first reading unit connected to each of the read signal lines L1 _n is input to each of the pixel portions P _{m1 and n} of the m1th column among the light receiving units selected by the first column selecting unit _{, and} reads the signal line L1. _n output data, and output data corresponding to the amount of charge generated in the photodiode of each pixel portion P _m1,n of the m1th column.

On the other hand, the second column selection unit selects any m2th column of the light receiving unit, and discharges the junction capacitance portion of the photodiode in each of the pixel portions P _{m2 and n} of the m2 column. The charge generated in the diode is stored in the charge storage portion, and the data corresponding to the stored charge amount in the charge storage portion is output to the read signal line L2 _n by turning off the second switch. In the second reading unit connected to each of the read signal lines L2 _n , each of the pixel portions P _{m2 and n} of the m2th column of the light receiving units selected by the second column selecting unit is input to the read signal line L2. _n output data, and output data corresponding to the amount of charge generated in the photodiode of each pixel portion P _m2,n of the m2th column.

The first column selection unit and the second column selection unit select columns different from each other in the light receiving unit. Further, the first column selection unit and the first reading unit and the second column selection unit and the second reading unit operate in parallel with each other. Thereby, for example, the image data is obtained by the first column selecting unit and the first reading unit, and the communication data is obtained by the second column selecting unit and the second reading unit.

Further, in the solid-state imaging device of the present invention, any m3th column in the light receiving portion is selected, and the junction capacitance portion of the photodiode is discharged in each of the pixel portions _{Pm3, n} of the m3th column.

In the solid-state imaging device of the present invention, preferably, the first column selection unit or the second column selection unit selects any m3th column different from the m1th column and the m2th column among the light receiving units, and the m3th column is selected. Each of the pixel portions P _m3,n outputs a control signal to discharge the junction capacitance portion of the photodiode. Among them, m1, m2, and m3 are integers of 1 or more and M or less and different from each other. In the solid-state imaging device of the present invention, the first column selection unit or the second column selection unit selects any m3th column in the light receiving unit that is different from the m1th column and the m2th column, and each of the m3th columns In the pixel portion P _m3,n , the junction capacitance portion of the photodiode is discharged.

Preferably, the solid-state imaging device according to the present invention further includes a switching mechanism that switches the first column selection unit and the second column selection unit to output a control signal to each of the pixel portions P _{m3 and n} of the m3th column of the light receiving unit. The column selection unit that discharges the junction capacitance portion of the photodiode is either the first column selection unit or the second column selection unit.

Preferably, in the solid-state imaging device of the present invention, (a) the first column selection unit includes M latch circuits, and when the data held in the m1th latch circuit is an effective value, each pixel of the m1th column is used. The portion P _m1,n outputs a control signal; (b) the second column selection portion includes M latch circuits, and when the data held in the m2th latch circuit is an effective value, each pixel portion of the m2 column P _m2,n output control signal; (c) one of the first column selection unit and the second column selection unit is held in the m3th latch circuit of the M latch circuits of the other column selection unit When the data is a non-effective value, a control signal is output to each of the pixel portions P _m3,n of the m3th column.

In the solid-state imaging device of the present invention, it is preferable that the M latch circuits of the first column selection unit and the second column selection unit are cascade-connected in the column order to form a shift register, and the M-bit data string is formed. The column is input to the latch circuit of the initial stage in the shift register, and the data is held by each latch circuit.

Preferably, in the solid-state imaging device of the present invention, (a) the first column selecting unit sequentially performs a fixed time interval for a plurality of columns corresponding to a latch circuit in which M data is held in the M latch circuits included therein. The control signal is output; (b) the second column selection unit sequentially outputs the control signals at a fixed time interval for the plurality of columns corresponding to the latch circuits in which the data is held in the M latch circuits included therein.

Preferably, the solid-state imaging device according to the present invention further includes a third column selecting unit that selects any m3th column of the light receiving unit, and outputs a control signal to each of the pixel portions _{Pm3, n of} the m3th column, thereby making the photoelectric The junction capacitance portion of the diode is discharged. In the solid-state imaging device of the present invention, the third column selection unit selects any m3th column of the light receiving unit, and the junction capacitance of the photodiode is made in each of the pixel portions _{Pm3 and n} of the m3th column. Part discharge.

Preferably, in the solid-state imaging device of the present invention, (a) the first column selection unit includes M latch circuits, and when the data held in the m1th latch circuit is an effective value, each pixel of the m1th column is used. The portion P _m1,n outputs a control signal; (b) the second column selection portion includes M latch circuits, and when the data held in the m2th latch circuit is an effective value, each pixel portion of the m2 column P _m2,n output control signal; (c) the third column selection unit includes M latch circuits, and when the data held in the m3th latch circuit is an effective value, each pixel portion P of the m3th column _M3,n output control signals.

In the solid-state imaging device of the present invention, it is preferable that the M latch circuits of the first column selection unit, the second column selection unit, and the third column selection unit are cascade-connected in the column order to form a shift register. The data of the M bit is serially input to the latch circuit of the initial stage in the shift register, and the data is held by each latch circuit.

Preferably, in the solid-state imaging device of the present invention, (a) the first column selecting unit sequentially performs a fixed time interval for the plurality of columns corresponding to the latch circuits in which the data is held in the M latch circuits included therein. The control signal is output; (b) the second column selection unit sequentially outputs the control signals at a fixed time interval for the plurality of columns corresponding to the latch circuits in which the data is held in the M latch circuits included therein.

The solid-state imaging device of the present invention can correctly receive an optical signal from an optical signal source even when tracking the position of the optical signal source.

Hereinafter, embodiments for carrying out the invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same components are denoted by the same reference numerals, and the description thereof will not be repeated.

(First embodiment)

FIG. 1 is a view showing a schematic configuration of a solid-state imaging device 1 according to the first embodiment. The solid-state imaging device 1 shown in the figure includes a light receiving unit 10, a first column selecting unit 20, a second column selecting unit 30, a first reading unit 40, a second reading unit 50, and a control unit 60.

The light receiving unit 10 includes M×N pixel portions P _1,1 to P _M,N . The M×N pixel portions P _1,1 to P _M,N have a common configuration, and are two-dimensionally arranged in M columns and N rows. Each of the pixel portions P _m,n is located in the nth row of the mth column. Here, M and N are integers of 2 or more, m is an integer of 1 or more and M or less, and n is an integer of 1 or more and N or less.

Each of the pixel portions P _m,n includes a photodiode that generates an electric charge corresponding to the amount of incident light, and a charge storage portion that stores the electric charge. Each of the pixel portions P _m,n can discharge the junction capacitance portion of the photodiode based on various control signals received from the first column selection portion 20 or the second column selection portion 30 via the control signal line, and the photodiode The charge generated in the charge is stored in the charge storage portion, and the data corresponding to the stored charge amount in the charge storage portion is output to the read signal line L1 _n or the read signal line L2 _n .

The first column selection unit 20 selects any m1th column of the light receiving unit 10, and outputs a control signal to each of the pixel portions _{Pm1, n of} the m1th column, thereby discharging the junction capacitance portion of the photodiode, and photoelectrically The charge generated in the diode is stored in the charge storage portion, and the data corresponding to the stored charge amount in the charge storage portion is output to the readout signal line L1 _n .

The second column selecting unit 30 selects any m2th column of the light receiving unit 10, and outputs a control signal to each of the pixel portions _{Pm2, n of} the m2th column, thereby discharging the junction capacitance portion of the photodiode, and photoelectrically The charge generated in the diode is stored in the charge storage portion, and the data corresponding to the stored charge amount in the charge storage portion is output to the readout signal line L2 _n .

Further, the first column selecting unit 20 selects any m3th column in the light receiving unit 10, and outputs a control signal to each of the pixel portions _{Pm3, n of} the m3th column, thereby discharging the junction capacitance portion of the photodiode. The charge generated in the photodiode is stored in the charge storage portion.

Here, m1, m2, and m3 are integers of 1 or more and M or less and different from each other. The first column selection unit 20 and the second column selection unit 30 select the columns different from each other in the light receiving unit 10 . The number of columns selected by each of the first column selection unit 20 and the second column selection unit 30 is arbitrary, but the output of the data is sequentially performed column by column.

The first reading unit 40 is connected to the N read signal lines L1 ₁ to L1 _N and is input to each of the pixel portions P _{m1 and n} of the m1th column of the light receiving unit 10 selected by the first column selecting unit 20. The data outputted to the read signal line L1 _{n is} outputted with data corresponding to the amount of charge generated in the photodiode of each pixel portion P _m1,n of the m1th column.

The second reading unit 50 is connected to the N read signal lines L2 ₁ to L2 _N and is input to each of the pixel portions P _{m2 and n} of the m2th column of the light receiving unit 10 selected by the second column selecting unit 30. The data outputted to the read signal line L2 _{n is} outputted with data corresponding to the amount of charge generated in the photodiode of each pixel portion P _m2,n of the m2th column.

The control unit 60 controls the operation of the entire solid-state imaging device 1 by controlling the operations of the first column selection unit 20, the second column selection unit 30, the first reading unit 40, and the second reading unit 50. By the control unit 60, the first column selection unit 20 and the first reading unit 40, and the second column selection unit 30 and the second reading unit 50 can be operated in parallel.

FIG. 2 is a view showing the configuration of the first reading unit 40 and the second reading unit 50 of the solid-state imaging device 1 according to the first embodiment. In the figure, the light-receiving unit 10 typically represents the pixel portions P _m,n of the m-th pixel portions P _1,1 to P _M, the m-th row and the n-th row, and the first read. Each of the output unit 40 and the second reading unit 50 indicates a component related to the pixel portion P _m,n .

The first reading unit 40 includes N holding units 41 ₁ to 41 _N , a first line selecting unit 42 , and a difference calculating unit 43 . The N holding portions 41 ₁ to 41 _N have a common configuration. Each of the holding portions 41 _n is connected to the M pixel portions P _1n to P _{M, n} of the nth row of the light receiving portion 10 via the read signal line L1 _n , and can be input from the first column selecting portion 20 The pixel portion P _m1,n of the m1th column is selected to output the data to the read signal line L1 _n , and the data is held, and the held data is output. Each holding portion 41 _n is preferably input into and held information signal component superimposed with the noise components, and data input into and held only noise components.

The N holding units 41 ₁ to 41 _N can sample and hold the data at the same timing based on various control signals received from the first line selecting unit 42, and sequentially output the held data. The difference calculation unit 43 inputs the data sequentially output from each of the N holding units 41 ₁ to 41 _N , and subtracts only the data of the noise component from the data of the signal component in which the noise component is superimposed, and the output corresponds to the signal. Information on ingredients. The difference calculation unit 43 may output the data corresponding to the signal component as analog data, or may have an AD conversion function to output digital data. In this manner, the first reading unit 40 can output data corresponding to the amount of electric charge generated in the photodiode of each of the pixel portions P _m1,n of the m1th column.

The second reading unit 50 includes N holding units 51 ₁ to 51 _N , a second line selecting unit 52 , and a difference calculating unit 53 . The N holding portions 51 ₁ to 51 _N have a common configuration. Each of the holding portions 51 _n is connected to the M pixel portions P _1n to P _M,n of the nth row of the light receiving portion 10 via the read signal line L2 _n , and can be input from the second column selecting portion 20 The pixel portion P _m2,n of the m2th column is selected to output the data to the read signal line L2 _n , and the data is held, and the held data is output. Each of the holding portions 51 _n preferably inputs and holds data of a signal component in which a noise component is superimposed, and inputs and holds only data of a noise component.

The N holding units 51 ₁ to 51 _N can sample and hold the data at the same timing based on the various control signals received from the second line selecting unit 52, and sequentially output the held data. The difference calculation unit 53 inputs the data sequentially output from each of the N holding units 51 ₁ to 51 _N , and subtracts only the data of the noise component from the data of the signal component in which the noise component is superimposed, and the output corresponds to the signal. Information on ingredients. The difference calculation unit 53 may output the data corresponding to the signal component as analog data, or may have an AD conversion function to output digital data. In this manner, the second reading unit 50 can output data corresponding to the amount of electric charge generated in the photodiode of each of the pixel portions P _m2,n of the m2th column.

FIG. 3 is a view showing a circuit configuration of the pixel portion P _m,n and the holding portion 41 _n of the solid-state imaging device 1 according to the first embodiment. In the figure, the light receiving unit 10 also typically represents the pixel portions P _{m,n of} the nth row and the nth row of the M×N pixel portions P _1,1 to P _M,N , and The reading unit 40 indicates a holding portion 41 _n related to the pixel portion P _{m, n} . Further, the configuration of the holding portion 51 _{n is} the same as the configuration of the holding portion 41 _n .

Each of the pixel portions P _m,n is an APS (Active Pixel Sensor) method, and includes a photodiode PD and six MOS (Metal Oxide Semiconductor) transistors T1, T2, T3, and T4. ₁ , T4 ₂ , T5. As shown in the figure, the transistors T1 and T2 and the photodiode PD are connected in series, and a reference voltage is applied to the terminal of the transistor T1, and the anode terminal of the photodiode PD is grounded. The junction of the transistor T1 and the transistor T2 is connected to the gate terminal of the transistor T3 via the transistor T5.

There is a reference voltage to the 汲 terminal input of transistor T3. The source terminal of the transistor T3 is connected to the respective terminal terminals of the transistors T4 ₁ and T4 ₂ . The source terminal of the transistor T4 ₁ of each pixel portion P _m,n is connected to the read signal line L1 _n . The source terminal of the transistor T4 ₂ of each pixel portion P _m,n is connected to the read signal line L2 _n . A constant current source is connected to the read signal line L1 _n and the read signal line L2 _n , respectively.

Each pixel unit P _m, the gate transistor T2 is conveyed by _{n of} the terminal lines control signal line LT _m is connected, the input from the Trans 30 outputs the column selecting section 20 or the second column selection section (m) signal. Each pixel unit P _{m, n} reset transistor T1 of the gate terminal of a system and the control signal line LR _m is connected, the input from the Reset 30 outputs the column selecting section 20 or the second column selection section (m) signal . Each pixel unit P _{m, n} of the holding transistor with the gate terminal lines and control signal lines LH _m T5 of connector, input from Hold 30 outputs the column selecting section 20 or the second column selection section (m) signal.

The gate terminal of the transistor T4 _{1 for} output selection of each pixel portion P _m,n is connected to the control signal line LA1 _m , and the Address 1 (m) signal output from the first column selecting portion 20 is input. The gate terminal of the transistor T4 _{2 for} output selection of each pixel portion P _m,n is connected to the control signal line LA2 _m , and the Address 2 (m) signal output from the second column selecting portion 30 is input. The control signals (Reset (m) signal, Trans (m) signal, Hold (m) signal, Address 1 (m) signal, Address 2 (m) signal) are N pixels portion P _m,1 ~ in the mth column. P _m,N are input in common.

The control signal line LT _m , the control signal line LR _{m ,} and the control signal line LH _m are provided for each column, and transmit the junction capacitance portion and the charge storage of the photodiode PD in each pixel portion P _m,n of the mth column. Control signals (Reset (m) signal, Trans (m) signal, Hold (m) signal) for the discharge of each part and the charge storage of the charge storage portion. The Reset (m) signal is a logical sum of the Reset 1 (m) signal output from the first column selecting portion 20 and the Reset 2 (m) signal output from the second column selecting portion 30. The Trans(m) signal is a logical sum of a Trans1(m) signal output from the first column selecting unit 20 and a Trans2(m) signal output from the second column selecting unit 30. Further, the Hold(m) signal is a logical sum of the Hold1(m) signal output from the first column selecting unit 20 and the Hold2(m) signal output from the second column selecting unit 30.

The control signal line LA1 _m and the control signal line LA2 _m are provided for each column, and control for outputting data to the read signal line L1 _n or the read signal line L2 _n of each pixel portion P _m,n of the mth column is transmitted. Signal (Address1 (m) signal, Address 2 (m) signal). Each control signal line LA1 _{m is} connected to the first column selection unit 20. Each control signal line LA2 _{m is} connected to the second column selection unit 30. The Address1(m) signal and the Address2(m) signal do not become high at the same time, so that the transistor T4 ₁ and the transistor T4 ₂ do not become conductive at the same time.

When the Reset(m) signal, the Trans(m) signal, and the Hold(m) signal are at a high level, the junction capacitance portion of the photodiode PD is discharged, and is connected to the diffusion region of the gate terminal of the transistor T3 (charge storage). Department) Discharge. When the Trans(m) signal is at a low level, the charge generated in the photodiode PD is stored in the junction capacitance portion. If the Reset(m) signal is at a low level and the Trans(m) signal and the Hold(m) signal are at a high level, the charge stored in the junction capacitance portion of the photodiode PD is delivered to the gate terminal of the transistor T3. The diffusion region (charge storage portion) is connected and stored.

When the Address1(m) signal is at a high level, the data corresponding to the amount of charge stored in the diffusion region (charge storage portion) connected to the gate terminal of the transistor T3 (data of the signal component superimposed with the noise component) The transistor T4 ₁ outputs the signal to the read signal line L1 _{n and is} input to the holding portion 41 _{n of the} first read unit 40. In other words, the transistor T4 ₁ functions as a first switch for outputting data corresponding to the amount of stored charge in the charge storage unit to the read signal line L1 _n . Further, when the charge storage portion is in the discharge state, only the data of the noise component is output to the readout signal line L1 _n via the transistor T4 ₁ .

When the Address 2 (m) signal is at a high level, the data corresponding to the amount of charge stored in the diffusion region (charge storage portion) connected to the gate terminal of the transistor T3 (data of the signal component superimposed with the noise component) The transistor T4 ₂ outputs the signal to the read signal line L2 _{n and is} input to the holding portion 51 _{n of} the second read unit 50. That is, the transistor T4 ₂ functions as a second switch for outputting the data corresponding to the stored charge amount in the charge storage portion to the read signal line L2 _n . Further, when the charge storage portion is in the discharge state, only the data of the noise component is output to the readout signal line L2 _n via the transistor T4 ₂ .

Each of the holding portions 41 _n includes two capacitive elements C ₁ and C ₂ and four switches SW ₁₁ , SW ₁₂ , SW ₂₁ , and SW ₂₂ . In the holding portion 41 _n , the switch SW ₁₁ and the switch SW _{12 are} connected in series and disposed between the read signal line L1 _n and the wiring Hline_s1 , and one end of the capacitive element C ₁ is connected between the switch SW ₁₁ and the switch SW ₁₂ . At the connection point, the other end of the capacitive element C ₁ is grounded. Further, the switch SW ₂₁ and the switch SW _{22 are} connected in series and disposed between the read signal line L1 _n and the wiring Hline_n1, and one end of the capacitive element C ₂ is connected to a connection point between the switch SW ₂₁ and the switch SW ₂₂ , and the capacitor element The other end of C ₂ is grounded.

In the holding portion 41 _n , the switch SW ₁₁ is opened and closed based on the level of the set_s1 signal supplied from the first row selecting unit 42. The switch SW ₂₁ is opened and closed based on the level of the set_n1 signal supplied from the first row selecting unit 42. The set_s1 signal and the set_n1 signal are commonly input to the N holding portions 41 ₁ to 41 _N . The switches SW ₁₂ and SW ₂₂ are opened and closed based on the level of the hshiftl(n) signal supplied from the first row selecting unit 42.

In the holding portion 41 _n , when the set_n1 signal is changed from the high level to the low level and the switch SW _{21 is} turned on, the noise component is output from the pixel portion P _m,n to the read signal line L1 _n , and thereafter the capacitor is used. The element C _{2 is held} as the voltage value out_n1(n). When the set_s1 signal is changed from the high level to the low level and the switch SW _{11 is} turned on, the signal component of the noise component is superimposed from the pixel portion P _m,n to the read signal line L1 _n , and thereafter by the capacitive element C ₁ It is held as the voltage value out_s1(n). Further, if hshift1 (n) signal becomes high level, the switch SW ₁₂ is closed, the capacitor element C by _holding the voltage value out_s1 (n) to the output line Hline_s1, and the switch SW ₂₂ is closed by the capacitance element C _{2 The} held voltage value out_n1(n) is output to the wiring Hline_n1. The difference between the voltage value out_s1(n) and the voltage value out_n1(n) represents a voltage value corresponding to the amount of charge generated in the photodiode PD of the pixel portion Pm _,n .

FIG. 4 is a view showing a circuit configuration of the difference calculation unit 43 of the solid-state imaging device 1 according to the first embodiment. The configuration of the difference calculation unit 53 is the same as that of the difference calculation unit 43. As shown in the figure, the difference calculation unit 43 includes amplifiers A ₁ to A ₃ , switches SW ₁ and SW ₂ , and resistors R ₁ to R ₄ . The inverting input terminal of the amplifier A ₃ is connected to the output terminal of the buffer amplifier A ₁ via the resistor R ₁ , and is connected to its own output terminal via the resistor R ₃ . The non-inverting input terminal of the amplifier A ₃ is connected to the output terminal of the buffer amplifier A ₂ via the resistor R ₂ , and is connected to the ground potential via the resistor R ₄ . The input terminal of the buffer amplifier A ₁ is connected to the N holding portions 41 ₁ to 41 _N via the wiring Hline_s1, and is connected to the ground potential via the switch SW ₁ . The input terminal of the buffer amplifier A ₂ is connected to the N holding portions 41 ₁ to 41 _N via the wiring Hline_n1, and is connected to the ground potential via the switch SW ₂ .

The switches SW ₁ and SW _{2 of the} difference calculation unit 43 are controlled to be opened and closed by the hreset1 signal supplied from the first line selection unit 42. The voltage value input to the input terminal of the buffer amplifier A ₁ is reset by the switch SW _{1 being} turned off. The voltage value input to the input terminal of the buffer amplifier A ₂ is reset by the switch SW _{2 being} turned off. When the switches SW ₁ and SW _{2 are} turned on, the voltage values out_s1(n) and out_n1(n) output from the arbitrary holding portions 41 _{n of the} N holding portions 41 ₁ to 41 _N to the wirings Hline_s1 and Hline_n1 are input to the buffer amplifier A. ₁ , A ₂ input terminal. When the amplification factor of each of the buffer amplifiers A ₁ and A _{2 is} set to 1, and the resistance values of the four resistors R ₁ to R ₄ are equal to each other, the voltage value of the output terminal of the self-difference calculation unit 43 is expressed. The difference between the voltage values input through each of the wiring Hline_s1 and the wiring Hline_n1 is the noise component removed.

FIG. 5 is a view showing a configuration of the first column selection unit 20 and the second column selection unit 30 of the solid-state imaging device 1 according to the first embodiment. As shown in the figure, the first column selecting unit 20 includes M control signal generating circuits 21 ₁ to 21 _M constituting the first shift register and M latch circuits 22 constituting the second shift register. ₁ ~ 22 _M. Further, the second column selecting unit 30 includes M control signal generating circuits 31 ₁ to 31 _M constituting the first shift register and M latch circuits 32 ₁ to 32 _M constituting the second shift register. .

Each of the M control signal generating circuits 21 ₁ to 21 _M included in the first column selecting unit 20 has a common configuration and is connected in cascade. That is, the input terminal 21 _m of the respective control signal generating circuit I is connected to the front portion of the control signal generating circuit the output terminal O 21 _m-1 (where, m is integers of 2 or more and M or less). The input terminal I of the first stage control signal generating circuit 21 ₁ is input to a vshift1(0) signal whose timing indicated by the clock VCLK1 is a high level and then is a low level. Each control signal generating circuit 21 _m VCLK1 synchronization with the clock operation, a control signal input base 1, when the information held by the 22 _m corresponding to the latch circuit row_sell_data [m] is at a high time, in particular the timing of the Reset1 (m) The signal, the Trans1(m) signal, the Hold1(m) signal, and the Address1(m) signal are output as high levels.

Each of the M latch circuits 22 ₁ to 22 _M is a D flip-flop and is connected in cascade. That is, the input terminal D of each latch circuit 22 _m is connected to the output terminal Q of the latch circuit 22 _m-1 of the previous stage (here, m is an integer of 2 or more and M or less). The input terminal D of the latch circuit 22 ₁ of the first stage inputs the data of the M bit row_sel1_data[M:1] in series. Each latch circuit 22 _m can hold the data row_sel1_data[m] by synchronizing with the clock row_sel1_clk. Each latch circuit 22 _m supplies the held data row_sel1_data[m] to the corresponding control signal generating circuit 21 _m .

The first column selection unit 20 supplies the vshift1(0) signal, the clock VCLK1, the basic control signal 1, and the M-bit data row_sel1_data[M:1] and the pulse_sel1_clk from the control unit 60.

Each of the M control signal generating circuits 31 ₁ to 31 _M included in the second column selecting unit 30 has a common configuration and is cascade-connected in order. That is, the input terminal 31 _m of the respective control signal generating circuit I is connected to the front portion of the control signal generating circuit 31 _m-1 of the output terminal O (here, m is integers of 2 or more and M or less). The input terminal I of the first stage control signal generating circuit 31 ₁ is input to a vshift2(0) signal whose timing indicated by the clock VCLK2 is a high level and then is a low level. Each control signal generating circuit 31 _m line VCLK2 synchronization with the clock operation, a control signal input base 2, when the information held by 32 _m corresponding to the latch circuit row_sel2_data [m] is at a high time, in particular the timing of the Reset2 (m The signal, the Trans2(m) signal, the Hold2(m) signal, and the Address2(m) signal are output as high levels.

Each of the M latch circuits 32 ₁ to 32 _M is a D flip-flop and is connected in cascade. That is, the input terminal D of each latch circuit 32 _m is connected to the output terminal Q of the latch circuit 32 _m-1 of the previous stage (where m is an integer of 2 or more and M or less). The input terminal D of the latch circuit 32 ₁ of the first stage inputs the data of the M bit row_sel2_data[M:1] in series. Each latch circuit 32 _m can hold the data row_sel2_data[m] by synchronizing with the clock row_sel2_clk. Each data latch circuit 32 _m The holding the row_sel2_data [m] to 31 _m corresponding to the control signal generating circuit is supplied, and also supplied to the control signal generating circuit 21 _m.

The second column selecting unit 30 supplies the vshift2(0) signal, the clock VCLK2, the basic control signal 2, the M bit data row_sel2_data[M:1], and the time pulse row_sel2_clk from the control unit 60.

FIG. 6 is a view showing a configuration of a control signal generating circuit 21 _m of the first column selecting unit 20 of the solid-state imaging device 1 according to the first embodiment. Each control signal generating circuit 21 _m includes a D flip-flop 210, a logic inverting circuit 211, logic product circuits 212 to 217, logic sum circuits 218 and 219, a logic product circuit 221, and a logic inversion circuit 222. Each of the control signal generating circuits 21 _m inputs the All_reset1 signal, the Reset1 signal, the Trans1 signal, the Hold1 signal, and the Address1 signal as the basic control signal 1 illustrated in FIG.

The D flip-flop 210 of each control signal generating circuit 21 _m is input from the vshift1 (m-1) signal output from the control signal generating circuit 21 _{m-1 of the} previous stage, and holds the data at the timing indicated by the clock VCLK1, and outputs the data. Keep the information.

The logic product circuit 212 of each control signal generating circuit 21 _m inputs the data row_sel1_data[m] output from the corresponding latch circuit 22 _m , and also inputs the data output from the D flip-flop 210, and outputs the logical product of the data. data.

The logic product circuit 213 of each control signal generating circuit 21 _m inputs the data row_sel1_data[m] output from the corresponding latch circuit 22 _m by the logic inversion circuit 211 for logic inversion, and also inputs the control signal from the previous segment. The data of the vshift1(m-1) signal outputted by the circuit 21m _{-1 is} generated, and the data of the logical products are output.

21 _m of the respective control signal generating circuit, and a logic circuit 218 inputs the logical product circuit 212 the logical product circuit 213 and respective information, and the logical sum of information such as vshift1 (m) signal outputs.

The logic product circuit 214 of each of the control signal generating circuits 21 _m inputs the data inverted by the logic inversion circuit 222 from the data row_sel2_data[m] output from the latch circuit 32 _m corresponding to the second column selecting unit 30, The data of the Reset1 signal is also input, and the data of the logical products are output as the Reset1(m) signal.

The logical product circuit 215 of each control signal generating circuit 21 _m inputs the data row_sel2_data[m] output from the latch circuit 32 _m corresponding to the second column selecting unit 30, and the logic inverting circuit 222 performs logical inversion data, and The data of the Trans1 signal is also input, and the data of the logical products is output as a Trans1(m) signal.

The logical product circuit 221 of each control signal generating circuit 21 _m is input from the data row_sel1_data[m] output from the corresponding latch circuit 22 _m , and also inputs the data of the All_reset1 signal, and outputs the data of the logical products.

21 _m of the respective control signal generating circuit, and a logic circuit 219 inputs the logical product circuit 221 outputs data, the output data Qieyi input of the AND circuit 212, and outputs a logic sum of these data.

The logical product circuit 216 of each control signal generating circuit 21 _m inputs the output data of the logical sum circuit 219, and also inputs the data of the Hold1 signal, and outputs the data of the logical products as the Hold1 (m) signal.

The logical product circuit 217 of each control signal generating circuit 21 _m inputs the data of the Address 1 signal, and also inputs the output data of the logical product circuit 212, and outputs the data of the logical products as the Address 1 (m) signal.

FIG. 7 is a view showing a configuration of a control signal generating circuit 31 _m of the second column selecting unit 30 of the solid-state imaging device 1 according to the first embodiment. Each control signal generating circuit 31 _m includes a D flip-flop 310, a logic inverting circuit 311, logical product circuits 312 to 317, logic sum circuits 318 and 319, and a logical product circuit 321. Each of the control signal generating circuits 31 _m inputs the All_reset2 signal, the Reset2 signal, the Trans2 signal, the Hold2 signal, and the Address2 signal as the basic control signal 2 illustrated in FIG.

The D flip-flop 310 of each control signal generating circuit 31 _m inputs the vshift 2 (m - 1 ) signal output from the control signal generating circuit 31 _{m-1 of the} previous stage, holds the data at the timing indicated by the clock VCLK 2, and outputs the data. Keep the information.

The logic product circuit 312 of each control signal generating circuit 31 _m inputs the data row_sel2_data[m] output from the corresponding latch circuit 32 _m , and also inputs the data output from the D flip-flop 310, and outputs the logical product of the data. data.

The logic product circuit 313 of each control signal generating circuit 31 _m inputs the data row_sel2_data[m] output from the corresponding latch circuit 32 _m by the logic inversion circuit 311 for logic inversion, and also inputs the control signal from the previous stage. The data of the vshift2(m-1) signal outputted by the circuit 31m _{-1 is} generated, and the data of the logical products are output.

The logical sum circuit 318 of each control signal generating circuit 31 _m inputs the data of each of the logical product circuit 312 and the logical product circuit 313, and outputs the logical sum data as a vshift 2 (m) signal.

The logic product circuit 314 of each control signal generating circuit 31 _m inputs the data row_sel2_data[m] output from the corresponding latch circuit 32 _m , and also inputs the data of the Reset 2 signal, and uses the data of the logical products as Reset2 (m). ) Signal and output.

The logic product circuit 315 of each control signal generating circuit 31 _m inputs the data row_sel2_data[m] output from the corresponding latch circuit 32 _m , also inputs the data of the Trans2 signal, and uses the data of the logical products as Trans2(m). The signal is output.

The logical product circuit 321 of each control signal generating circuit 31 _m inputs the data row_sel2_data[m] output from the corresponding latch circuit 32 _m , and also inputs the data of the All_reset 2 signal, and outputs the data of the logical products.

Information output logic 31 _m of the respective control signal generating circuit and the input circuit 319 the logical product circuit 321, the output data Qieyi input of the AND circuit 312, and outputs a logic sum of these data.

The logical product circuit 316 of each control signal generating circuit 31 _m inputs the output data of the logical sum circuit 319, and also inputs the data of the Hold2 signal, and outputs the data of the logical products as the Hold2 (m) signal.

The logical product circuit 317 of each control signal generating circuit 31 _m inputs the data of the Address 2 signal, and also inputs the output data of the logical product circuit 312, and outputs the data of the logical products as the Address 2 (m) signal.

The data row_sel1_data[m1] is set to a high level corresponding to the m1th column to be selected by the first column selection unit 20. Further, the data row_sel2_data[m2] is set to a high level in accordance with the m2th column to be selected by the second column selecting unit 30. In order to make the m1th column selected by the first column selecting unit 20 and the m2th column selected by the second column selecting unit 30 different from each other, the data row_sel1_data[m] and the data row_sel2_data[m] must be different for each m value. High level, at least one of which is low.

Column having a first configuration of the selection unit 20 of FIG. 6, when the data 22 ₁ ~ 22 _{M M} latch circuits in the first latch circuit 22 is _m1 m1 held the row_sel1_data [m1] is at a high level ( At this time, when the data row_sel2_data[m1] is necessarily a low level, the control signal generating circuit 21 _m1 corresponding thereto can control signals (Reset1 (m1) signal, Trans1 (for each pixel portion P _{m1, n of} the m1th column). The m1) signal and the Hold1 (m1) signal are output as a high level at a specific timing, and the Address1 (m1) signal can also be output as a high level at a specific timing.

Further, in the first column selecting unit 20, the control signal generating circuit corresponding to the latch circuit in which the holding data row_sel1_data[m] of the M latch circuits 22 ₁ to 22 _M is low level can reach vshift1 from the previous stage. The signal is output directly to the back segment. That is, among the M latch circuits 22 ₁ to 22 _M , only the latch circuit that holds the data row_sel1_data[m] at a high level constitutes a substantially shift register. Therefore, the first column selecting unit 20 can be in a column corresponding to the latch circuit holding the data row_sel1_data[m] in the M latch circuits 22 ₁ to 22 _M at a fixed time interval (cycle of the clock VCLK1). The control signals are output in sequence.

Having the second column selecting section 30 shown in the configuration of FIG. 7, when the data of 32 _m2 m2 latch circuits 32 ₁ ~ 32 _{M M} latch circuits in the row_sel2_data held in the [m2] at the high level ( At this time, when the data row_sel1_data[m2] is necessarily a low level, the control signal generating circuit 31 _m2 corresponding thereto can control signals (Reset2 (m2) signal, Trans2 (for each pixel portion P _{m2, n of} the m2th column). The m2) signal and the Hold2 (m2) signal are output as a high level at a specific timing, and the Address2 (m2) signal can also be output as a high level at a specific timing.

Further, in the second column selecting unit 30, the control signal generating circuit corresponding to the latch circuit in which the data row_sel2_data[m] is held in the M latch circuits 32 ₁ to 32 _M can transmit the vshift 2 signal from the previous stage. Output directly to the back section. That is, among the M latch circuits 32 ₁ to 32 _M , only the latch circuit that holds the data row_sel2_data[m] at a high level constitutes a substantially shift register. Therefore, the second column selecting unit 30 can be in a column corresponding to the latch circuit in which the data row_sel2_data[m] is held at the M latch circuits 32 ₁ to 32 _M at a fixed time interval (cycle of the clock VCLK2). The control signals are output in sequence.

Further, in the row selecting section 20 of the M latch circuits 22 ₁ ~ 22 _M in the m3-th latch circuit 22 is _m3 held the row_sel1_data [m3] at a low level, and the second column selecting section 30 of 32 ₁ ~ 32 M data latch circuits 32 m3 _m3 of _M in the latch circuit as the holding row_sel2_data [m3] is also at low level, corresponding to the column selecting section 20 of the control signal generating circuit 21 is to be _m3 Each of the pixel portions P _{m3,n of} the m3th column outputs a control signal (Reset1 (m3) signal, Trans1 (m3) signal) as a high level at a specific timing, without the Hold1 (m3) signal and Address1 (m3). The signal is output as a high level at a specific timing.

In other words, the first column selection unit 20 does not use the m2th column selected by the m1th column and the second column selection unit 30 selected by the first column selection unit 20 in the first to the Mth columns of the light receiving unit 10. All of the columns are selected as the m3th column, and a control signal is outputted to each of the pixel portions _{Pm3,n of} the m3th column, whereby the junction capacitance portion of the photodiode PD can be discharged, and the photodiode can be The charge generated in the charge is stored in the charge storage portion.

Next, an example (Figs. 10 and 11) of the operation of the solid-state imaging device 1 according to the first embodiment will be described in comparison with a comparative example (Figs. 8 and 9). In the comparative example, none of the first column selection unit and the second column selection unit does not correspond to each of the pixel portions P _m3 of any m3th column of the light receiving unit 10 that is different from the m1th column and the m2th column _{. n} also discharges the junction capacitance portion of the photodiode. In any of the examples and the comparative examples, the description is simplified and M=N=8.

FIG. 8 is a view for explaining a pixel portion of the light receiving unit 10 in which data is read by each of the first reading unit 40 and the second reading unit 50 in the case of the operation of the comparative example. In the comparative example, before a certain time t, as shown in FIG. 8(a), the communication data of each of the pixel portion P _{5, 3} and the pixel portion P _{5, 4 of} the light receiving portion 10 is selected by the first column and the first column. 1 readout portion (region A in Fig. 8(a)), pixel portion _P3,2 to pixel portion _{P3,5 of} the light receiving portion 10, pixel portion _P4,2 to pixel portion _P4,5 The image data of each of the pixel portion P _6,2 to the pixel portion P _6,5 and the pixel portion P _7,2 to the pixel portion P _{7,5 is} read by the second column selection portion and the second reading portion ( Area B) in Figure 8(a).

Further, in the comparative example, after the time t, as shown in FIG. 8(b), the communication data of each of the pixel portion P4, ₄ and the pixel portion P4, _{5 of} the light receiving portion 10 is selected by the first column. Reading with the first reading unit (region A in FIG. 8(b)), pixel portion P _2,3 to pixel portion P _{2,6 of} the light receiving portion 10, and pixel portion P _3,3 to pixel portion P _{3 6} , the image data of each of the pixel portion P _5,3 to the pixel portion P _5,6 and the pixel portion P _6,3 to the pixel portion P _{6,6 is} read by the second column selection portion and the second reading portion Out (area B in Figure 8(b)).

In other words, in the comparative example, the regions A and B of the pixel portion of the light receiving portion 10 read by the first reading portion or the second reading portion are aligned in the column direction and the row direction at a certain time t. Offset by 1 pixel.

Fig. 9 is a timing chart showing the operation of the comparative example. In FIG. 9, the operation of the pixel portion of each of the eighth to the first columns of the light receiving unit 10 and the data input operation of the holding unit 41 of the first reading unit 40 are sequentially shown from the top to the bottom. The data output operation of the reading unit 40, the data input operation of the holding unit 51 of the second reading unit 50, and the data output operation from the second reading unit 50 are performed.

In FIG. 9, "turning 1" indicates that the charge of the junction capacitance portion of the photodiode PD is transferred to the FD region (connected to the transistor) by turning on the transistor T2 and the transistor T5 in the pixel portion. Diffusion region (charge storage portion) of the gate terminal of T3). "Turn 2" means that the data corresponding to the amount of stored charge in the charge storage portion is transferred to the holding portion 41 or the holding portion 51 by turning on the transistor T4 ₁ or the transistor T4 ₂ in the pixel portion. The "initialization" indicates that the charge of the junction capacitance portion of the photodiode PD is discharged by the discharge of the transistor T1 and the transistor T2 in the pixel portion. "Storage" means that the charge generated in the photodiode PD is stored in the junction capacitance portion by the transistor T1 being turned off in the pixel portion.

As shown in the figure, in the comparative example, the communication data of each of the pixel portion P _{4, 4} and the pixel portion P _{4, 5 which} are first read by the first reading unit 40 after the time t is equivalent to the time t. The amount of charge that was stored last for a long period of time, and thus there is a case where the value is an error. Therefore, the optical signal from the optical signal source cannot be correctly received.

On the other hand, in the comparative example, the image data of each of the pixel portions P _{2, 3} to P _{2, 6} of the second column read by the second reading unit 50 after the time t is equivalent to The amount of charge stored in the last longer period than before the time t, and thus there is a case where the value is an error. Further, the image data of each of the pixel portions P _{5, 3} to P _{5, 6} of the fifth column read by the second reading unit 50 after the time t is equivalent to being shorter than the time before the time t. The amount of charge stored during the period is such that it becomes a wrong value. However, since the information is not the communication data and is the image data, there is no problem even if the data is incorrect, or because the data of the error can be interpolated using the data of the adjacent column, it will not become larger. The problem.

FIG. 10 is a view for explaining a pixel portion of the light receiving unit 10 in which data is read by each of the first reading unit 40 and the second reading unit 50 in the case of the operation of the embodiment. In the embodiment, before a certain time t, as shown in FIG. 10(a), the communication data of each of the pixel portion P _{5, 3} and the pixel portion P _{5, 4 of} the light receiving portion 10 is selected by the first column and the first column. 1 readout portion (region A in Fig. 10(a)), pixel portion _P2,2 to pixel portion _{P2,5 of} the light receiving portion 10, pixel portion _P3,2 to pixel portion _P3,5 The image data of each of the pixel portion P _7,2 to the pixel portion P _7,5 and the pixel portion _P8,2 to the pixel portion _{P8,5 is} read by the second column selection portion and the second reading portion ( Area B) in Figure 10(a). Further, in the first column selecting unit 20, the junction capacitance portion of the photodiode PD of each of the pixel portions of the first column, the fourth column, and the sixth column is in the photodiode of each pixel portion of the fifth column. The bonding capacitors of the body PD are initialized at the same timing.

Further, in the embodiment, after the time t, as shown in FIG. 10(b), the communication data of each of the pixel portion P4, ₄ and the pixel portion P4, _{5 of} the light receiving portion 10 is selected by the first column. a second readout unit read out (FIG. 10 (b) in the region A), the light receiving portion 10 of the pixel portions P _1,3 ~ pixel portions P _1,6, P _2,3 ~ pixel unit pixel portion P _{2 6.} The image data of each of the pixel portion P _6,3 to the pixel portion P _6,6 and the pixel portion P _7,3 to the pixel portion P _{7,6 is} read by the second column selection portion and the second reading portion. Out (area B in Figure 10(b)). Further, in the first column selecting unit 20, the junction capacitance portion of the photodiode PD of each of the pixel portions of the third column, the fifth column, and the eighth column is in the photodiode of each pixel portion of the fourth column. The bonding capacitors of the body PD are initialized at the same timing.

In other words, in the embodiment, each of the regions A and B of the pixel portion of the light receiving portion 10 read by the first reading portion or the second reading portion is a column direction and a row direction at a certain time t as a boundary. In the first column selection unit 20, only the column of the junction capacitance portion of the photodiode PD is shifted downward by one column.

Fig. 11 is a timing chart showing the operation of the embodiment. In FIG. 11, the operation of the pixel portion of each of the eighth to the first columns of the light receiving unit 10 and the data input operation of the holding unit 41 of the first reading unit 40 are sequentially shown from the top to the bottom. The data output operation of the reading unit 40, the data input operation of the holding unit 51 of the second reading unit 50, and the data output operation from the second reading unit 50 are performed. The "turn 1", "turn 2", "initialize" and "storage" in Fig. 11 are the same as those in Fig. 9, respectively.

As shown in the figure, in the embodiment, the communication data of the pixel portion P _{4, 4} and the pixel portion P _{4, 5 which} are first read by the first reading unit 40 after the time t are equivalent to before the time t. The amount of charge stored during the same period as after time t. Therefore, the optical signal from the optical signal source can be correctly received. As described above, the solid-state imaging device 1 according to the first embodiment can accurately receive the optical signal from the optical signal source even when the position of the optical signal source is tracked.

On the other hand, in this embodiment, the image data of each of the pixel portions of the first column and the sixth column which are first read by the second reading unit 50 after the time t corresponds to the last time before the time t. The amount of charge stored in the short period of time is therefore a case of a wrong value. However, since the information is not the communication data and is the image data, there is no problem even if the data is incorrect, or because the data of the error can be interpolated using the data of the adjacent column, it will not become larger. The problem.

Further, the solid-state imaging device 1 according to the first embodiment can be operated in various aspects. For example, the first column selecting unit 20 may select the odd-numbered columns in the light receiving unit 10, and the second column selecting unit 30 may select the even-numbered columns in the light receiving unit 10. In this case, the position of the optical data source of the image data of the even-numbered column read by the second column selecting unit 30 and the second reading unit 50 is determined by the first column selecting unit 20 and the first The reading unit 40 reads the data of the pixel portion of any odd-numbered column located at a specific position in the image as communication data. In this case, the first column selecting unit 20 initializes the junction capacitance portion of the photodiode PD of each pixel portion of the odd-numbered columns other than the column of the communication data read by the first reading unit 40.

(Second embodiment)

Next, the second embodiment will be described. In the solid-state imaging device 1 of the first embodiment, the discharge capacitance portion of the photodiode PD of each pixel portion P _{m3,n in} the m3th column can be set only as the first column selection portion 20. On the other hand, in the solid-state imaging device 2 of the second embodiment, the first column selection unit 20A and the second column selection unit 20B can be switched, and each pixel portion P _m3 in the m3th column of the light receiving unit 10 can be switched. _{The n} selection control unit outputs a control signal, and the column selection unit that discharges the junction capacitance portion of the photodiode PD is either the first column selection unit 20A and the second column selection unit 30A.

FIG. 12 is a view showing a schematic configuration of the solid-state imaging device 2 according to the second embodiment. In comparison with the schematic configuration of the solid-state imaging device 1 of the first embodiment shown in FIG. 1, the solid-state imaging device 2 of the second embodiment shown in FIG. 12 differs in that the first column selection unit 20A is included instead of the first column. The one column selection unit 20 includes a second column selection unit 30A instead of the second column selection unit 30, and a control unit 60A instead of the control unit 60. The light receiving unit 10, the first reading unit 40, and the second reading unit 50 are the same as those of the first embodiment.

The control unit 60A controls the operation of the entire solid-state imaging device 2 by controlling the operations of the first column selection unit 20A, the second column selection unit 30A, the first reading unit 40, and the second reading unit 50. The first column selection unit 20A and the first reading unit 40 and the second column selection unit 30A and the second reading unit 50 can be operated in parallel with each other by the control unit 60A.

FIG. 13 is a view showing the configuration of the first column selection unit 20A and the second column selection unit 30A of the solid-state imaging device 2 according to the second embodiment. As shown in the figure, the first column selecting unit 20 includes M control signal generating circuits 23 ₁ to 23 _M constituting the first shift register and M latch circuits 22 constituting the second shift register. ₁ ~ 22 _M. Further, the second column selecting unit 30 includes M control signal generating circuits 33 ₁ to 33 _M constituting the first shift register and M latch circuits 32 ₁ to 32 _M constituting the second shift register. .

Each of the M control signal generating circuits 23 ₁ to 23 _M included in the first column selecting unit 20 has a common configuration and is connected in cascade. That is, each of the control signal generating circuit 23 _m of the input terminal I is connected to the front portion of the control signal generating circuit 23 _m-1 of the output terminal O (here, m is an integer of 2 or more and M or less each of). The input terminal I of the control signal generating circuit 23 ₁ of the first stage is input to a vshift1 (0) signal whose timing indicated by the clock VCLK1 is a high level and then is a low level. Each control signal generating circuit 23 _m line VCLK1 synchronization with the clock operation, a control signal input base 1, when the data corresponding to 22 _m by the latch circuit holding the row_sel1_data [m] is at a high time, in particular of a Reset1 the timing ( m) The signal, the Trans1 (m) signal, the Hold 1 (m) signal, and the Address 1 (m) signal are output as high levels.

Each of the M latch circuits 22 ₁ to 22 _M is a D flip-flop and is connected in cascade. That is, the input terminal D of each latch circuit 22 _m is connected to the output terminal Q of the latch circuit 22 _m-1 of the previous stage (here, m is an integer of 2 or more and M or less). The input terminal D of the latch circuit 22 ₁ of the first stage inputs the data of the M bit row_sel1_data[M:1] in series. Each latch circuit 22 _m by synchronizing with the clock row_sel1_clk operation, the data can be maintained row_sel1_data [m]. Each latch circuit 22 _m of the data held row_sel1_data [m] to the control signal generating circuit corresponding to the supplied 23 _m, 33 _m Qieyi supplied to the control signal generating circuit.

The first column selection unit 20 supplies the vshift1(0) signal, the clock VCLK1, the basic control signal 1, and the M-bit data row_sel1_data[M:1] to the clock_sel1_clk from the control unit 60A.

Each of the M control signal generating circuits 33 ₁ to 33 _M included in the second column selecting unit 30 has a common configuration and is connected in cascade. That is, each control signal generating circuit of the input terminal I 33 _m is connected to the front stage of the control signal generating circuit 33 _m-1 of the output terminal O (where, m is an integer of 2 or more and M or less each of). The input terminal I of the first stage control signal generating circuit 33 ₁ is input to a vshift2(0) signal whose timing indicated by the clock VCLK2 is a high level and then is a low level. Each control signal generating circuit 33 _m with the clock line VCLK2 embodiment operates in synchronization, basic control input signal 2, when the data corresponding to 32 _m by the latch circuit holding the row_sel2_data [m] is at a high time, in particular the timing of the The Reset2 (m) signal, the Trans2 (m) signal, the Hold 2 (m) signal, and the Address 2 (m) signal are output as high levels.

Each of the M latch circuits 32 ₁ to 32 _M is a D flip-flop and is connected in cascade. That is, the input terminal D of each latch circuit 32 _m is connected to the output terminal Q of the latch circuit 32 _m-1 of the previous stage (where m is an integer of 2 or more and M or less). The input terminal D of the latch circuit 32 ₁ of the first stage inputs the data of the M bit row_sel2_data[M:1] in series. Each of the latch circuits 32 _m can hold the data row_sel2_data[m] by performing an action in synchronization with the clock row_sel2_clk. Each data latch circuit 32 holding the row_sel2_data The _m [m] _m is supplied to the control signal generating circuit 33 corresponding to the, Qieyi supplied to the control signal generating circuit 23 _m.

The second column selecting unit 30 supplies the vshift2(0) signal, the clock VCLK2, the basic control signal 2, the M bit data row_sel2_data[M:1] and the clock pulse row_sel2_clk from the control unit 60A.

FIG 14 represents a system configuration of FIG 23 _m 2 of the first column selecting unit solid-state imaging device of the second embodiment of the control signal generating circuit 20A. Each control signal generating circuit 23 _m includes a D flip-flop 210, a logic inversion circuit 211, logic product circuits 212 to 217, logic sum circuits 218 and 219, a logic product circuit 221, logic inversion circuits 222 and 223, and a logic product circuit. 224, 225 and logic sum circuit 226. Each of the control signal generating circuits 23 _m inputs the All_reset1 signal, the Reset1 signal, the Trans1 signal, the Hold1 signal, the Address1 signal, and the Reset_sel signal as the basic control signal 1 illustrated in FIG.

21 _m compared with the configuration of FIG. 1 shown in the first form of embodiment 6 control signal generating circuit 14 shown in the embodiment of the second aspect of the control signal generating circuit in FIG. 23 _m further includes a logic inversion circuit 223, the logic The aspects of the product circuits 224, 225 and the logic sum circuit 226 are different.

The logical product circuit 224 of each control signal generating circuit 23 _m inputs the data of the data row_sel2_data[m] outputted from the latch circuit 32 _m corresponding to the second column selecting unit 30A by the logic inverting circuit 222, and The Reset_sel signal is also input and the data of the logical products are output.

The logic product circuit 225 of each control signal generating circuit 23 _m is input from the data row_sel1_data[m] output from the corresponding latch circuit 22 _m , and also outputs the data of the logic inversion signal of the Reset_sel signal by the logic inversion circuit 223, and outputs Information on the logical product of these.

Each control signal generating circuit 23 _m and the logic sum circuit 226 outputs information input AND circuit 224, the input-output Qieyi information of the logical product circuit 225, and outputs a logic sum of these data. That is, the logic sum circuit 226 outputs the logical inversion data of the data row_sel2_data[m] when the Reset_sel signal is high, and outputs the data row_sel1_data[m] when the Reset_sel signal is low.

The logical product circuit 214 of each control signal generating circuit 23 _m inputs the output data of the logical sum circuit 226, and also inputs the data of the Reset1 signal, and outputs the data of the logical products as the Reset1 (m) signal.

The logical product circuit 215 of each control signal generating circuit 23 _m inputs the output data of the logical sum circuit 226, and also inputs the data of the Trans1 signal, and outputs the data of the logical products as the Trans1 (m) signal.

15 are diagrams showing the configuration of 33 _m 2 of the second column selection control unit 30A of the signal of the second embodiment of the solid-state imaging device generating circuit. Each control signal generating circuit 33 _m includes a D flip-flop 310, a logic inversion circuit 311, logic product circuits 312 to 317, logic sum circuits 318 and 319, a logic product circuit 321, logic inversion circuits 322 and 323, and a logic product circuit. 324, 325 and logic sum circuit 326. Each control signal generating circuit 33 _m All_reset2 input signal, Reset2 signal, Trans2 signal, Hold2 signal, Address2 signal and Reset_sel signal as illustrated in FIG. 13 of the basic control signal 2.

31 _m compared with the configuration of FIG. 1 shown in the first embodiment of the seventh aspect of the control signal generating circuit of the second control signal generating circuit 15 shown in FIG. 33 _m the form of embodiment in FIG. 322, 323 further includes a logic inversion circuit The logical product circuits 324, 325 and the logical sum circuit 326 are different in aspect.

The logical product circuit 324 of each control signal generating circuit 33 _m inputs the data row_sel1_data[m] output from the latch circuit 22 _m corresponding to the corresponding column selecting unit 20A, and the logic inverting circuit 322 performs logical inversion data, and The Reset_sel signal is also input and the data of the logical products are output.

The logic product circuit 325 of each control signal generating circuit 33 _m inputs the data row_sel2_data[m] output from the corresponding latch circuit 32 _m , and also inputs the data of the logic inversion by the logic inversion circuit 323 of the Reset_sel signal, and outputs the data. Information on the logical product of these.

Information output logic 33 _m of the respective control signal generating circuit and the input circuit 326 the logical product circuit 324, the output data Qieyi input of the logical product circuit 325, and outputs a logic sum of these data. That is, the logic sum circuit 326 outputs the logical inversion data of the data row_sel1_data[m] when the Reset_sel signal is high, and outputs the data row_sel2_data[m] when the Reset_sel signal is low.

Each control signal generating logic circuit 33 _m outputs the data input AND circuit 314 and the logic circuit 326, the signal Reset2 Qieyi input data, the logical product of the data such as Reset2 and (m) signal outputs.

Output data of 33 _m each control signal generating circuit 315 inputs a logical product circuit and a logic circuit 326, the Trans2 Qieyi input data signals, and the logical product of the data such as Trans2 (m) signal outputs.

The first column selecting unit 20A and the second column selecting unit 30A having the configuration shown in FIGS. 13 to 15 can be one of the high level and the low level according to the Reset_sel signal, and which one is assumed to be applied to the light receiving unit 10 Each of the pixel portions P _m3,n in the m3th column outputs a control signal to discharge the junction capacitance portion of the photodiode PD.

When the Reset_sel signal is at the high level, the first column selection unit 20A of the second embodiment has the same function as the first column selection unit 20 of the first embodiment, and the second column selection unit 30A of the second embodiment has the first The second column selection unit 30 of the embodiment has the same function. In other words, the first column selecting unit 20A has a function of discharging the junction capacitance portion of the photodiode PD by outputting a control signal to each of the pixel portions P _m3,n in the m3th column of the light receiving portion 10. Therefore, in this case, the solid-state imaging device 2 of the second embodiment can be operated in the same manner as the solid-state imaging device 1 of the first embodiment.

On the other hand, when the Reset_sel signal is at the low level, the second column selecting unit 30A has a control signal for outputting the control signal to each of the pixel portions Pm3, n of the m3th column of the light receiving unit 10 _, thereby connecting the capacitance portion of the photodiode PD. The function of discharge. In addition to this point, the solid-state imaging device 2 of the second embodiment can be operated in the same manner as the solid-state imaging device 1 of the first embodiment.

(Third embodiment)

Next, a third embodiment will be described. In the solid-state imaging device 1 of the first embodiment and the solid-state imaging device 2 of the second embodiment, the discharge capacitance portion of the photodiode PD of each pixel portion P _{m3,n in} the m3th column is the first Column selection unit or second column selection unit. On the other hand, in the solid-state imaging device 3 of the third embodiment, the junction capacitance portion of the photodiode PD is output by outputting a control signal to each of the pixel portions P _{m3 and n} of the m3th column of the light receiving unit 10 . The third column selection section of the discharge. As described above, instead of the first column selection unit or the second column selection unit, the third column selection unit can discharge the junction capacitance portion of the photodiode PD of each of the pixel portions P _{m3 and n} of the m3th column.

FIG. 16 is a view showing a schematic configuration of a solid-state imaging device 3 according to the third embodiment. Compared with the schematic configuration of the solid-state imaging device 1 of the first embodiment shown in FIG. 1, the solid-state imaging device 3 of the third embodiment shown in FIG. 16 differs in that the third column selection unit 70 is further included. The light receiving unit 10, the first column selecting unit 20, the second column selecting unit 30, the first reading unit 40, the second reading unit 50, and the control unit 60 are the same as those of the first embodiment and the second embodiment.

The third column selecting unit 70 selects any m3th column of the light receiving unit 10 instead of the first column selecting unit 20 or the second column selecting unit in the first embodiment and the second embodiment, and selects each pixel of the m3th column. The portion P _m3,n outputs a control signal, thereby discharging the junction capacitance portion of the photodiode, and storing the charge generated in the photodiode in the charge storage portion.

Here, m1 and m2 are integers of 1 or more and M or less and different from each other. M3 is an integer of 1 or more and M or less. The first column selection unit 20 and the second column selection unit 30 select the columns different from each other in the light receiving unit 10 . The number of columns selected by each of the first column selection unit 20 and the second column selection unit 30 is arbitrary, but the output of the data is sequentially performed column by column. The number of columns selected by the third column selection unit 70 is also arbitrary.

The control unit 60 controls the solid-state imaging by controlling the operations of the first column selection unit 20, the second column selection unit 30, the third column selection unit 70, the first reading unit 40, and the second reading unit 50. The overall operation of the device 3. The first column selection unit 20 and the first reading unit 40, and the second column selection unit 30 and the second reading unit 50 can be operated in parallel with each other by the control unit 60.

Fig. 17 is a view showing the configuration of the first reading unit 40 and the second reading unit 50 of the solid-state imaging device 3 according to the third embodiment, similarly to Fig. 2 . The description of Fig. 17 is omitted because it is the same as that of Fig. 2 described above.

FIG. 18 is a view showing a circuit configuration of the pixel portion P _m,n and the holding portion 41 _n of the solid-state imaging device 3 according to the third embodiment, similarly to FIG. 3 . The description of Fig. 18 is omitted because it is the same as that of Fig. 3 described above.

In addition, in FIG. 18, the Reset (m) signal is a Reset1 (m) signal output from the first column selecting unit 20, a Reset 2 (m) signal output from the second column selecting unit 30, and a selection from the third column. The logical sum of the Reset3(m) signals output by the unit 70. Further, the Trans(m) signal is a Trans1 (m) signal output from the first column selecting unit 20, a Trans2 (m) signal output from the second column selecting unit 30, and a Trans3 outputted from the third column selecting unit 70 ( m) The logical sum of the signals.

FIG. 19 is a view showing the configuration of the first column selection unit 20, the second column selection unit 30, and the third column selection unit 70 of the solid-state imaging device 3 according to the third embodiment. The description of the first column selection unit 20 and the second column selection unit 30 is omitted since it is the same as that of the above-described FIG. 5 . The third column selecting unit 70 includes M latch circuits 72 ₁ to 72 _M constituting the shift register, M logical product circuits 73 ₁ to 73 _M , and M logical product circuits 74 ₁ to 74 _M .

Each of the M latch circuits 72 ₁ to 72 _M included in the third column selecting unit 70 is a D flip-flop and is connected in cascade. That is, each latch circuit input terminal D 72 _m is connected to the front stage of the latch circuit an output terminal of Q 72 _m-1 (where, m is integers of 2 or more and M or less). The input terminal D of the latch circuit 72 ₁ of the first stage inputs the data of the M bit row_sel3_data[M:1] in series. Each of the latch circuits 72 _m can hold the data row_sel3_data[m] by performing an action in synchronization with the clock row_sel3_clk.

Each of the logical product circuits 73 _m included in the third column selecting unit 70 receives the data row_sel3_data[m] output from the latch circuit 72 _m , and also inputs the data of the Trans3 signal, and uses the data of the logical products as Trans3. (m) and output. Each input logical product circuit 74 _m 72 _m from the latch circuit outputs the data row_sel3_data [m], Qieyi RESET3 input information signals, and a logical product of the data such as Reset3 (m) is output.

The third column selection unit 70 supplies the Trans3 signal, the Reset3 signal, and the M-bit data row_sel3_data[M:1] and the pulse_row3_clk from the control unit 60.

Information in the _M, the m3-th latch circuit 72 _m3 M latch circuits 72 ₁ to 72 retained in the third column selecting section 70 row_sel3_data [m3] is at a high time, may each pixel unit P _m3 the first m3 column of _{, n} outputs the control signal (Reset3 (m3) signal, Trans3 (m3) signal) as a high level at a specific timing.

FIG. 20 is a view showing a configuration of a control signal generating circuit 21 _m of the first column selecting unit 20 of the solid-state imaging device 3 according to the third embodiment, similarly to FIG. 6 . In Fig. 20, the configuration of Fig. 6 is different in that each control signal generating circuit _21m does not include the logic inverting circuit 222. That is, as shown below, the inputs of the logical product circuits 214, 215 are different. The description of the other configurations is omitted since it is the same as the description of FIG. 6 described above.

The logic product circuit 214 of each control signal generating circuit 21 _m inputs the data row_sel1_data[m] output from the corresponding latch circuit 22 _m , and also inputs the data of the Reset1 signal, and uses the data of the logical products as Reset1 (m). ) Signal and output.

The logical product circuit 215 of each control signal generating circuit 21 _m inputs the data row_sel1_data[m] output from the corresponding latch circuit 22 _m , and also inputs the data of the Trans1 signal, and uses the data of the logical products as Trans1 (m). ) Signal and output.

As described above, the data row_sel1_data[m1] is set to a high level in accordance with the m1th column to be selected by the first column selecting unit 20. The data row_sel2_data[m2] is set to a high level in accordance with the m2th column to be selected by the second column selecting unit 30. Further, the data row_sel3_data[m3] is set to a high level in accordance with the m3th column to be selected by the third column selecting unit 70. In order to make the m1th column selected by the first column selecting unit 20 and the m2th column selected by the second column selecting unit 30 different from each other, the data row_sel1_data[m] and the data row_sel2_data[m] must be different for each m value. High level, at least one of which is low.

Further, as aforesaid, the first column selecting section 20 to the data M latch circuits 22 ₁ ~ 22 _M in the m1-th latch circuit 22 is _m1 held the row_sel1_data [m1] is at a high time, can m1-th row of Each of the pixel portions P _m1,n outputs a Reset1 (m1) signal, a Trans1 (m1) signal, a Hold1 (m1) signal, and Address 1 (m1) at a specific level as a high level. When the data row_sel2_data[m2] held by the m2th latch circuit 32 _m2 among the M latch circuits 32 ₁ to 32 _M is at a high level, the second column selecting unit 30 can be used for each pixel portion P _{m2 of the} m2th column. _{, n} outputs the Reset2 (m2) signal, the Trans2 (m2) signal, the Hold2 (m2) signal, and the Address 2 (m2) signal as a high level at a specific timing. Further, information on the first m3 latch circuit _M in the 72 _m3 M latch circuits 72 ₁ to 72 retained in the third column selecting section 70 row_sel3_data [m3] is at a high time, may each pixel unit of the m3-th column of P _m3,n outputs the Reset3 (m3) signal and the Trans3 (m3) signal as a high level at a specific timing.

Next, an embodiment (Figs. 8 and 21) of the operation of the solid-state imaging device 3 according to the third embodiment will be described in comparison with the above-described comparative example (Figs. 8 and 9). Also set in this embodiment is M=N=8.

In the case of the operation of the embodiment, the pixel portion of the light receiving unit 10 that reads data by each of the first reading unit 40 and the second reading unit 50 is the same as that shown in FIG. However, in the embodiment, the third column selecting unit 70 reads out the pixel portions of the fourth column of the light receiving unit 10 of the data by the first column selecting unit and the first reading unit after time t. The junction capacitance portion of the photodiode PD is initialized at a timing before the data readout period of the first readout portion is advanced from the time t. Thereby, the data of each pixel portion of the fourth column of the light receiving unit 10 is read at a fixed time interval after the initialization immediately before the time t.

Fig. 21 is a timing chart showing the operation of the embodiment. In FIG. 21, the operation of the pixel portion of the eighth column to the first column in the light receiving portion 10 and the data input operation of the holding portion 41 of the first reading portion 40 are sequentially shown from the top to the bottom. The data output operation of the reading unit 40, the data input operation of the holding unit 51 of the second reading unit 50, and the data output operation from the second reading unit 50 are performed. The "turn 1", "turn 2", "initialize" and "storage" in Fig. 21 are the same as those in Fig. 9, respectively.

As shown in the figure, in the embodiment, the communication data of each of the pixel portion P _{4, 4} and the pixel portion P _{4, 5 which} are first read by the first reading unit 40 after the time t is equivalent to before the time t. The amount of charge stored during the same period as after time t. Therefore, the optical signal from the optical signal source can be correctly received. As described above, the solid-state imaging device 1 of the present embodiment can accurately receive the optical signal from the optical signal source even when the position of the optical signal source is tracked.

On the other hand, in this embodiment, the image data of each of the second column pixel portions P _{2, 3} to P _{2, 6 which} are first read by the second reading unit 50 after the time t is equivalent to The amount of charge that was last stored in the period longer than the original time before time t, and thus there is a case where the value is an error. Further, the image data of the pixel portions P _{5, 3} to P _{5, 6} of the fifth column which are first read by the second reading unit 50 after the time t are equivalent to being shorter than the time before the time t. The amount of charge stored during the period is therefore a case of a wrong value. However, since the information is not the communication data and is the image data, there is no problem even if the data is incorrect, or because the error data can be interpolated using the data of the adjacent column, it will not become a larger one. problem.

Further, the solid-state imaging device 3 according to the third embodiment can be operated in various aspects. For example, the first column selecting unit 20 may select the odd-numbered columns in the light receiving unit 10, and the second column selecting unit 30 may select the even-numbered columns in the light receiving unit 10. In this case, the position of the optical signal source is specified based on the image data of the even-numbered columns read by the second column selecting unit 30 and the second reading unit 50, and the first column selecting unit 20 and The first reading unit 40 reads data of a pixel portion from an arbitrary odd-numbered column located at a specific position in the image as communication data. In this case, the third column selecting unit 70 initializes the junction capacitance portion of the photodiode PD of each pixel portion of the m3th column to which the data is newly read before the start of reading.

Further, the solid-state imaging device 3 of the third embodiment can also perform operations as shown in FIGS. 22 and 23.

FIG. 22 is a view for explaining a pixel portion of the light receiving unit 10 in which data is read by each of the first reading unit 40 and the second reading unit 50 in the case of the operation of another embodiment. In this embodiment, before a certain time t ₁ , as shown in FIG. 22( a ), the communication data of each of the pixel portion P _{5 , 3} and the pixel portion P _{5 , 4 of} the light receiving unit 10 is selected by the first column. Reading with the first reading unit (region A in FIG. 22(a)), the communication data of each of the pixel portion _{P6, 6} and the pixel portion _{P6, 7 of} the light receiving unit 10 is selected by the second column selection unit and The second reading unit reads (region B in Fig. 22(a)).

From the time t ₁ to time t _2, as shown in FIG 22 (b), the pixel portion and the pixel portions P _4,2 P _4,3 respective data communication by the light receiving section 10 of the second column selecting section 1 The reading unit reads (region A in FIG. 22(b)), and the communication data of each of the pixel portion P _6,6 and the pixel portion P _{6,7 of} the light receiving unit 10 is selected by the second column and the second reading. Read out and output (area B in Fig. 22(b)). Further, since at time t _2, FIG. 22 (c), the light receiving portion 10 of the pixel portions P _4,2 P _4,3 and the pixel unit by respective communication data selection unit reads the first column and the second one The portion is read (region A in FIG. 22(c)), and the communication data of each of the pixel portion P _7,6 and the pixel portion P _{7,7 of} the light receiving portion 10 is selected by the second column selection portion and the second reading portion. And read out (area B in Fig. 22(c)).

That is, in this embodiment, there are two optical signal sources that can move independently of each other, and the data of the optical signals from one optical signal source is read by the first column selection unit and the first reading unit, and The data of the optical signal of an optical signal source is read by the second column selection unit and the second reading unit.

Figure 23 is a timing diagram of the operation of another embodiment. In FIG. 23, the operation of the pixel portion of each of the eighth to the first columns of the light receiving unit 10 and the data input operation of the holding unit 41 of the first reading unit 40 are sequentially shown from the top to the bottom. The data output operation of the reading unit 40, the data input operation of the holding unit 51 of the second reading unit 50, and the data output operation from the second reading unit 50 are performed. The "turn 1", "turn 2", "initialize" and "storage" in Fig. 23 are the same as those in Fig. 9, respectively. As shown in the figure, the data reading of the first reading unit and the data reading of the second reading unit are the same, but the phases are different.

The data read by the first column selecting unit and the first reading unit changes at the time t ₁ as a boundary, and the pixel portion P _{4, 2 which} is first read by the first reading unit after the time t ₁ The communication data of each of the pixel portions P _{4, 3} corresponds to the amount of charge stored in the same period as after the time t ₁ before the time t ₁ . Further, by the second column selection section and the second readout unit reads out the data column ₂ to the time t changes as a boundary, at time t ₂ after the first pixel portion by the second readout unit reads out the P ₇ The communication data of each of ₆ and the pixel portions P _{7, 7} corresponds to the amount of charge stored in the same period as after time t ₂ before time t ₂ . Therefore, optical signals from two optical signal sources can be correctly received. As described above, the solid-state imaging device 1 of the present embodiment can accurately receive the optical signals from the respective optical signal sources even when the positions of the two optical signal sources are tracked.

Industrial availability

In the solid-state imaging device for optical communication, it can be used for the purpose of correctly receiving an optical signal from an optical signal source even when tracking the position of the optical signal source.

1, 2, 3. . . Solid state camera

10. . . Light receiving department

20, 20A. . . Column 1 selection

21 ₁ ~ 21 _M . . . Control signal generation circuit

22 ₁ ~ 22 _M . . . Latch circuit

23 ₁ ~ 23 _M . . . Control signal generation circuit

30, 30A. . . Column 2 selection

31 ₁ ~ 31 _M . . . Control signal generation circuit

32 ₁ ~ 32 _M . . . Latch circuit

33 ₁ ~ 33 _M . . . Control signal generation circuit

40. . . First reading unit

41 ₁ ~41 _N . . . Holding department

42. . . Column 1 selection

43. . . Difference calculation unit

50. . . Second reading unit

51 ₁ ~ 51 _N . . . Holding department

52. . . Column 1 selection

53. . . Difference calculation unit

60, 60A. . . Control department

70. . . Column 3 selection

72 ₁ ~ 72 _M . . . Latch circuit

L1 ₁ ~ L1 _N , L2 ₁ ~ L2 _N . . . Readout signal line

LT ₁ ~LT _M , LR ₁ ~LR _M , LH ₁ ~LH _M , LA1 ₁ ~LA1 _M , LA2 ₁ ~LA2 _M . . . Control signal line

P _1,1 ~P _M,N . . . Pixel section

FIG. 1 is a view showing a schematic configuration of a solid-state imaging device 1 according to the first embodiment.

FIG. 2 is a view showing the configuration of the first reading unit 40 and the second reading unit 50 of the solid-state imaging device 1 according to the first embodiment.

FIG. 3 is a view showing a circuit configuration of the pixel portion P _m,n and the holding portion 41 _n of the solid-state imaging device 1 according to the first embodiment.

FIG. 4 is a view showing a circuit configuration of the difference calculation unit 43 of the solid-state imaging device 1 according to the first embodiment.

FIG. 5 is a view showing a configuration of the first column selection unit 20 and the second column selection unit 30 of the solid-state imaging device 1 according to the first embodiment.

FIG. 6 is a view showing a configuration of a control signal generating circuit 21 _m of the first column selecting unit 20 of the solid-state imaging device 1 according to the first embodiment.

FIG. 7 is a view showing a configuration of a control signal generating circuit 31 _m of the second column selecting unit 30 of the solid-state imaging device 1 according to the first embodiment.

(a) and (b) of FIG. 8 are views showing a pixel portion of the light receiving unit 10 in which data is read by each of the first reading unit 40 and the second reading unit 50 in the case of the operation of the comparative example.

Fig. 9 is a timing chart showing the operation of the comparative example.

FIGS. 10(a) and 10(b) are views showing a pixel portion of the light receiving unit 10 in which data is read by each of the first reading unit 40 and the second reading unit 50 in the case of the operation of the embodiment.

Fig. 11 is a timing chart showing the operation of the embodiment.

FIG. 12 is a view showing a schematic configuration of the solid-state imaging device 2 according to the second embodiment.

FIG. 13 is a view showing the configuration of the first column selection unit 20A and the second column selection unit 30A of the solid-state imaging device 2 according to the second embodiment.

FIG 14 represents a system configuration of FIG 23 _m 2 of the first column selecting unit solid-state imaging device of the second embodiment of the control signal generating circuit 20A.

15 are diagrams showing the configuration of 33 _m 2 of the second column selection control unit 30A of the signal of the second embodiment of the solid-state imaging device generating circuit.

FIG. 16 is a view showing a schematic configuration of a solid-state imaging device 3 according to the third embodiment.

FIG. 17 is a view showing the configuration of the first reading unit 40 and the second reading unit 50 of the solid-state imaging device 3 according to the third embodiment.

FIG. 18 is a view showing a circuit configuration of the pixel portion P _m,n and the holding portion 41 _n of the solid-state imaging device 3 according to the third embodiment.

FIG. 19 is a view showing a configuration of the first column selection unit 20, the second column selection unit 30, and the third column selection unit 70 of the solid-state imaging device 3 according to the third embodiment.

FIG. 20 is a view showing a configuration of a control signal generating circuit 21 _m of the first column selecting unit 20 of the solid-state imaging device 3 according to the third embodiment.

Fig. 21 is a timing chart showing the operation of the embodiment.

22(a) to (c) illustrate the pixel portion of the light receiving unit 10 in which data is read by each of the first reading unit 40 and the second reading unit 50 in the case of the operation of another embodiment. Figure.

Figure 23 is a timing diagram of the operation of another embodiment.

1. . . Solid state camera

10. . . Light receiving department

20. . . Column 1 selection

30. . . Column 2 selection

40. . . First reading unit

50. . . Second reading unit

60. . . Control department

L1 ₁ ~ L1 _N , L2 ₁ ~ L2 _N . . . Readout signal line

P _1,1 ~P _M,N . . . Pixel section

Claims (10)

A solid-state imaging device comprising: a light receiving unit that two-dimensionally arranges M×N pixel portions P _1,1 to P _M,N in M rows and N rows _, and the pixel portion P _1,1 to P _M Each of _N includes a photodiode that generates a charge corresponding to the amount of incident light, a charge storage portion that stores the charge, a first switch that outputs data corresponding to the amount of stored charge in the charge storage portion, and a second switch that outputs data corresponding to the amount of stored charge in the charge storage unit; and a first column selection unit that selects any m1th column of the light receiving unit, and selects each pixel portion P _{m1 of} the m1 column _{And n} outputting a control signal to discharge the junction capacitance portion of the photodiode, storing the charge generated in the photodiode in the charge storage portion, and closing the first switch to correspond to The data of the stored charge amount in the charge storage unit is output to the read signal line L1 _n , and the second column selection unit selects any m2th column different from the m1th column among the light receiving units, and selects the m2th column. each of the pixel portion P _{m2, n} outputs a control signal, whereby the above-described photodiode Discharging the junction capacitance portion of the body, storing the charge generated in the photodiode in the charge storage portion, and reading the data corresponding to the stored charge amount in the charge storage portion by turning off the second switch The output signal line L2 _{n is} output; the first readout unit is connected to the N read signal lines L1 ₁ to L1 _N and is input from the m1th column of the light receiving units selected by the first column selecting unit. Each of the pixel portions P _m1,n outputs data to the read signal line L1 _{n and} outputs data corresponding to the amount of charge generated in the photodiode of each pixel portion P _m1,n of the m1th column; The second reading unit is connected to the N read signal lines L2 ₁ to L2 _N and is input to each of the pixel portions P _{m2 and n} of the m2th column among the light receiving units selected by the second column selecting unit _. And outputting the data to the read signal line L2 _{n and} outputting data corresponding to the amount of charge generated in the photodiode of each pixel portion P _m2,n of the m2th column; and selecting any of the light receiving portions In the m3th column, a control signal is outputted to each of the pixel portions _{Pm3, n of} the m3th column, thereby connecting the photodiode The combined capacitance portion is discharged; the first column selection unit and the first reading unit are operated in parallel with the second column selection unit and the second reading unit (where M and N are integers of 2 or more, m1 M2 is an integer of 1 or more and M or less, and m3 is an integer of 1 or more and M or less, and n is an integer of 1 or more and N or less. The solid-state imaging device according to claim 1, wherein the first column selection unit or the second column selection unit selects an arbitrary m3th column different from the m1th column and the m2th column among the light receiving units, and the m3th column is selected Each of the pixel portions P _m3,n outputs a control signal, thereby discharging the junction capacitance portion of the photodiode (where m1, m2, and m3 are 1 or more and M or less and different from each other). The solid-state imaging device according to claim 2, further comprising a switching mechanism that switches the first column selection unit and the second column selection unit to each pixel portion P of the m3th column of the light receiving unit _{M3, n} outputs a control signal, and the column selection unit that discharges the junction capacitance portion of the photodiode is any one of the first column selection unit and the second column selection unit. The solid-state imaging device according to claim 2, wherein the first column selection unit includes M latch circuits, and when the data held in the m1th latch circuit is an effective value, each pixel portion P of the m1th column is used. M1 _{, n} output the control signal; the second column selection unit includes M latch circuits, and when the data held in the m2th latch circuit is an effective value, for each pixel portion P _m2 of the m2th column _{, n} outputting the control signal; any one of the first column selection unit and the second column selection unit holding the data in the m3 latch circuit of the M latch circuits of the other column selection unit is non- In the case of an effective value, the control signal is outputted to each of the pixel portions P _m3,n of the m3th column. The solid-state imaging device according to claim 4, wherein the M latch circuits of the first column selection unit and the second column selection unit are cascade-connected in a column order to form a shift register, and the M bit is formed by The data is serially input to the latch circuit of the initial stage in the shift register, and the data is held by each latch circuit. The solid-state imaging device according to claim 4, wherein the first column selecting unit sequentially outputs the plurality of columns corresponding to the latch circuits in which the data is held in the M latch circuits included therein, at a fixed time interval. a control signal; the second column selecting unit sequentially outputs the control signal at a fixed time interval for the plurality of columns corresponding to the latch circuits in which the data is held in the M latch circuits included therein. The solid-state imaging device according to claim 1, further comprising: a third column selecting unit that selects any m3th column of the light receiving unit and outputs the pixel portion P _{m3, n of} the m3th column The signal is controlled to discharge the junction capacitance portion of the photodiode. The solid-state imaging device according to claim 7, wherein the first column selection unit includes M latch circuits, and when the data held in the m1th latch circuit is an effective value, each pixel portion P of the m1th column is used. M1 _{, n} output the control signal; the second column selection unit includes M latch circuits, and when the data held in the m2th latch circuit is an effective value, for each pixel portion P _m2 of the m2th column _{, n} outputting the control signal; the third column selection unit includes M latch circuits, and when the data held in the m3th latch circuit is an effective value, the pixel portions P _{m3, n} of the m3th column are output. The above control signal. The solid-state imaging device according to claim 8, wherein the M latch circuits of the first column selection unit, the second column selection unit, and the third column selection unit are cascade-connected in a column order to form a shift register. The data is held by each latch circuit by serially inputting the M bit data into the latch circuit of the initial stage in the shift register. The solid-state imaging device according to claim 8, wherein the first column selection unit sequentially outputs the plurality of columns corresponding to the latch circuits in which the data is held in the M latch circuits included therein, at a fixed time interval. a control signal; the second column selecting unit sequentially outputs the control signal at a fixed time interval for the plurality of columns corresponding to the latch circuits in which the data is held in the M latch circuits included therein.