JP5426587B2 - Solid-state imaging device and pixel averaging processing method thereof - Google Patents

Description

  Embodiments of the present invention relate to a solid-state imaging device such as a CMOS image sensor and a pixel averaging method thereof, and are applied to, for example, a mobile phone with an image sensor, a digital camera, and a video camera.

  CMOS image sensors are used in mobile phones with image sensors, digital cameras, video cameras, and the like. In this type of CMOS image sensor, a noise reduction processing operation (referred to as a CDS: Correlated Double Sampling operation) is performed during analog / digital conversion of the read signal charges. Also, the AD converter has a two-stage configuration in order to perform highly accurate AD conversion. As the vertical line selection circuit, a shift register circuit or a decoder circuit is generally used (see, for example, Patent Document 1).

  By the way, in the CMOS image sensor as described above, in order to average the same color, a thinning operation is performed in which two lines of pixels arranged in the vertical direction are read and two lines are skipped. However, when such a thinning operation is performed, the sampling point of the G signal (Gr signal and Gb signal) for generating the luminance signal becomes discontinuous in the color sensor with the Bayer arrangement, and the image quality deteriorates due to the false signal.

  As a countermeasure against image quality degradation due to this false signal, Patent Document 2 proposes a technique for averaging vertical signals using capacitors. However, the addition of capacitors increases the pattern occupying area, and corresponds to each capacitor. The power consumption increases depending on the buffer circuit provided.

  Therefore, there is a demand for a solid-state imaging device and its pixel averaging processing method that can prevent image quality deterioration due to false signals without increasing the pattern occupation area and power consumption.

Japanese Patent No. 3361005 JP 09-247535 A

  According to the present embodiment, a solid-state imaging device and its pixel averaging processing method that can prevent image quality degradation due to a false signal without increasing the pattern occupation area and power consumption are provided.

A solid-state imaging device according to one embodiment of the present invention converts a light signal into a signal charge on a semiconductor substrate, stores the signal charge, and reads out the charge accumulated in the photoelectric conversion means to a detection unit. An image pickup region in which pixels having a means, an amplifying means for outputting a signal corresponding to the charge amount of the detection section, and a reset means for resetting the charge of the detection section are two-dimensionally arranged in rows and columns And between the vertical signal lines so as to short-circuit between the vertical signal line from which the output of the amplifying means of each pixel column in the imaging region is read and the vertical signal line of each pixel column by one or more switching transistors connect the plurality of switches adding means provided by commonly connected control signal line to the gate of each transistor of the plurality of switches adding means, the switch adder means Comprising the addition control means for controlling simultaneously, and a column signal processing means for signal processing for each column the signal added by said switch adding means.

According to one aspect of the present invention, there is provided a pixel averaging method for a solid-state imaging device, which converts an optical signal into a signal charge on a semiconductor substrate, stores the signal charge, and stores the charge stored in the photoelectric conversion unit. A pixel including a reading unit that reads out to the detection unit, an amplification unit that outputs a signal corresponding to the charge amount of the detection unit, and a reset unit that resets the charge of the detection unit is two-dimensionally arranged in rows and columns. In order to short-circuit between the arranged imaging region, the vertical signal line from which the output of the amplifying unit of each pixel column in the imaging region is read, and one or more switching transistors between the vertical signal lines, a plurality of switches adding means provided to connect between the between the vertical signal line, the common connected control signal line to the gate of each transistor of the plurality of switches adding means Ri, and addition control means for simultaneously controlling the switching addition unit, wherein a pixel averaging processing method of the solid-state imaging device and a column signal processing means for signal processing for each column the signal added by switching addition means And a step of operating two or more lines of the amplifying means in the pixel row of the imaging region in parallel and a step of operating a switch adding means for connecting the vertical signal lines of the respective pixel columns. .

1 is a circuit diagram illustrating a configuration example of an amplification type CMOS image sensor, for explaining a solid-state imaging device and a pixel averaging processing method thereof according to a first embodiment. FIG. FIG. 2 is a circuit diagram showing a configuration example of an in-block line selection circuit and a pulse selector circuit in the circuit shown in FIG. 1. 2 is a timing chart showing standard sensor operation timing in the circuit shown in FIG. 1. 2 is a timing chart showing operation timings for reducing the number of pixels in the circuit shown in FIG. FIG. 5 is a circuit diagram illustrating a configuration example of an amplifying CMOS image sensor for explaining a solid-state imaging device and a pixel averaging processing method thereof according to a second embodiment. FIG. 9 is a circuit diagram illustrating a configuration example of an amplifying CMOS image sensor for explaining a solid-state imaging device and a pixel averaging processing method thereof according to a third embodiment. FIG. 10 is a circuit diagram illustrating a configuration example of an amplifying CMOS image sensor for explaining a solid-state imaging device and a pixel averaging processing method thereof according to a fourth embodiment.

  Hereinafter, embodiments will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram illustrating a configuration example of an amplifying CMOS image sensor, for explaining a solid-state imaging device and a pixel averaging method thereof according to the first embodiment of the present invention. In the imaging region 11, unit cells 12-11, 12-12,..., 12-mn are arranged two-dimensionally in m rows and n columns. In FIG. 1, four rows and four columns in the imaging area 11 are extracted and shown in detail. The imaging area 11 is divided into a plurality of blocks in the vertical direction. Vertical signal lines VLIN1, VLIN2, VLIN3,... Are connected to each unit cell column in the imaging region 11, respectively.

  At one end (upper part) of the imaging region 11, load transistors TLM1, TLM2, TLM3,... For the source follower circuit are arranged in the horizontal direction. The current paths of these load transistors TLM1, TLM2, TLM3,... Are connected between one end of the vertical signal lines VLIN1, VLIN2, VLIN3,. A bias voltage VTL is applied from the bias circuit 21 (bias means) to the gates of the load transistors TLM1, TLM2, TLM3,. The load transistors TLM1, TLM2, TLM3,... And the bias circuit 21 function as load means. The bias circuit 21 includes resistors R1 to R3 and a changeover switch SW. The resistors R1 to R3 are connected in series between the power supply VDD and the ground point. The changeover switch SW selects the voltage (H) at the connection point of the resistors R1 and R2 or the voltage (L) at the connection point of the resistors R2 and R3 as the bias voltage VTL in response to the signal PMONI. As a result, the on-resistance (conducting resistance) of the load transistors TLM1, TLM2, TLM3,... Changes, and the amount of current flowing through the vertical signal lines VLIN1, VLINE2, VLINE3,.

  At the other end (lower part) of the vertical signal lines VLIN1, VLIN2, VLIN3,..., A column type noise cancel circuit and an analog / digital converter (CDS & ADC) 13, a latch circuit 14 for latching an analog / digital converted signal, a latch A line memory (10 Bit) 15 for storing the processed signal and a horizontal shift register circuit 16 for reading the signal of the line memory 15 are connected. The circuit unit 17 such as the latch circuit 14, the line memory 15, and the horizontal shift register circuit 16 functions as a holding unit that holds the digital data obtained by the CDS & ADC 13. The circuit unit 17 and the CDS & ADC 13 function as storage means.

  Adjacent to the imaging region 11, a vertical block selection circuit (vertical block selection means) 18, an intra-block line selection circuit (in-block line selection means) 19, and a pulse selector circuit (pulse selector means) 20 are provided. The pulse signal ADRES1, ADRES2,..., The pulse signals RESET1, RESET2,... And the pulse signals READ1, READ2,.

  That is, the block in the imaging region 11 is selected by the block selection signals Vblock1 and Vblock2 output from the vertical block selection circuit 18. The vertical block selection circuit 18 is formed by a shift register circuit or a decoder circuit. The unit cell row (pixel row) in the block selected by the vertical block selection circuit 18 is selected by the in-block line selection circuit 19 based on the signals BLine1 to BLine4. A unit cell row is selected by the pulse selector circuit 20 based on the output signal of the intra-block line selection circuit 19 and the pixel drive pulse signals RESET, READ, ADRES.

  Each unit cell 12-11, 12-12,... Has four transistors (row selection transistor Ta, amplification transistor Tb as amplification means, reset transistor Tc as reset means, read transistor Td as read means) and photo It is composed of a diode (photoelectric conversion means) PD. Taking the unit cell 12-11 as an example, the current paths of the transistors Ta and Tb are connected in series between the power supply VDD and the vertical signal line VLIN1. A pulse signal ADRES1 is supplied to the gate of the transistor Ta. The current path of the transistor Tc is connected between the power supply VDD and the gate (detector FD) of the transistor Tb, and a pulse signal RESET1 is supplied to the gate. One end of the current path of the transistor Td is connected to the detection unit FD, and a pulse signal (readout pulse) READ1 is supplied to its gate. The cathode of the photodiode PD is connected to the other end of the current path of the transistor Td, and the anode of the photodiode PD is grounded.

  In the CDS & ADC 13, noise canceller capacitors (capacitances) C11, C12, C13,... And C21, C22, C23,. , Transistors TS21, TS22, TS23,... For inputting a reference waveform for AD conversion, and two-stage comparator circuits COMP11, COMP12, COMP13,... And COMP21, COMP22, COMP23,. ... are arranged.

  One end of the current path of the transistors TS11, TS12, TS13,... Is connected to the vertical signal lines VLIN1, VLIN2, VLIN3,..., And a pulse signal S1 output from a timing generator (not shown) is supplied to the gate. .., And one electrode of capacitors C11, C12, C13,... And C21, C22, C23,... Are connected to the other ends of the current paths of the transistors TS11, TS12, TS13,. A reference voltage VREF (triangular wave) for comparison of the analog / digital converter (ADC) is supplied from the amplifier circuit AMP to the other electrodes of the capacitors C11, C12, C13,. The other electrodes of the capacitors C21, C22, C23,... Are connected to the input terminals of the comparator circuits COMP11, COMP12, COMP13,.

  Each of the comparator circuits COMP11, COMP12, COMP13,... Is an inverter INV11, INV12, INV13,. , TS22, TS23,... The comparator circuits COMP21, COMP22, COMP23,... Are transistors having inverters INV21, INV22, INV23,... And current paths connected between the input terminals and output terminals of the inverters INV21, INV22, INV23,. TS31, TS32, TS33,... Capacitors C31, C32, C33,... Are connected between the comparator circuits COMP11, COMP12, COMP13,... And COMP21, COMP22, COMP23,. The pulse signal S2 is supplied to the gates of the transistors TS21, TS22, TS23,..., And the pulse signal S3 is supplied to the gates of the transistors TS31, TS32, TS33,.

  Digital signals output from the comparator circuits COMP21, COMP22, COMP23,... Are latched by the latch circuit. The latch circuit 14 is connected to a line memory 15 and a horizontal shift register circuit 16 for reading the latched signal. Then, a 10-bit digital signal is output from the line memory 15.

  FIG. 2 is a circuit diagram showing a configuration example of the in-block line selection circuit 19 and the pulse selector circuit 20 in the circuit shown in FIG. 1, and shows a logical configuration for averaging two vertical lines. In this example, both the intra-block line selection circuit 19 and the pulse selector circuit 20 are realized by AND circuits. The in-block line selection circuit 19 includes AND gates 30-1 to 30-4. The signal Vblock1 output from the vertical block selection circuit 18 is supplied to one input terminal of the AND gates 30-1 to 30-4, and the signals BLine1 to BLine4 are supplied to the other input terminals. The output signals of these AND gates 30-1 to 30-4 are supplied to the pulse selector circuit 20.

  The intra-block line selection circuit 19 is 1 in one vertical block based on a vertical block selection signal Vblock1 output from the vertical block selection circuit 18 and signals BLine1 to BLine4 for setting the number of lines to be selected. A pixel row is selected, or a plurality of pixel rows are simultaneously selected in one vertical block. In the example shown in FIG. 2, one line or two lines of the block selected by the selection signal Vblock1 can be simultaneously selected according to the combination of the levels of the signals BLine1 to BLine4.

  The pulse selector circuit 20 includes AND gates 31-1 to 31-4, AND gates 32-1 to 32-4, and AND gates 33-1 to 33-4. An output signal of the AND gate 30-1 is supplied to one input terminal of each of the AND gates 31-1, 32-1, and 33-1, and pixel drive pulse signals ADRES, RESET, and READ are supplied to the other input terminal. The pulse signals ADRES1, RESET1, and READ1 are output. The output signal of the AND gate 30-2 is supplied to one input terminal of each of the AND gates 31-2, 32-2, and 33-2, and the pixel drive pulse signals ADRES, RESET, READ is input, and pulse signals ADRES2, RESET2, and READ2 are output. Further, the output signal of the AND gate 30-3 is supplied to one input terminal of each of the AND gates 31-3, 32-3, and 33-3, and the pixel drive pulse signals ADRES, RESET, READ is input, and pulse signals ADRES3, RESET3, and READ3 are output. Furthermore, the output signal of the AND gate 30-4 is supplied to one input terminal of each of the AND gates 31-4, 32-4, 33-4, and the pixel drive pulse signals ADRES, RESET are supplied to the other input terminal. , READ are input, and pulse signals ADRES4, RESET4, READ4 are output.

  FIG. 3 is a timing chart showing standard sensor operation timings in the circuits shown in FIGS. The output signals Vblock1 and Vblock2 of the vertical block selection circuit 18 sequentially become “H” level in a cycle of 4H in response to the horizontal synchronization pulse HP (one horizontal period is H). The in-block line selection circuit 19 is supplied with signals BLine1, BLine2, BLine3, and BLine4 in synchronization with the horizontal synchronization pulse HP. These signals BLine1, BLine2, BLine3, and BLine4 are repeated in a period of “H” level in order of 1H.

  Pixel drive pulse signals RESET, READ, and ADRES are input to the pulse selector circuit 20, and logical products (pulse signals RESET1, RESET2, RESET3,..., READ1, READ2) with the output signal of the in-block line selection circuit 19 are input. , READ3, ..., ADRES1, ADRES2, ADRES3, ...) are supplied to the unit cell rows (pixel rows) of the imaging region 11. Here, first, the pulse signals ADRES1, RESET1, and READ1 of the vertical line 1 output from the pulse selector circuit 20 are set to the “H” level. When the pulse signal ADRES1 becomes “H” level, the source follower circuit including the amplification transistor Tb and the load transistor TLM1 operates. The signal charge photoelectrically converted by the photodiode PD for a certain period is accumulated, and the pulse signal RESET1 is set to “H” level in order to remove a noise signal such as a dark current of the detection unit FD before reading. Set to power supply voltage VDD (= 2.8V). Next, when the pulse signal RESET1 becomes “L” level, a voltage (reset level) in a state where no signal is output to the reference detection unit FD is output to the vertical signal line VLIN1. This signal is stored in the capacitor C21. Next, the read transistor Td is turned on by setting the pulse signal READ1 to the “H” level, and the signal charge accumulated in the photodiode PD is read to the detection unit FD. Then, the voltage (signal + reset) level of the detection unit FD is read out to the vertical signal line VLIN1. This signal is stored in the capacitor C11. Next, when the pulse signal READ1 becomes “L” level, the reference voltage VREF is changed and the threshold voltage of the comparator COMP11 is used to convert the analog signal into a digital signal. At this time, the signal becomes C11-C21, and the reset level can be removed because the polarity of the reset level of the capacitor C21 is inverted.

  Signals supplied to the unit cell rows (pixel rows) in the imaging region 11 are sequentially output in synchronization with the horizontal synchronization pulse HP. The reset level voltage and the detection unit voltage (signal + reset level) are both electrodes of capacitors C11, C12, C13,... And C21, C22, C23,. Is input. Then, it is held in the circuit section 17 such as the latch circuit 14, the line memory 15, and the horizontal shift register circuit 16.

  FIG. 4 is a timing chart showing the operation timing for reducing the number of pixels in the circuit shown in FIG. In this example, two vertical lines are read sequentially. In the vertical block selection circuit 18, in response to the horizontal synchronization pulse HP, the signals Vblock1, Vblock2,... Alternately become “H” level in a cycle of 2H. The in-block line selection circuit 19 receives signals BLine1, Bline2, BLine3, and BLine4 in synchronization with the horizontal synchronization pulse HP. The signals BLine1 and BLine3 are simultaneously set to “H” level, and the operation in which the signals BLine2 and Bline4 are simultaneously set to “H” level is sequentially repeated in the next period H. The pixel selector pulses RESET, READ, and ADRES are input to the pulse selector circuit 20, and a signal obtained by performing a logical product with the output signal of the in-block line selection circuit 19 is supplied to the pixel row. Therefore, the signals RESET1 and RESET3, the signals READ1 and READ3, and the signals ADRES1 and ADRES3 are simultaneously at the “H” level.

  In the next period H, the signals RESET2 and RESET4, the signals READ2 and READ4, and the signals ADRES2 and ADRES4 are simultaneously at the “H” level. This operation is sequentially repeated in block order. The reset level voltage of the two vertical lines and the detection unit voltage (signal + reset level) are both the capacitors C11, C12, C13,... And C21, C22, C23 during the period when the pulse signal S1 is at the “H” level. ,... Are input to one of the electrodes. Here, one line is skipped and averaged in order to average the same color corresponding to the Bayer array color sensor.

  In the solid-state imaging device and the pixel averaging processing method thereof according to the first embodiment, averaging by resistance is realized by using the output impedance of the source follower circuit. At this time, the load transistors TLM1, TLM2, TLM3,... Are shared. Furthermore, when the number of vertical lines to be averaged is increased to 3 lines and 4 lines (the ADRES line is simultaneously turned on to 2 lines, 3 lines, and 4 lines), the operating point is pulled to the power supply side and the operating margin decreases. To do. As a countermeasure, if the switch SW is controlled by the signal PMONI and the bias voltage VTL is set high, the on-resistance of the load transistors TLM1, TLM2, TLM3,... Becomes small, and can be pulled back to the ground (GND) side. The operating margin can be expanded.

  In the resistance averaging method as described above, it is not necessary to increase the number of capacitors and a buffer circuit is not required. Moreover, the circuit scale of the vertical block selection circuit 18 can be 1/4. In addition, since the random noise of the pixels and the noise of the source follower can be averaged by the averaging operation using the resistance, the noise can be reduced.

  Therefore, according to the configuration and method as described above, in the operation for reducing the number of pixels, it is possible to realize averaging between pixels without generating a false signal, without increasing the pattern occupation area, and suppressing an increase in power consumption. .

  In the above description of the circuit and operation shown in FIG. However, the in-block line selection circuit 19 can easily cope with 3-line averaging and 4-line averaging by increasing the number of AND circuits and inputs BLine.

[Second Embodiment]
FIG. 5 is a circuit diagram illustrating a configuration example of an amplifying CMOS image sensor for explaining a solid-state imaging device and a pixel averaging method thereof according to the second embodiment of the present invention. The circuit shown in FIG. 5 is different from the circuit shown in FIG. 1 in that a horizontal switch addition circuit 40 is provided between the imaging region 11 and the CDS & ADC 13. The switch adding circuit 40 includes transistors TSM11, TSM12, TSM13,... (First combining switch) and transistors TSM21, TSM22,. The current paths of the transistors TSM11, TSM12, TSM13,... Are connected between the other ends of the vertical signal lines VLIN1, VLIN2, VLIN3, and so on and one end of the current paths of the transistors TS11, TS12, TS13,. . The current path of the transistor TSM21 is connected between the other end of the vertical signal line VLIN3 and one end of the current path of the transistor TS11. Further, the current path of the transistor TSM22 is connected between the other end of the vertical signal line VLIN4 and one end of the current path of the transistor TS12.

  A control signal SM1 is supplied to the gates of the transistors TSM11, TSM12,. A control signal SM2 is supplied to the gates of the transistors TSM13, TSM14,. A control signal SM2 is inverted by an inverter INV3 and supplied to the gates of the transistors TSM21, TSM22,. The control signal SM2 is supplied to inverters INV13, INV14, INV23, INV24, and controls the operation of these inverters.

  In the above configuration, when there is no horizontal averaging, the control signals SM1 and SM2 are set to the “H” level. On the other hand, in the case of horizontal averaging, the control signal SM2 is set to the “L” level while the “H” level of the control signal SM1 is maintained. As a result, the transistors TSM13 and TSM14 are turned off, and the transistors TSM21 and TSM22 are turned on. In other words, the output of the source follower circuit that has skipped one line in the horizontal direction is connected via the ON resistances of the transistors TSM11 and TSM21, and the averaged signal is stored in the capacitors C11 and C21 via the current path of the transistor TS11.

  In the horizontal averaging method, even if the number of averaging lines is increased to 2, 3, and 4, the bias voltage VTL may remain at the “L” level. This is because the transistors TLM1, TLM2, TLM3,... Are not shared and are arranged in each line, so that it is not necessary to increase the bias voltage VTL.

  The feature of the horizontal averaging method according to the second embodiment is that the power of the comparators CMP13, CMP14, CMP23, and CMP24 can be turned off by setting the control signal SM2 to the “L” level. Since the comparator operates only ½ of the total number of stages, the power consumption can be reduced to ½. In addition, since the number of horizontal reading stages can be halved, the operation speed can be doubled. Of course, by increasing the horizontal averaging transistor TSM and the control signal SM, it is possible to average three horizontal lines and four lines in the same manner.

  The horizontal averaging may be performed by reading out all horizontal pixels and averaging them by digital signal processing.

  In the operation of reducing the number of pixels using the amplification type CMOS image sensor, pixel averaging processing is realized by a resistance mix operation. As a result, the false signal that has been a problem in the conventional thinning-out operation is not generated, and the circuit is simple and noise can be reduced.

[Third Embodiment]
FIG. 6 is a circuit diagram illustrating a configuration example of an amplifying CMOS image sensor for explaining a solid-state imaging device and a pixel averaging processing method thereof according to the third embodiment of the present invention. The circuit shown in FIG. 6 differs from the circuit shown in FIG. 5 in the circuit configuration of the switch adder circuit. That is, the transistors TSM11, TSM12, TSM13,..., The transistors TSM21, TSM22,... And the inverter INV3 are deleted, and transistors TSM31, TSM32,. The control signal SM3 is used instead of the control signals SM1 and SM2.

  The switch addition circuit 41 includes transistors TSM31, TSM32,. The current path of the transistor TSM31 is connected between the other ends of the vertical signal lines VLIN1 and VLIN3. The current path of the transistor TSM32 is connected between the other ends of the vertical signal lines VLIN2 and VLIN4. A control signal SM3 is supplied to the gates of these transistors TSM31, TSM32,.

  In the configuration as described above, when there is no horizontal averaging, the control signal SM3 is set to the “L” level to turn off the transistors TSM31, TSM32,. On the other hand, in the case of horizontal averaging, the control signal SM3 is set to the “H” level. Thereby, the transistors TSM31, TSM32,... Are turned on. In other words, the output of the source follower circuit that skips one line in the horizontal direction is connected via the ON resistance of the transistor TSM31, and the averaged signal is accumulated in the capacitors C11 and C21 via the current path of the transistor TS11. At the same time, the averaged signal is stored in the capacitors C13 and C23 via the current path of the transistor TS13. The averaged signal is accumulated in the capacitors C12 and C22 via the current path of the transistor TS12, and the averaged signal is accumulated in the capacitors C14 and C24 via the current path of the transistor TS14.

  Therefore, according to such a configuration, the noise mixed in the vertical signal line is first reduced by averaging the analog signal, and the noise mixed from the AD converter is digitally averaged by the digital conversion output, so that the noise can be further reduced. .

[Fourth Embodiment]
FIG. 7 is a circuit diagram illustrating a configuration example of an amplifying CMOS image sensor for explaining a solid-state imaging device and a pixel averaging method thereof according to the fourth embodiment of the present invention. The circuit shown in FIG. 7 differs from the circuit shown in FIG. 6 in the circuit configuration of the switch adder circuit. This switch adding circuit 42 includes transistors TSM31, TSM32,... (Combining switches) and resistors RM1, RM2, RM3,. One end of the resistors RM1, RM2,... Is connected to the other end of the vertical signal lines VLIN1, VLIN2, VLIN3,..., And the other end is connected to one end of the current path of the transistors TS11, TS12, TS13,. . The current path of the transistor TSM31 is connected between the other ends of the resistors RM1 and RM3. The current path of the transistor TSM32 is connected between the other ends of the resistors RM2 and RM4. A control signal SM3 is supplied to the gates of these transistors TSM31, TSM32,.

  In the configuration as described above, the average output voltage of the vertical signal lines VLIN1 and VLIN2 is increased by increasing the resistance values of the resistors RM1, RM2, RM3,... And decreasing the on-resistances of the transistors TSM31, TSM32,. The difference in signal voltage between the two storage units C11, C21 and C13, C23 stored simultaneously can be reduced. By setting the ratio of the on-resistance of the transistors TSM31, TSM32,... And the resistance values of RM1, RM2, RM3,... To 1:10, the signal voltage difference between the two storage units can be reduced to 1/10. Thereby, according to the fourth embodiment, the noise reduction effect can be further enhanced as compared with the third embodiment.

  The horizontal averaging may be performed by reading out all horizontal pixels and averaging them by digital signal processing.

  As described above, according to one aspect of the present invention, in the operation for reducing the number of pixels, the generation of false signals can be prevented without increasing the pattern occupying area and the power consumption, thereby reducing the average between pixels. Can be realized. In addition, a pixel noise reduction effect can be obtained.

  The present invention has been described using the first to fourth embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention in the implementation stage. Is possible. Each of the above embodiments includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in each embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When at least one of the effects is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

  DESCRIPTION OF SYMBOLS 11 ... Imaging area | region, 12-11, 12-12, ..., 12-mn ... Unit cell (pixel), 13 ... Column type noise cancellation circuit and analog / digital converter (CDS & ADC), 14 ... Latch circuit, 15 ... Line Memory: 16 ... Horizontal shift register circuit, 17 ... Circuit unit, 18 ... Vertical block selection circuit, 19 ... In-block line selection circuit, 20 ... Pulse selector circuit, 21 ... Bias circuit, 40, 41, 42 ... Switch addition circuit, Ta ... row selection transistor, Tb ... amplification transistor, Tc ... reset transistor, Td ... readout transistor, FD ... detection unit, PD ... photodiode, VLIN1, VLIN2, VLIN3 ... vertical signal line, TLM1, TLM2, TLM3 ... load transistor, VTL: Bias voltage, READ, ADRES, RE ET ... pixel drive pulse signal.

Claims (2)

A photoelectric conversion means for converting an optical signal into a signal charge on a semiconductor substrate and storing the signal charge, a reading means for reading out the charge stored in the photoelectric conversion means to a detection section, and a signal corresponding to the charge amount of the detection section An image pickup region in which a pixel having amplifying means for outputting and a reset means for resetting the charge of the detection unit are arranged two-dimensionally in rows and columns;
A vertical signal line from which the output of the amplifying means of each pixel column in the imaging region is read out;
A plurality of switch adding means provided between the vertical signal lines so as to short-circuit the vertical signal lines of the pixel columns with one or more switching transistors;
Addition control means for simultaneously controlling the switch addition means by a control signal line commonly connected to the gates of the transistors of the plurality of switch addition means;
Column signal processing means for performing signal processing for each column on the signals added by the switch addition means;
A solid-state imaging device comprising: A photoelectric conversion means for converting an optical signal into a signal charge on a semiconductor substrate, and accumulating the signal charge, a reading means for reading the charge accumulated in the photoelectric conversion means to a detection section, and a signal corresponding to the charge amount of the detection section An image pickup region in which a pixel having amplifying means for outputting and a reset means for resetting the charge of the detection unit are arranged two-dimensionally in rows and columns;
A vertical signal line from which the output of the amplifying means of each pixel column in the imaging region is read out;
A plurality of switch adding means provided between the vertical signal lines so as to short-circuit the vertical signal lines of the pixel columns with one or more switching transistors;
Addition control means for simultaneously controlling the switch addition means by a control signal line commonly connected to the gates of the transistors of the plurality of switch addition means;
Column signal processing means for performing signal processing for each column on the signals added by the switch addition means;
A pixel averaging method for a solid-state imaging device comprising:
Operating two or more lines of the amplifying means in parallel in the pixel rows of the imaging region;
Operating switch addition means for connecting the vertical signal lines of each pixel column;
A pixel averaging processing method for a solid-state imaging device.

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