JP5070945B2 - Solid-state imaging device, imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device and an imaging device which are an example of a semiconductor device for physical quantity distribution detection. Specifically, for example, a plurality of unit components that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged, and an analog signal indicating a physical quantity distribution converted into an electric signal by the unit components. The present invention relates to a mechanism for converting an electrical signal into digital data and outputting it externally.

  For example, a plurality of unit components (for example, pixels) that are sensitive to changes in physical quantity such as electromagnetic waves input from the outside such as light and radiation or pressure (contact, etc.) are arranged in a matrix (matrix). Physical quantity distribution detection semiconductor devices are used in various fields.

  For example, in the field of video equipment, a CCD (Charge Coupled Device) type, a MOS (Metal Oxide Semiconductor) or CMOS (Complementary Metal-oxide) that detects a change in light (an example of an electromagnetic wave) which is an example of a physical quantity. A solid-state imaging device using a semiconductor (complementary metal oxide semiconductor) type imaging device (imaging device) is used.

  In recent years, MOS and CMOS type image sensors that can overcome various problems of CCD image sensors have attracted attention as an example of solid-state imaging devices. In the field of computer equipment, fingerprint authentication devices that detect fingerprint images based on changes in electrical characteristics based on pressure and changes in optical characteristics are used. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device).

  For example, a CMOS image sensor has an amplifying circuit such as a floating diffusion amplifier for each pixel. When reading a pixel signal, one row in the pixel array unit is selected as an example of address control. A so-called column-parallel output type or column type is often used in which row signals are accessed simultaneously and in units of rows, that is, pixel signals are read from the pixel array unit simultaneously in parallel for all pixels in one row. ing.

  Further, in the solid-state imaging device, there is a method in which an analog pixel signal read from the pixel array unit is converted into digital data by an analog-digital conversion device (AD conversion device; Analog Digital Converter) and then output to the outside. Sometimes taken.

  The same applies to the column parallel output type solid-state imaging device, and various signal output circuits have been devised. As an example of the most advanced form, an AD conversion device is provided for each column. There is a method of taking out pixel information as digital data to the outside (see, for example, Patent Document 1).

JP 2005-323331 A

  Various methods are considered as AD conversion methods from the viewpoint of circuit scale, processing speed (speedup), resolution, etc. As an example, changes in gradual values for conversion to analog unit signals and digital data are considered as an example. Compared with a so-called ramp-shaped reference signal (ramp wave), a count process is performed in parallel with this comparison process, and the digital data of the unit signal is obtained based on the count value at the time when the comparison process is completed. There is an AD conversion method called a slope integration type or a ramp signal comparison type (hereinafter referred to as a reference signal comparison type). The above-described Patent Document 1 also discloses a configuration example that employs a reference signal comparison AD conversion method. By combining the reference signal comparison AD conversion method with the aforementioned column parallel output type, analog output from pixels can be AD converted in a low bandwidth in a column parallel, making it suitable for image sensors that achieve both high image quality and high speed. It can be said that.

  However, when digital data that has been AD-converted for each column in the column parallel output type is output to the subsequent stage (generally referred to as horizontal data transfer), the parasitic capacitance existing in the horizontal data transfer bus line is a problem. Become. If the capacitance value of the parasitic capacitance is increased, signal delay is caused by that amount, and the speeding up of data transfer is hindered.

  For example, when high-speed operation is performed for reasons such as increasing the frame rate, operations such as row scanning, AD conversion, and horizontal data transfer must be performed at high speed. Of these, when it is desired to speed up horizontal data transfer, the data output stage of the column specified by column address selection drives the bus line, and the time until the data of that column reaches the subsequent circuit is dominant. It becomes.

  A data output stage for pixels in the horizontal direction is connected to the bus line, the parasitic capacitances of the data output stages are combined, and the data output stage of the selected column is driven using the large capacity as a load. It will be. In recent years, since there is a demand for increasing the number of pixels, the number of data output stages connected to the bus line tends to increase, and in recent years, there is a restriction on high speed operation that is particularly required.

  The present invention has been made in view of the above circumstances, and provides a mechanism that can improve problems caused by parasitic capacitance on a bus line in a mechanism for digitally converting a pixel signal and outputting it to the outside of the apparatus. The purpose is to do.

In one embodiment of the solid-state imaging device according to the present invention, a pixel unit in which unit pixels are arranged, an AD conversion unit that converts an analog pixel signal read from each unit pixel of the pixel unit into digital data, A first amplitude level changing unit that changes one of two voltage levels corresponding to the logic level of the digital data output from the AD conversion unit to a third voltage level between the two voltage levels ; A horizontal scanning unit that transfers information output from the first amplitude level changing unit to a common signal line, and information whose amplitude level has been changed by the first amplitude level changing unit is set to a logic level for a subsequent circuit. taking a second amplitude level changing unit for changing, a column-parallel configuration with.
Note that a data holding unit that holds the digital data converted by the AD conversion unit may be provided after the AD conversion unit of each column. In terms of a mechanism in which pixel signals are converted into digital signals and output to the outside of the apparatus, the pixels are not limited to those arranged in a two-dimensional matrix but are so-called one-dimensional (line) pixels. There is also application to line sensors.

Further, the first voltage level is changed from one of the two voltage levels corresponding to the logic level of the digital data output from the AD conversion unit (or data holding unit; the same applies below) to a third voltage level between the two voltage levels . Amplitude level changing unit, a horizontal scanning unit for transferring information output from the first amplitude level changing unit to a signal line common to each column, and information on the amplitude level changed by the first amplitude level changing unit And a second amplitude level changing unit for changing to a voltage level for a subsequent circuit.

In short, when the digital output AD-converted for each column is horizontally transferred, the digital output amplitude at the logic level is converted into information of a smaller amplitude and transferred on the horizontal signal line. It is characterized in that it returns to the voltage level for the circuit.

For example, the lower voltage level of the AD converted digital output is changed to a third voltage level between two voltage levels, and the higher voltage level is maintained at the same voltage level. Voltage information with a narrow voltage amplitude that is biased toward the power supply voltage side is converted into voltage information of a logic level for the subsequent circuit and output. Alternatively, the higher voltage level of the AD-converted digital output is changed to a third voltage level between the two voltage levels, and the lower voltage level is maintained at the same voltage level. Voltage information with a narrow voltage amplitude that is biased toward the ground voltage side is converted into voltage information of a logic level for the subsequent circuit and output. If necessary, the voltage information with a small amplitude shifted to the power supply voltage side or the ground voltage side is shifted to the voltage information located in the middle between the power supply voltage and the ground voltage, and then the voltage at the logic level for the subsequent circuit. It may be converted into information.

  Note that the solid-state imaging device may have a form formed as a single chip, or a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Also good.

  The mechanism of the embodiment of the solid-state imaging device according to the present invention can also be applied to the imaging device. In this case, the same effect as the solid-state imaging device can be obtained as the imaging device. Here, the imaging device indicates, for example, a camera (or camera system) or a portable device having an imaging function. “Imaging” includes not only capturing an image during normal camera shooting, but also includes fingerprint detection in a broad sense.

According to an embodiment of the present invention, a digital output amplitude of an AD converted logic level is converted into information of a smaller amplitude, transferred on a horizontal signal line, and returned to a voltage level for a subsequent circuit on the output side. Since it did in this way, the problem resulting from the parasitic capacitance on the horizontal signal line which is a bus line can be improved. This is because a transfer with small amplitude information consumes less power and a high-speed transfer operation is possible than a transfer with large amplitude information.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where a CMOS solid-state imaging device, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. The CMOS solid-state imaging device will be described on the assumption that all pixels are made of NMOS.

  However, this is an example, and the target device is not limited to the MOS type solid-state imaging device. All the semiconductor device for physical quantity distribution detection in which a plurality of unit components that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged in a line or matrix form, and all implementations described later. Forms are applicable as well.

<Overview of solid-state imaging device>
FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device (CMOS image sensor) which is an embodiment of the solid-state imaging device according to the present invention.

  The solid-state imaging device 1 has a pixel unit in which a plurality of pixels including a light receiving element (an example of a charge generation unit) that outputs a signal corresponding to an incident light amount is arranged in rows and columns (that is, in a two-dimensional matrix form). The signal output from each pixel is a voltage signal, and a CDS (Correlated Double Sampling) processing function unit, a digital conversion unit (ADC), etc. are provided in parallel in a column. It is.

  “A CDS processing function unit and a digital conversion unit are provided in parallel in a column” means that a plurality of CDS processing function units substantially parallel to a vertical signal line (an example of a column signal line) 19 in a vertical column This means that a digital conversion unit is provided.

  Each of the plurality of functional units is arranged only on one edge side in the column direction (output side arranged on the lower side of the figure) with respect to the pixel array unit (pixel unit) 10 when the device is viewed in plan view. It may be of the form that is arranged, or one end side in the column direction with respect to the pixel array unit 10 (output side arranged on the lower side of the figure) and the other end side that is the opposite side (The upper side of the figure) may be arranged separately. In the latter case, it is preferable that the horizontal scanning unit that performs readout scanning (horizontal scanning) in the row direction is also arranged separately on each edge side so that each can operate independently.

  For example, as a typical example in which a CDS processing function unit and a digital conversion unit are provided in parallel in a column, a CDS processing function unit and a digital conversion unit are arranged for each vertical column in a portion called a column area provided on the output side of the imaging unit. And is a column type that sequentially reads out to the output side. In addition to the column type (column parallel type), one CDS processing function unit or digital conversion unit is allocated to a plurality of adjacent (for example, two) vertical signal lines 19 (vertical columns), N A mode in which one CDS processing function unit or digital conversion unit is allocated to N vertical signal lines 19 (vertical columns) every other number (N is a positive integer; N−1 are arranged therebetween). It can also be taken.

  Except for the column type, in any form, since a plurality of vertical signal lines 19 (vertical columns) commonly use one CDS processing function unit and digital conversion unit, they are supplied from the pixel array unit 10 side. A switching circuit (switch) that supplies pixel signals for a plurality of columns to one CDS processing function unit or digital conversion unit is provided. Depending on the subsequent processing, a separate measure such as providing a memory for holding the output signal is required.

  In any case, the signal processing of each pixel signal is read out in units of pixel columns by adopting a form in which one CDS processing function unit or digital conversion unit is assigned to a plurality of vertical signal lines 19 (vertical columns). By performing the processing later, the configuration in each unit pixel can be simplified and the number of pixels of the image sensor can be reduced, the size can be reduced, and the cost can be reduced as compared with the case where the same signal processing is performed in each unit pixel.

  In addition, since a plurality of signal processing units arranged in parallel in a column can simultaneously process pixel signals for one row, one CDS processing function unit or digital conversion unit is provided on the output circuit side or outside the device. Therefore, the signal processing unit can be operated at a low speed as compared with the case where processing is performed, which is advantageous in terms of power consumption, bandwidth performance, noise, and the like. In other words, when the power consumption and bandwidth performance are the same, the entire sensor can be operated at high speed.

  In the case of a column type configuration, it can be operated at a low speed, which is advantageous in terms of power consumption, bandwidth performance, noise, and the like, and has an advantage that a switching circuit (switch) is unnecessary. In the following embodiments, this column type will be described unless otherwise specified.

  As shown in FIG. 1, the solid-state imaging device 1 of the present embodiment includes a pixel array unit 10 that is also referred to as a pixel unit or an imaging unit in which a plurality of unit pixels 3 are arranged in rows and columns, and a pixel array unit 10. Drive control unit 7 provided outside, a read current source unit 24 for supplying an operation current (read current) for reading a pixel signal to the unit pixels 3 of the pixel array unit 10, and a column arranged for each vertical column A column processing unit 26 having an AD circuit 25 and an output circuit 28 are provided. Each of these functional units is provided on the same semiconductor substrate.

  In FIG. 1, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of unit pixels 3 are arranged in each row and each column. The unit pixel 3 typically includes a photodiode as a light receiving element (charge generation unit) that is an example of a detection unit, and an intra-pixel amplifier (for example, a transistor) of an amplification semiconductor element (for example, a transistor). Example).

  Note that the solid-state imaging device 1 can make the pixel array unit 10 compatible with color imaging by using a color separation (color separation) filter. That is, color separation comprising a combination of a plurality of color filters for capturing a color image on a light receiving surface on which electromagnetic waves (light in this example) of each charge generation unit (photodiode, etc.) in the pixel array unit 10 are incident. Any color filter of the filter is provided in, for example, a so-called Bayer array, so that color image capturing is supported.

  The column AD circuit 25 of the present embodiment performs a difference process between a signal level immediately after pixel reset (hereinafter referred to as a reset level), which is a reference level of the pixel signal So, and a signal level, whereby the reset level and the signal A difference processing unit (CDS) 25a that acquires a signal component indicated by a level difference, and an AD conversion unit that converts a signal component that is a difference between a reset level that is a reference level of a pixel signal and a signal level into N-bit digital data (ADC) 25b is provided.

  The difference processing unit 25a and the AD conversion unit 25b can be arranged in any order. For example, as shown in FIG. 1, the difference processing unit 25a performs difference processing between an analog reset level and a signal level. The difference processing result may be converted into digital data by the AD conversion unit 25b. Although not shown, the AD conversion unit 25b converts the reset level and the signal level into digital data, and the difference between the digital data. The difference processing unit 25a may take the above.

  The function of the difference processing unit 25a is equivalent to a process (equivalent to a so-called CDS process) that takes a difference between a reset level and a true signal level (according to a received light amount), and is equivalent to a fixed pattern noise (FPN). A noise signal component called reset noise can be removed.

  As described above, the column AD circuit 25 of the present embodiment has both an AD conversion function that converts an analog pixel signal transferred from the pixel array unit 10 into digital data and a function that suppresses and removes noise components. It functions as an AD conversion / noise removal signal processing apparatus. In the column AD circuit (AD conversion / noise removal signal processing device) 25, the pixel signals output from the unit pixels 3 in the row selected by the vertical scanning unit 14 for selecting the row address are simultaneously converted into N-bit digital data for each row. Conversion to noise and noise removal signal processing are performed.

  As AD conversion processing in the column processing unit 26, analog signals held in parallel in units of rows are converted in units of rows using a column AD circuit 25 (specifically, the AD conversion unit 25b) provided for each column. A method of performing AD conversion in parallel for all the columns of one row can also be adopted. In this case, a reference signal comparison type (single slope integration type or ramp signal comparison type) AD conversion method may be employed. Since this method can realize an AD converter with a simple configuration, it has a feature that the circuit scale does not increase even if it is provided in parallel.

  In the reference signal comparison type AD conversion in the column AD circuit 25 (AD conversion unit 25b), for example, based on the time from the start of conversion until the reference signal Vslop and the processing target signal voltage (pixel signal voltage Vx) match, The analog processing target signal is converted into a digital signal. As a mechanism for this, in principle, a ramp-like reference signal Vslop is supplied to a comparator (voltage comparator), and counting (counting) with a clock signal is started and input via a vertical signal line 19. AD conversion is performed by counting the number of clocks until a pulse signal indicating the comparison result is obtained by comparing the analog pixel signal thus obtained with the reference signal Vslop.

  At this time, by devising the circuit configuration and operation of the AD conversion unit 25b, with respect to the voltage mode pixel signal input through the vertical signal line 19 together with the AD conversion, CDS processing that takes a difference from the true signal level (according to the amount of received light) can be performed, and it can also function as a difference processing unit 25a that removes noise signal components such as fixed pattern noise.

  Although details will be described later, this embodiment is characterized by a mechanism of a horizontal transfer system that solves a problem caused by a load capacity on the horizontal signal line 18 in horizontal data transfer, and is a specific example of reference signal comparison type AD conversion. For example, any mechanism such as the mechanism described in Patent Document 1 may be used.

  For example, Reference 1 (US Pat. No. 6,518,910) discloses a mechanism related to the ADC architecture of an ADC (ADC: AD converter) mixed CMOS image sensor. In this mechanism, the time when the difference between the current source (204 to 206 in the figure) provided for each pixel and the reference current source (213 in the figure) is inverted is measured by an N-bit counter and latched (in the figure). 303), AD conversion is performed by capturing the value. The voltage for controlling the reference current source (213) is generated by a Vref generator (302 in the figure). Such a mechanism described in Reference 1 can also be applied to this embodiment.

  Reference 2 (US Pat. No. 5,920,274) also discloses a mechanism relating to the architecture of the ADC mixed CMOS image sensor C. In this mechanism, the pixel output (FIG. 15) and the output from the 10-bit DAC (24 in the figure) are input to the comparator (42 in the figure), and the time when the difference is inverted is countered (44 in the figure). A / D conversion is performed by measuring. Such a mechanism described in Reference 2 can also be applied to this embodiment.

  Further, the use of the reference signal comparison type configuration as the column AD circuit 25 is merely an example, and any other configuration that can perform AD conversion processing and noise removal signal processing is employed. can do.

  The drive control unit 7 has a control circuit function for sequentially reading signals from the pixel array unit 10. For example, as the drive control unit 7, a horizontal scanning unit (column scanning circuit) 12 that controls column addresses and column scanning, a vertical scanning unit (row scanning circuit) 14 that controls row addresses and row scanning, and an internal clock are generated. And a communication / timing control unit 20 having functions such as

  The unit pixel 3 includes a vertical scanning unit 14 via a row control line 15 for row selection, a column processing unit 26 in which a column AD circuit 25 is provided for each vertical column via a vertical signal line 19, Each is connected. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning unit 14.

  The vertical scanning unit 14 selects a row of the pixel array unit 10 and supplies a necessary pulse to the row. For example, the vertical scanning unit 14 defines a readout row in the vertical direction (selects a row of the pixel array unit 10). It has a vertical decoder 14a and a vertical driver 14b that supplies a pulse to the row control line 15 for the unit pixel 3 on the read address (in the row direction) defined by the vertical decoder 14a and drives it. Note that the vertical decoder 14a selects not only a row from which a signal is read (reading row: also referred to as a selection row or a signal output row) but also a row for an electronic shutter.

  The horizontal scanning unit 12 has a function of a reading scanning unit that sequentially selects the column AD circuit 25 of the column processing unit 26 in synchronization with the clock and reads data obtained by digitally converting the pixel signal to the horizontal signal line 18. For example, the horizontal scanning unit 12 defines a horizontal readout row (selects each column AD circuit 25 in the column processing unit 26), and a read address defined by the horizontal decoder 12a. A horizontal driving unit 12b for guiding each signal of the column processing unit 26 to the horizontal signal line 18;

  The horizontal signal lines 18 are, for example, n * m lines corresponding to the number of bits n (n is a positive integer) handled by the column AD circuit 25 and the parallel number m (m is a positive integer), for example, 10 (= n). If the number of parallel bits is 2 (= m), 10 * 2 = 20 bus lines are arranged.

  Although not shown, the communication / timing control unit 20 is externally connected via a functional block of a timing generator TG (an example of a read address control device) that supplies a clock signal required for the operation of each unit and a pulse signal of a predetermined timing, and a terminal 5a. Receives the master clock CLK0 supplied from the main control unit, receives data instructing the operation mode supplied from the external main control unit via the terminal 5b, and further includes data including information of the solid-state imaging device 1. And a functional block of a communication interface that outputs to an external main control unit.

  For example, the horizontal address signal is output to the horizontal decoder 12a and the vertical address signal is output to the vertical decoder 14a, and each decoder 12a, 14a receives it and selects a corresponding row or column. The horizontal scanning unit 12 and the vertical scanning unit 14 include address setting decoders 12a and 14a, and perform a shift operation (scanning) in response to control signals CN1 and CN2 provided from the communication / timing control unit 20. Switch the read address.

  At this time, since the unit pixels 3 are arranged in a two-dimensional matrix, analog pixel signals generated by the pixel signal generation unit provided in the unit pixels 3 and output in the column direction via the vertical signal lines 19 are processed. Access and fetch (vertical) scan reading in units (in parallel), and then access the row direction, which is the arrangement direction of the vertical columns, and output pixel signals (digital pixel data in this example) to the output side Reading (horizontal) scan reading is preferably performed to speed up reading of pixel signals and pixel data. Of course, not only scanning reading but also random access for reading out only the information of the necessary unit pixel 3 is possible by directly addressing the unit pixel 3 to be read out.

  The elements of the drive control unit 7 such as the horizontal scanning unit 12 and the vertical scanning unit 14 are formed integrally with the pixel array unit 10 in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique. As a so-called one-chip (provided on the same semiconductor substrate), a CMOS image sensor which is an example of a semiconductor system is configured to form part of the solid-state imaging device 1 of the present embodiment. .

  Note that the solid-state imaging device 1 may be configured as one chip in which each unit is integrally formed in the semiconductor region as described above. Although not illustrated, the pixel array unit 10 and the drive control unit are omitted. 7. In addition to various signal processing units such as the column processing unit 26, an imaging function in which these are collectively packaged in a state including an optical system such as a photographing lens, an optical low-pass filter, or an infrared light cut filter It is good also as a modular form which has.

  In the solid-state imaging device 1 having such a configuration, the pixel signal output from the unit pixel 3 is supplied to the column AD circuit 25 of the column processing unit 26 via the vertical signal line 19 for each vertical column.

  In the case of a basic configuration in which the data storage / transfer output unit 256 is not provided, the output of the AD conversion unit 25 b or the difference processing unit 25 a is connected to the horizontal signal line 18. When analog difference processing is performed by the difference processing unit 25a and then converted into digital data by the AD conversion unit 25b, the output of the AD conversion unit 25b is connected to the horizontal signal line 18, and conversely, by the AD conversion unit 25b. When differential processing is performed by the differential processing unit 25 a after conversion to digital data, the output of the differential processing unit 25 a is connected to the horizontal signal line 18. Hereinafter, the former case will be described as shown in FIG.

  A control pulse (horizontal data transfer clock φH) is input from the horizontal scanning unit 12 to the AD conversion unit 25b via the control line 12c. The AD conversion unit 25b has a latch function for holding the count result, and holds data until an instruction by a control pulse is given via the control line 12c.

  In the present embodiment, as shown in the drawing, the output side of each column AD circuit 25 has data as an N-bit memory device that holds the count result held by the AD conversion unit 25b at the subsequent stage of the AD conversion unit 25b. A storage / transfer output unit 256 and a switch (SEL) 258 that is an example of a data switching unit disposed between the AD conversion unit 25b and the data storage / transfer output unit 256 are provided.

  When the configuration including the data storage / transfer output unit 256 is adopted, the switch 258 is in common with the switches 258 in the other vertical columns, and from the communication / timing control unit 20, a memory transfer instruction as a control pulse at a predetermined timing. A pulse CN8 is supplied.

  When the memory transfer instruction pulse CN8 is supplied based on the load function, the switch 258 transfers the data of the corresponding AD conversion unit 25b in the own column to the data storage / transfer output unit 256. The data storage / transfer output unit 256 holds and stores the transferred data.

  Corresponding to the provision of the switch 258, the horizontal scanning unit 12 of the present embodiment is parallel to the processing performed by the difference processing unit 25a and the AD conversion unit 25b of the column processing unit 26. The data storage / transfer output unit 256 has a function of a reading scanning unit that reads data held by the data storage / transfer output unit 256.

  The output of the data storage / transfer output unit 256 is connected to the horizontal signal line 18. As an example, the horizontal signal line 18 has a signal line of n-bit width which is the bit width of the column AD circuit 25, and is connected to an output circuit 28 having n sense circuits corresponding to the respective output lines (not shown). Is done.

  In particular, if the data storage / transfer output unit 256 is configured, the AD conversion data held by the AD conversion unit 25b can be transferred to the data storage / transfer output unit 256. The conversion processing and the reading operation of the AD conversion result to the horizontal signal line 18 can be controlled independently, and a pipeline operation in which the AD conversion processing and the external signal reading operation are performed in parallel can be realized.

For example, when the reference signal comparison type AD conversion method is adopted as the column AD circuit 25, the column AD circuit 25 reads out the pixel signal from the pixel array unit 10 at a predetermined timing in one horizontal period, and then compares the reference signal. A type AD conversion process is performed, and an AD conversion result is output at a predetermined timing. That is, first, the voltage comparison unit compares the reference signal for comparison processing (for practical AD conversion processing) with the pixel signal voltage input via the vertical signal line 19, and the two voltages are the same. Then, the comparator output of the voltage comparison unit is inverted. For example, the voltage comparison unit sets the higher voltage level such as the power supply potential to the inactive state, and transitions to the lower voltage level (active state) when the pixel signal voltage matches the reference signal.

  The counter unit provided in the subsequent stage of the voltage comparison unit starts the count operation in the down-count mode or the up-count mode in synchronization with the change of the reference signal, and performs the count operation when the inverted information of the comparator output is notified. The AD conversion is completed by latching (holding / storing) the count value at that time as pixel data. Thereafter, the data is transferred to the data storage / transfer output unit 256 at a predetermined timing, and stored / held.

  Thereafter, the column AD circuit 25 stores the pixels stored / held in the data storage / transfer output unit 256 based on a shift operation synchronized with a control pulse input from the horizontal scanning unit 12 via the control line 12c at a predetermined timing. Data is sequentially output from the output terminal 5 c to the outside of the column processing unit 26 or the outside of the chip having the pixel array unit 10.

<Problems of horizontal data transfer>
Here, when the data held in the data storage / transfer output unit 256 of each column is sequentially transferred to the output circuit 28 side via the horizontal signal line 18 which is a bus line, the horizontal signal connected to the output circuit 28 Since parasitic capacitance exists in the line 18, parasitic capacitance such as deterioration in transfer speed and increase in chip size due to increase in wiring width (Metal width) used for the horizontal signal line 18 to suppress parasitic capacitance. Various problems arise due to the presence of the.

For example, the value of parasitic capacitance is
(1) Capacity due to the horizontal signal line 18,
(2) capacitance due to the input stage of the output circuit 28;
(3) Capacity by output stage of one data storage / transfer output unit 256 × total number of data storage / transfer output units 256,
(4) capacity of wiring connecting the horizontal signal line 18 and the output stage of one data storage / transfer output unit 256 × total number of data storage / transfer output units 256,
It is the total value.

  Therefore, when the data stored in the data storage / transfer output unit 256 of each column is sequentially selected by the data storage / transfer output unit 256 and read out to the horizontal signal line 18, the above-described parasitic capacitance of the horizontal signal line 18 is caused. , Data transfer failure. In particular, if the capacitance value of the parasitic capacitance is increased, it causes signal delay and hinders speeding up of data transfer.

  For example, when high-speed operation is performed for reasons such as increasing the frame rate, operations such as row scanning, AD conversion, and horizontal data transfer must be performed at high speed. Of these, when it is desired to speed up the horizontal data transfer, the time until the data storage / transfer output unit 256 selected by the horizontal scanning unit 12 drives the horizontal signal line 18 and the signal reaches the output circuit 28. Becomes dominant.

  In the case of the pixel array section 10 having horizontal pixels, for example, 2000 columns of unit pixels 3, 2000 data storage / transfer output sections 256 are connected to the horizontal signal line 18, and data storage / transfer output is performed. The parasitic capacitances of the output stages of the unit 256 are combined, and the selected data storage / transfer output unit 256 is driven with the large capacity as a load. In recent years, since there is a demand for increasing the number of pixels, the number of data storage / transfer output units 256 connected to the horizontal signal line 18 tends to increase, and in recent years, there is a restriction on high-speed operation that is particularly required.

  As a technique for solving such a problem, a technique of widening the wiring width used for the horizontal signal line 18 in order to reduce parasitic resistance and suppress wiring delay due to parasitic capacitance can be considered. In order to transfer by the horizontal signal line 18 as a bus line, the chip size becomes large.

  Therefore, in the present embodiment, in the mechanism in which the pixel signal is digitally converted and output to the outside of the solid-state imaging device 1, the column processing unit 26 and the horizontal scanning unit 12 are caused to have a problem caused by the parasitic capacitance of the horizontal signal line 18. Make it a mechanism that can be improved. This will be specifically described below.

<Configuration of data storage / transfer output unit and output circuit: Basic>
2 and 2A illustrate the basic configuration of the column processing unit 26 (particularly the periphery of the data storage / transfer output unit 256) and the output circuit 28 shown in FIG. Here, FIG. 2 is a circuit block diagram showing the basic configuration, and FIG. 2A is a voltage level diagram for explaining the basic operation. 3 to 3B are diagrams illustrating a comparative example with respect to FIGS. 2 and 2A. Here, FIG. 3 is a circuit block diagram showing a configuration example thereof, and FIGS. 3A and 3B are voltage level diagrams for explaining the operation thereof.

In the solid-state imaging device 1 of the present embodiment, as a mechanism for realizing high-speed data transfer without being affected by the parasitic capacitance of the horizontal signal line 18, it is output from the data holding function unit of each data storage / transfer output unit 256. The data having two voltage levels corresponding to the logic level is not directly output to the horizontal signal line 18 through the transfer driver, but is converted into information of a smaller amplitude level and transferred on the horizontal signal line 18. The output circuit 28 re-converts to the voltage level for the subsequent circuit.

  As a basic configuration of the mechanism for that, first, as shown in FIG. 2A, the data storage / transfer output unit 256 is input to the D input terminal in synchronization with the subclock SUBCK input to the clock terminal CK. A D-type flip-flop (D-FF) 402 that is an example of a data holding unit that captures and holds data from the column AD circuit 25, and a transfer driver that is an example of a bus drive circuit (data output stage) as a transfer output function unit 404. The output of the transfer driver 404 is connected to the output circuit 28 via the horizontal signal line 18 that is a bus line.

Corresponding horizontal data transfer clocks φH_1 to φH_h are input from the communication / timing controller 20 to the output enable terminals OE of the transfer drivers 404_1 to 404_h. Each of the transfer drivers 404_1 to 404_h is when the corresponding horizontal data transfer clocks φH_1 to φH_h are active (in this example, H (high) level) (that is, when the output enable terminal OE is at the higher voltage level ). The input information is transferred to the output circuit 28 via the horizontal signal line 18.

As shown in FIG. 2B, in the solid-state imaging device 1, the D-type flip-flop (D-FF) 402 has a subsequent stage according to the logic level of data (information) output from the D-type flip-flop 402 . the third and the first amplitude level changing section 410 for changing the voltage level, the information that the amplitude level is changed in the first amplitude level changing unit 410 subsequent circuit between hand of two voltage levels of the two voltage levels A second amplitude level changing unit 416 for changing to a voltage level for use. The second amplitude level changing unit 416 is provided in an output circuit 28 provided for the horizontal signal line 18 common to each column.

The first amplitude level changing unit 410 First, D-type inverter 412 for inverting the data (information) output from the flip-flop 402, hand the two voltage levels corresponding to logic levels of the data output from the inverter 412 Is provided in the transfer driver 404 for each column. The first level adjustment unit 414 converts the signal to a third voltage level between the two voltage levels . Note that depending on the circuit configuration, the inverter 412 can be a non-inverting buffer or can be eliminated.

The first amplitude level changing section 410, the second level adjustment unit 415 to maintain substantially the same voltage level other side of the two voltage levels corresponding to logic levels of data outputted from the D-type flip-flop 402 Have The second level adjustment unit 415 is provided in an output circuit 28 provided for the horizontal signal line 18 common to each column.

More preferably, a level shift unit 418 may be provided in the output circuit 28 as indicated by a dotted line in the drawing. The level shift unit 418 converts the midpoint potential of the information output from the first amplitude level change unit 410 between the horizontal signal line 18 that is a signal line common to each column and the second amplitude level change unit 416 to two voltages. Shift to a fourth voltage level between levels . When the level shift unit 418 is provided, the second amplitude level change unit 416 changes the information output from the level shift unit 418 to the voltage logic level for the subsequent circuit.

For example, as in the first example shown in FIG. 2A (A), the first level adjustment unit 414 sets the other (lower) voltage level of data (information) output from the D-type flip-flop 402 to two voltages. Change to a third voltage level VL1 between levels . In response to this, the second level adjustment unit 415 maintains the higher voltage level of the data output from the D-type flip-flop 402 at the H level VH1 that is substantially the same voltage level. H level VH1 is at the same potential as power supply voltage Vdd of a logic circuit such as D flip-flop 402, for example.

Alternatively, as in the second example shown in FIG. 2A (B), the first level adjustment unit 414 sets one (higher) voltage level of data (information) output from the D-type flip-flop 402 to two voltages. Change to the third voltage level VH2 between the levels. In response to this, the second level adjustment unit 415 maintains the other (lower) voltage level of the data (information) output from the D-type flip-flop 402 at the L level VL2 which is substantially the same voltage level. . L level VL2 is at the same potential as the ground voltage of a logic circuit such as D flip-flop 402, for example.

As described above, the transfer driver 404 (particularly, the first level adjustment unit 414) and the second level adjustment unit 415 of this embodiment are output from the D-type flip-flop 402 as shown in FIG. VL (equivalent ground potential), VH data voltage level for binary (power supply potential equivalent logic circuit) (Fig. (A1) or (B1)), the narrower the analog-like voltage signals voltage amplitude The signal is converted and output to the horizontal signal line 18 ((A2) or (B2) in the figure). This is because, in the driving of a high load horizontal signal line, from the viewpoint of high-speed data transfer, the driving is performed more than when information is transferred to the output circuit 28 via the horizontal signal line 18 while maintaining the original voltage levels of VL and VH. This is because it is advantageous in terms of performance, power consumption, and anti-noise performance.

The second amplitude level changing unit 416 of the output circuit 28 is data (analog data ) having a voltage level corresponding to the logic level (logic level) by the transfer driver 404 (particularly the first level adjusting unit 414) and the second level adjusting unit 415. When the voltage information (VL1 to VH1) on the horizontal signal line 18 converted into an analog signal with a narrow voltage amplitude is received, the voltage information VLout of the logic level (logic level) for the subsequent circuit is received again. VHout is converted and output ((A4) or (B4) in the figure)).

For example, in the case of the first example shown in FIG. 2A that does not include the level shift unit 418, the second amplitude level changing unit 416 is a voltage that varies between VL1 and VH1 as shown in FIG. 2A (A2). Using “(VH1−VL1) / 2 + VL1” which is the midpoint potential of the information as a threshold voltage Vbias1, a voltage comparator (comparator) compares whether the voltage value on the horizontal signal line 18 is higher or lower than the threshold voltage Vbias1. The voltage difference is amplified to logic information voltage information VLout and VHout for the subsequent stage circuit by an amplification function of the voltage comparator (when necessary, by cooperation with the output buffer).

Further, in the case of the second example shown in FIG. 2A without the level shift unit 418, the second amplitude level changing unit 416 changes between VL2 and VH2 as shown in FIG. 2A (B2). A voltage comparator (comparator) compares whether the voltage value on the horizontal signal line 18 is higher or lower than the threshold voltage Vbias2 with (VH2−VL2) / 2 + VL2 being the midpoint potential of the voltage information as the threshold voltage Vbias2. The voltage difference is amplified to logic information voltage information VLout and VHout for the subsequent stage circuit by an amplification function of the voltage comparator (when necessary, by cooperation with the output buffer).

  However, in these cases, the logic level for the subsequent circuit is centered on the midpoint potential (= threshold voltages Vbias1, Vbias2) of the voltage information (VL1 to VH1 or VL2 to VH2) output from the first amplitude level changing unit 410. While the voltage information VLout and VHout can be generated with almost accurate timing, the voltage level on the horizontal signal line 18 is shifted to the power supply voltage Vdd side in the first example, and shifted to the ground voltage GND side in the first example. Therefore, it is difficult to devise the circuit configuration to perform the processing.

  Considering the compactness of the circuit configuration, for example, the voltage information (VL1 to VH1 or VL2 to VH2) output from the first amplitude level changing unit 410 is input to the gate terminal of the MOS transistor and inverted and output. It is also conceivable to adopt a configuration in which the logic is inverted with an inverting output buffer. However, in this case, at the time of inversion output processing by the MOS transistor, it is affected by the threshold voltage, and the logic change is compared with the comparison processing and amplification processing centering on the above-described midpoint potential (= threshold voltages Vbias1 and Vbias2). There is a difficult point that timing shifts.

In order to solve these problems, in order to facilitate the processing in the second amplitude level changing unit 416 while avoiding the deviation of the timing of the logical change, the first amplitude level changing unit 416 is arranged between the horizontal signal line 18 and the second amplitude level changing unit 416. The midpoint potential (= threshold voltages Vbias1 and Vbias2) of the voltage information (VL1 to VH1 or VL2 to VH2) of the data output from the amplitude level changing unit 410 is an intermediate potential of the fourth voltage level between VL and VH. It is preferable to provide a level shift unit 418 for shifting to voltage information data having an amplitude of VL3 to VH3. At this time, the level shift unit 418 may maintain the amplitude of the input voltage information (VL1 to VH1 or VL2 to VH2), or amplifies the amplitude and performs a comparison process in the second amplitude level change unit 416. May be made easier.

In this case, as shown in FIG. 2A (A3) and FIG. 2A (B3), the second amplitude level changing unit 416 is the midpoint potential of the voltage information that changes in VL3 to VH3, “(VH3−VL3) / 2 + VL3”. ”As a threshold voltage Vbias3, a voltage comparator (comparator) compares whether the voltage value on the horizontal signal line 18 is higher or lower than the threshold voltage Vbias3, and the voltage difference is compared with the amplification function of the voltage comparator (necessary In accordance with the output buffer), the voltage information VLout and VHout of the logic level for the subsequent circuit is amplified.

On the other hand, in the configuration of the comparative example, as illustrated in FIG. 3, the transfer driver 404 includes a non-inverting buffer 512 and an analog switch 514 for each column after the D flip-flop 402. The buffer 512 outputs data that swings with a high voltage in the vicinity of the power supply voltage Vdd corresponding to the higher voltage level and a low voltage in the vicinity of the ground voltage GND corresponding to the lower voltage level. The signal is transmitted to the signal line 18 and transferred to the output circuit 28. Note that the buffer 512 can be replaced with an inverter. In this case, the logic may be inverted on the output circuit 28 side.

  Each analog switch 514 has a so-called transfer gate configuration in which two CMOS SW transistors (switch transistors) 514N and 514P having different polarities of CMOS structure formed by complementary circuit technology are connected to each other between source ends and drain ends. Is adopted. Therefore, an inverter 516 for driving the gate end of one SW transistor 514P of the analog switch 514 is provided for each column.

  The gate terminal of the SW transistor 514N and the input terminal of the inverter 516 are supplied with the column corresponding to the horizontal data transfer clocks φH_1 to φH_h from the horizontal scanning unit 12, and the horizontal scanning unit 12 is connected to the gate end of the SW transistor 514P. The horizontal data transfer clocks φNH_1 to φNH_h corresponding to the columns obtained by logically inverting the horizontal data transfer clocks φH_1 to φH_h corresponding to the columns from the inverter 516 are supplied.

The analog switch 514 composed of the SW transistors 514N and 514P is turned on when the gate terminal of the SW transistor 514N is at the higher voltage level and the gate terminal of the SW transistor 514P is at the lower voltage level , so that the source terminal The voltage levels VL and VH input to the side are output to the drain end side.

  In principle, the analog switch 514 may be a switch composed of only one of the SW transistors 514N and 514P, or an n-channel MOS transistor or a p-channel MOS transistor. However, in this case, there is a problem of the threshold voltage Vth. For this reason, a CMOS switch using a combination of both an n-channel type and a p-channel type is employed.

  However, in the configuration of such a comparative example, regarding the increase in the number of pixels, the horizontal signal line 18 is provided with MOS switches (SW transistors 514N and 514P) provided at the output portion of the D-type flip-flop 402 as a latch circuit. Since many analog switches 514 are connected, for example, many parasitic capacitances due to the drain-gate capacitances C514N and C514P of the SW transistors 514N and 514P are connected.

  For example, when the pixel array has 8M pixels of 4000 (V) × 2000 (H), the parasitic capacitance is about several fF per latch circuit (D-type flip-flop 402 in this example). Since there are columns, the horizontal signal line 18 is eventually connected to several to several tens of pF. Further, since the horizontal signal line 18 extends in the row direction, there is also a grounding capacitance C515 with respect to the substrate, and this grounding capacitance varies depending on the width of the horizontal signal line 18 and the influence of surrounding wiring. There are several pF. For this reason, the horizontal signal line 18 has a high load for the latch circuit.

  Regarding the increase in the frame rate, similarly, when the pixel array has 8M pixels of 4000 (V) × 2000 (H), the time required for 1H (one horizontal period) at 30 fps is (1/30) / 2000 = Although it is 17 μsec, if the frame rate is further increased, for example, it becomes 4.2 μsec at 120 fps. When a latch circuit provided for each column holds data of one pixel and horizontally transfers the data within a time of 1H, if pixels of 4000 columns are transferred in a time of 1H at 120 fps, per pixel The transfer time is about 4.2 / 4000 = 1.1 nsec.

  As described above, driving the high-load horizontal signal line 18 at a high speed requires driving the horizontal signal line 18 with a buffer having a high driving capability, which increases power consumption. The driving current I of the horizontal signal line 18, the power supply voltage V, and the charge Q charged / discharged to the horizontal signal line 18 are generally P = I · V = (dQ / dt) · V = C (dV / dt) · V. In the above example, if C = 10 pF, V = 1.8 V, and t = 1.1 nsec, then P = 10 pF × (1.8 V / 1.1 nsec) = 16 mW. Actually, the power consumption of the drive circuit of the buffer itself for driving the horizontal signal line 18 must be taken into consideration, and the power consumption is several times to ten times the power consumption.

  In the case of driving by the buffer 512 or the inverter, the horizontal signal line 18 corresponding to the pixel pitch × the number of horizontal pixels in the horizontal direction must be driven between the power supply voltage Vdd and the ground voltage GND, and a repeater is inserted in the middle. Even so, it is difficult to increase the speed due to the RC delay caused by the resistance component R and the capacitance component C, and the power consumption due to the through current of the buffer 512 or the inverter increases.

  Further, when the high load horizontal signal line 18 is driven at a high speed, it is difficult to secure a slew rate. This is shown in FIG. 3A. As shown in the figure, the potential of the horizontal signal line 18 that should originally swing to the power supply voltage V can actually swing only a small amplitude. This is because the horizontal signal line 18 has a resistance and the buffer has a finite output impedance, so that the amplitude becomes very small due to a so-called CR delay.

  In addition, when the signal can swing only with such a small amplitude, resistance to noise is deteriorated, and there is a possibility of causing a signal error. This is shown in FIG. 3B. As shown in the figure, when the outputs of the adjacent columns are always different and the horizontal signal line 18 always changes, the amplitude decreases, and when there is no change, the amplitude increases. For this reason, the threshold value for discriminating the value varies depending on the output change, which causes a misjudgment.

  From these factors, for example, the horizontal signal line 18 is divided into a plurality of lines, the capacity of the horizontal signal line 18 per line is reduced, and the drive frequency is further reduced. It is conceivable to avoid this. However, in this case, since a plurality of horizontal signal lines 18 and a plurality of output circuits 28 connected to the horizontal signal lines 18 are provided, noise due to an increase in layout area and crosstalk between the horizontal signal lines 18 of a plurality of systems is provided. This causes a problem such as a factor and a skew between the horizontal signal lines 18.

On the other hand, in the present embodiment, the data is not transferred on the horizontal signal line 18 with the logic output level of the latch circuit (D-type flip-flop 402 in this example), but is converted into a voltage signal having a smaller amplitude. Then, it is transmitted to the output circuit 28, and the output circuit 28 amplifies the voltage signal with a small amplitude so that it becomes voltage information (voltage level) for the subsequent circuit again. By transferring the voltage on the horizontal signal line 18 with a voltage signal having a small amplitude, high speed operation is realized as a result. Hereinafter, some specific configuration examples will be shown and described.

<First Embodiment: First Example>
4 and 4A are diagrams illustrating a first example of the first embodiment. Here, FIG. 4 is a circuit showing a configuration example when the L voltage level output from the D-type flip-flop 402 is changed to the third voltage level VL1 as in the first example shown in FIG. 2A (A). FIG. 4A is a block diagram, and FIG. 4A is a timing chart illustrating the operation. FIG. 4B is a circuit block diagram showing a configuration example when the H voltage level output from the D-type flip-flop 402 is changed to the third voltage level VL2 as in the second example shown in FIG. 2A (B). FIG. 4C is a timing chart illustrating the operation.

  As shown in FIG. 4A, in the configuration of the first example of the first embodiment, first, the first level adjustment unit 414 of the data storage / transfer output unit 256 is connected between the inverter 412 and the horizontal signal line 18. An NMOS transistor 420N, a PMOS transistor 422P as a switch transistor having an analog switch function, and an inverter 424 for controlling the gate terminal of the PMOS transistor 422P are provided.

  The gate end of the PMOS transistor 422P is supplied with a column corresponding to the horizontal data transfer clocks φNH_1 to φNH_h obtained by logically inverting the column corresponding to the horizontal data transfer clocks φH_1 to φH_h from the horizontal scanning unit 12 by the inverter 424. . Although the inverter 424 is interposed, the PMOS transistor 422P outputs the inverted output of the NMOS transistor 420N to the common horizontal signal line 18 side of each column under the control of the horizontal scanning unit 12.

In the NMOS transistor 420N, the output data of the inverter 412 is input to the gate terminal, the source terminal is grounded, and the drain terminal is connected to one input / output terminal (for example, drain terminal) of the PMOS transistor 422P.

Further, the horizontal signal line 18 is substantially the same as the higher voltage level of the D flip-flop 402 with respect to the higher one of the two voltage levels of the data (information) output from the D flip-flop 402. A second level adjustment unit 415 that maintains the same voltage level at the H level VH1 is connected. In the first example of the first embodiment, the second level adjustment unit 415 uses a function that functions as pull-up means for maintaining the potential of the horizontal signal line 18 at the power supply voltage Vdd on the high potential side. The horizontal signal line 18 is previously pulled up to the power supply voltage Vdd, and the horizontal signal line 18 is fixed at the power supply voltage Vdd.

The second amplitude level changing unit 416 provided in the output circuit 28 includes a differential amplifier circuit 430 such as an operational amplifier. The differential amplifier circuit 430 has both a voltage comparator (comparator) function and an amplifier circuit function. A non-inverting output buffer 438 is provided following the differential amplifier circuit 430. In addition to the general buffer function, the output buffer 438 supplies a power supply voltage when the signal voltage output from the differential amplifier circuit 430 is insufficient for the logic information VLout and VHout (also referred to as full amplitude) for the subsequent circuit. Full amplitude operation between Vdd and ground voltage GND is performed. The output of the output buffer 438 is connected to an output terminal 5c (not shown), and logic level voltage information VLout and VHout data for the subsequent circuit is output outside the chip.

  In the differential amplifier circuit 430, the power supply voltage Vdd is supplied to the high potential side power supply end, and the low potential side power supply end is grounded. The differential amplifier circuit 430 is configured such that the horizontal signal line 18 is connected to the non-inverting input terminal (+) and the differential amplifier circuit 430 is driven by the horizontal signal line 18, and the threshold value is connected to the inverting input terminal (−). The voltage Vbias1 = “(VH1−VL1) / 2 + VL1” is supplied as a reference voltage.

  The differential amplifying circuit 430 uses its own voltage difference and the amplifying circuit so that when the voltage value on the horizontal signal line 18 is higher than the threshold voltage Vbias1, the differential amplifying circuit 430 has its voltage difference by its own amplifying function (output as necessary). Amplifying to the H logic voltage level VHout for the post-stage circuit (by cooperating with the buffer 438), and when the voltage value on the horizontal signal line 18 is lower than the threshold voltage Vbias1, the voltage difference itself has an amplification function. It amplifies to the L logic voltage level VLout for the subsequent circuit (by cooperating with the output buffer 438 as necessary).

For example, if the output data of the AD conversion unit 25b in a certain column (i column) is “H”, and the output of the D-type flip-flop 402 is also “H”, an inverter connected to the output of the D-type flip-flop 402 Since the output of 412 becomes “L” and the NMOS transistor 420N connected to the tip of the inverter 412 is turned off, the voltage of the horizontal signal line 18 remains the power supply voltage Vdd pulled up by the second level adjustment unit 415. Thus, the H level VH1, which is substantially the same voltage level as one (higher) voltage level of the data (information) output from the D-type flip-flop 402, is maintained.

On the other hand, when the output data is “L”, if the output of the D-type flip-flop 402 is “L”, the output of the inverter 412 connected to the output of the D-type flip-flop 402 becomes “H”. previously set to connect the NMOS transistor 420N is turned on, between the ground voltage GND to decrease by a voltage has a horizontal signal line 18, corresponding to the higher voltage level of the power supply voltage Vdd and lower corresponding to the voltage level of the It becomes the third voltage level VL1. The amount of voltage drop depends on the drain-source drive capability (related to the drain-source drive current and output resistance) of the NMOS transistor 420N and the load resistance and load capacitance on the horizontal signal line 18 side. Determined.

In configuring the first level adjusting section 414, NMOS transistor in inversion transistors (in this example two voltage levels corresponding to logic levels of the data (information) output from the AD converter 25b and the D-type flip-flop 402 420N) has an advantage that one of the H and L voltage levels (the lower voltage level in this example) can be easily converted to the third voltage level VL1.

The differential amplifier circuit 430 in the output circuit 28 is supplied with the threshold voltage Vbias1 = “(VH1−VL1) / 2 + VL1” as a reference voltage at the inverting input terminal, and is connected to the horizontal signal line 18 using this as a reference voltage. Compared with the potential of the non-inverting input terminal, the voltage difference is amplified up to voltage information VLout and VHout of the logic level for the subsequent circuit. As a result, output data corresponding to the signal values (VL1, VH1) of the horizontal signal line 18 is obtained, and the output data of a certain column is transferred, and horizontal transfer can be performed.

In the example shown, the output data of the first inverter 412 is provided D-type flip-flop 402 logically inverts and inverted two voltage levels of the data output from the inverter 412 (information) in NMOS transistor 420N structure However, this is not essential. For example, if the differential amplifier circuit 430 of the output circuit 28 has an inverting amplifier configuration, the inverter 412 can be replaced with a non-inverting buffer or eliminated. This also applies to other embodiments described later.

  FIG. 4A shows a timing chart when “H” and “L” are alternately output from the i-th column when the configuration of the first example of the first embodiment is taken. As shown in the figure, the voltage of the horizontal signal line 18 swings between the power supply voltage Vdd and the third voltage level VL1, that is, the horizontal signal line 18 is powered according to the digital output from the column AD circuit 25. It can be driven with a small amplitude voltage near the voltage Vdd. For this reason, as compared with the case of the amplitude between the power supply voltage Vdd and the ground voltage GND as in the comparative example, an increase in power consumption can be prevented, and since the amplitude is small, there is no problem due to a decrease in the slew rate. The horizontal transfer in the small amplitude operation between VL1 to VH1 enables low power consumption and high speed operation.

  When the H level is output, the pull-up function of the second level adjustment unit 415 always pulls up to the power supply voltage Vdd (= VH1). When the L level is output, the NMOS transistor 420N provided for each column Pull down to 3 voltage level VL1. The current value necessary for charging / discharging the horizontal signal line 18 which is a high load can be relaxed, and since there is no steady current path at the time of H level output, there is no power consumption by the horizontal signal line 18 and low power consumption. A horizontal transfer circuit to be driven can be provided. Since the through current does not flow at the transition from the L level (third voltage level VL1) where the NMOS transistor 420N is turned off to the H level (VH1 = Vdd), there is also an advantage of operating with lower power consumption than the comparative example.

  When the horizontal signal line 18 is driven through the buffer 512 as in the comparative example, data that is amplified by a high voltage in the vicinity of the power supply voltage Vdd corresponding to the H level and a low voltage in the vicinity of the ground voltage GND corresponding to the L level is displayed on the horizontal signal line. 18 is output. For this reason, there are actually a few current paths both at the time of H level output and at the time of L level output, which is different from the increase in power consumption corresponding to the transmission speed. When the configuration of the first example of the first embodiment is adopted, it aims at low power consumption while improving high speed, which is an advantage for future high speed CMOS image sensor development.

Further, as shown in FIG. 4A, the second amplitude level changing unit 416 uses a differential amplifier circuit 430 such as an operational amplifier, and is a midpoint potential of voltage information that changes in VL1 to VH1. VH1−VL1) / 2 + VL1 ″ is set as a threshold voltage Vbias1 to compare whether the voltage value on the horizontal signal line 18 is higher or lower than the threshold voltage Vbias1, and the voltage difference is amplified to the voltage levels VLout and VHout for the subsequent circuit. By doing so, even if there is a voltage change of the horizontal signal line 18 due to a signal change for each column, the determination can be made with a certain threshold value, so noise resistance is improved.

  As shown in FIG. 4B, the second amplitude level changing unit 416 provided in the output circuit 28 may include a PMOS transistor 434P and a load resistor 436 instead of the differential amplifier circuit 430 such as an operational amplifier. Good. The PMOS transistor 434P functions as an inverter, the power supply voltage Vdd is supplied to the source terminal, the drain terminal is connected to one terminal of the load resistor 436, and the gate terminal outputs the first amplitude level changing unit 410. Voltage information (VL1 to VH1) is supplied. The other terminal of the load resistor 436 is grounded.

  Correspondingly, the output buffer 438 is not inverted but inverted. As an example, the PMOS transistor 438P and the NMOS transistor 438N are arranged in series between the power supply voltage Vdd and the ground voltage GND.

  The power supply voltage Vdd is supplied to the source terminal of the PMOS transistor 438P, and the ground voltage GND is supplied to the source terminal of the NMOS transistor 438N. The drain ends of the PMOS transistor 438P and the NMOS transistor 438N are connected in common, and the connection point is connected to the output terminal 5c. As a whole, a CMOS inverter is configured. The gate ends of the PMOS transistor 438P and the NMOS transistor 438N are connected in common, and the connection point is connected to the connection point between the PMOS transistor 434P and the load resistor 436.

When the output of the D-type flip-flop 402 is “H”, the voltage of the horizontal signal line 18 becomes the power supply voltage Vdd (= H level VH1) pulled up by the second level adjustment unit 415. For this reason, the PMOS transistor 434P is off, and the input of the CMOS inverter composed of the PMOS transistor 438P and the NMOS transistor 438N becomes the ground voltage GND. As a result, the PMOS transistor 438P is turned on, so that the output of the CMOS inverter becomes the power supply voltage Vdd, and the voltage information VHout corresponding to one (higher) voltage level for the subsequent circuit is output.

On the other hand, when the output of the D-type flip-flop 402 is “L”, the voltage of the horizontal signal line 18 becomes the third voltage level VL1 between the power supply voltage Vdd and the ground voltage GND. When the absolute value of the third voltage level VL1 exceeds the absolute value of the threshold voltage of the PMOS transistor 434P, the PMOS transistor 434P is turned on, so that the input of the CMOS inverter composed of the PMOS transistor 438P and the NMOS transistor 438N is the power source. The voltage becomes Vdd. As a result, the NMOS transistor 438N is turned on, so that the output of the CMOS inverter becomes the ground voltage GND, and the voltage information VLout corresponding to the other (lower) voltage level for the subsequent circuit is output.

  However, in the case of the configuration shown in FIG. 4B, the second amplitude level changing unit 416 can be configured more compactly than the configuration shown in FIG. 4A, but the threshold voltage is applied during the inverted output processing by the PMOS transistor 434P. As a result, there is a problem that the timing of the logic change is shifted as compared with the case of comparison processing and amplification processing centering on the midpoint potential (= threshold voltage Vbias1). For this reason, when there is a voltage change of the horizontal signal line 18 accompanying a signal change for each column, the determination cannot be made with a certain threshold value, and the noise resistance is lowered.

<First Embodiment: Second Example>
4B and 4C are diagrams illustrating a second example of the first embodiment. Here, FIG. 4B shows a third voltage level corresponding to one (lower) logic level of the data output from the D-type flip-flop 402 as in the second example shown in FIG. 2A (B). FIG. 4C is a circuit block diagram showing a configuration example in the case of changing to VL2, and FIG. 4C is a timing chart for explaining the operation.

  As shown in FIG. 4B (A), in the configuration of the second example of the first embodiment, first, the first level adjustment unit 414 of the data storage / transfer output unit 256 is connected between the inverter 412 and the horizontal signal line 18. A PMOS transistor 420P and an NMOS transistor 422N as a switch transistor having an analog switch function are included.

  The gate end of the NMOS transistor 422N is supplied with a column corresponding to the horizontal data transfer clocks φH_1 to φH_h from the horizontal scanning unit 12. In the PMOS transistor 420P, the output data of the inverter 412 is input to the gate terminal, the power supply voltage Vdd is supplied to the source terminal, and the drain terminal is connected to one input / output terminal (for example, the drain terminal) of the NMOS transistor 422N. The NMOS transistor 422N outputs the inverted output of the PMOS transistor 420P to the common horizontal signal line 18 side of each column under the control of the horizontal scanning unit 12.

The horizontal signal line 18 has an L level of the D flip-flop 402 with respect to the lower voltage level of the two voltage levels corresponding to the logic level of the data (information) output from the D flip-flop 402. A second level adjustment unit 415 that maintains the L level VL2 that is substantially the same voltage level as the voltage is connected. In the second example of the first embodiment, the second level adjustment unit 415 is used as a pull-down unit that maintains the potential of the horizontal signal line 18 at the ground voltage GND on the low potential side. The horizontal signal line 18 is previously pulled down to the ground voltage GND, and the horizontal signal line 18 is fixed at the ground voltage GND.

  Further, the second amplitude level changing unit 416 provided in the output circuit 28 is not non-inverted with a differential amplifier circuit 430 such as an operational amplifier similar to the first example of the first embodiment, as shown in FIG. 4B (A). A type output buffer 438 may be included. However, in the differential amplifier circuit 430 of the second example of the first embodiment, the horizontal signal line 18 is connected to the non-inverting input terminal (+), and the threshold voltage Vbias2 = (VH2−VL2) is connected to the inverting input terminal (−). / 2 + VL2 is supplied as a reference voltage.

  The differential amplifier circuit 430 has its voltage difference when the voltage value on the horizontal signal line 18 is higher than the threshold voltage Vbias2 due to the functions of the voltage comparator and the amplifier circuit (output as necessary). Amplifying to the H logic voltage level VHout for the post-stage circuit (by cooperating with the buffer 438), and when the voltage value on the horizontal signal line 18 is lower than the threshold voltage Vbias2, the voltage difference of its own is amplified by its own amplifying function. It amplifies to the L logic voltage level VLout for the subsequent circuit (by cooperating with the output buffer 438 as necessary).

  FIG. 4C shows a timing chart when “H” and “L” are alternately output from the i-th column when the configuration of the second example of the first embodiment is taken. As shown in the figure, since the voltage of the horizontal signal line 18 swings between the ground voltage GND and the third voltage level VL2, as compared with the case where it swings between the power supply voltage Vdd and the ground voltage GND as in the comparative example. The increase in power consumption can be prevented, and since the amplitude is small, there is no problem due to a decrease in slew rate. The horizontal transfer in the small amplitude operation between VL2 and VH2 enables low power consumption and high speed operation.

  When the L level is output, the pull-down function of the second level adjustment unit 415 always pulls down to the ground voltage GND (= VL2). When the H level is output, the PMOS transistor 420P provided for each column causes the third level. Pull up to voltage level VH2. The current value required for charging / discharging the horizontal signal line 18 which is a high load can be relaxed, and since there is no steady current path at the time of L level output, there is no power consumption by the horizontal signal line 18 and low power consumption. A horizontal transfer circuit to be driven can be provided. Since no through current flows at the transition from the H level (third voltage level VH2) at which the PMOS transistor 420P is turned off to the L level (VL2 = GND), there is an advantage of operating with lower power consumption than the comparative example. Similar to the first example of the first embodiment, it aims at low power consumption while improving high speed.

Further, as shown in FIG. 4B (A), as the second amplitude level changing unit 416, a differential amplifier circuit 430 such as an operational amplifier is used, which is a midpoint potential of voltage information that changes in VL2 to VH2 (VH2 -VL2) / 2 + VL2 as a threshold voltage Vbias2 and voltage information VLout which compares whether the voltage value on the horizontal signal line 18 is higher or lower than the threshold voltage Vbias2, corresponding to the voltage difference to a logical level for subsequent circuit, By amplifying to VHout, as in the first example of the first embodiment, even when there is a voltage change of the horizontal signal line 18 due to a signal change for each column, it can be determined with a constant threshold, so noise Resistance is improved.

As shown in FIG. 4B (B), the second amplitude level changing unit 416 provided in the output circuit 28 may include an NMOS transistor 434N and a load resistor 436 instead of the differential amplifier circuit 430 such as an operational amplifier. Good. The NMOS transistor 434N functions as an inverter. The ground voltage GND is supplied to the source terminal, the drain terminal is connected to one terminal of the load resistor 436, and the gate terminal outputs from the first amplitude level changing unit 410. Voltage information (VL2 to VH2) is supplied. A power supply voltage Vdd is supplied to the other terminal of the load resistor 436.

  Correspondingly, the output buffer 438 is not a non-inverting type, but an inverting type as shown in FIG. 4B (B). As an example, a PMOS transistor 438P and an NMOS transistor 438N are arranged in series between the power supply voltage Vdd and the ground voltage GND in the same manner as that shown in FIG. The gate ends of the PMOS transistor 438P and the NMOS transistor 438N are connected in common, and the connection point is connected to the connection point between the NMOS transistor 434N and the load resistor 436.

When the output of the D-type flip-flop 402 is “L”, the voltage of the horizontal signal line 18 becomes the ground voltage GND (= L level VL2) pulled down by the second level adjustment unit 415. Therefore, the NMOS transistor 434N is off, and the input of the CMOS inverter constituted by the PMOS transistor 438P and the NMOS transistor 438N becomes the power supply voltage Vdd. As a result, the NMOS transistor 438N is turned on, so that the output of the CMOS inverter becomes the ground voltage GND, and the voltage information VLout corresponding to the other (lower) voltage level for the subsequent circuit is output.

  On the other hand, when the output of the D-type flip-flop 402 is “H”, the voltage of the horizontal signal line 18 becomes the third voltage level VH2 between the power supply voltage Vdd and the ground voltage GND. The amount of voltage rise is determined by the drive current between the drain and source of the PMOS transistor 422P and the load resistance on the horizontal signal line 18 side.

In configuring the first level adjusting section 414, PMOS transistor in inversion transistors (in this example two voltage levels corresponding to logic levels of the data (information) output from the AD converter 25b and the D-type flip-flop 402 420P) has an advantage that one of the two voltage levels (H level in this example) can be easily converted to the third voltage level VH2.

When the third voltage level VH2 exceeds the threshold voltage of the NMOS transistor 434N, the NMOS transistor 434N is turned on, so that the input of the CMOS inverter constituted by the PMOS transistor 438P and the NMOS transistor 438N becomes the ground voltage GND. As a result, the POS transistor 438P is turned on, so that the output of the CMOS inverter becomes the power supply voltage Vdd, and the voltage information VHout corresponding to one (lower) voltage level for the subsequent circuit is output.

  However, in the case of the configuration shown in FIG. 4B (B), the second amplitude level changing unit 416 can be configured more compactly than the configuration shown in FIG. 4B (A), but the threshold voltage is applied during the inversion output processing by the NMOS transistor 434N. As a result, there is a problem that the timing of the logic change is shifted as compared with the case of comparison processing and amplification processing centered on the midpoint potential (= threshold voltage Vbias2). For this reason, when there is a voltage change of the horizontal signal line 18 accompanying a signal change for each column, the determination cannot be made with a certain threshold value, and the noise resistance is lowered.

If the first example and the second example of the first embodiment are compared, whether the NMOS transistor 422N is between the inverter 412 and the analog switch (NMOS transistor 422N or PMOS transistor 422P) that switches the output data string is PMOS. The basic difference is whether it is the transistor 422P (that is, whether it is an N-type transistor or a P-type transistor). Here, when comparing the N-type and the P-type, the N-type is generally superior in terms of drive capability and frequency characteristics. In terms of saying, as the first amplitude level changing unit 410 relates to a data output from the D-type flip-flop 402 as the data holding unit (latch circuit), inversion has been H inverter 412, L voltage level The lower voltage level side of the first example is considered to be superior to the first example in which the NMOS transistor 420N, which is an N-type transistor, is used to change to a third voltage level VL1 between the two voltage levels. It is done.

<Second Embodiment: First Example>
FIG. 5 is a diagram illustrating a first example of the second embodiment. Here, FIG. 5 is a circuit showing a configuration example when the L voltage level output from the D-type flip-flop 402 is changed to the third voltage level VL1 as in the first example shown in FIG. 2A (A). It is a block diagram.

  The mechanism of the first example of the second embodiment basically adopts the same configuration as that of the first example of the first embodiment shown in FIG. 4, and the second level adjustment unit 415 that functions as pull-up means. In order to fix the horizontal signal line 18 to the power supply voltage Vdd, it is pulled up using a PMOS transistor.

  Specifically, a second level adjustment unit 415 having PMOS transistors 440P and 442P and a constant current source 444 that are current mirror connected is provided between the horizontal signal line 18 and the power supply voltage Vdd. The power supply voltage Vdd is supplied to the source terminals of the PMOS transistors 440P and 442P, and the drain terminal of the PMOS transistor 440P is connected to the horizontal signal line 18. The gate ends of the PMOS transistors 440P and 440P and the drain end of the PMOS transistor 442P are commonly connected to one terminal of the constant current source 444, and the other terminal of the constant current source 444 is grounded.

  In the configuration of the second amplitude level changing unit 416 having the PMOS transistor 440P as a pull-up means, when the output data of a certain column is “H”, the voltage of the horizontal signal line 18 is set to the power supply voltage Vdd using the PMOS transistor 440P. Pull up to (= VH1). Further, when the output data of a certain column becomes “L”, the signal value “L” is pulled down by the NMOS transistor 420N driven by the inverter 412 connected to the output of the D-type flip-flop 402 of that column. Is transmitted. Of course, when the output data of a certain column is “H”, the NMOS transistor 420N is turned off, so that the signal value “H” is transmitted by pull-up by the PMOS transistor 440P.

In concretely configuring the pull-up means, if a MOS transistor is used, there is an advantage that it can be realized with a small area as compared with a third embodiment to be described later using a resistance element. In addition, since the driving capability of the PMOS transistor 440P can be utilized at the time of transition from the lower voltage level to the higher voltage level , the driving capability is higher than that of the resistance element.

  However, when a bias current from the constant current source 444 flows to the PMOS transistor 442P and the NMOS transistor 420N is turned on, a through current from the PMOS transistor 440P to the NMOS transistor 420N may flow through the PMOS transistor 422P (described later). Compared to the second and third examples of the second embodiment).

Although illustration is omitted, the mechanism of the first example of the second embodiment is one (higher) of data (information) output from the D-type flip-flop 402 as in the second example shown in FIG. 2A (B). also applicable to a case of changing the voltage level to the third voltage level VH2. In this case, a configuration similar to that of the second example of the first embodiment shown in FIG. 4B is adopted, and the second level adjustment unit 415 functioning as a pull-down means is used to fix the horizontal signal line 18 to the ground voltage GND. A configuration may be adopted in which a pair of NMOS transistors and a constant current source connected in a current mirror connection and a constant current source are provided and pulled down using the NMOS transistors.

<Second Embodiment: Second Example>
FIG. 5A is a diagram illustrating a second example of the second embodiment. Here, in FIG. 5A, as in the first example shown in FIG. 2A (A), the other (lower) voltage level of the data (information) output from the D-type flip-flop 402 is changed to the third voltage level VL1. It is a circuit block diagram which shows the structural example in the case of changing.

  The mechanism of the second example of the second embodiment is basically based on the first example of the second embodiment shown in FIG. 5 between the pull-up PMOS transistor 440P and the horizontal signal line 18. This is characterized in that a PMOS transistor 446P for switching and an inverter 448 for driving the gate terminal of the PMOS transistor 446P are provided. The PMOS transistor 446P has a gate terminal connected to the output terminal of the differential amplifier circuit 430, and is driven using the output of the differential amplifier circuit 430. Although the inverter 448 is interposed, the differential amplifier circuit 430 effectively controls on / off of the PMOS transistor 446P for switching. Unlike the third example of the second embodiment which will be described later, since the switch control is performed by self-excitation, there is an advantage that a functional unit for generating a control pulse for other excitation is not required.

  For example, when the voltage of the horizontal signal line 18 is at the “L” level, the output of the differential amplifier circuit 430 is also at the “L” level, so that the PMOS transistor 446P is turned off. In this way, when the NMOS transistor 422N in a certain column is turned on, it is possible to prevent a bias current from flowing due to the PMOS transistor 440P for pull-up being turned on, thereby preventing wasteful power consumption. Can do.

Although illustration is omitted, the mechanism of the second example of the second embodiment is one (higher) of data (information) output from the D-type flip-flop 402 as in the second example shown in FIG. 2A (B). This can also be applied to the case where the voltage level is changed to the third voltage level VH2. In this case, a configuration similar to that of the second example of the first embodiment shown in FIG. 4B is adopted, and the second level adjustment unit 415 functioning as a pull-down means is used to fix the horizontal signal line 18 to the ground voltage GND. , A pair of NMOS transistors and a constant current source connected in a current mirror, and pull-down using the NMOS transistors. A switching NMOS transistor that is turned off when the voltage of the horizontal signal line 18 is at “H” level is provided between the NMOS transistor and the horizontal signal line 18, and the gate end of the NMOS transistor is differentially amplified. A structure in which driving is performed based on the output of the circuit 430 may be employed.

<Second Embodiment: Third Example>
5B and 5C are diagrams illustrating a third example of the second embodiment. Here, in FIG. 5B, as in the first example shown in FIG. 2A (A), the other (lower) voltage level of the data (information) output from the D-type flip-flop 402 is changed to the third voltage level VL1. It is a circuit block diagram which shows the structural example in the case of changing. FIG. 5C is a timing chart for explaining the operation.

  The mechanism of the third example of the second embodiment is basically based on the second example of the second embodiment shown in FIG. 5A. The PMOS transistor 446P for switching is used as the output of the differential amplifier circuit 430. It is characterized in that it can be controlled independently without using it.

  Specifically, as illustrated, an inverter 449 is provided in the same manner as the inverter 448 of the second example, and a control pulse generator 450 for controlling the inverter 449 is provided outside the output circuit 28. The control pulse generator 450 generates a control pulse φf for driving the gate terminal of the PMOS transistor 446P. Although the inverter 449 is interposed, in effect, the control pulse generator 450 controls on / off of the PMOS transistor 446P for switching. Unlike the second example of the second embodiment described above, the switch control is performed by separate excitation, so that it is possible to use the control pulse by utilizing the degree of freedom in generating the control pulse.

  As shown in FIG. 5C, the control pulse φf generated by the control pulse generator 450 is such that the switching PMOS transistor 446 is turned on only during the last certain period of the output period of the column. In this way, the pull-up PMOS transistor 446P can be turned off until the voltage value of the horizontal signal line 18 is determined. When the output of a certain column is “L”, the third NMOS transistor 422N Since the voltage level VL1 can be easily output, the power consumption can be further reduced.

Although illustration is omitted, the mechanism of the third example of the second embodiment is one (higher) of data (information) output from the D-type flip-flop 402 as in the second example shown in FIG. 2A (B). This can also be applied to the case where the voltage level is changed to the third voltage level VH2. In this case, a configuration similar to that of the second example of the first embodiment shown in FIG. 4B is adopted, and the second level adjustment unit 415 functioning as a pull-down means is used to fix the horizontal signal line 18 to the ground voltage GND. , A pair of NMOS transistors and a constant current source connected in a current mirror, and pull-down using the NMOS transistors. Then, a switching NMOS transistor may be provided between the NMOS transistor and the horizontal signal line 18, and a control unit for generating a control pulse for on / off control of the NMOS transistor may be provided. The control unit may turn on the NMOS transistor for switching only for a certain period at the end of the output period of the column.

<Third Embodiment>
FIG. 6 is a diagram for explaining the third embodiment. Here, in FIG. 6, as in the first example shown in FIG. 2A (A), the other (lower) voltage level of the data (information) output from the D-type flip-flop 402 is changed to the third voltage level VL1. It is a circuit block diagram which shows the structural example in the case of changing.

  The mechanism of the third embodiment basically adopts the same configuration as that of the first example of the first embodiment shown in FIG. 4, and more specifically the second level adjustment unit 415 that functions as pull-up means. In order to fix the horizontal signal line 18 to the power supply voltage Vdd, it is pulled up using a resistance element.

  Specifically, a resistance element 460 is provided between the horizontal signal line 18 and the power supply voltage Vdd near the non-inverting input side of the differential amplifier circuit 430. The resistance element 460 may be of any type, such as a diffusion resistance or a wiring resistance. When the resistance element 460 is used as the pull-up means, there is an advantage that a circuit such as the constant current source 444 necessary for each example of the second embodiment using the PMOS transistor 440P is unnecessary.

  Of course, even when the resistance element 460 is used, a mode in which a PMOS transistor 446P for switching is inserted between the horizontal signal line 18 and the resistance element 460 as in the second and third examples of the second embodiment. Can be taken.

Although illustration is omitted, the mechanism of the third example of the second embodiment is one (higher) of data (information) output from the D-type flip-flop 402 as in the second example shown in FIG. 2A (B). This can also be applied to the case where the voltage level is changed to the third voltage level VH2. In this case, a configuration similar to that of the second example of the first embodiment shown in FIG. 4B is adopted, and the second level adjustment unit 415 functioning as a pull-down means is used to fix the horizontal signal line 18 to the ground voltage GND. A resistive element may be provided between the horizontal signal line 18 and the ground voltage GND.

<Fourth embodiment>
7 and 7A are diagrams illustrating the fourth embodiment. FIG. 7 is a circuit block diagram showing a configuration example of the fourth embodiment. FIG. 7A is a timing chart for explaining the operation.

  The mechanism of the fourth embodiment basically adopts the same configuration as that of the first example or the second example of the first embodiment shown in FIG. 4 and is provided with a level shift unit 418, and its level. The shift unit 418 is more specifically configured.

  In this example, a source follower circuit is used as the level shift unit 418. Specifically, NMOS transistors 470N and 472N connected in cascade are provided between the horizontal signal line 18 and the non-inverting input terminal (+) of the differential amplifier circuit 430. The NMOS transistor 470N has a gate terminal connected to the horizontal signal line 18, and a drain terminal supplied with the power supply voltage Vdd. The source terminal of the NMOS transistor 470N and the drain terminal of the NMOS transistor 472N are connected, and the connection point is connected to the non-inverting input terminal (+) of the differential amplifier circuit 430. The source of the NMOS transistor 472N is grounded, and the bias voltage Vb is supplied to the gate end.

  In such a configuration, the operation reference voltage at the connection point where the source terminal of the NMOS transistor 470N and the drain terminal of the NMOS transistor 472N are connected is defined by the drive current based on the bias voltage Vb of the NMOS transistor 472N. In this example, the bias voltage Vb is set so that the operation reference voltage is just an intermediate level between the power supply voltage Vdd of the differential amplifier circuit 430 and the ground voltage GND.

By doing so, the other (lower) voltage level of the data (information) output from the D-type flip-flop 402 is changed to the third voltage level VL1 as in the first example shown in FIG. 2A (A). In this case, the amplitude (VH1−VL1) of the voltage (VL1 to VH1) of the horizontal signal line 18 that is offset from the power supply voltage Vdd output from the first amplitude level changing unit 410 is substantially maintained. In this state, the third voltage level corresponding to the lower voltage level (L level) is shifted to VL3, the voltage level VH1 corresponding to the higher voltage level (H level) is shifted to VH3, and changes in VL3 to VH3. In addition to the voltage information, the midpoint potential “(VH3−VL3) / 2 + VL3” is just an intermediate level between the power supply voltage Vdd and the ground voltage GND. That is, the level shift unit 418 shifts the potential (VL1 to VH1) that is offset toward the power supply voltage Vdd side to another intermediate voltage (VL3 to VH3) using the source follower circuit.

Although not shown, the level shift unit 418 may be configured by using a source follower circuit having two cascaded PMOS transistors as a circuit having a dual relationship with the cascaded NMOS transistors 470N and 472N. Is possible. In this case, when one (higher) voltage level of data (information) output from the D-type flip-flop 402 is changed to the third voltage level VH2 as in the second example shown in FIG. 2A (B). Is the voltage (VL2 to VH2) of the horizontal signal line 18 that is offset from the ground voltage GND output from the first amplitude level changing unit 410 while the amplitude (VH2−VL2) is substantially maintained. The third voltage level corresponding to the higher voltage level (H level) is shifted to VH3, the voltage level VL2 corresponding to the lower voltage level (L level) is shifted to VL3, and the voltage varies between VL3 and VH3. In addition to information, the midpoint potential “(VH3−VL3) / 2 + VL3” is just an intermediate level between the power supply voltage Vdd and the ground voltage GND. That is, the level shift unit 418 shifts the potential (VL2 to VH2) that is offset toward the ground voltage GND side to another intermediate voltage (VL3 to VH3) using the source follower circuit.

The differential amplifier circuit 430 of the second amplitude level changing unit 416 uses “(VH3−VL3) / 2 + VL3”, which is the midpoint potential of the voltage information that changes in VL3 to VH3, as the threshold voltage Vbias3 on the horizontal signal line 18. Compares whether the voltage value is higher or lower than the threshold voltage Vbias3, and amplifies the voltage difference to the voltage levels VLout and VHout for the subsequent circuit by an amplification function (by cooperating with the output buffer 438 if necessary) To do.

FIG. 7A shows a timing chart when “H” and “L” are alternately output from the i-th column when the configuration of the fourth embodiment is adopted. Here, as in the first example shown in FIG. 2A, the other (lower) voltage level of data (information) output from the D-type flip-flop 402 is changed to the third voltage level VL1. Show.

  As shown in the figure, first, the first amplitude level changing section 410 causes the voltage of the horizontal signal line 18 to swing between the power supply voltage Vdd (= VH1) and the third voltage level VL1. By passing through the source follower circuit 418, it is possible to shift to another intermediate voltage (VL3 to VH3).

  In particular, by adjusting the drive current of the NMOS transistor 472N, the midpoint potential “(VH3−VL3) / 2 + VL3” of the intermediate voltage (VL3 to VH3) is set near the midpoint of the power supply voltage Vdd and the ground voltage GND. Can be shifted. In this case, the differential amplifier circuit 430 of the second amplitude level changing unit 416 can operate near the midpoint between the power supply voltage Vdd and the ground voltage GND, and thus has an advantage of facilitating comparison processing and amplification processing.

  Also, the amplitude of the symmetrical voltage (VL3 to VH3) near the midpoint can be amplified symmetrically with the low potential side VLout as the ground voltage GND and the high potential side VHout as the power supply voltage Vdd. The accuracy of the data change timing is increased as compared with the case where the level shift unit 418 is not provided.

  Furthermore, since a source follower circuit is used as the level shift unit 418, impedance conversion is performed, so that it becomes easier to drive the differential amplifier circuit 430 than the horizontal signal line 18 without providing the level shift unit 418. .

  In the present embodiment, the level shift unit 418 is configured by the source follower circuit at the input stage of the differential amplifier circuit 430 forming the second amplitude level changing unit 416. However, the function of the level shift unit 418 is It is also possible to adopt a configuration in which the two amplitude level changing unit 416 is incorporated. For example, by performing level shift in the process of comparison processing and amplification processing, amplification in the subsequent stages can be facilitated.

<Fifth Embodiment>
8 to 8B are diagrams illustrating the fifth embodiment. Here, FIG. 8 is a circuit block diagram showing a configuration example of the fifth embodiment. FIG. 8A is a circuit diagram illustrating a detailed configuration example of the differential amplifier circuit 430 of the fifth embodiment. FIG. 8B is a timing chart for explaining the operation.

  The mechanism of the fifth embodiment is characterized in that the voltage (VL3 to VH3) after the level shift by the level shift unit 418 is binarized by a clock comparator based on the fourth embodiment shown in FIG.

  Therefore, a control pulse generator 480 that generates a control pulse φg for controlling the differential amplifier circuit 430 in clock synchronization is provided outside the output circuit 28. The control pulse generator 480 supplies a control pulse φg for performing comparison processing in synchronization with the clock to the differential amplifier circuit 430. The voltage comparison function unit of the differential amplifier circuit 430 of the present embodiment is a clock comparator that performs comparison processing based on the control pulse φg.

Although details will be described later, when the differential amplifier circuit 430 is configured as a clock comparator, the output signal is a voltage after level shift by the level shift unit 418 when the control pulse φg is at an active level (for example, a higher voltage level ). The voltage levels VLout (≈GND) and VHout (≈Vdd) according to (one of VL3 and VH3), but when the control pulse φg is at the inactive level (for example, the lower voltage level ), the voltage level VLout, Since it becomes an appropriate voltage between VHout and becomes an output signal different from those in the first to fourth embodiments, a signal interface with a subsequent circuit may be a problem.

  Correspondingly, the output buffer 438 is included in the second amplitude level changing unit 416, and the signal output from the differential amplifier circuit 430 having the clock comparator configuration is converted into the normal data output format in the output buffer 438. A function should be provided. Note that the function unit for converting to the normal data output format may be provided not in the output buffer 438 but in a subsequent circuit.

  As an example, a D-type flip-flop as an output data generation unit that generates digital data for a subsequent circuit by holding (latching) the output signal of the differential amplifier circuit 430 in synchronization with the falling edge of the control pulse φg It is good to have a configuration comprising Alternatively, as shown in the figure, output data generation for generating digital data for the subsequent circuit by holding (latching) the output signal of the differential amplifier circuit 430 using another control pulse φck synchronized with the control pulse φg A D-type flip-flop 439 as a part may be provided.

  In the former configuration, the hold margin of the D-type flip-flop cannot be secured, and there is a possibility of malfunction. In contrast, in the latter configuration shown in the figure, the clock (control pulse φck) of the D-type flip-flop 439 is delayed by about π / 2 to π with respect to the clock (control pulse φg) of the clock comparator. A hold margin can be secured.

  Specifically, as shown in FIG. 8A, the differential amplifier circuit 430 of the fifth embodiment having a clock comparator configuration includes a first circuit block 482_1 and a second circuit block 482_1 that adopt a positive feedback configuration. It consists of a combination. In the following description, when describing each circuit block, each component member, node, signal, etc. is shown with reference symbols “_1” and “_2” for each circuit block. The reference is shown without a reference for each circuit block.

  The circuit blocks 482_1 and 482_2 are supplied with the same power supply voltage Vdd and ground voltage GND as the power supply voltage Vdd and ground voltage GND supplied to the logic circuit such as the D-type flip-flop 402.

  The first circuit block 482_1 includes a differential input node IN_1 and a differential output node OUT_1, and the second circuit block 482_2 includes a differential input node IN_2 and a differential output node OUT_2. The differential input node IN_1 is connected to the connection point of the NMOS transistors 470N and 472N forming the source follower circuit, and is supplied with information on an intermediate voltage (VL3 to VH3) having a threshold voltage Vbias3 of “(VH3−VL3) / 2 + VL3”. Is done. The differential input node IN_1 corresponds to the non-inverting input terminal (+) of the differential amplifier circuit 430, and the differential input node IN_2 corresponds to the inverting input terminal (−) of the differential amplifier circuit 430.

  The differential amplifier circuit 430 of the fifth embodiment includes NMOS transistors 484N and 486N that are cascade-connected to form a source follower circuit on the differential input node IN_2 side, similarly to the differential input node IN_1 side. In the NMOS transistor 484N, a predetermined bias voltage Vbias is supplied to the gate terminal, and the power supply voltage Vdd is supplied to the drain terminal. The source end of the NMOS transistor 484N and the drain end of the NMOS transistor 486N are connected, and the connection point is connected to the differential input node IN_2. The NMOS transistor 486N has a source terminal grounded and a gate terminal supplied with the bias voltage Vb in common with the NMOS transistor 472N.

  The operation reference voltage at the connection point where the source terminal of the NMOS transistor 484N and the drain terminal of the NMOS transistor 486N are connected is defined by the drive current based on the bias voltage Vb of the NMOS transistor 486N. In this example, the operation reference voltage is just the intermediate level between the power supply voltage Vdd of the differential amplifier circuit 430 and the ground voltage GND, and is the midpoint potential of the voltage information changing from VL3 to VH3 “(VH3−VL3)”. Bias voltages Vb and Vbias are set so that / 2 + VL3 "= threshold voltage Vbias3.

  In the first circuit block 482_1, information on the intermediate voltages (VL3 to VH3) output from the connection point of the NMOS transistors 470N and 472N forming the source follower circuit is supplied to the gate terminal (control input) via one differential input node IN_1. A PMOS transistor 490_1 having a source connected to the power supply voltage Vdd and a drain (output terminal of the transistor) connected to one differential output node OUT_1.

  The first circuit block 482_1 includes an NMOS transistor 492_1 whose gate is supplied with the feedback signal SFB_2 from the differential output node OUT_2 of the second circuit block 482_2 and whose drain is connected to the drain of the PMOS transistor 490_1.

  The second circuit block 482_2 is basically different from the second circuit block 482_2 in that the information (bias input signal Vin_2) output from the connection point of the NMOS transistors 484N and 486N forming the source follower circuit is used as an input signal. The same configuration as that of one circuit block 482_1.

  For example, in the second circuit block 482_2, the bias input signal Vin_2 is input to the gate via the other differential input node IN_2, the source is connected to the power supply voltage Vdd, and the drain (output terminal of the transistor) is the difference between the other. A PMOS transistor 490_2 connected to the dynamic output node OUT_2 is provided.

  In addition, the second circuit block 482_2 includes an NMOS transistor 492_2 whose gate receives the feedback signal SFB_1 from the differential output node OUT_1 of the first circuit block 482_1 and whose drain is connected to the drain of the transistor 490_2.

The differential amplifier circuit 430 of the fifth embodiment further includes an NMOS transistor 494N that is commonly used as a bias circuit for the first and second circuit blocks 482_1 and 482_2. The NMOS transistor 494N has a drain end connected in common to the source ends of the transistors 492_1 and 492_2, a source end supplied with the ground voltage GND, and a gate end supplied with the control pulse φg from the control pulse generator 480. . The NMOS transistor 494N can pass a bias current to the first and second circuit blocks 482_1 and 482_2 only when the control pulse φg is at the higher voltage level .

  As can be seen, the differential amplifier circuit 430 of the fifth embodiment has a differential input interface at its input stage, and the input signals (intermediate voltages (VL3 to VH3) information) are connected to the gates of the transistors 490_1 and 490_2. And a bias input signal Vin_2), the output stage has a positive positive feedback loop.

  Output pulse signals corresponding to information on the intermediate voltages (VL3 to VH3) are obtained in a complementary relationship at the output terminals (drains) of the transistors 490_1 and 490_2. In this example, the information on the drain end of the transistor 490_2 is supplied as it is to the differential output node OUT_2 as the output signal Vout. The differential output node OUT_2 is connected to the input of the output buffer 438.

FIG. 8B shows a timing chart when “H” and “L” are alternately output from the i-th column when the configuration of the fifth embodiment is adopted. As shown in FIG. 8B, the control pulse φg generated by the control pulse generation unit 480 has a lower voltage level (L level) after the voltage at the non-inverting input terminal (+) of the differential amplifier circuit 430 is level-shifted. is supplied to the gate terminal of the NMOS transistor 494N of the differential amplifier circuit 430 the higher voltage level when in the voltage VH3 corresponding to the voltage level of the voltage VL3 or higher corresponding (H level), the threshold voltage Vbias3 Is used as a reference voltage for comparison processing.

As described above, NMOS transistor 494N, since the first and second circuit blocks 482_1,482_2 only when the control pulse φg is higher voltage level can flow a bias current, who control pulse φg is high The voltage VL3 corresponding to the lower voltage level (L level) after the level shift or the higher voltage level (H level) only when the voltage level of the non-inverting input terminal (+) is Only when the voltage VH3 is present, an effective comparison process is actually performed.

For example, when the voltage of the input signal Vin_1 to the PMOS transistor 490_1 of the first circuit block 482_1 is on the VH3 side when the control pulse φg is at the higher voltage level , the PMOS transistor 490_2 of the second circuit block 482_2 Input signal Vin_2 = “(VH3−VL3) / 2 + VL3” = the voltage of the input signal Vin_1 is larger than the threshold voltage Vbias3, the PMOS transistor 490_1 is turned off, and the voltage of the differential output node OUT_1 as its drain is grounded. It is assumed that the voltage is at GND and the PMOS transistor 490_2 is in the ON state, and the voltage of the differential output node OUT_2 as its drain is at the power supply voltage Vdd.

  At this time, the NMOS transistor 492_2 has its gate at the voltage of the differential output node OUT_1 = the ground voltage GND and is in the off state, so that the voltage of the differential output node OUT_2 which is the output of the PMOS transistor 490_2 in the off state. Becomes the same potential as the power supply voltage Vdd. Further, since the NMOS transistor 492_1 has the gate at the voltage of the differential output node OUT_2 = the power supply voltage Vdd and is in the on state, the voltage of the differential output node OUT_1 which is the output of the PMOS transistor 490_1 in the off state is It becomes the same potential as the ground voltage GND.

  In this state, the drain current Ids_1 of the PMOS transistor 490_1 does not flow, but the drain current Ids_2 of the PMOS transistor 490_2 is in a non-saturated state.

Next, in a period in which the voltage of the input signal Vin_1 of the PMOS transistor 490_1 is on the VL3 side, the NMOS transistor 494N is first turned off until the control pulse φg reaches the higher voltage level, and the first and second circuits. No bias current is supplied to the blocks 482_1 and 482_2. For this reason, the voltages of the differential output nodes OUT_1 and OUT_2 become an appropriate voltage Voff between the ground voltage GND and the power supply voltage Vdd.

Next, when the control pulse φg reaches the higher voltage level , the NMOS transistor 494N causes a bias current to flow through the first and second circuit blocks 482_1 and 482_2, and thus the first and second circuit blocks. The comparison processing in 482_1 and 482_2 becomes functional.

  At this time, since the voltage of the input signal Vin_1 is VL3, the PMOS transistor 490_1 is turned on. In the process of turning on the PMOS transistor 490_1, the PMOS transistor 490_2 is initially in the on state. When the PMOS transistor 490_1 is turned on, the NMOS transistor 492_2 remains in the off state or is in the process of being shifted to the on state for a while depending on the on state of the PMOS transistor 490_1. The potential slowly decreases from the previous voltage Voff to a value obtained by dividing the power supply voltage Vdd by the operating resistance of the NMOS transistor 492_2 and the ON resistance of the PMOS transistor 490_2.

  The voltage at the differential output node OUT_2, which is the drain output of the PMOS transistor 490_2, becomes the gate voltage of the NMOS transistor 492_1, and the gate voltage drops from the voltage Voff, becomes lower than the threshold voltage of the NMOS transistor 492_1, and turns off the NMOS transistor 492_1. When the state is allowed to be changed, the NMOS transistor 492_1 transits from the saturated state to the non-saturated state. In this state, since the PMOS transistor 490_1 is in the on state, the voltage of the differential output node OUT_1 that is the output rises from the voltage Voff. Then, as the voltage of the differential output node OUT_1 increases, the NMOS transistor 492_2 shifts to the on state.

  By continuing such an operation, the voltage of the differential output node OUT_2 rapidly changes from the voltage Voff to the ground voltage GND, and the voltage of the differential output node OUT_1 rapidly changes from the voltage Voff to the power supply voltage Vdd. Thus, the comparison operation ends.

  Even when the voltage of the input signal Vin_1 changes from VL3 to VH3, the same operation as described above is performed in the reverse block transistor.

As is apparent from the figure, when the differential amplifier circuit 430 has a clock comparator configuration, its output signal is at the voltage levels VLout (≈GND) and VHoutt (≈Vdd) when the control pulse φg is active H. When the control pulse φg is inactive L, an appropriate voltage Voff between the voltage levels VLout and VHout is obtained, which is an output signal different from those in the first to fourth embodiments.

Therefore, in the output buffer 438, the output signal of the differential amplifier circuit 430 is latched by the D-type flip-flop 439 at the rising edge of the control pulse φck whose rising timing is slightly delayed with respect to the control pulse φg. In this way, the data output timing is relatively shifted, but the signal output from the differential amplifier circuit 430 having the clock comparator configuration normally indicates only the voltage levels VLout and VHout without the voltage Voff period. Is converted to the data output format.

As described above, when the differential amplifier circuit 430 has a clock comparator configuration that operates based on the control pulses φg and φck, when the voltage of the input signal Vin_1 changes from VL3 to VH3 and from VH3 to VL3. Are excluded from the comparison process , and the voltage VL3 corresponding to the lower voltage level (L level) after the level shift or the higher voltage is surely applied to the non-inverting input terminal (+) of the differential amplifier circuit 430. Is compared with the threshold voltage Vbias3 as a reference voltage when the voltage is at a voltage VH3 corresponding to the voltage level (H level), and the voltage difference is amplified by an amplification function (by cooperating with the output buffer 438 as necessary). Thus, it is possible to amplify up to voltage levels VLout and VHout for the subsequent circuit.

In addition, by using the clock comparator, the actually effective comparison process is performed only during the period of the higher voltage level of the control pulse φg, so that the power consumption can be reduced. Furthermore, when the voltage of the input signal Vin_1 changes from VL3 to VH3 and when it changes from VH3 to VL3, the transition period is largely excluded, and when the voltage is more reliably at VL3 or VH3, the higher of the control pulse φg Since the voltage level period is used, it is possible not only to always make a determination with a constant threshold value, but also to realize a comparison process with excellent noise resistance.

<Imaging device>
FIG. 9 is a diagram illustrating a schematic configuration of an imaging apparatus (camera system) that is an example of a physical information acquisition apparatus that uses a mechanism similar to that of the solid-state imaging apparatus 1 of the present embodiment described above. The imaging device 8 is an imaging device that obtains a visible light color image.

  Specifically, the imaging device 8 includes a photographing lens 802 that guides light L carrying an image of the subject Z under the light source 801 such as sunlight or a fluorescent lamp to the imaging device side, and an optical lens. A low-pass filter 804, a color filter group 812 in which, for example, R, G, and B color filters are arranged in a Bayer array, a pixel array unit 10, a drive control unit 7 that drives the pixel array unit 10, and a pixel array unit 10 A column processing unit 26 that performs CDS processing, AD conversion processing, and the like on the pixel signal output from, and a camera signal processing unit 810 that processes imaging data output from the column processing unit 26.

The camera signal processing unit 810 includes an imaging signal processing unit 820 and a camera control unit 900 that functions as a main control unit that controls the entire imaging apparatus 8. The imaging signal processing unit 820 outputs a digital imaging signal supplied from the column AD circuit 25b (see FIG. 1) of the column processing unit 26 as R (red), when a color filter other than the primary color filter is used. G (green), B
A signal separation unit 822 having a primary color separation function that separates into (blue) primary color signals, and a color signal that performs signal processing on the color signal C based on the primary color signals R, G, and B separated by the signal separation unit 822 And a processing unit 830.

  The imaging signal processing unit 820 also converts the luminance signal Y / color signal C into a luminance signal processing unit 840 that performs signal processing on the luminance signal Y based on the primary color signals R, G, and B separated by the signal separation unit 822. And an encoder unit 860 that generates a video signal VD based on the encoder 860.

  The camera control unit 900 of the present embodiment is a microprocessor that forms the center of an electronic computer whose representative example is a CPU (Central Processing Unit) in which calculation and control functions performed by a computer are integrated into an ultra-small integrated circuit. 902, a ROM (Read Only Memory) 904 that is a read-only storage unit, a RAM (Random Access Memory) 906 that is an example of a volatile storage unit that can be written and read at any time, and others that are not illustrated The peripheral member is included. The microprocessor 902, the ROM 904, and the RAM 906 are collectively referred to as a microcomputer.

  In the above description, the “volatile storage unit” means a storage unit in which the stored contents are lost when the power of the apparatus is turned off. On the other hand, the “nonvolatile storage unit” means a storage unit in a form that keeps stored contents even when the main power supply of the apparatus is turned off. Any memory device can be used as long as it can retain the stored contents. The semiconductor memory device itself is not limited to a nonvolatile memory device, and a backup power supply is provided to make a volatile memory device “nonvolatile”. You may comprise as follows.

  The camera control unit 900 controls the entire system. The ROM 904 stores a control program for the camera control unit 900. In this example, in particular, the camera control unit 900 stores a program for setting on / off timings of various control pulses. The RAM 906 stores data for the camera control unit 900 to perform various processes.

  The camera control unit 900 is configured so that a recording medium 924 such as a memory card can be inserted and removed, and can be connected to a communication network such as the Internet. For example, the camera control unit 900 includes a memory reading unit 907 and a communication I / F (interface) 908 in addition to the microprocessor 902, the ROM 904, and the RAM 906.

  The recording medium 924 includes, for example, program data for causing the microprocessor 902 to perform software processing, a convergence range of the photometric data DL based on the luminance system signal from the luminance signal processing unit 840, and exposure control processing (including electronic shutter control). It is used for registering data such as various set values such as on / off timing of various control pulses for the purpose.

  The memory reading unit 907 stores (installs) the data read from the recording medium 924 in the RAM 906. The communication I / F 908 mediates transfer of communication data with a communication network such as the Internet.

  In addition, although such an imaging device 8 shows the drive control unit 7 and the column processing unit 26 in a module form separately from the pixel array unit 10, as described for the solid-state imaging device 1, Needless to say, the one-chip solid-state imaging device 1 integrally formed on the same semiconductor substrate as the pixel array unit 10 may be used.

  In the figure, in addition to the pixel array unit 10, the drive control unit 7, the column processing unit 26, and the camera signal processing unit 810, an optical system such as a photographing lens 802, an optical low-pass filter 804, or an infrared light cut filter 805 is provided. In this state, the imaging device 8 is shown. This aspect is suitable for a module-like form having an imaging function packaged together.

  Here, in relation to the modules in the solid-state imaging device 1 described above, as shown in the figure, the pixel array unit 10 (imaging unit), the column processing unit 26 having an AD conversion function and a difference (CDS) processing function, and the like A solid-state imaging device in the form of a module having an imaging function in a state where signal processing units closely related to the pixel array unit 10 side (excluding the camera signal processing unit following the column processing unit 26) are packaged together 1 is provided, and a camera signal processing unit 810, which is the remaining signal processing unit, is provided in the subsequent stage of the solid-state imaging device 1 provided in the module form so that the entire imaging device 8 is configured. Also good.

  Alternatively, although not shown, the solid-state imaging device 1 is provided in a modular form having an imaging function in a state where the pixel array unit 10 and the optical system such as the photographing lens 802 are packaged together. In addition to the solid-state imaging device 1 provided in the form of a module, a camera signal processing unit 810 may be provided in the module to constitute the entire imaging device 8.

  Further, as a module form in the solid-state imaging device 1, a camera signal processing unit 810 corresponding to the camera signal processing unit 200 may be included. In this case, the solid-state imaging device 1 and the imaging device 8 are practically the same. It can also be regarded as a thing.

  Such an imaging device 8 is provided as a portable device having an imaging function, for example, for performing “imaging”. Note that “imaging” includes not only capturing an image during normal camera shooting but also includes fingerprint detection in a broad sense.

  The imaging device 8 having such a configuration is configured to include all the functions of the solid-state imaging device 1 described above, and can be the same as the basic configuration and operation of the solid-state imaging device 1 described above. By applying any one of the above-described embodiments as the data storage / transfer output unit 256 and the output circuit 28, the problem caused by the load capacity on the horizontal signal line 18 in the horizontal data transfer can be solved.

It is a schematic block diagram of the CMOS solid-state imaging device which is one Embodiment of the solid-state imaging device concerning this invention. FIG. 2 is a circuit block diagram showing a basic configuration of a column processing unit (particularly around a data storage / transfer output unit) and an output circuit shown in FIG. 1. FIG. 3 is a voltage level diagram for explaining a basic operation of the configuration shown in FIG. 2. FIG. 3 is a circuit block diagram illustrating a configuration example of a comparative example with respect to the configuration illustrated in FIG. 2. FIG. 4 is a voltage level diagram (part 1) for explaining the operation of the comparative example shown in FIG. 3; FIG. 4 is a voltage level diagram (part 2) for explaining the operation of the comparative example shown in FIG. 3; It is a circuit block diagram showing an example of composition of the 1st example of a 1st embodiment. It is a timing chart explaining operation | movement of the 1st example of 1st Embodiment. It is a circuit block diagram which shows the structural example of the 2nd example of 1st Embodiment. It is a timing chart explaining operation of the 2nd example of a 1st embodiment. It is a circuit block diagram which shows the structural example of the 1st example of 2nd Embodiment. It is a circuit block diagram which shows the structural example of the 2nd example of 2nd Embodiment. It is a circuit block diagram which shows the structural example of the 3rd example of 2nd Embodiment. It is a timing chart explaining operation of the 3rd example of a 2nd embodiment. It is a circuit block diagram which shows the structural example of 3rd Embodiment. It is a circuit block diagram which shows the structural example of 4th Embodiment. It is a timing chart explaining operation of a 4th embodiment. It is a circuit block diagram which shows the structural example of 5th Embodiment. It is a circuit diagram which shows the detailed structural example of the differential amplifier circuit of 5th Embodiment. It is a timing chart explaining operation of a 5th embodiment. It is a figure which shows schematic structure of the imaging device which is an example of the physical information acquisition apparatus using the structure similar to the solid-state imaging device of this embodiment.

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 10 ... Pixel array part, 12 ... Horizontal scanning part, 14 ... Vertical scanning part, 18 ... Horizontal signal line, 19 ... Vertical signal line, 20 ... Communication / timing control part, 23 ... Clock conversion part, 24 ... Read current control unit, 25 ... Column AD circuit, 25a ... Difference processing unit, 25b ... AD conversion unit, 256 ... Data storage / transfer output unit, 258 ... Switch, 26 ... Column processing unit, 27 ... Reference signal generation unit 27a ... DA converter circuit, 28 ... output circuit, 3 ... unit pixel, 402 ... D-type flip-flop, 404 ... transfer driver, 410 ... first amplitude level changing unit, 412 ... inverter, 414 ... first level adjusting unit, 415: second level adjustment unit, 416: second amplitude level changing unit, 418 ... level shift unit, 430 ... differential amplifier circuit, 438 ... output buffer, 439 ... D-type flip-flop Flop, 450 ... control pulse generating unit, 460 ... resistance element 480 ... control pulse generating unit, 7 ... drive control unit, 8 ... imaging apparatus, 900 ... camera control unit

Claims (15)

A pixel portion in which unit pixels are arranged; and
An AD converter that converts an analog pixel signal read from each unit pixel of the pixel unit into digital data;
A first amplitude level changing unit that changes one of the two voltage levels corresponding to the logic level of the digital data output from the AD conversion unit to a third voltage level between the two voltage levels ;
A horizontal scanning unit for transferring information output from the first amplitude level changing unit to a common signal line;
A second amplitude level changing unit for changing information whose amplitude level has been changed by the first amplitude level changing unit to a logic level for a subsequent circuit ;
With a solid-state imaging device. In the pixel portion, the unit pixels are arranged in a matrix,
A vertical scanning unit that reads an analog pixel signal from each unit pixel of the pixel unit;
The AD conversion unit is provided for each column with respect to the pixel unit .
The solid-state imaging device according to 請 Motomeko 1. The first amplitude level changing unit includes:
The two voltage levels of the digital data output from the AD converter and the transistor to invert,
Under the control of the horizontal scanning unit, a switch transistor that outputs an inverted output of the transistor to the signal line side common to the columns ;
Having,
The solid-state imaging device according to 請 Motomeko 1. First amplitude level changing unit, out of the two voltage levels of the digital data output from the AD conversion unit, to change the lower the voltage level of the third voltage level,
The solid-state imaging device according to 請 Motomeko 1. The first amplitude level changing unit includes:
Has a first level adjusting unit for changing to the third voltage level between one of said two voltage levels of the two voltage levels for each column,
A second level adjustment unit common to each column for maintaining the other of the two voltage levels at the same voltage level ;
The solid-state imaging device according to 請 Motomeko 1. The second level adjusting section is maintained at a low voltage corresponding to the voltage level of the lower of the pull-up means or the two voltage levels to maintain the high voltage corresponding to the voltage level of the higher of the two voltage levels with a pull-down means that,
The solid-state imaging device according to 請 Motomeko 5. The pull-up means and the pull-down means are composed of transistors .
Solid-state imaging device according to 請 Motomeko 6. The pull-up means and the pull-down means are composed of resistance elements ,
The solid-state imaging device according to 請 Motomeko 6. Wherein said pull-up means and said pull-down means between the columns common signal line, the switch transistor that operates on or off is provided,
The solid-state imaging device according to 請 Motomeko 6. It said second amplitude level changing section controls the operation of the on or off the switching transistor based on its own output signal,
The solid-state imaging device according to 請 Motomeko 9. With a control pulse generator for generating a control pulse for controlling the operation of the on or off the switching transistor,
The solid-state imaging device according to 請 Motomeko 9. Between the signal line common to each column and the second amplitude level changing unit, the midpoint potential of the information output from the first amplitude level changing unit is changed to a fourth voltage level between the two voltage levels . Having a level shift section that shifts to a voltage level;
It said second amplitude level changing unit, the information output from the level shift unit is changed to a logic level for subsequent circuit,
The solid-state imaging device according to claim 1. Said second amplitude level changing unit, in synchronism with the clock input, amplifying the two voltage levels corresponding to logic levels of the information outputted from the level shift unit to the voltage level for the subsequent circuit Having an amplification section ,
The solid-state imaging device according to 請 Motomeko 12. By maintaining synchronization with output of the amplifying unit to the clock, and an output data generating unit for generating a digital data for the subsequent circuit,
The solid-state imaging device according to 請 Motomeko 13. A pixel array unit in which unit pixels are arranged in a matrix;
A vertical scanning unit that reads an analog pixel signal from each unit pixel of the pixel array unit;
An AD conversion unit provided for each column for converting an analog pixel signal read from each unit pixel of the pixel array unit for each row into digital data;
A first amplitude level changing unit that changes one of the two voltage levels corresponding to the logic level of the digital data output from the AD conversion unit to a third voltage level between the two voltage levels ;
A horizontal scanning unit for transferring information output from the first amplitude level changing unit to a signal line common to each column;
The first information by the amplitude level is changed in amplitude level changing unit, and a second amplitude level changing unit for changing the voltage level of the information for subsequent circuit,
A main control unit that generates control information for controlling the vertical scanning unit and the horizontal scanning unit ;
With,
Imaging device.

Images