JP5941783B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus.

  As an imaging apparatus using an AD conversion method according to a conventional example, a configuration described in Patent Document 1 is known. First, the configuration and operation of the imaging apparatus described in Patent Document 1 will be described.

  FIG. 16 shows a schematic configuration of a (C) MOS imaging device using the AD conversion method according to the conventional example described in Patent Document 1. The imaging apparatus 1001 includes an imaging unit 1002, a vertical selection unit 1012, a readout current source unit 1005, an analog unit 1006, a column processing unit 1015, a reference signal generation unit 1016, a horizontal selection unit 1014, an output unit 1017, a change unit 1018, and timing control Part 1020.

  The timing control unit 1020 controls each unit such as a vertical selection unit 1012, a read current source unit 1005, an analog unit 1006, a column processing unit 1015, a reference signal generation unit 1016, a horizontal selection unit 1014, and an output unit 1017. The imaging unit 1002 is configured by unit pixels 1003 having photoelectric conversion elements arranged in a matrix, generates a pixel signal corresponding to the magnitude of incident electromagnetic waves, and outputs to a vertical signal line 1013 provided for each column. Output.

  The vertical selection unit 1012 controls the row address and row scanning of the imaging unit 1002 via the row control line 1011 when driving each unit pixel 1003 of the imaging unit 1002. The horizontal selection unit 1014 controls the column address and column scanning of the column AD conversion unit 1030 of the column processing unit 1015. The read current source unit 1005 is a current source for reading the pixel signal from the imaging unit 1002 as a voltage signal. The analog unit 1006 performs amplification or the like as necessary.

  The column processing unit 1015 includes a changing unit 1018 and a column AD conversion unit 1030 provided for each column of the imaging unit 1002. The changing unit 1018 changes the voltage applied to the column AD conversion unit 1030. The column AD conversion unit 1030 converts an analog signal that is a pixel signal output for each column from each unit pixel 1003 of the imaging unit 1002 into digital data and outputs the digital data. The reference signal generation unit 1016 includes, for example, an integration circuit or a DAC circuit, and generates a reference signal Ramp whose level changes in an inclined manner as time elapses.

  Next, the configuration of the column AD conversion unit 1030 will be described. FIG. 17 shows a configuration of a column processing unit 1015 including a column AD conversion unit 1030. The column AD conversion units 1030 are all configured in the same manner, and each column AD conversion unit 1030 includes a comparison unit 1031 and a measurement unit 1032.

  The comparison unit 1031 is a comparator circuit whose basic configuration is a generally well-known differential amplifier. The comparison unit 1031 compares the pixel signal output from the unit pixel 1003 of the imaging unit 1002 with the reference signal Ramp. For example, when the reference signal Ramp is larger than the pixel signal, the reference signal Ramp is the pixel signal. When it is smaller than that, it outputs Low level.

  The measuring unit 1032 includes an up / down counter circuit, and measures a comparison time from when the comparison unit 1031 starts comparison until the comparison is completed. Thereby, a measurement value of the comparison time according to the magnitude of the pixel signal is obtained. The horizontal selection unit 1014 includes a shift register, a decoder, and the like, and controls the column address and column scanning of each column AD conversion unit 1030 in the column processing unit 1015. Thus, the AD converted digital data is sequentially output to the output unit 1017 via the horizontal signal line.

  The change unit 1018 is configured with a switch element. One end of the switch element is connected to an input terminal to which a reference signal Ramp is applied, out of two input terminals of the comparison units 1031 in all columns, and the other end of the switch element is connected to the power supply VDD. When the switching element configuring the changing unit 1018 is turned on (activated), the input terminal of the comparison unit 1031 to which the reference signal Ramp is applied is short-circuited to the power supply VDD.

  The comparison operation by the comparison unit 1031 is started after reset (balance) of voltages at two input terminals of the differential amplifier constituting the comparison unit 1031 is performed. After the reset operation, the output of the comparison unit 1031 does not invert due to some variation in the voltage of the two input terminals of the differential amplifier that constitutes the comparison unit 1031 or the comparison unit 1031 immediately after the reference signal Ramp is input. In order to prevent a problem that the output of the image is inverted, a change unit 1018 is provided in the imaging apparatus 1001.

  Next, the AD conversion operation will be described. Although the description of the specific operation of the unit pixel 1003 is omitted, the unit pixel 1003 outputs a reset level and a signal level as pixel signals.

  First, after the reset level reading from the unit pixel 1003 is stabilized, the voltages of the two input terminals of the differential amplifier constituting the comparison unit 1031 are reset. Subsequently, the changing unit 1018 applies a predetermined voltage (offset) to the input terminal to which the reference signal Ramp is given. After that, the comparison unit 1031 compares the reference signal Ramp with the reset level using the predetermined voltage as a comparison start voltage, and ends the comparison process when the reference signal Ramp satisfies a predetermined condition with respect to the reset level. To do. The measurement unit 1032 performs measurement in the down-count mode, and the measurement value at the end of the comparison process becomes digital data at the reset level.

  Subsequently, when the signal level is read from the unit pixel 1003, the reset operation in the comparison unit 1031 and the change operation by the change unit 1018 are not performed. After the signal level reading from the unit pixel 1003 is stabilized, the comparison unit 1031 compares the reference signal Ramp with the signal level using the predetermined voltage as a comparison start voltage, and the reference signal Ramp is compared with the signal level. The comparison process ends at a timing when a predetermined condition is satisfied. The measurement unit 1032 performs measurement in the up-count mode, and the measurement value of the measurement unit 1032 at the end of the comparison becomes digital data of a signal component (a signal obtained by subtracting the reset level from the signal level).

  As described above, the pixel signal can be AD converted. In addition, after the reset operation, even if some variation remains in the voltages of the two input terminals of the differential amplifier constituting the comparison unit 1031, the change unit 1018 applies an offset to the input terminal to which the reference signal Ramp is applied. As a result, the voltage at the input terminal to which the reference signal Ramp is applied is higher than the voltage at the input terminal to which the pixel signal is applied, so that the output of the comparison unit 1031 can be reliably inverted during the comparison operation.

JP 2006-340044 A

  However, the above conventional imaging apparatus has the following problems.

(1) Problems related to the configuration in which the voltage at the input terminal of the differential amplifier is directly changed The voltages at the two input terminals of the differential amplifier after reset are approximately equal to the reset voltage V _RST . After the reset is performed, the switch element configuring the changing unit 1018 is controlled (ON) so that an offset is applied to the input terminal to which the reference signal is applied, and then AD conversion is performed. In this manner, by applying an offset to the input terminal to which the reference signal is applied, the output of the comparison unit 1031 can be reliably inverted during the comparison operation, and AD conversion accuracy is improved. However, since only a uniform offset is applied to the input terminals of the differential amplifier for the number of pixels in one row, there is a high possibility that the comparison units 1031 for the number of pixels in one row will simultaneously finish the comparison process. In particular, it is conceivable that the comparison units 1031 for the number of pixels in one row simultaneously complete the comparison process during AD conversion at the reset level. In the comparison unit 1031, a current flows by switching on / off of the transistors in the differential amplifier constituting the comparison unit 1031 at the end of the comparison process. For this reason, when the comparison units 1031 for the number of pixels in one row simultaneously complete the comparison process, there is a problem of malfunction due to a voltage drop due to power concentration.

(2) Regarding a configuration in which the voltage at the input terminal of the differential amplifier is indirectly changed by controlling the reference signal In place of the above method, the voltage at the input terminal to which the reference signal is given is predetermined by controlling the reference signal. It is conceivable to change the voltage to In this case as well, the AD conversion accuracy is improved. However, a uniform offset is still applied to the input terminals of the differential amplifier for the number of pixels in one row, and there is a high possibility that the comparison units 1031 for the number of pixels in one row simultaneously complete the comparison process. Therefore, there is a problem of malfunction due to voltage drop due to power concentration.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide an imaging apparatus capable of performing AD conversion with higher accuracy.

The present invention has been made to solve the above-described problem. A plurality of unit pixels having photoelectric conversion elements are arranged in a matrix, and an analog signal is applied to a column signal line corresponding to each column of the unit pixel array. An imaging unit that outputs a reference signal generation unit that generates a reference signal that increases or decreases over time, and a row selection unit that selectively controls each unit pixel of the imaging unit for each row of the unit pixel array, A first input terminal electrically connected to the column signal line, and a second input terminal electrically connected to the reference signal generation unit via a first capacitive element, A comparator having a differential amplifier that compares voltages of the first input terminal and the second input terminal, and a reset unit that resets voltages of the first input terminal and the second input terminal; The ratio from the start of comparison to the end of comparison by the comparison unit A measuring unit for measuring a comparison time; and a switch element, wherein one end of the switch element is connected to the second input terminal, and the other end of the switch element is connected to a voltage source after a reset operation by the reset unit And the second input terminal is offset according to the voltage of the voltage source so that the voltage difference between the first input terminal and the second input terminal is a voltage that guarantees a comparison operation by the comparison unit. A plurality of unit pixels arranged in the imaging unit, the unit pixels included in the first pixel group, and a second pixel different from the first pixel group And the second unit of the comparison unit connected to the column signal line corresponding to any column of the array of unit pixels included in the first pixel group. The offset applied to the input terminal and the second pixel group An image pickup apparatus, wherein the offset applied to the second input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the unit pixel is different It is.
In the imaging device according to the aspect of the invention, the change unit according to the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group may include the change unit. The comparison unit in which the voltage value of the voltage source to which the other end of the switch element is connected is connected to the column signal line corresponding to any column of the unit pixel array included in the second pixel group It is different from the voltage value of the said voltage source to which the other end of the said switch element which the said change part which concerns on has is connected.
In addition, the present invention provides an imaging unit in which a plurality of unit pixels having photoelectric conversion elements are arranged in a matrix, and outputs an analog signal to a column signal line corresponding to each column of the unit pixel array, and over time A reference signal generation unit that generates a reference signal that increases or decreases, a row selection unit that selects and controls each unit pixel of the imaging unit for each row of the unit pixel array, and the column via a first capacitive element A first input terminal electrically connected to a signal line; and a second input terminal electrically connected to the reference signal generation unit; the first input terminal and the second input A comparison unit having a differential amplifier unit for comparing terminal voltages, a reset unit for resetting voltages of the first input terminal and the second input terminal, and from a comparison start to a comparison end by the comparison unit A measurement unit that measures the comparison time of A second capacitor element, and one end of the second capacitor element is connected to the first input terminal, and the other end of the second capacitor element is connected to the switch during a reset operation by the reset unit. Connected to a first voltage source via an element, and after a reset operation by the reset unit, connected to a second voltage source different from the first voltage source via the switch element, and the first input terminal And an offset according to the voltages of the first voltage source and the second voltage source so that a voltage difference between the second input terminal and the second input terminal is a voltage that guarantees a comparison operation by the comparison unit. A plurality of unit pixels arranged in the imaging unit, and a second pixel different from the first pixel group. And the unit pixel included in the pixel group, and included in the first pixel group The offset applied to the first input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array, and the second pixel group The imaging apparatus is characterized in that the offset applied to the first input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array is different.

  In addition, the present invention provides an imaging unit in which a plurality of unit pixels having photoelectric conversion elements are arranged in a matrix, and outputs an analog signal to a column signal line corresponding to each column of the unit pixel array, and over time A reference signal generation unit that generates a reference signal that increases or decreases, a row selection unit that selects and controls each unit pixel of the imaging unit for each row of the unit pixel array, and the column signal line are electrically connected. A first input terminal and a second input terminal electrically connected to the reference signal generation unit via a first capacitive element, the first input terminal and the second input A comparison unit having a differential amplifier unit for comparing terminal voltages, a reset unit for resetting voltages of the first input terminal and the second input terminal, and from a comparison start to a comparison end by the comparison unit A measurement unit that measures the comparison time of A second capacitor element, and one end of the second capacitor element is connected to the second input terminal, and the other end of the second capacitor element is the switch during a reset operation by the reset unit. Connected to a first voltage source via an element, and after a reset operation by the reset unit, connected to a second voltage source different from the first voltage source via the switch element, and the first input terminal And an offset according to the voltages of the first voltage source and the second voltage source so that a voltage difference between the second input terminal and the second input terminal is a voltage that guarantees a comparison operation by the comparison unit. A plurality of unit pixels arranged in the imaging unit, and a second pixel different from the first pixel group. And the unit pixel included in the pixel group, and included in the first pixel group The offset applied to the second input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array, and the second pixel group includes the offset The imaging apparatus is characterized in that the offset applied to the second input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array is different.

  In the imaging device according to the aspect of the invention, the change unit according to the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group may include the change unit. The change unit according to the comparison unit connected to the column signal line corresponding to any column of the capacitance value of the second capacitor element and the column of the unit pixels included in the second pixel group has The capacitance value of the second capacitor element is different.

  In the imaging device according to the aspect of the invention, the change unit according to the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group may include the change unit. The unit pixel array in which the voltage value of at least one of the first voltage source and the second voltage source to which the other end of the second capacitive element is connected is included in the second pixel group The first voltage source to which the other end of the second capacitive element of the change unit of the comparison unit connected to the column signal line corresponding to any one of the columns is connected and the second voltage source The voltage value is different from the voltage value of at least one of the voltage sources.

  In the imaging device of the present invention, the second voltage source is the analog signal.

  In the imaging device of the present invention, the second voltage source is the reference signal.

  In addition, the present invention provides an imaging unit in which a plurality of unit pixels having photoelectric conversion elements are arranged in a matrix, and outputs an analog signal to a column signal line corresponding to each column of the unit pixel array, and over time A reference signal generation unit that generates a reference signal that increases or decreases, a row selection unit that selects and controls each unit pixel of the imaging unit for each row of the unit pixel array, and the column via a first capacitive element A first input terminal electrically connected to a signal line; and a second input terminal electrically connected to the reference signal generation unit; the first input terminal and the second input A comparison unit having a differential amplifier unit for comparing terminal voltages, a reset unit for resetting voltages of the first input terminal and the second input terminal, and from a comparison start to a comparison end by the comparison unit A measurement unit that measures the comparison time of One end of the switch element is connected to the first input terminal, and the other end of the switch element is connected to a voltage source after a reset operation by the reset unit, and the first input terminal and the A changing unit that applies an offset according to the voltage of the voltage source to the first input terminal so that the voltage difference of the second input terminal is a voltage that guarantees a comparison operation by the comparing unit. The plurality of unit pixels arranged in the imaging unit include the unit pixels included in a first pixel group and the unit pixels included in a second pixel group different from the first pixel group. The offset applied to the first input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group, Any of the arrangement of the unit pixels included in the second pixel group The imaging apparatus is characterized in that the offset applied to the first input terminal of the comparison unit connected to the column signal line corresponding to the column is different.

  According to the present invention, the change unit of the AD conversion unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group is the first input terminal of the comparison unit or the first The change unit of the AD conversion unit connected to the column signal line corresponding to any column of the offset and the unit pixel array included in the second pixel group is the first applied to the comparison unit. Since the offset applied to the input terminal or the second input terminal is different, even when the comparison units start comparison at substantially the same time, the comparison units can finish the comparison at different timings. As a result, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

1 is a block diagram illustrating a configuration of an imaging apparatus according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of a column processing unit included in the imaging apparatus according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a configuration of a comparison unit and a change unit included in the imaging apparatus according to the first embodiment of the present invention and a voltage change at an input terminal of the comparison unit. 6 is a diagram for explaining a voltage change at an input terminal of a comparison unit included in the imaging apparatus according to the first embodiment of the present invention. FIG. FIG. 5 is a block diagram illustrating a configuration of a column processing unit included in an imaging apparatus according to a second embodiment of the present invention. FIG. 6 is a diagram illustrating a configuration of a comparison unit and a change unit included in an imaging apparatus according to a second embodiment of the present invention, and a voltage change at an input terminal of the comparison unit. FIG. 10 is a diagram for describing a voltage change at an input terminal of a comparison unit included in the imaging apparatus according to the second embodiment of the present invention. FIG. 10 is a block diagram illustrating a configuration of a column processing unit included in an imaging apparatus according to a third embodiment of the present invention. FIG. 10 is a diagram illustrating a configuration of a comparison unit and a change unit included in an imaging apparatus according to a third embodiment of the present invention, and a voltage change at an input terminal of the comparison unit. FIG. 10 is a block diagram illustrating a configuration of a column processing unit included in an imaging apparatus according to a fourth embodiment of the present invention. FIG. 10 is a diagram illustrating a configuration of a comparison unit and a change unit included in an imaging apparatus according to a fourth embodiment of the present invention, and a voltage change at an input terminal of the comparison unit. FIG. 10 is a block diagram illustrating a configuration of a column processing unit included in an imaging apparatus according to a fifth embodiment of the present invention. FIG. 10 is a diagram illustrating a configuration of a comparison unit and a change unit provided in an imaging apparatus according to a fifth embodiment of the present invention and a voltage change at an input terminal of the comparison unit. FIG. 10 is a block diagram illustrating a configuration of a column processing unit included in an imaging apparatus according to a sixth embodiment of the present invention. FIG. 10 is a diagram illustrating a configuration of a comparison unit and a change unit included in an imaging apparatus according to a sixth embodiment of the present invention, and a voltage change at an input terminal of the comparison unit. It is a block diagram which shows the structure of the conventional imaging device. It is a block diagram which shows the structure of the column process part with which the conventional imaging device is provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 shows an example of the configuration of a (C) MOS imaging device according to this embodiment. The imaging apparatus 1 shown in FIG. 1 includes an imaging unit 2, a vertical selection unit 12, a column processing unit 15, a reference signal generation unit 16, a change unit 18a, a horizontal selection unit 14, an output unit 17, and a timing control unit 20. Yes.

  In the imaging unit 2, a plurality of unit pixels 3 that generate and output pixel signals according to the magnitude of incident electromagnetic waves are arranged in a matrix. The vertical selection unit 12 selects each row of the imaging unit 2. The reference signal generator 16 generates a reference signal Ramp (ramp wave) whose level changes in an inclined manner as time elapses. The column processing unit 15 is connected to the reference signal generation unit 16. The horizontal selection unit 14 reads the AD-converted digital data to the horizontal signal line. The output unit 17 outputs the digital data read by the horizontal selection unit 14 to a subsequent circuit. The timing control unit 20 controls each unit.

  In FIG. 1, for the sake of simplicity, the case of the imaging unit 2 composed of 4 rows × 6 columns of unit pixels 3 is described, but in reality, each row and each column of the imaging unit 2 has several tens of Tens of thousands of unit pixels 3 are arranged. Although not shown, the unit pixel 3 constituting the imaging unit 2 is configured by a photoelectric conversion element such as a photodiode / photogate / phototransistor and a transistor circuit.

  Below, a more detailed description of each part is given. In the imaging unit 2, unit pixels 3 are arranged two-dimensionally by 4 rows and 6 columns, and row control lines 11 are wired for each row with respect to the pixel array of 4 rows and 6 columns. Each one end of the row control line 11 is connected to each output end corresponding to each row of the vertical selection unit 12. The vertical selection unit 12 includes a shift register or a decoder, and controls the row address and row scanning of the imaging unit 2 via the row control line 11 when driving each unit pixel 3 of the imaging unit 2. A vertical signal line 13 is wired for each column with respect to the pixel array of the imaging unit 2.

  The column processing unit 15 includes a column AD conversion unit 30 and a changing unit 18a provided for each pixel column of the imaging unit 2, that is, for each vertical signal line 13. The column AD conversion unit 30 converts an analog pixel signal read from each unit pixel 3 of the imaging unit 2 through the vertical signal line 13 for each pixel column into digital data. The changing unit 18a changes the voltage applied to the column AD conversion unit 30.

  The unit pixel 3 of the imaging unit 2 is included in any of the three pixel groups 4a, 4b, and 4c. That is, the plurality of unit pixels 3 constituting the imaging unit 2 are configured by the unit pixels 3 included in the pixel group 4a, the unit pixels 3 included in the pixel group 4b, and the unit pixels 3 included in the pixel group 4c. ing. As shown in FIG. 1, the unit pixels 3 in the first and second columns are included in the pixel group 4a, and the unit pixels 3 in the third and fourth columns are included in the pixel group 4b. The unit pixel 3 in the column is included in the pixel group 4c.

  The pixel signal output from the unit pixel 3 included in the pixel group 4a is input to the column AD conversion unit 30 disposed in the region 39a corresponding to the pixel group 4a via the vertical signal line 13. The pixel signal output from the unit pixel 3 included in the pixel group 4b is input to the column AD conversion unit 30 disposed in the region 39b corresponding to the pixel group 4b via the vertical signal line 13. The pixel signal output from the unit pixel 3 included in the pixel group 4c is input to the column AD conversion unit 30 disposed in the region 39c corresponding to the pixel group 4c via the vertical signal line 13.

  In this example, the column AD conversion unit 30 is arranged with a one-to-one correspondence with the pixel columns of the imaging unit 2, but this is only an example and is limited to this arrangement relationship. It is not something. For example, one column AD conversion unit 30 may be arranged for a plurality of pixel columns, and the one column AD conversion unit 30 may be used in a time division manner between the plurality of pixel columns. The column processing unit 15, together with a reference signal generation unit 16 to be described later, configures an analog-digital conversion circuit that converts an analog pixel signal read from the unit pixel 3 in the selected pixel row of the imaging unit 2 into digital pixel data. Yes. Details of the column AD conversion unit 30 will be described later.

  The reference signal generation unit 16 generates a so-called ramp wave whose level changes in an inclined manner as time elapses according to the control by the timing control unit 20, and sends the reference signal Ramp to the column AD conversion unit 30 via the reference signal line. Supply as.

  The horizontal selection unit 14 includes a shift register or a decoder, and controls the column address and column scanning of the column AD conversion unit 30 of the column processing unit 15. According to the control by the horizontal selection unit 14, the digital data AD-converted by the column AD conversion unit 30 is sequentially read out to the output unit 17 through the horizontal signal line.

  The timing control unit 20 receives a clock necessary for the operation of each unit such as the vertical selection unit 12, the change unit 18a, the reference signal generation unit 16, the column processing unit 15, the horizontal selection unit 14, and the output unit 17, and a pulse signal at a predetermined timing. A function block of a supplied TG (= Timing Generator: timing generator) and a function block for communicating with the TG are provided.

  In addition to the buffering function, the output unit 17 may incorporate signal processing functions such as black level adjustment, column variation correction, and color processing. Furthermore, n-bit parallel digital data may be converted into serial data and output.

  Next, the configuration of the column AD conversion unit 30 and the change unit 18a will be described. FIG. 2 shows an example of the configuration of the column processing unit 15 including the column AD conversion unit 30 and the changing unit 18a. The column AD conversion unit 30 and the change unit 18a are provided for each column, and in FIG. 1 and FIG. 2, six column AD conversion units 30 and change units 18a are provided. Each column AD conversion unit 30 has the same configuration. Each changing unit 18a has the same configuration except for a connected voltage source.

  The column AD conversion unit 30 compares the analog pixel signal read out from each unit pixel 3 of the imaging unit 2 through the vertical signal line 13 with the reference signal Ramp supplied from the reference signal generation unit 16, and thereby the reset level and signal A pulse signal having a magnitude (pulse width) in the time axis direction corresponding to each magnitude of the level is generated. Then, AD conversion is performed by using data corresponding to the pulse width period of the pulse signal as digital data corresponding to the magnitude of the pixel signal.

  Hereinafter, the details of the configuration of the column AD conversion unit 30 and the change unit 18a will be described. The column AD conversion unit 30 includes a comparison unit 31 and a measurement unit 32.

  The comparison unit 31 is supplied to the first input terminal, the signal voltage corresponding to the analog pixel signal output from the unit pixel 3 of the imaging unit 2 through the vertical signal line 13, and the second input terminal, By comparing the reference signal Ramp supplied from the reference signal generation unit 16, the magnitude of the pixel signal is converted into information in the time axis direction (pulse width of the pulse signal). The comparison output of the comparison unit 31 becomes, for example, a high level (H level) when the ramp voltage of the reference signal Ramp is larger than the signal voltage, and becomes a low level (L level) when the ramp voltage is equal to or lower than the signal voltage.

  The measuring unit 32 includes, for example, an n-bit up / down counter circuit for measuring the comparison time from the comparison start to the comparison end by the comparison unit 31. The n bits are, for example, 10 bits. Note that the n bits are 10 bits, and the n bits may be less than 10 bits (for example, 8 bits) or more than 10 bits (for example, 12 bits). Absent. Further, it is not necessary to limit to an up / down counter circuit.

The changing unit 18a includes a capacitive element and a switch element. One end of the capacitive element is connected to the first input terminal of the comparison unit 31, and the other end of the capacitive element is connected to the voltage source V1 [n] (n: 1 to 3) (first voltage source via the switch element). ) And a vertical signal line 13 to which an analog signal (second voltage source) from the unit pixel 3 is supplied. The voltage source V1 [1] supplies a power supply voltage (voltage value: V _{1 [1]} ) to the changing unit 18a corresponding to the column AD conversion unit 30 in the region 39a. The voltage source V1 [2] supplies a power supply voltage (voltage value: V _{1 [2]} ) to the changing unit 18a corresponding to the column AD conversion unit 30 in the region 39b. The voltage source V1 [3] supplies a power supply voltage (voltage value: V _{1 [3]} ) to the changing unit 18a corresponding to the column AD conversion unit 30 in the region 39c. The magnitude relationship between the voltage values V _{1 [n]} (n: 1 to 3) is, for example, V _{1 [1]} <V _{1 [2]} <V _{1 [3]} . These are merely examples, and need not be limited to these.

  Next, the operation of this example will be described. Here, a description of a specific operation of the unit pixel 3 is omitted, but as is well known, the unit pixel 3 outputs a reset level and a signal level.

  AD conversion is performed as follows. For example, a ramp wave (reference signal Ramp) that falls at a predetermined slope is compared with a reset level or signal level voltage that is a pixel signal from the unit pixel 3, and a ramp wave used in this comparison process is generated The digital data corresponding to each magnitude of the reset level or signal level by measuring the period until the signal corresponding to the reset level or signal level matches the ramp wave (ramp voltage), for example, with a reference clock Get.

  Here, from each unit pixel 3 in the selected row of the imaging unit 2, the reset level including the noise of the pixel signal is read out as an analog pixel signal in the first reading operation, and then in the second reading operation. The signal level is read out. Then, the reset level and the signal level are input to the column AD conversion unit 30 through the vertical signal line 13 in time series.

<First reading>
After the first reading from the unit pixel 3 in the arbitrary pixel row to the vertical signal line 13 is stabilized, the reset operation of the comparison unit 31 is performed. Subsequently, the changing unit 18a changes the voltage of the first input terminal of the comparison unit 31 to which the reset level is given to a predetermined voltage lower than the reset level. At this time, a different offset is applied to each of the regions 39a, 39b, and 39c to the first input terminal of the comparison unit 31 of each column AD conversion unit 30 in each of the regions 39a, 39b, and 39c.

  Thereafter, the timing control unit 20 supplies the reference signal generation unit 16 with control data for ramp wave generation. In response to this, the reference signal generator 16 outputs a reference signal Ramp, which is a ramp wave whose waveform changes in a ramp shape over time, as a comparison voltage applied to the second input terminal of the comparator 31. The comparison unit 31 compares the voltage of the second input terminal to which the reference signal Ramp from the reference signal generation unit 16 is given with the voltage of the first input terminal to which the reset level is given, and both voltages are When substantially matching, the comparison output is inverted.

  The measurement unit 32 starts measurement in the down-count mode based on the comparison start in the comparison unit 31, and holds the measurement value at the time when the comparison output of the comparison unit 31 is inverted. That is, the measuring unit 32 holds digital data corresponding to the reset level. The timing control unit 20 stops supplying control data to the reference signal generation unit 16 and outputting a reference clock when a predetermined period has elapsed. As a result, the reference signal generator 16 stops generating the reference signal Ramp.

<Second reading>
Subsequently, in the second reading, a signal level corresponding to the incident light amount for each unit pixel 3 is read. At the time of this second reading, the reset operation of the comparison unit 31 and the change operation by the change unit 18a are not performed.

  After the second reading from the unit pixel 3 in the arbitrary pixel row to the vertical signal line 13 is stabilized, the timing control unit 20 supplies the reference signal generation unit 16 with control data for ramp wave generation. In response to this, the reference signal generator 16 outputs a reference signal Ramp. The comparison unit 31 compares the voltage of the second input terminal to which the reference signal Ramp from the reference signal generation unit 16 is given with the voltage of the first input terminal to which the signal level is given. When substantially matching, the comparison output is inverted.

  The measurement unit 32 starts measurement in the up-count mode based on the comparison start in the comparison unit 31, and holds the measurement value when the comparison output of the comparison unit 31 is inverted. That is, the measurement unit 32 holds digital data corresponding to a signal component obtained by subtracting the reset level from the signal level (CDS (= Correlated Double Sampling) processing). The timing control unit 20 stops supplying control data to the reference signal generation unit 16 and outputting a reference clock when a predetermined period has elapsed. As a result, the reference signal generator 16 stops generating the reference signal Ramp.

  Next, the configuration of the comparison unit 31 and the change unit 18a and details of the voltage change at the input terminal of the comparison unit 31 will be described. FIG. 3 shows an example of a specific circuit configuration of the comparison unit 31 and the change unit 18a. The circuit configuration of this example will be described below.

  In FIG. 3, the differential amplifier in the comparison unit 31 is connected between transistors N1 and N2, which are composed of NMOSs whose sources are connected in common, and between the drains of these transistors N1 and N2 and the power supply VDD. It consists of transistors P3 and P4 composed of PMOSs with their gates connected in common, and an NMOS current source N5 connected between the node connected in common to the sources of the transistors N1 and N2 and the ground GND. ing.

  In this differential amplifier, transistors P6 and P7 made of PMOS are connected between the gates and drains of the transistors N1 and N2, respectively. These transistors P6 and P7 are turned on when a low active reset pulse Reset is given to each gate from the timing controller 20, and the gates and drains of the transistors N1 and N2 are short-circuited. It functions as a reset unit that resets the gate voltage, that is, the voltages of the two input terminals IN1 and IN2 of the differential amplifier.

  One end of each of capacitive elements C1 and C2 for cutting the DC level is connected to each gate of the transistors N1 and N2. A pixel signal Pixel output from each unit pixel 3 of the imaging unit 2 is given to the other end of the capacitive element C1 (first capacitive element). The reference signal Ramp from the reference signal generation unit 16 is given to the other end of the capacitive element C2.

  The changing unit 18a includes a capacitive element C3 (second capacitive element) and a switch element SW1. One end of the capacitive element C3 is connected to the gate of the transistor N1, and the other end of the capacitive element C3 is connected to the first terminal of the switch element SW1. The second terminal of the switch element SW1 is connected to the voltage source V1 [n] (n: 1 to 3), and the third terminal of the switch element SW1 is connected to the other end of the capacitive element C1. The switch element SW1 is connected to the voltage source V1 [n] and the other end of the capacitive element C3 by short-circuiting the first terminal and the second terminal by a control signal (not shown) from the timing control unit 20. Then, the first terminal and the third terminal are short-circuited to switch the state where the other end of the capacitive element C1 and the other end of the capacitive element C3 are connected. A bias voltage Vbias for controlling the current value is applied to the gate of the current source N5.

The operation of this example will be described below. Here, the voltage of the voltage source V1 [n] is V _{1 [n]} , the reset level voltage is V _R (where V _R <V _{1 [n]} ), and the signal level voltage is V _S (where V _S ≦ V _R ), the capacitance value of the capacitive element C1 is C ₁ , and the capacitive value of the capacitive element C3 is C ₃ . Further, the first input terminal IN1 of the differential amplifier connected to the voltage source V1 [n] through the capacitive element C3 and the switch element SW1 is replaced with the first input terminal IN1 [n] (n: 1 to 3). To do. FIG. 3 shows the voltage change of the first input terminal IN1 [n] and the second input terminal IN2 of the differential amplifier in the comparison unit 31 and the waveform of the reference signal Ramp.

  After the reset level is given to the first input terminal IN1 [n] as the pixel signal Pixel from the unit pixel 3, and the reference signal Ramp given from the reference signal generator 16 to the second input terminal IN2 is stabilized, timing control is performed. The unit 20 activates the reset pulse Reset (low active) before the comparison unit 31 starts comparison. As a result, the transistors P6 and P7 are turned on to short-circuit the gates and drains of the transistors N1 and N2, and the voltages at the two input terminals are reset with the operating point of these transistors N1 and N2 as the drain voltage. During the reset operation, the other end of the capacitive element C3 is connected to the voltage source V1 [n] by the switch element SW1.

At the operating point determined by this reset, the voltages at the two input terminals of the differential amplifier, that is, the offset components of the gate voltages of the transistors N1 and N2, are almost canceled. That is, the voltages at the two input terminals of the differential amplifier are reset so as to be substantially the same voltage _VRST . At this time (time T1), the voltage of the first input terminal IN1 [n] is V _RST and the voltage of the second input terminal IN2 is V _RST . After reset, the transistors P6 and P7 are turned off.

Subsequently, the switching element SW1 connects the other end of the capacitive element C3 to the other end of the capacitive element C1, so that the voltage of the first input terminal IN1 [n] to which the pixel signal Pixel is applied, that is, the gate voltage of the transistor N1. Is changed from the voltage V _RST to a predetermined voltage. Since the voltage at the other end of the capacitive element C3 changes from V _{1 [n]} to V _R by (V _R −V _{1 [n]} ), at this time (time T2), the first input terminal IN1 [n] The voltage V _{IN1 [n]} is expressed by the following equation (1).

After the reset operation of the comparison unit 31, even if some variation in the voltage of the two input terminals of the differential amplifier constituting the comparison unit 31 remains, V _R <V _{1 [n].} The voltage of the first input terminal IN1 [n] (Equation (1)) at the start of the comparison in the comparison unit 31 is lower than the voltage (V _RST ) of the second input terminal IN2. As shown in FIG. 3, by giving a ramp wave that decreases as time passes as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

  After time T2, a ramp wave is applied as the reference signal Ramp to the second input terminal IN2. The comparison output of the comparison unit 31 is inverted at the timing when the voltage of the second input terminal IN2 to which the ramp wave is applied and the voltage of the first input terminal IN1 [n] substantially coincide. The reference signal generator 16 stops generating the ramp wave when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 has started (time T3).

After the reset operation of the comparison unit 31, the voltage according to the second term on the right side of the equation (1) is applied as an offset to the first input terminals IN1 [1], IN1 [2], IN1 [3]. Since the voltage values V _{1 [1]} , V _{1 [2]} , and V _{1 [3]} are different and the reset levels output from the unit pixels 3 in each column are substantially the same, the first input terminal IN1 [1 ], IN1 [2], and IN1 [3] are applied with different offsets. Therefore, the voltages V _{IN1 [1]} , V _{IN1 [2]} of the first input terminals IN1 [1], IN1 [2], IN1 [3] at the start of comparison in the comparison unit 31 relating to the first reading, V _{IN1 [3]} (Equation (1)) is different. Thus, even when the comparison start timing in the comparison unit 31 related to the first reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  Subsequently, the signal level is given to the first input terminal IN1 [n] as the pixel signal Pixel from the unit pixel 3. Hereinafter, the voltage of the first input terminal IN1 [n] at the time (time T4) when the signal level is input will be described with reference to FIG. FIG. 4 shows only the configuration around the first input terminal IN1 [n]. Hereinafter, description will be made assuming a parasitic capacitance CP between the first input terminal IN1 [n] and the ground GND.

When the other end of the capacitive element C3 is connected to the other end of the capacitive element C1 by the switch element SW1 (time T2), the voltage at the other end of the capacitive element C1 to which the reset level is given as the pixel signal Pixel is V _R It is. At the time (time T4) when the signal level is input as the pixel signal Pixel, the voltage at the other end of the capacitive element C1 becomes V _S. Assuming that the change in voltage at the other end of the capacitive element C1 from time T2 to time T4 is ΔV1, ΔV1 is expressed by the following equation (2).
ΔV1 = V _S -V _R (2)

Since the transistor P6 is in the OFF state from time T2 to time T4, the charge amount accumulated in the capacitive elements C1 and C3 and the parasitic capacitance CP is held. Therefore, if the change in voltage of the first input terminal IN1 [n] from time T2 to time T4 is ΔV2, ΔV2 is expressed by the following equation (3). Note that the capacitive element C1 and the capacitive element C3 are connected in parallel, and the capacitance value obtained by synthesizing the capacitive element C1 and the capacitive element C3 connected in parallel is _CC in the equation (3). In Equation (3), C _P is the capacitance value of the parasitic capacitance CP.

If you can ignore the C _P compared to _{C C (C C >> C P} ), the ΔV2 = ΔV1. Since the voltage of the first input terminal IN1 [n] at the time T2 is the expression (1), the voltage V _{IN1 [1]} of the first input terminal IN1 [n] at the time T4 is the following expression (4): Become.

Since V _R <V _{1 [n]} and V _S ≦ V _R , the voltage of the first input terminal IN1 [n] at the start of comparison in the comparison unit 31 related to the second reading (Equation (4)) Becomes lower than the voltage (V _RST ) of the second input terminal IN2. As shown in FIG. 3, by giving a ramp wave that decreases as time passes as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

  After time T4, a ramp wave is applied as the reference signal Ramp to the second input terminal IN2. The comparison output of the comparison unit 31 is inverted at the timing when the voltage of the second input terminal IN2 to which the ramp wave is applied and the voltage of the first input terminal IN1 [n] substantially coincide. The reference signal generation unit 16 stops generating the ramp wave when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 has started (time T5). Since the measurement unit 32 performs measurement in the down-count mode at the time of the first reading and the measurement unit 32 performs measurement in the up-count mode at the time of the second reading, as the measurement value of the measurement unit 32, the right side of Equation (4) The measurement value according to item 3 is obtained. In the equation (4), since the coefficient of the third term on the right side is 1, AD conversion operation without gain reduction due to the provision of the capacitive element C3 is possible.

As described above, the voltage values V _{1 [1]} , V _{1 [2]} , and V _{1 [3]} are different. The reset levels output from the unit pixels 3 in each column are substantially the same, and the signal levels are often different. Therefore, the voltages V _{IN1 [1]} and V _{IN1 [2]} of the first input terminals IN1 [1], IN1 [2], and IN1 [3] at the start of comparison in the comparison unit 31 related to the second reading , V _{IN1 [3]} (Equation (4)) are often different. Thus, even when the comparison start timing in the comparison unit 31 related to the second reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  As described above, according to the present embodiment, after the reset operation by the transistors P6 and P7, the voltage difference between the first input terminal IN1 and the second input terminal IN2 guarantees the comparison operation by the comparison unit 31. So that the changing unit 18a (capacitance element C3 and switching element SW1) changes the voltage of the first input terminal IN1 to a lower voltage, so that the comparison unit 31 compares the reference signal Ramp with the pixel signal Pixel. The operation can be performed reliably.

  In addition, since different offsets are applied to the first input terminal IN1 of the comparison unit 31 for each of the regions 39a, 39b, and 39c, each comparison unit 31 in each column AD conversion unit 30 of the regions 39a, 39b, and 39c Even when the comparison is started substantially simultaneously, the comparison units 31 can finish the comparison at different timings. As a result, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  Further, the changing unit 18a is connected so that the other end of the capacitive element C3 is connected to the voltage source V1 [n] and the vertical signal line 13 to which the analog signal from the unit pixel 3 is supplied via the switch element SW1. By configuring this, it is possible to perform an AD conversion operation without a gain decrease due to the provision of the capacitive element C3.

(Second embodiment)
Next, a second embodiment of the present invention will be described. In the present embodiment, the changing unit is different from that of the first embodiment. FIG. 5 shows an example of the configuration of the column processing unit 15 including the column AD conversion unit 30 and the changing unit 18b. The other configuration is substantially the same as the configuration shown in FIG.

The changing unit 18b includes a capacitive element and a switch element. One end of the capacitive element is connected to the second input terminal of the comparison unit 31, and the other end of the capacitive element is connected to the voltage source V1 [n] (n: 1 to 3) (first voltage source via the switch element. ) And a reference signal line to which a reference signal Ramp (second voltage source) from the reference signal generator 16 is supplied. The voltage source V1 [1] supplies a power supply voltage (voltage value: V _{1 [1]} ) to the changing unit 18b corresponding to the column AD conversion unit 30 in the region 39a. The voltage source V1 [2] supplies a power supply voltage (voltage value: V _{1 [2]} ) to the changing unit 18b corresponding to the column AD conversion unit 30 in the region 39b. The voltage source V1 [3] supplies a power supply voltage (voltage value: V _{1 [3]} ) to the changing unit 18b corresponding to the column AD conversion unit 30 in the region 39c. The magnitude relationship between the voltage values V _{1 [n]} (n: 1 to 3) is, for example, V _{1 [1]} <V _{1 [2]} <V _{1 [3]} . These are merely examples, and need not be limited to these.

  In the following, the operation of this example will be described with a focus on the differences from the first embodiment. As in the first embodiment, the unit pixel 3 outputs a reset level and a signal level.

<First reading>
After the first reading from the unit pixel 3 in the arbitrary pixel row to the vertical signal line 13 is stabilized, the reset operation of the comparison unit 31 is performed. Subsequently, the changing unit 18b changes the voltage of the second input terminal of the comparison unit 31 to which the reference signal Ramp is given to a predetermined voltage higher than the reset level. Thereafter, the timing control unit 20 supplies the reference signal generation unit 16 with control data for ramp wave generation. In response to this, the reference signal generation unit 16 outputs a reference signal Ramp whose waveform changes as a whole in a ramp shape as a comparison voltage to be applied to the second input terminal of the comparison unit 31. The comparison unit 31 compares the voltage of the second input terminal to which the reference signal Ramp from the reference signal generation unit 16 is given with the voltage of the first input terminal to which the reset level is given, and both voltages are When substantially matching, the comparison output is inverted.

  The measurement unit 32 starts measurement in the down-count mode based on the comparison start in the comparison unit 31, and holds the measurement value at the time when the comparison output of the comparison unit 31 is inverted. That is, the measuring unit 32 holds digital data corresponding to the reset level. The timing control unit 20 stops supplying control data to the reference signal generation unit 16 and outputting a reference clock when a predetermined period has elapsed. As a result, the reference signal generator 16 stops generating the reference signal Ramp.

<Second reading>
Subsequently, in the second reading, a signal level corresponding to the incident light amount for each unit pixel 3 is read. At the time of this second reading, the reset operation of the comparison unit 31 and the change operation by the change unit 18b are not performed.

  After the second reading from the unit pixel 3 in the arbitrary pixel row to the vertical signal line 13 is stabilized, the timing control unit 20 supplies the reference signal generation unit 16 with control data for ramp wave generation. In response to this, the reference signal generator 16 outputs a reference signal Ramp. The comparison unit 31 compares the voltage of the second input terminal to which the reference signal Ramp from the reference signal generation unit 16 is given with the voltage of the first input terminal to which the signal level is given. When substantially matching, the comparison output is inverted.

  The measurement unit 32 starts measurement in the up-count mode based on the comparison start in the comparison unit 31, and holds the measurement value when the comparison output of the comparison unit 31 is inverted. That is, the measurement unit 32 holds digital data corresponding to the signal component obtained by subtracting the reset level from the signal level. The timing control unit 20 stops supplying control data to the reference signal generation unit 16 and outputting a reference clock when a predetermined period has elapsed. As a result, the reference signal generator 16 stops generating the reference signal Ramp.

  Next, the configuration of the comparison unit 31 and the change unit 18b and details of the voltage change at the input terminal of the comparison unit 31 will be described. FIG. 6 illustrates an example of specific circuit configurations of the comparison unit 31 and the change unit 18b. The circuit configuration of this example will be described below. Only the configuration different from the configuration shown in FIG. 5 will be described below.

  The changing unit 18b includes a capacitive element C4 (second capacitive element) and a switch element SW2. One end of the capacitive element C4 is connected to the gate of the transistor N2, and the other end of the capacitive element C4 is connected to the first terminal of the switch element SW2. The second terminal of the switch element SW2 is connected to the voltage source V1 [n] (n: 1 to 3), and the third terminal of the switch element SW2 is connected to the other end of the capacitive element C2. In the switch element SW2, the first terminal and the second terminal are short-circuited so that the voltage source V1 [n] and the other end of the capacitive element C4 are connected, and the first terminal and the third terminal are short-circuited Thus, switching between the state in which the other end of the capacitive element C2 and the other end of the capacitive element C4 are connected is performed.

The operation of this example will be described below. Here, the voltage of the voltage source V1 [n] is V _{1 [n]} , the reset level voltage is V _R , the signal level voltage is V _S (where V _S ≦ V _R ), and the capacitance value of the capacitive element C2 is C _2, the capacitance of the capacitor C4 and C _4. Further, the second input terminal IN2 of the differential amplifier connected to the voltage source V1 [n] through the capacitive element C4 and the switch element SW2 is replaced with the second input terminal IN2 [n] (n: 1 to 3). To do. FIG. 6 shows the voltage change of the first input terminal IN1 and the second input terminal IN2 [n] of the differential amplifier in the comparison unit 31 and the waveform of the reference signal Ramp.

  After the reset level is given to the first input terminal IN1 as the pixel signal Pixel from the unit pixel 3, and the reference signal Ramp given from the reference signal generator 16 to the second input terminal IN2 [n] is stabilized, timing control is performed. The unit 20 activates the reset pulse Reset (low active) before the comparison unit 31 starts comparison. As a result, the transistors P6 and P7 are turned on to short-circuit the gates and drains of the transistors N1 and N2, and the voltages at the two input terminals are reset with the operating point of these transistors N1 and N2 as the drain voltage. During the reset operation, the other end of the capacitive element C4 is connected to the voltage source V1 [n] by the switch element SW2.

At the operating point determined by this reset, the voltages at the two input terminals of the differential amplifier, that is, the offset components of the gate voltages of the transistors N1 and N2, are almost canceled. That is, the voltages at the two input terminals of the differential amplifier are reset so as to be substantially the same voltage _VRST . At this time (time T1), the voltage at the first input terminal IN1 is V _RST and the voltage at the second input terminal IN2 [n] is V _RST . After reset, the transistors P6 and P7 are turned off.

Subsequently, the switching element SW2 connects the other end of the capacitive element C4 to the other end of the capacitive element C2, so that the voltage of the second input terminal IN2 [n] to which the reference signal Ramp is applied, that is, the gate voltage of the transistor N2 Is increased from the voltage V _RST to a predetermined voltage. If the voltage of the reference signal Ramp at this time (time T2) is V _Ramp (0), the voltage at the other end of the capacitive element C4 changes from V _{1 [n]} to V _Ramp (0) (V _Ramp (0) − V _{1 [n]} ) changes, and at this time (time T2), the voltage V _IN2 of the second input terminal IN2 [n] is expressed by the following equation (5). Here, the relationship between the voltage V _{1 [n]} of the voltage source V _{1 [n]} and the voltage V _Ramp (0) of the reference signal Ramp is V _{1 [n]} <V _Ramp (0).

Even after the reset operation of the comparison unit 31, even if there is some variation in the voltage of the two input terminals of the differential amplifier constituting the comparison unit 31, V _{1 [n]} <V _Ramp (0). The voltage of the second input terminal IN2 [n] (Equation (5)) at the start of comparison in the comparison unit 31 related to the second reading is higher than the voltage (V _RST ) of the first input terminal IN1. As shown in FIG. 6, by giving a ramp wave that decreases with time as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

  After time T2, a ramp wave is given as the reference signal Ramp to the second input terminal IN2 [n]. Hereinafter, the voltage of the second input terminal IN2 [n] to which the ramp wave is applied will be described with reference to FIG. FIG. 7 shows only the configuration around the second input terminal IN2 [n]. Hereinafter, description will be made assuming a parasitic capacitance CP between the second input terminal IN2 [n] and the ground GND.

The other end of the capacitive element C2 when the voltage of the ramp wave applied to the other end of the capacitive element C2 changes from V _Ramp (0) to V _Ramp (t) (V _Ramp (t)-V _Ramp (0)) Assuming that the change in voltage is ΔV3, ΔV3 is expressed by the following equation (6).
ΔV3 = V _Ramp (t)-V _Ramp (0) (6)

Since the transistor P7 is in the OFF state from time T2 to time T4, the charge amount accumulated in the capacitive elements C2 and C4 and the parasitic capacitance CP is retained. Therefore, the second voltage when the voltage of the ramp wave applied to the other end of the capacitive element C2 changes from V _Ramp (0) to V _Ramp (t) (V _Ramp (t)-V _Ramp (0)). When the change in voltage at the input terminal IN2 [n] is ΔV4, ΔV4 is expressed by the following equation (7). Note that the capacitive element C2 and the capacitive element C4 are connected in parallel, and the capacitance value obtained by synthesizing the capacitive element C2 and the capacitive element C4 connected in parallel is _CC in the equation (7). In Equation (7), C _P is a capacitance value of the parasitic capacitance CP.

If you can ignore the C _P compared to _{C C (C C >> C P} ), the ΔV4 = ΔV3. Since the voltage of the second input terminal IN2 [n] at time T2 is the expression (5), the voltage V _{IN2 [n]} of the second input terminal IN2 [n] after the time T2 is the following expression (8) It becomes. In the equation (8), since the coefficient of the third term on the right side is 1, also in the present embodiment in which the capacitive element C4 is provided, the rate of change over time of the reference signal Ramp (the slope of the reference signal Ramp) is expressed as follows. It is possible to keep the reference signal Ramp equal to the rate of change with time in the embodiment.

  The comparison output of the comparison unit 31 is inverted at the timing when the second input terminal IN2 [n] to which the ramp wave is applied and the voltage of the first input terminal IN1 substantially coincide. The reference signal generation unit 16 stops generating the ramp wave when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 [n] is started (time T3).

After the reset operation of the comparison unit 31, the voltage according to the second term on the right side of the equation (5) is applied as an offset to the second input terminals IN2 [1], IN2 [2], IN2 [3]. The voltage values V _{1 [1]} , V _{1 [2]} , and V _{1 [3]} are different from each other, and the reference signal Ramp supplied to the second input terminal IN2 [n] of the comparison unit 31 in each column is substantially the same. Therefore, different offsets are applied to the second input terminals IN2 [1], IN2 [2], IN2 [3], respectively. Therefore, the voltages V _{IN2 [1]} , V _{IN2 [2]} of the second input terminals IN2 [1], IN2 [2], IN2 [3] at the start of comparison in the comparison unit 31 related to the first reading, V _{IN2 [3]} (Equation (5)) is different. Thus, even when the comparison start timing in the comparison unit 31 related to the first reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

Subsequently, a signal level is given to the first input terminal IN1 as a pixel signal Pixel from the unit pixel 3. When the other end of the capacitive element C4 is connected to the other end of the capacitive element C2 by the switch element SW2 (time T2), the voltage at the other end of the capacitive element C1 to which the reset level is given as the pixel signal Pixel is V _R It is. At the time (time T4) when the signal level is input as the pixel signal Pixel, the voltage at the other end of the capacitive element C1 becomes V _S. Therefore, the voltage V _IN1 of the first input terminal IN1 at time T4 is expressed by the following equation (9).
V _IN1 = V _RST + (V _S -V _R ) (9)

At time T4 related to the second reading, the voltage of the second input terminal IN2 [n] to which the reference signal Ramp is applied is expressed by the above-described equation (5). Since V _{1 [n]} <V _Ramp (0) in equation (5) and V _S ≦ V _R in equation (9), voltage V _{IN2 [n] in} equation (5) is It becomes higher than the voltage V _IN1 . That is, the voltage of the second input terminal IN2 [n] at the start of the comparison in the comparison unit 31 related to the second reading is higher than the voltage of the first input terminal IN1. As shown in FIG. 6, by giving a ramp wave that decreases with time as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

After time T4, a ramp wave is applied as the reference signal Ramp to the second input terminal IN2 [n]. The voltage V _{IN2 [n]} of the second input terminal IN2 [n] after the point in time when the ramp wave is applied to the second input terminal _{IN2 [n]} is expressed by the above-described equation (8). The comparison output of the comparison unit 31 is inverted at the timing at which the voltage of the second input terminal IN2 [n] to which the ramp wave is applied substantially matches the voltage of the first input terminal IN1. At a time point (time T5) when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 [n] is started, the reference signal generation unit 16 stops the ramp wave generation. Since the measurement unit 32 performs measurement in the down-count mode at the first reading and the measurement unit 32 performs measurement in the up-count mode at the second reading, as the measurement value of the measurement unit 32, the right side of Equation (9) Measured value according to item 2 (V _S -V _R ) is obtained.

As described above, the voltages V _{IN2 [1]} and V _{IN2 [} at the second input terminals IN2 [1], IN2 [2], and IN2 [3] at the start of comparison in the comparison unit 31 related to the second reading are described _{. 2]} and V _{IN2 [3]} are expressed by equation (5) and are different from each other. Thus, even when the comparison start timing in the comparison unit 31 related to the second reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  As described above, according to the present embodiment, after the reset operation by the transistors P6 and P7, the voltage difference between the first input terminal IN1 and the second input terminal IN2 guarantees the comparison operation by the comparison unit 31. As a result, the changing unit 18b (capacitance element C4 and switch element SW2) changes the voltage of the second input terminal IN2 to a higher voltage, so that the comparison unit 31 compares the reference signal Ramp with the pixel signal Pixel. The operation can be performed reliably.

  Further, since different offsets are applied to the second input terminal IN2 of the comparison unit 31 for each of the regions 39a, 39b, and 39c, each comparison unit 31 in each column AD conversion unit 30 of the regions 39a, 39b, and 39c Even when the comparison is started substantially simultaneously, the comparison units 31 can finish the comparison at different timings. As a result, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  In addition, the other end of the capacitive element C4 is changed to be connected to the voltage source V1 [n] and the reference signal line to which the reference signal Ramp from the reference signal generation unit 16 is supplied via the switch element SW2. By configuring the unit 18b, it is possible to keep the rate of time change of the reference signal Ramp equal to the rate of time change of the reference signal Ramp in the first embodiment.

(Third embodiment)
Next, a third embodiment of the present invention will be described. In the present embodiment, the changing unit is different from that of the first embodiment. FIG. 8 shows an example of the configuration of the column processing unit 15 including the column AD conversion unit 30 and the changing unit 18c. The other configuration is substantially the same as the configuration shown in FIG.

The changing unit 18c includes a capacitive element and a switch element. One end of the capacitive element is connected to the first input terminal of the comparison unit 31, and the other end of the capacitive element is connected to the voltage source V1 (first voltage source) and the analog signal from the unit pixel 3 via the switch element. It is connected to the vertical signal line 13 to which (second voltage source) is supplied. The voltage source V1 supplies a power supply voltage (voltage value: V ₁ ) to the changing unit 18c. The capacitive element included in the changing unit 18c is a capacitive element C3 [n] (n: 1 to 3), and the capacitance value is C _{3 [n]} (n: 1 to 3). Capacitance of the capacitor C3 [1] of the changing unit 18c corresponding to the column AD conversion section 30 in the region 39a is C _{3 [1].} Capacitance of the capacitor C3 [2] of the changing unit 18c corresponding to the column AD conversion section 30 of the region 39b is C _{3 [2].} Capacitance of the capacitor C3 [3] of the changing unit 18c corresponding to the column AD conversion section 30 in the region 39c is C _{3 [3].} The magnitude relationship between the capacitance values C _{3 [n]} is, for example, C _{3 [1]} <C _{3 [2]} <C _{3 [3]} . These are merely examples, and need not be limited to these.

  Since the operations of the column AD conversion unit 30 and the change unit 18c at the time of the first read and the second read are the same as the operations of the column AD conversion unit 30 and the change unit 18a in the first embodiment, the description will be made. Omitted.

  Next, the configuration of the comparison unit 31 and the change unit 18c and details of the voltage change at the input terminal of the comparison unit 31 will be described. FIG. 9 shows an example of a specific circuit configuration of the comparison unit 31 and the change unit 18c. Hereinafter, only the parts of the circuit configuration of this example that are different from the first embodiment will be described.

  The changing unit 18c includes a capacitive element C3 [n] (second capacitive element) and a switch element SW1. One end of the capacitive element C3 [n] is connected to the gate of the transistor N1, and the other end of the capacitive element C3 [n] is connected to the first terminal of the switch element SW1. The second terminal of the switch element SW1 is connected to the voltage source V1, and the third terminal of the switch element SW1 is connected to the other end of the capacitive element C1. The switch element SW1 is connected to the voltage source V1 and the other end of the capacitive element C3 [n] by short-circuiting the first terminal and the second terminal by a control signal (not shown) from the timing control unit 20. Then, the first terminal and the third terminal are short-circuited to switch between the state in which the other end of the capacitive element C1 and the other end of the capacitive element C3 [n] are connected.

  For example, the capacitive element C3 [n] may be configured by a plurality of unit capacitive elements having the same capacitance value, and the capacitance value may be changed by controlling the connection. In the case of the configuration illustrated in FIG. 9, the capacitive element C1 is configured as a capacitive element C1 [n] (n: 1 to 3) having different capacitance values for each region, and the capacitive element C1 [n] and the capacitive element C3 It is desirable that the total capacitance value of [n] is constant.

The operation of this example will be described below. Here, the voltage of the voltage source V1 is V ₁ , the reset level voltage is V _R (where V _R <V ₁ ), the signal level voltage is V _S (where V _S ≦ V _R ), and the capacitance element C1 Assume that the capacitance value is C ₁ and the capacitance value of the capacitive element C3 [n] is C _{3 [n]} . Further, the first input terminal IN1 of the differential amplifier connected to the voltage source V1 via the capacitive element C3 [n] and the switch element SW1 is replaced with the first input terminal IN1 [n] (n: 1 to 3). To do. FIG. 9 shows the voltage change of the first input terminal IN1 [n] and the second input terminal IN2 of the differential amplifier in the comparison unit 31 and the waveform of the reference signal Ramp.

  After the reset level is given to the first input terminal IN1 [n] as the pixel signal Pixel from the unit pixel 3, and the reference signal Ramp given from the reference signal generator 16 to the second input terminal IN2 is stabilized, timing control is performed. The unit 20 activates the reset pulse Reset (low active) before the comparison unit 31 starts comparison. As a result, the transistors P6 and P7 are turned on to short-circuit the gates and drains of the transistors N1 and N2, and the voltages at the two input terminals are reset with the operating point of these transistors N1 and N2 as the drain voltage. During the reset operation, the other end of the capacitive element C3 [n] is connected to the voltage source V1 by the switch element SW1.

At the operating point determined by this reset, the voltages at the two input terminals of the differential amplifier, that is, the offset components of the gate voltages of the transistors N1 and N2, are almost canceled. That is, the voltages at the two input terminals of the differential amplifier are reset so as to be substantially the same voltage _VRST . At this time (time T1), the voltage of the first input terminal IN1 [n] is V _RST and the voltage of the second input terminal IN2 is V _RST . After reset, the transistors P6 and P7 are turned off.

Subsequently, the switching element SW1 connects the other end of the capacitive element C3 to the other end of the capacitive element C1, so that the voltage of the first input terminal IN1 [n] to which the pixel signal Pixel is applied, that is, the gate voltage of the transistor N1. Is changed from the voltage V _RST to a predetermined voltage. The voltage V _{IN1 [n]} of the first input terminal IN1 [n] at this time (time T2) is expressed by the following expression (10), similar to the expression (1) in the first embodiment.

Even after the reset operation of the comparison unit 31, even if there is some variation in the voltage of the two input terminals of the differential amplifier that constitutes the comparison unit 31, since V _R <V ₁ , the comparison related to the first reading The voltage of the first input terminal IN1 [n] (Equation (10)) at the start of comparison in the unit 31 is lower than the voltage (V _RST ) of the second input terminal IN2. As shown in FIG. 9, by giving a ramp wave that decreases with time as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

  After time T2, a ramp wave is applied as the reference signal Ramp to the second input terminal IN2. The comparison output of the comparison unit 31 is inverted at the timing when the voltage of the second input terminal IN2 to which the ramp wave is applied and the voltage of the first input terminal IN1 [n] substantially coincide. The reference signal generator 16 stops generating the ramp wave when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 has started (time T3).

After the reset operation of the comparison unit 31, the voltage according to the second term on the right side of the equation (10) is applied as an offset to the first input terminals IN1 [1], IN1 [2], IN1 [3]. Since the capacitance values C _{3 [1]} , C _{3 [2]} , and C _{3 [3]} are different and the reset levels output from the unit pixels 3 in each column are substantially the same, the first input terminal IN1 [1 ], IN1 [2], and IN1 [3] are applied with different offsets. Therefore, the voltages V _{IN1 [1]} , V _{IN1 [2]} of the first input terminals IN1 [1], IN1 [2], IN1 [3] at the start of comparison in the comparison unit 31 relating to the first reading, V _{IN1 [3]} (Equation (10)) is different. Thus, even when the comparison start timing in the comparison unit 31 related to the first reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

Subsequently, the signal level is given to the first input terminal IN1 [n] as the pixel signal Pixel from the unit pixel 3. The voltage V _{IN1 [1]} of the first input terminal IN1 [n] at this time (time T4) is expressed by the following expression (11), similar to the expression (4) in the first embodiment.

Since V _R <V ₁ and V _S ≦ V _R , the voltage of the first input terminal IN1 [n] at the start of comparison in the comparison unit 31 related to the second reading (equation (11)) is It becomes lower than the voltage (V _RST ) of the input terminal IN2. As shown in FIG. 9, by giving a ramp wave that decreases with time as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

  After time T4, a ramp wave is applied as the reference signal Ramp to the second input terminal IN2. The comparison output of the comparison unit 31 is inverted at the timing when the voltage of the second input terminal IN2 to which the ramp wave is applied and the voltage of the first input terminal IN1 [n] substantially coincide. The reference signal generation unit 16 stops generating the ramp wave when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 has started (time T5). Since the measurement unit 32 performs measurement in the down-count mode at the first reading and the measurement unit 32 performs measurement in the up-count mode at the second reading, as the measurement value of the measurement unit 32, the right side of Equation (11) The measurement value according to item 3 is obtained. Therefore, it is possible to perform an AD conversion operation without a gain reduction due to the provision of the capacitive element.

The capacitance values C _{3 [1]} , C _{3 [2]} , and C _{3 [3]} are different. The reset levels output from the unit pixels 3 in each column are substantially the same, and the signal levels are often different. Therefore, the voltages V _{IN1 [1]} and V _{IN1 [2]} of the first input terminals IN1 [1], IN1 [2], and IN1 [3] at the start of comparison in the comparison unit 31 related to the second reading , V _{IN1 [3]} (Equation (11)) are often different. Thus, even when the comparison start timing in the comparison unit 31 related to the second reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  As described above, according to the present embodiment, after the reset operation by the transistors P6 and P7, the voltage difference between the first input terminal IN1 and the second input terminal IN2 guarantees the comparison operation by the comparison unit 31. The changing unit 18c (capacitance element C3 [n] and switching element SW1) changes the voltage of the first input terminal IN1 to a lower voltage so that the comparison unit 31 causes the reference signal Ramp and the pixel signal Pixel to change. The comparison operation can be performed reliably.

  In addition, since different offsets are applied to the first input terminal IN1 of the comparison unit 31 for each of the regions 39a, 39b, and 39c, each comparison unit 31 in each column AD conversion unit 30 of the regions 39a, 39b, and 39c Even when the comparison is started substantially simultaneously, the comparison units 31 can finish the comparison at different timings. As a result, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  In addition, the changing unit 18c can be easily configured by configuring the changing unit 18c so that the capacitance value of the capacitive element C3 [n] of the changing unit 18c is different for each of the regions 39a, 39b, and 39c.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. In the present embodiment, the changing unit is different from that of the second embodiment. FIG. 10 shows an example of the configuration of the column processing unit 15 including the column AD conversion unit 30 and the changing unit 18d. The other configuration is substantially the same as the configuration shown in FIG.

The changing unit 18d includes a capacitive element and a switch element. One end of the capacitive element is connected to the second input terminal of the comparison unit 31, and the other end of the capacitive element is connected to the voltage source V1 (first voltage source) and the reference signal generation unit 16 via the switch element. The reference signal line is connected to a reference signal line to which a reference signal Ramp (second voltage source) is supplied. The voltage source V1 supplies a power supply voltage (voltage value: V ₁ ) to the changing unit 18d. A capacitive element included in the changing unit 18d is a capacitive element C4 [n] (n: 1 to 3), and a capacitance value thereof is C _{4 [n]} (n: 1 to 3). Capacitance of the capacitor C4 [1] of the changing unit 18d corresponding to the column AD conversion section 30 in the region 39a is C _{4 [1].} Capacitance of the capacitor C4 [2] of the change section 18d corresponding to the column AD conversion section 30 of the region 39b is C _{4 [2].} Capacitance of the capacitor C4 [3] of the change section 18d corresponding to the column AD conversion section 30 in the region 39c is C _{4 [3].} The magnitude relationship of each capacitance value C _{4 [n]} is, for example, C _{4 [1]} > C _{4 [2]} > C _{4 [3]} . These are merely examples, and need not be limited to these.

  The operations of the column AD conversion unit 30 and the change unit 18d at the time of the first read and the second read are the same as the operations of the column AD conversion unit 30 and the change unit 18a in the first embodiment. Omitted.

  Next, the configuration of the comparison unit 31 and the change unit 18d and details of the voltage change at the input terminal of the comparison unit 31 will be described. FIG. 11 shows an example of a specific circuit configuration of the comparison unit 31 and the change unit 18d. Hereinafter, only the parts of the circuit configuration of this example that are different from the first embodiment will be described.

  The changing unit 18d includes a capacitive element C4 [n] (second capacitive element) and a switch element SW2. One end of the capacitive element C4 [n] is connected to the gate of the transistor N2, and the other end of the capacitive element C4 [n] is connected to the first terminal of the switch element SW2. A second terminal of the switch element SW2 is connected to the voltage source V1, and a third terminal of the switch element SW2 is connected to the other end of the capacitive element C2. The switch element SW2 short-circuits the first terminal and the second terminal to connect the voltage source V1 and the other end of the capacitive element C4 [n], and short-circuits the first terminal and the third terminal. Thus, switching between the state in which the other end of the capacitive element C2 and the other end of the capacitive element C4 [n] are connected is performed.

  For example, the capacitive element C4 [n] may be configured by a plurality of unit capacitive elements having the same capacitance value, and the capacitance value may be changed by controlling the connection. In the configuration shown in FIG. 11, the capacitive element C2 is configured as a capacitive element C2 [n] (n: 1 to 3) having a different capacitance value for each region, and the capacitive element C2 [n] and the capacitive element C4 It is desirable that the total capacitance value of [n] is constant.

The operation of this example will be described below. Here, the voltage of the voltage source V1 is V ₁ , the reset level voltage is V _R , the signal level voltage is V _S (where V _S ≦ V _R ), the capacitance value of the capacitive element C2 is C ₂ , and the capacitive element C4 Let the capacity value of _[n] be C4 _[n] . Further, the second input terminal IN2 of the differential amplifier connected to the voltage source V1 via the capacitive element C4 [n] and the switch element SW2 is replaced with the second input terminal IN2 [n] (n: 1 to 3). To do. FIG. 11 shows the voltage change of the first input terminal IN1 and the second input terminal IN2 [n] of the differential amplifier in the comparison unit 31 and the waveform of the reference signal Ramp.

  After the reset level is given to the first input terminal IN1 as the pixel signal Pixel from the unit pixel 3, and the reference signal Ramp given from the reference signal generator 16 to the second input terminal IN2 [n] is stabilized, timing control is performed. The unit 20 activates the reset pulse Reset (low active) before the comparison unit 31 starts comparison. As a result, the transistors P6 and P7 are turned on to short-circuit the gates and drains of the transistors N1 and N2, and the voltages at the two input terminals are reset with the operating point of these transistors N1 and N2 as the drain voltage. During the reset operation, the other end of the capacitive element C4 [n] is connected to the voltage source V1 by the switch element SW2.

At the operating point determined by this reset, the voltages at the two input terminals of the differential amplifier, that is, the offset components of the gate voltages of the transistors N1 and N2, are almost canceled. That is, the voltages at the two input terminals of the differential amplifier are reset so as to be substantially the same voltage _VRST . At this time (time T1), the voltage at the first input terminal IN1 is V _RST and the voltage at the second input terminal IN2 [n] is V _RST . After reset, the transistors P6 and P7 are turned off.

Subsequently, the switching element SW2 connects the other end of the capacitive element C4 [n] to the other end of the capacitive element C2, so that the voltage of the second input terminal IN2 [n] to which the reference signal Ramp is applied, that is, the transistor N2 Is increased from the voltage V _RST to a predetermined voltage. The voltage V _{IN2 [n]} of the second input terminal IN2 [n] at this time (time T2) is expressed by the following expression (12), similar to the expression (5) in the second embodiment.

After the reset operation of the comparison unit 31, even if there is some variation in the voltage at the two input terminals of the differential amplifier that constitutes the comparison unit 31, V ₁ <V _Ramp (0) The voltage at the second input terminal IN2 [n] (equation (12)) at the start of the comparison in the comparison unit 31 is higher than the voltage (V _RST ) at the first input terminal IN1. As shown in FIG. 11, by giving a ramp wave that decreases with time as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

After time T2, a ramp wave is given as the reference signal Ramp to the second input terminal IN2 [n]. The second input terminal IN2 when the voltage of the ramp wave applied to the other end of the capacitive element C2 changes from V _Ramp (0) to V _Ramp (t) (V _Ramp (t)-V _Ramp (0)) The voltage V _{IN2 [n]} of _[n] is expressed by the following expression (13), similar to the expression (8) in the second embodiment. In the equation (13), since the coefficient of the third term on the right side is 1, also in the present embodiment in which the capacitive element C4 [n] is provided, the rate of change with time of the reference signal Ramp (the slope of the reference signal Ramp) is calculated. Thus, it is possible to keep the reference signal Ramp equal to the rate of change over time in the first embodiment.

  The comparison output of the comparison unit 31 is inverted at the timing when the second input terminal IN2 [n] to which the ramp wave is applied and the voltage of the first input terminal IN1 substantially coincide. The reference signal generation unit 16 stops generating the ramp wave when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 [n] is started (time T3).

After the reset operation of the comparison unit 31, the voltage according to the second term on the right side of the equation (12) is applied as an offset to the second input terminals IN2 [1], IN2 [2], IN2 [3]. The capacitance values C _{4 [1]} , C _{4 [2]} , and C _{4 [3]} are different from each other, and the reference signal Ramp given to the second input terminal IN2 [n] of the comparison unit 31 in each column is substantially the same. Therefore, different offsets are applied to the second input terminals IN2 [1], IN2 [2], IN2 [3], respectively. Therefore, the voltages V _{IN2 [1]} , V _{IN2 [2]} of the second input terminals IN2 [1], IN2 [2], IN2 [3] at the start of comparison in the comparison unit 31 related to the first reading, V _{IN2 [3]} (Equation (12)) is different. Thus, even when the comparison start timing in the comparison unit 31 related to the first reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

Subsequently, a signal level is given to the first input terminal IN1 as a pixel signal Pixel from the unit pixel 3. The voltage V _IN1 of the first input terminal IN1 at this time (time T4) is expressed by the following equation (14), similar to the equation (9) in the second embodiment.
V _IN1 = V _RST + (V _S -V _R ) (14)

At time T4 related to the second reading, the voltage of the second input terminal IN2 [n] to which the reference signal Ramp is applied is expressed by the above-described equation (12). Since V ₁ <V _Ramp (0) in equation (12) and V _S ≦ V _R in equation (14), voltage V _{IN2 [n] in} equation (12) is equal to voltage V _{IN1 in} equation (14). Higher than. That is, the voltage of the second input terminal IN2 [n] at the start of the comparison in the comparison unit 31 related to the second reading is higher than the voltage of the first input terminal IN1. As shown in FIG. 11, by giving a ramp wave that decreases with time as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

After time T4, a ramp wave is applied as the reference signal Ramp to the second input terminal IN2 [n]. The voltage V _{IN2 [n]} of the second input terminal IN2 [n] after the point in time when the ramp wave is applied to the second input terminal _{IN2 [n]} is expressed by the above-described equation (13). The comparison output of the comparison unit 31 is inverted at the timing at which the voltage of the second input terminal IN2 [n] to which the ramp wave is applied substantially matches the voltage of the first input terminal IN1. At a time point (time T5) when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 [n] is started, the reference signal generation unit 16 stops the ramp wave generation. Since the measurement unit 32 performs measurement in the down-count mode at the time of the first reading and the measurement unit 32 performs measurement in the up-count mode at the time of the second reading, as the measurement value of the measurement unit 32, the right side of Equation (14) Measured value according to item 2 (V _S -V _R ) is obtained.

As described above, the voltages V _{IN2 [1]} and V _{IN2 [} at the second input terminals IN2 [1], IN2 [2], and IN2 [3] at the start of comparison in the comparison unit 31 related to the second reading are described _{. 2]} and V _{IN2 [3]} are expressed by equation (12) and are different from each other. Thus, even when the comparison start timing in the comparison unit 31 related to the second reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  As described above, according to the present embodiment, after the reset operation by the transistors P6 and P7, the voltage difference between the first input terminal IN1 and the second input terminal IN2 guarantees the comparison operation by the comparison unit 31. The changing unit 18d (the capacitive element C4 [n] and the switching element SW2) changes the voltage of the second input terminal IN2 to a higher voltage so that the comparison unit 31 can generate the reference signal Ramp and the pixel signal Pixel. The comparison operation can be performed reliably.

  Further, since different offsets are applied to the second input terminal IN2 of the comparison unit 31 for each of the regions 39a, 39b, and 39c, each comparison unit 31 in each column AD conversion unit 30 of the regions 39a, 39b, and 39c Even when the comparison is started substantially simultaneously, the comparison units 31 can finish the comparison at different timings. As a result, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  In addition, the changing unit 18d can be easily configured by configuring the changing unit 18d so that the capacitance value of the capacitive element C4 [n] of the changing unit 18d is different for each of the regions 39a, 39b, and 39c.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described. In the present embodiment, the changing unit is different from that of the first embodiment. FIG. 12 shows an example of the configuration of the column processing unit 15 including the column AD conversion unit 30 and the changing unit 18e. The other configuration is substantially the same as the configuration shown in FIG.

The changing unit 18e is composed of a switch element. One end of the switch element is connected to the first input terminal of the comparison unit 31, and the other end of the switch element is connected to the voltage source V1 [n] (n: 1 to 3). The voltage source V1 [1] supplies a power supply voltage (voltage value: V _{1 [1]} ) to the changing unit 18e corresponding to the column AD conversion unit 30 in the region 39a. The voltage source V1 [2] supplies a power supply voltage (voltage value: V _{1 [2]} ) to the changing unit 18e corresponding to the column AD conversion unit 30 in the region 39b. The voltage source V1 [3] supplies a power supply voltage (voltage value: V _{1 [3]} ) to the changing unit 18e corresponding to the column AD conversion unit 30 in the region 39c. The magnitude relationship of each voltage value V _{1 [n]} (n: 1 to 3) is, for example, V _{1 [1]} > V _{1 [2]} > V _{1 [3]} . These are merely examples, and need not be limited to these.

  The operations of the column AD conversion unit 30 and the change unit 18e at the time of the first read and the second read are the same as the operations of the column AD conversion unit 30 and the change unit 18a in the first embodiment. Omitted.

  Next, the configuration of the comparison unit 31 and the change unit 18e and details of the voltage change at the input terminal of the comparison unit 31 will be described. FIG. 13 shows an example of a specific circuit configuration of the comparison unit 31 and the change unit 18e. Hereinafter, only the parts of the circuit configuration of this example that are different from the first embodiment will be described.

  The changing unit 18e is composed of a switch element SW5. One end of the switch element SW5 is connected to the gate of the transistor N1, and the other end of the switch element SW5 is connected to the voltage source V1 [n] (n: 1 to 3). The switch element SW5 is controlled in an ON state and an OFF state by a control signal (not shown) from the timing control unit 20.

The operation of this example will be described below. Here, the voltage of the voltage source V1 [n] is V _{1 [n]} , the reset level voltage is V _R , the signal level voltage is V _S (where V _S ≦ V _R ), and the capacitance value of the capacitive element C1 is C ₁ In addition, the first input terminal IN1 of the differential amplifier connected to the voltage source V1 [n] via the switch element SW5 is defined as the first input terminal IN1 [n] (n: 1 to 3). FIG. 13 shows the voltage change of the first input terminal IN1 [n] and the second input terminal IN2 of the differential amplifier in the comparison unit 31 and the waveform of the reference signal Ramp.

  After the reset level is given to the first input terminal IN1 [n] as the pixel signal Pixel from the unit pixel 3, and the reference signal Ramp given from the reference signal generator 16 to the second input terminal IN2 is stabilized, timing control is performed. The unit 20 activates the reset pulse Reset (low active) before the comparison unit 31 starts comparison. As a result, the transistors P6 and P7 are turned on to short-circuit the gates and drains of the transistors N1 and N2, and the voltages at the two input terminals are reset with the operating point of these transistors N1 and N2 as the drain voltage. During the reset operation, the switch element SW5 is in the OFF state, and the other end of the switch element SW5 is disconnected from the voltage source V1 [1].

At the operating point determined by this reset, the voltages at the two input terminals of the differential amplifier, that is, the offset components of the gate voltages of the transistors N1 and N2, are almost canceled. That is, the voltages at the two input terminals of the differential amplifier are reset so as to be substantially the same voltage _VRST . At this time (time T1), the voltage of the first input terminal IN1 [n] is V _RST and the voltage of the second input terminal IN2 is V _RST . After reset, the transistors P6 and P7 are turned off.

Subsequently, when the switch element SW5 is switched from the OFF state to the ON state, the voltage of the first input terminal IN1 [n] to which the pixel signal Pixel is supplied, that is, the gate voltage of the transistor N1 is changed from the voltage _VRST to the predetermined voltage V Changed to _{1 [n]} . At this time (time T2), the voltage of the first input terminal IN1 [n] is V _{1 [n]} and the voltage of the second input terminal IN2 is V _RST . Here, the relationship between the voltage V _{1 [n]} and the reset voltage V _RST of the voltage source V1 [n] is _{V 1 [n] <V RST} . The switch element SW5 is turned on after being turned on.

Even after the reset operation of the comparison unit 31, even if there is some variation in the voltage of the two input terminals of the differential amplifier that constitutes the comparison unit 31, V _{1 [n]} <V _RST. The voltage (V _{1 [n]} ) of the first input terminal IN1 [n] at the start of the comparison in the comparison unit 31 is lower than the voltage (V _RST ) of the second input terminal IN2. As shown in FIG. 13, by giving a ramp wave that decreases with time as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

  After time T2, a ramp wave is applied as the reference signal Ramp to the second input terminal IN2. The comparison output of the comparison unit 31 is inverted at the timing when the voltage of the second input terminal IN2 to which the ramp wave is applied and the voltage of the first input terminal IN1 [n] substantially coincide. The reference signal generator 16 stops generating the ramp wave when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 has started (time T3).

After the reset operation of the comparison unit 31, the difference between V _{1 [n]} and V _RST is applied as an offset to the first input terminals IN1 [1], IN1 [2], IN1 [3]. Since the voltage values V _{1 [1]} , V _{1 [2]} , and V _{1 [3]} are different, the offsets are different for the first input terminals IN1 [1], IN1 [2], and IN1 [3] Is applied. Further, the voltages V _{1 [n]} of the first input terminals IN1 [1], IN1 [2], IN1 [3] at the start of comparison in the comparison unit 31 related to the first reading are different. Thus, even when the comparison start timing in the comparison unit 31 related to the first reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  Subsequently, the signal level is given to the first input terminal IN1 [n] as the pixel signal Pixel from the unit pixel 3. Hereinafter, the voltage of the first input terminal IN1 [n] at the time when the signal level is input (time T4) will be described. Hereinafter, description will be made assuming a parasitic capacitance CP between the first input terminal IN1 [n] and the ground GND.

When the voltage of the first input terminal IN1 [n] is changed from V _RST to V _{1 [n]} by the switch element SW5 (time T2), the capacitance element C1 to which the reset level is given as the pixel signal Pixel voltage at the other end is V _R. At the time (time T4) when the signal level is input as the pixel signal Pixel, the voltage at the other end of the capacitive element C1 becomes V _S. Assuming that the change in voltage at the other end of the capacitive element C1 from time T2 to time T4 is ΔV5, ΔV5 is expressed by the following equation (15).
ΔV5 = V _S -V _R ... (15)

Since the transistor P6 and the switch element SW5 are in the OFF state from time T2 to time T4, the charge amount accumulated in the capacitive element C1 and the parasitic capacitance CP is held. Therefore, if the change in voltage of the first input terminal IN1 [n] from time T2 to time T4 is ΔV6, ΔV6 is expressed by the following equation (16). In the equation (16), C _P is a capacitance value of the parasitic capacitance CP.

If you can ignore the C _P compared to _{C 1 (C 1 >> C P} ), the ΔV6 = ΔV5. Since the voltage of the first input terminal IN1 [n] at time T2 is V _{1 [n]} , the voltage V _{IN1 [n]} of the first input terminal IN1 [n] at time T4 is expressed by the following equation (17): It becomes.
V _{IN1 [n]} = V _{1 [n]} + ΔV6
= V _{1 [n]} + ΔV5
= V _{1 [n]} + (V _S -V _R ) (17)

Since V _{1 [n]} <V _RST and V _S ≦ V _R , the voltage of the first input terminal IN1 [n] at the start of comparison in the comparison unit 31 related to the second reading (Equation (17)) Becomes lower than the voltage (V _RST ) of the second input terminal IN2. As shown in FIG. 13, by giving a ramp wave that decreases with time as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

  After time T4, a ramp wave is applied as the reference signal Ramp to the second input terminal IN2. The comparison output of the comparison unit 31 is inverted at the timing when the voltage of the second input terminal IN2 to which the ramp wave is applied and the voltage of the first input terminal IN1 [n] substantially coincide. The reference signal generation unit 16 stops generating the ramp wave when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 has started (time T5). Since the measurement unit 32 performs measurement in the down-count mode at the time of the first reading and the measurement unit 32 performs measurement in the up-count mode at the time of the second reading, as the measurement value of the measurement unit 32, the right side of Equation (17) The measurement value according to item 2 is obtained.

As described above, the voltage values V _{1 [1]} , V _{1 [2]} , and V _{1 [3]} are different. The reset levels output from the unit pixels 3 in each column are substantially the same, and the signal levels are often different. Therefore, the voltages V _{IN1 [1]} and V _{IN1 [2]} of the first input terminals IN1 [1], IN1 [2], and IN1 [3] at the start of comparison in the comparison unit 31 related to the second reading , V _{IN1 [3]} (Equation (17)) are often different. Thus, even when the comparison start timing in the comparison unit 31 related to the second reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  As described above, according to the present embodiment, after the reset operation by the transistors P6 and P7, the voltage difference between the first input terminal IN1 and the second input terminal IN2 guarantees the comparison operation by the comparison unit 31. The changing unit 18e (switching element SW5) changes the voltage of the first input terminal IN1 to a lower voltage so that the comparison unit 31 reliably performs the comparison operation between the reference signal Ramp and the pixel signal Pixel. It can be carried out.

  In addition, since different offsets are applied to the first input terminal IN1 of the comparison unit 31 for each of the regions 39a, 39b, and 39c, each comparison unit 31 in each column AD conversion unit 30 of the regions 39a, 39b, and 39c Even when the comparison is started substantially simultaneously, the comparison units 31 can finish the comparison at different timings. As a result, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  In addition, the changing unit 18e can be easily configured by connecting the changing unit 18e to a different voltage source for each of the regions 39a, 39b, and 39c.

(Sixth embodiment)
Next, a sixth embodiment of the present invention will be described. In the present embodiment, the changing unit is different from that of the first embodiment. FIG. 14 shows an example of the configuration of the column processing unit 15 including the column AD conversion unit 30 and the changing unit 18f. The other configuration is substantially the same as the configuration shown in FIG.

The changing unit 18f is composed of a switch element. One end of the switch element is connected to the second input terminal of the comparison unit 31, and the other end of the switch element is connected to the voltage source V1 [n] (n: 1 to 3). The voltage source V1 [1] supplies a power supply voltage (voltage value: V _{1 [1]} ) to the changing unit 18f corresponding to the column AD conversion unit 30 in the region 39a. The voltage source V1 [2] supplies a power supply voltage (voltage value: V _{1 [2]} ) to the changing unit 18f corresponding to the column AD conversion unit 30 in the region 39b. The voltage source V1 [3] supplies a power supply voltage (voltage value: V _{1 [3]} ) to the changing unit 18f corresponding to the column AD conversion unit 30 in the region 39c. The magnitude relationship of each voltage value V _{1 [n]} (n: 1 to 3) is, for example, V _{1 [1]} > V _{1 [2]} > V _{1 [3]} . These are merely examples, and need not be limited to these.

  Since the operations of the column AD conversion unit 30 and the change unit 18f at the time of the first read and the second read are the same as the operations of the column AD conversion unit 30 and the change unit 18f in the first embodiment, an explanation will be given. Omitted.

  Next, the configuration of the comparison unit 31 and the change unit 18f and details of the voltage change at the input terminal of the comparison unit 31 will be described. FIG. 15 shows an example of a specific circuit configuration of the comparison unit 31 and the change unit 18f. Hereinafter, only the parts of the circuit configuration of this example that are different from the first embodiment will be described.

  The changing unit 18f is configured by a switch element SW6. One end of the switch element SW6 is connected to the gate of the transistor N2, and the other end of the switch element SW6 is connected to the voltage source V1 [n] (n: 1 to 3). The switch element SW6 is controlled to be in an ON state and an OFF state by a control signal (not shown) from the timing control unit 20.

The operation of this example will be described below. Here, the voltage of the voltage source V1 [n] is V _{1 [n]} , the reset level voltage is V _R , the signal level voltage is V _S (where V _S ≦ V _R ), and the capacitance value of the capacitive element C2 is and C _2. Further, the second input terminal IN2 of the differential amplifier connected to the voltage source V1 [n] via the switch element SW6 is defined as a second input terminal IN2 [n] (n: 1 to 3). FIG. 15 shows the voltage change of the first input terminal IN1 and the second input terminal IN2 [n] of the differential amplifier in the comparison unit 31 and the waveform of the reference signal Ramp.

  After the reset level is given to the first input terminal IN1 as the pixel signal Pixel from the unit pixel 3, and the reference signal Ramp given from the reference signal generator 16 to the second input terminal IN2 [n] is stabilized, timing control is performed. The unit 20 activates the reset pulse Reset (low active) before the comparison unit 31 starts comparison. As a result, the transistors P6 and P7 are turned on to short-circuit the gates and drains of the transistors N1 and N2, and the voltages at the two input terminals are reset with the operating point of these transistors N1 and N2 as the drain voltage. During the reset operation, the switch element SW6 is in the OFF state, and the other end of the switch element SW6 is disconnected from the voltage source V1 [1].

At the operating point determined by this reset, the voltages at the two input terminals of the differential amplifier, that is, the offset components of the gate voltages of the transistors N1 and N2, are almost canceled. That is, the voltages at the two input terminals of the differential amplifier are reset so as to be substantially the same voltage _VRST . At this time (time T1), the voltage at the first input terminal IN1 is V _RST and the voltage at the second input terminal IN2 [n] is V _RST . After reset, the transistors P6 and P7 are turned off.

Subsequently, when the switch element SW6 changes from the OFF state to the ON state, the voltage of the second input terminal IN2 [n] to which the reference signal Ramp is applied, that is, the gate voltage of the transistor N2 is changed from the voltage V _RST to a predetermined voltage. Highly changed. At this time (time T2), the voltage of the first input terminal IN1 is V _RST and the voltage of the second input terminal IN2 [n] is V _{1 [n]} . Here, the relationship between the voltage V _{1 [n]} of the voltage source V1 [n] and the reset voltage V _RST is V _RST <V _{1 [n]} . The switch element SW6 is turned on after being turned on.

Even after the reset operation of the comparison unit 31, even if there is some variation in the voltage at the two input terminals of the differential amplifier that composes the comparison unit 31, V _RST <V _{1 [n].} The voltage (V _{1 [n]} ) of the second input terminal IN2 [n] at the start of the comparison in the comparison unit 31 related to is higher than the voltage (V _RST ) of the first input terminal IN1. As shown in FIG. 13, by giving a ramp wave that decreases with time as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

  After time T2, a ramp wave is given as the reference signal Ramp to the second input terminal IN2 [n]. The comparison output of the comparison unit 31 is inverted at the timing at which the voltage of the second input terminal IN2 [n] to which the ramp wave is applied substantially matches the voltage of the first input terminal IN1. The reference signal generation unit 16 stops generating the ramp wave when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 [n] is started (time T3).

After the reset operation of the comparison unit 31, the difference between V _{1 [n]} and V _RST is applied as an offset to the second input terminals IN2 [1], IN2 [2], IN2 [3]. Since the voltage values V _{1 [1]} , V _{1 [2]} , and V _{1 [3]} are different, the offset is different for the second input terminals IN2 [1], IN2 [2], and IN2 [3]. Is applied. Further, the voltages V _{1 [n]} of the second input terminals IN2 [1], IN2 [2], IN2 [3] at the start of comparison in the comparison unit 31 relating to the first reading are different. Thus, even when the comparison start timing in the comparison unit 31 related to the first reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

Subsequently, a signal level is given to the first input terminal IN1 as a pixel signal Pixel from the unit pixel 3. The voltage V _IN1 of the first input terminal IN1 at this time (time T4) is expressed by the following equation (18), similarly to the equation (9) in the second embodiment.
V _IN1 = V _RST + (V _S -V _R ) (18)

The voltage of the second input terminal IN2 [n] at the time when the signal level is input (time T4) is V _{1 [n]} . Since V _RST <V _{1 [n]} and V _S ≦ V _R , the voltage of the second input terminal IN2 [n] (V _{1 [n]} at the start of comparison in the comparison unit 31 related to the second reading ₎ ) Becomes higher than the voltage (V _RST ) of the first input terminal IN1. As shown in FIG. 13, by giving a ramp wave that decreases with time as the reference signal Ramp, the output of the comparison unit 31 can be reliably inverted during the comparison operation, and the comparison operation by the comparison unit 31 can be guaranteed. it can.

  After time T4, a ramp wave is applied as the reference signal Ramp to the second input terminal IN2 [n]. Hereinafter, the voltage of the second input terminal IN2 [n] to which the ramp wave is applied will be described. Hereinafter, description will be made assuming a parasitic capacitance CP between the second input terminal IN2 [n] and the ground GND.

The other end of the capacitive element C2 when the voltage of the ramp wave applied to the other end of the capacitive element C2 changes from V _Ramp (0) to V _Ramp (t) (V _Ramp (t)-V _Ramp (0)) If the change in voltage is ΔV7, ΔV7 is expressed by the following equation (19).
ΔV7 = V _Ramp (t)-V _Ramp (0) ・ ・ ・ (19)

Since the transistor P7 is in the OFF state from time T2 to time T4, the charge amount accumulated in the capacitive element C2 and the parasitic capacitance CP is retained. Therefore, the second voltage when the voltage of the ramp wave applied to the other end of the capacitive element C2 changes from V _Ramp (0) to V _Ramp (t) (V _Ramp (t)-V _Ramp (0)). If the change in the voltage of the input terminal IN2 [n] is ΔV8, ΔV8 is expressed by the following equation (20). In the equation (20), C _P is a capacitance value of the parasitic capacitance CP.

If negligible C _P compared to _{C 2 (C 2 >> C P} ), a ΔV7 = ΔV8. Since the voltage of the second input terminal IN2 [n] at the time T4 is V _{1 [n]} , the voltage V _{IN1 [n]} of the second input terminal IN2 [n] after the time T4 is (21) It becomes an expression.
V _{IN2 [n]} = V _{1 [n]} + ΔV8
= V _{1 [n]} + ΔV7
= V _{1 [n]} + (V _Ramp (t)-V _Ramp (0)) (21)

  The comparison output of the comparison unit 31 is inverted at the timing at which the voltage of the second input terminal IN2 [n] to which the ramp wave is applied substantially matches the voltage of the first input terminal IN1. The reference signal generation unit 16 stops generating the ramp wave when a predetermined period has elapsed since the input of the ramp wave to the second input terminal IN2 has started (time T5). Since the measurement unit 32 performs measurement in the down-count mode at the first readout and the measurement unit 32 performs measurement in the up-count mode at the second readout, as the measurement value of the measurement unit 32, the right side of Equation (18) The measurement value according to item 2 is obtained.

As described above, the voltages V _{IN2 [1]} and V _{IN2 [} at the second input terminals IN2 [1], IN2 [2], and IN2 [3] at the start of comparison in the comparison unit 31 related to the second reading are described _{. 2]} and V _{IN2 [3 ]} become V _{1 [n]} , which are different from each other. Thus, even when the comparison start timing in the comparison unit 31 related to the second reading is substantially the same, the comparison end timing is the same in the comparison unit 31 of each column AD conversion unit 30 in the regions 39a, 39b, and 39c. Different. As described above, since the comparison unit 31 ends the comparison operation at different timings for each of the regions 39a, 39b, and 39c, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  As described above, according to the present embodiment, after the reset operation by the transistors P6 and P7, the voltage difference between the first input terminal IN1 and the second input terminal IN2 guarantees the comparison operation by the comparison unit 31. The changing unit 18f (switch element SW6) changes the voltage of the second input terminal IN2 to a higher voltage so that the comparison unit 31 reliably performs the comparison operation between the reference signal Ramp and the pixel signal Pixel. It can be carried out.

  Further, since different offsets are applied to the second input terminal IN2 of the comparison unit 31 for each of the regions 39a, 39b, and 39c, each comparison unit 31 in each column AD conversion unit 30 of the regions 39a, 39b, and 39c Even when the comparison is started substantially simultaneously, the comparison units 31 can finish the comparison at different timings. As a result, power concentration is reduced, so that AD conversion with higher accuracy can be performed.

  Further, the changing unit 18f can be easily configured by connecting the changing unit 18f to a different voltage source for each of the regions 39a, 39b, and 39c.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

  DESCRIPTION OF SYMBOLS 1,1001 ... Imaging device, 2,1002 ... Imaging part, 3,1003 ... Unit pixel, 11, 1011 ... Row control line, 12, 1012 ... Vertical selection part, 13, 1013 ... vertical signal lines, 14, 1014 ... horizontal selection unit, 15, 1015 ... column processing unit, 16, 1016 ... reference signal generation unit, 17, 1017 ... output unit, 18a, 18b , 18c, 18d, 18e, 18f, 1018 ... change unit, 20, 1020 ... timing control unit, 30, 1030 ... column AD conversion unit, 31, 1031 ... comparison unit, 32, 1032 ..Measurement unit, 1005 ... Reading current source unit, 1006 ... Analog unit

Claims (10)

A plurality of unit pixels having photoelectric conversion elements are arranged in a matrix, and an imaging unit that outputs an analog signal to a column signal line corresponding to each column of the unit pixel array;
A reference signal generator that generates a reference signal that increases or decreases over time;
A row selection unit that selects and controls each unit pixel of the imaging unit for each row of the array of the unit pixels;
A first input terminal electrically connected to the column signal line; and a second input terminal electrically connected to the reference signal generation unit via a first capacitor, and A differential amplifier that compares the voltage of the first input terminal and the second input terminal; and a reset unit that resets the voltage of the first input terminal and the second input terminal;
A measurement unit for measuring a comparison time from a comparison start to a comparison end by the comparison unit;
A switch element, one end of the switch element is connected to the second input terminal, the other end of the switch element is connected to a voltage source after a reset operation by the reset unit, and the first input terminal and A change unit that applies an offset according to the voltage of the voltage source to the second input terminal so that the voltage difference of the second input terminal is a voltage that guarantees a comparison operation by the comparison unit;
Have
The plurality of unit pixels arranged in the imaging unit include the unit pixels included in a first pixel group and the unit pixels included in a second pixel group different from the first pixel group. ,
The offset applied to the second input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group; and The offset applied to the second input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the second pixel group is different. An imaging device. The other end of the switch element of the change unit of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group is connected. The switch included in the changing unit according to the comparing unit connected to the column signal line corresponding to any column of the unit pixel array included in the second pixel group, the voltage value of the voltage source 2. The imaging apparatus according to claim 1 , wherein a voltage value of the voltage source to which the other end of the element is connected is different. A plurality of unit pixels having photoelectric conversion elements are arranged in a matrix, and an imaging unit that outputs an analog signal to a column signal line corresponding to each column of the unit pixel array;
A reference signal generator that generates a reference signal that increases or decreases over time;
A row selection unit that selects and controls each unit pixel of the imaging unit for each row of the array of the unit pixels;
A first input terminal electrically connected to the column signal line through a first capacitor element; a second input terminal electrically connected to the reference signal generation unit; and A differential amplifier that compares the voltage of the first input terminal and the second input terminal; and a reset unit that resets the voltage of the first input terminal and the second input terminal;
A measurement unit for measuring a comparison time from a comparison start to a comparison end by the comparison unit;
A switch element and a second capacitor element, wherein one end of the second capacitor element is connected to the first input terminal, and the other end of the second capacitor element is at the time of a reset operation by the reset unit; Connected to a first voltage source via a switch element, and after the reset operation by the reset unit, connected to a second voltage source different from the first voltage source via the switch element, and the first input An offset according to the voltages of the first voltage source and the second voltage source so that a voltage difference between the terminal and the second input terminal is a voltage that guarantees a comparison operation by the comparison unit. A changer applied to the input terminal of
Have
The plurality of unit pixels arranged in the imaging unit include the unit pixels included in a first pixel group and the unit pixels included in a second pixel group different from the first pixel group. ,
The offset applied to the first input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group; and The offset applied to the first input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the second pixel group is different. An imaging device. A plurality of unit pixels having photoelectric conversion elements are arranged in a matrix, and an imaging unit that outputs an analog signal to a column signal line corresponding to each column of the unit pixel array;
A reference signal generator that generates a reference signal that increases or decreases over time;
A row selection unit that selects and controls each unit pixel of the imaging unit for each row of the array of the unit pixels;
A first input terminal electrically connected to the column signal line; and a second input terminal electrically connected to the reference signal generation unit via a first capacitor, and A differential amplifier that compares the voltage of the first input terminal and the second input terminal; and a reset unit that resets the voltage of the first input terminal and the second input terminal;
A measurement unit for measuring a comparison time from a comparison start to a comparison end by the comparison unit;
A switching element and a second capacitive element, wherein one end of the second capacitive element is connected to the second input terminal, and the other end of the second capacitive element is in the reset operation by the reset unit; Connected to a first voltage source via a switch element, and after the reset operation by the reset unit, connected to a second voltage source different from the first voltage source via the switch element, and the first input An offset according to the voltages of the first voltage source and the second voltage source so that a voltage difference between the terminal and the second input terminal is a voltage that guarantees a comparison operation by the comparison unit. A changer applied to the input terminal of
Have
The plurality of unit pixels arranged in the imaging unit include the unit pixels included in a first pixel group and the unit pixels included in a second pixel group different from the first pixel group. ,
The offset applied to the second input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group; and The offset applied to the second input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the second pixel group is different. An imaging device. A capacitance value of the second capacitive element included in the change unit of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group; , The capacitance value of the second capacitor element included in the change unit of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the second pixel group 5. The imaging device according to claim 3 or claim 4 , wherein: The other end of the second capacitive element included in the change unit of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group is The voltage value of at least one of the first voltage source and the second voltage source to be connected corresponds to any column of the unit pixel array included in the second pixel group. The voltage source of at least one of the first voltage source and the second voltage source to which the other end of the second capacitive element of the change unit of the comparison unit connected to a column signal line is connected 5. The imaging device according to claim 3 or claim 4 , wherein the imaging device is different from the voltage value. 4. The imaging apparatus according to claim 3 , wherein the second voltage source is the analog signal. 5. The imaging apparatus according to claim 4 , wherein the second voltage source is the reference signal. A plurality of unit pixels having photoelectric conversion elements are arranged in a matrix, and an imaging unit that outputs an analog signal to a column signal line corresponding to each column of the unit pixel array;
A reference signal generator that generates a reference signal that increases or decreases over time;
A row selection unit that selects and controls each unit pixel of the imaging unit for each row of the array of the unit pixels;
A first input terminal electrically connected to the column signal line through a first capacitor element; a second input terminal electrically connected to the reference signal generation unit; and A differential amplifier that compares the voltage of the first input terminal and the second input terminal; and a reset unit that resets the voltage of the first input terminal and the second input terminal;
A measurement unit for measuring a comparison time from a comparison start to a comparison end by the comparison unit;
A switch element, one end of the switch element is connected to the first input terminal, the other end of the switch element is connected to a voltage source after a reset operation by the reset unit, and the first input terminal and A change unit that applies an offset according to the voltage of the voltage source to the first input terminal so that the voltage difference of the second input terminal is a voltage that guarantees a comparison operation by the comparison unit;
Have
The plurality of unit pixels arranged in the imaging unit include the unit pixels included in a first pixel group and the unit pixels included in a second pixel group different from the first pixel group. ,
The offset applied to the first input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group; and The offset applied to the first input terminal of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the second pixel group is different. An imaging device. The other end of the switch element of the change unit of the comparison unit connected to the column signal line corresponding to any column of the unit pixel array included in the first pixel group is connected. The switch included in the changing unit according to the comparing unit connected to the column signal line corresponding to any column of the unit pixel array included in the second pixel group, the voltage value of the voltage source 10. The imaging apparatus according to claim 9, wherein a voltage value of the voltage source to which the other end of the element is connected is different.

Images