JP6060500B2 - Image sensor - Google Patents

Description

The present invention relates to an imaging device.

  In recent years, video cameras and electronic cameras have become widespread. For these cameras, CCD type or CMOS type imaging devices are used. The CMOS imaging device is a device that guides signal charges accumulated in a light receiving pixel to a control electrode of a MOS transistor provided in a pixel portion, and outputs an amplified signal from a main electrode.

  For example, FIG. 8 is a circuit diagram showing a CMOS type solid-state imaging device. As shown in FIG. 8, the solid-state imaging device 1A includes a pixel unit 2 including a plurality of pixels PX arranged two-dimensionally, a vertical scanning circuit 3, a horizontal scanning circuit 4, and a column of pixels PX. Correspondingly provided vertical signal lines VL to which pixel signals of pixels PX in corresponding columns are supplied, PGAs (Programmable-Gain Amplifiers) connected to the respective vertical signal lines VL, and signals output from the PGAs ADC for A / D (analog / digital) conversion. In the example shown in FIG. 8, the number of pixels PX is 6 × 4 (6 rows, 4 columns), but the number is not limited to this. In FIG. 8, a pixel PX indicated by a symbol Gr is a pixel that senses Gr (green), a pixel PX indicated by a symbol R is a pixel that senses R (red), and a pixel PX indicated by a symbol B Are pixels that sense B (blue). As described above, in the pixel unit 2, pixels that sense Gr (green), pixels that sense R (red), and pixels that sense B (blue) are alternately arranged. Note that the configuration (circuit configuration) of the pixel PX is the configuration shown in FIG. 9 (details will be described later).

  When expanding the dynamic range of the pixel signal in the CMOS type solid-state imaging device, a method of expanding the dynamic range by combining the central pixel and a plurality of surrounding pixels is used. is there. For example, as shown in the weighting example of the image in FIG. 10, the same color pixel R1, pixel R2, and pixel R3 may be weighted and added. That is, the signal Sig1 output from the pixel R1 via the vertical signal line VL, the signal Sig2 output from the pixel R2 via the vertical signal line VL, and the signal output from the pixel R3 via the vertical signal line VL. Each signal level with Sig3 may be weighted and added (added at a constant rate) to improve the dynamic range of the signal with respect to noise.

  For example, when the signal level of the output signal Sig1 of the pixel R1 is Sig1, the signal level of the output signal Sig2 of the pixel R2 is Sig2, and the signal level of the output signal Sig3 of the pixel R3 is Sig3, “weighted addition value = Sig1 + 2 XSig2 + Sig3 "and the like.

When performing such weighted addition, the output signals Sig1, Sig2, and Sig3 respectively output from the pixels R1, R2, and R3 are converted into ADCs (A / D conversion circuits) in the solid-state imaging device 1A (in the chip). Alternatively, a method of converting to digital data (digital value) by an external A / D conversion circuit and performing weighted addition using the pixel signal converted to this digital value is used.
This is because the signals Sig1, Sig2, and Sig3 output from the vertical signal line VL are not output simultaneously from the vertical signal line VL and are sequentially output in time series, so that the signals Sig1, Sig2, and Sig3 are temporarily converted into digital data. This is because the digital value stored in the memory or the like is used to perform weighted addition after being converted into the data and stored in the memory or the like.

  There is a related solid-state imaging device (see Patent Document 1). An object of the solid-state imaging device described in Patent Document 1 is to provide a fixed imaging device including an ADC that can be arranged in a limited space. In this solid-state imaging device, a pixel signal output via a vertical readout line is held as a potential at a node, and a plurality of capacitors are capacitively coupled to a node where the pixel signal is held. Then, by controlling the transistors to sequentially switch the voltages at the counter electrodes of the plurality of capacitors, the potential at the node is lowered stepwise. The comparator compares the potential of the node with the potential of the pixel in the dark state, and determines the upper bit of the digital value when the potential of the node is lower. Subsequently, conversion of the lower bits of the digital value is started.

  There is also a related imaging device (see Patent Document 2). The imaging device described in Patent Document 2 achieves linearity that matches the characteristics of the human eye as much as possible and expands the dynamic range without dynamically changing the accumulation period of the solid-state imaging device. The purpose is to plan. In the image pickup apparatus described in Patent Document 2, the sensor chip is configured so that the image pickup signal read out from the pixel portion a plurality of times in one frame period is paralleled in N channels in an exposure period shorter than the existing one frame period specified in the standard. Output. The frame memory stores this image pickup signal for a plurality of frames. The frame addition circuit adds a plurality of frames of signals read from the frame memory to create a standard frame signal. As a result, the dynamic range can be increased to a square of N at the maximum.

JP 2010-239604 A JP 2009-239398 A

  As described above, as a method for expanding the dynamic range of a pixel signal in a CMOS type solid-state imaging device, the pixel signal output from the pixel is converted into an analog / digital (A / D) signal by an A / D conversion circuit provided inside or outside the imaging device. A method of performing weighted addition using the pixel signal converted into the digital value after performing the (digital) conversion processing is used.

  FIG. 11 is a diagram illustrating an example of an A / D conversion circuit that converts the above-described pixel signal into a digital value, and is a diagram illustrating a configuration of a normal A / D conversion circuit. In the A / D conversion circuit shown in FIG. 11, the configurations of the PGA (amplifier) 11 and the ADC (A / D conversion circuit) 12 are the same as those of the solid-state imaging device described in Patent Document 1. The circuit shown in FIG. 11 is configured by connecting an integrating ADC 12 at the subsequent stage of the PGA 11. The PGA 11 and the ADC 12 are connected to each vertical signal line VL in each column in the solid-state imaging device 1A shown in FIG. Is provided.

  The ADC 12 first reads the dark signal Vdark, holds it in the capacitor C10 connected to the input terminal (−) of the comparator CP1, then reads the pixel signal from the PGA 11, and sets the voltage level of this pixel signal to the node Hold at Vcm. Then, the voltage of the node Vcm is changed by changing the potential of the counter electrode of the capacitor C, and the voltage of the node Vcm and the voltage (dark potential Vdark) stored in the capacitor C10 are compared by the comparator CP1. / D conversion is performed. In this A / D conversion, the upper bits (for example, upper 3 bits) of the digital value of the pixel signal are determined by coarse conversion, and the lower bits (for example, pixel information) of the pixel information by fine conversion. , Lower 12 bits) is determined, and A / D conversion processing of the pixel signal is performed at high speed (refer to Patent Document 1 for details).

  When weighted addition is performed on the output signals Sig1, Sig2, and Sig3 of the pixels R1, R2, and R3 of the same color shown in FIG. 10, the individual signals Sig1, Sig2, and Sig3 are amplified by the PGA and amplified. A method is used in which the pixel signal is converted into digital data (digital value) by the ADC 12, temporarily stored in a memory, and weighted addition is performed using the digital value stored in the memory.

  However, in the method of weighted addition using the pixel data converted into the digital value, an error that occurs when the pixel signal is amplified by the PGA and a conversion error that occurs when the image signal is A / D converted are included as they are. The addition is performed at. For example, there is a conversion error or a quantization error caused by noise generated when a pixel signal is amplified by PGA, an error caused by a response delay, or noise generated in the ADC 12 (for example, noise caused by a changeover switch). In addition, the weights are added as they are. For this reason, weighted addition of pixel signals is performed without including errors that occur when the pixel signals are amplified by PGA, conversion errors that occur when the pixel signals are converted into digital values (digital data), and quantization errors. It was desired to provide a method that could be performed.

  The present invention has been made in view of such circumstances, and an object of the present invention is to amplify a pixel signal by an amplifier when a plurality of pixel signals output from a vertical signal line of a solid-state imaging device are weighted and added. Weighted addition can be performed without including errors (errors due to noise or response delay) generated during the process, and errors (conversion error or quantization error due to noise) generated when the pixel signal is A / D converted. An object of the present invention is to provide a solid-state imaging device that can be used.

The present invention has been made to solve the above problem, an imaging device of the present invention includes a first pixel for generating a first signal by incident light to generate a second signal by the light entering A signal line connected to the second pixel, the signal line outputting the first signal generated by the first pixel and the second signal generated by the second pixel, respectively. A first holding unit that holds the first signal output to the signal line; and a second holding unit that holds the second signal output to the signal line while holding the first signal in the first holding unit. A second holding unit different from the first holding unit, and the first signal held in the first holding unit and the second signal held in the second holding unit A signal processing unit that generates a third signal, and amplifies the third signal generated by the signal processing unit It includes a wide portion.
Further, an imaging device of the present invention includes a first pixel for outputting a first signal generated by the charge that has been photoelectrically converted to a signal line, a second signal generated by the charge generated through photoelectric conversion to the signal line a second pixel outputting a first signal output to the signal line, an amplifying unit that amplifies the second signal output to the signal line, respectively, said first amplified by the amplifying section a first holding portion for holding a signal, different from said first holding portion for holding said second signal which is amplified by the first holding portion to said first signal the amplifier section while maintaining the A signal processing unit that generates a third signal from the first signal held in the first holding unit and the second signal held in the second holding unit And comprising.
Further, an imaging device of the present invention includes a first pixel for outputting a first signal generated by the charge that has been photoelectrically converted to a signal line, a second signal generated by the charge generated through photoelectric conversion to the signal line The second pixel to be output, the first holding unit that holds the first signal output to the signal line, and the first signal that is output to the signal line while holding the first signal in the first holding unit A second holding unit different from the first holding unit that holds the second signal, the first signal held in the first holding unit, and the second signal held in the second holding unit A signal processing unit that generates a third signal using the second signal; and a conversion unit that converts the third signal generated by the signal processing unit into a digital signal.

In the solid-state imaging device of the present invention, a plurality of pixels sequentially output from the vertical signal line between the vertical signal line of the solid-state imaging device and an amplifier that amplifies the pixel signal output from the vertical signal line. A signal synthesizer for temporarily holding the signal and synthesizing one pixel signal from the held plurality of pixel signals is provided.
As a result, when a plurality of pixel signals output from the vertical signal line of the solid-state imaging device are weighted and added, an error (error due to noise or response delay) generated when the pixel signal is amplified by an amplifier, Weighted addition can be performed without including errors (conversion errors and quantization errors due to noise) that occur when A / D converting the signal.

It is a figure which shows the structure of the solid-state imaging device concerning the 1st Embodiment of this invention. 2 is a diagram illustrating a configuration of a weighted addition circuit 10. FIG. It is a time chart for demonstrating operation | movement (with weighting addition) of a weighting addition circuit. 4 is a time chart for explaining the operation of the weighted addition circuit 10 (without weighted addition). It is a figure which shows the structure of the solid-state imaging device concerning the 2nd Embodiment of this invention. It is a figure which shows the modification of 2nd Embodiment. It is a figure which shows the structure of the solid-state imaging device concerning the 3rd Embodiment of this invention. It is a figure which shows the example of a CMOS type solid-state imaging device. It is a figure which shows the example of a pixel circuit. It is a figure which shows the example of weighting of a pixel signal. It is a figure which shows the structure of the A / D conversion circuit as an example.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment]
(Description of pixel circuit)
First, the pixel PX constituting the pixel portion in the CMOS type solid-state imaging device will be briefly described. FIG. 9 is a diagram illustrating a configuration of the pixel circuit, and is a circuit diagram illustrating one pixel PX, a vertical signal line VL, and a constant current source TD.
The pixel circuit shown in FIG. 9 includes a photodiode PD as a photoelectric conversion unit, a floating diffusion FD as a charge-voltage conversion unit that receives charge and converts the charge into voltage, and a reset transistor RST that resets the potential of the floating diffusion FD. A selection transistor SEL that supplies a signal corresponding to the potential of the floating diffusion FD to the vertical signal line VL, a transfer transistor TX as a charge transfer unit that transfers charges from the photodiode PD to the floating diffusion FD, and a floating diffusion FD. It has an amplifying transistor SF as an amplifying unit that outputs a signal corresponding to the potential.

  In FIG. 9, VDD is a power supply potential. Note that the transistors SF, TX, RST, and SEL of the pixel PX are all NMOS transistors. The gates of the transfer transistors TX are commonly connected to each row, and a control signal φTX for controlling the transfer transistors TX is supplied from the vertical scanning circuit 3 thereto. The gates of the reset transistors RST are commonly connected to each row, and a control signal φRST for controlling the reset transistors RST is supplied from the vertical scanning circuit 3 (see FIG. 8). The gates of the selection transistors SEL are connected in common to each row, and a control signal φSEL for controlling the selection transistors SEL is supplied from the vertical scanning circuit 3 thereto.

  The photodiode PD of each pixel PX generates a signal charge according to the amount of incident light (subject light). The transfer transistor TX of each pixel PX is turned on during the high level period of the control signal φTX, and transfers the charge of the photodiode PD to the floating diffusion FD. The reset transistor RST is turned on during the high level period of the control signal φRST (the period of the power supply potential VDD), and resets the floating diffusion FD.

  The amplification transistor SF has its drain connected to the power supply potential VDD, its gate connected to the floating diffusion FD, and its source connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line VL. The constant current source TD supplies a current to the vertical signal line VL when the selection transistor SEL of the pixel PX corresponding to the vertical signal line VL is turned on.

  The amplification transistor SF of each pixel PX outputs a voltage to the vertical signal line VL via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during the high level period of the control signal φSEL, and connects the source of the amplification transistor SF to the vertical signal line VL.

  In the following description, the photodiode PD in the pixel R1 (see FIG. 10) is referred to as “photodiode PD1”, the transfer transistor TX in the pixel R1 is referred to as “transfer transistor TX1”, and the floating in the pixel R1. The diffusion FD may be referred to as “floating diffusion FD1”, and the amplification transistor SF in the pixel R1 may be referred to as “amplification transistor SF1”. The same applies to the pixel R2 and the pixel R3.

(Description of configuration of solid-state imaging device)
Next, the configuration of the solid-state imaging device of the present invention will be described. FIG. 1 is a diagram showing a configuration of a solid-state imaging apparatus according to the first embodiment of the present invention. The solid-state imaging device 1 shown in FIG. 1 is different from the conventional solid-state imaging device 1A shown in FIG. 8 in that a weighted addition circuit 10 is newly added to each of the vertical signal lines VL. This is the same as the solid-state imaging device 1A shown in FIG. For this reason, the same code | symbol is attached | subjected to a corresponding structure and the overlapping description is abbreviate | omitted.

  As shown in FIG. 1, the weighted addition circuit 10 is a circuit connected to the node Na on the signal output side of the vertical signal line VL, and a predetermined plurality of pixel signals (for example, sequentially output from the vertical signal line VL) The output signals of the pixels R1, R2, and R3 shown in FIG. 10 are held, and the held pixel signals are subjected to weighted addition, and the weighted and added pixel signals are output onto the node Na. The weighted and added pixel signal output from the weighted addition circuit 10 onto the node Na is amplified by the PGA 11 which is a variable gain amplifier, and the pixel signal amplified by the PGA 11 is converted into a digital value (digital data) by the ADC 12. Converted.

FIG. 2 is a diagram illustrating a configuration of the weighted addition circuit 10.
The weighted addition circuit 10 shown in FIG. 2 converts each of a plurality of pixel signals (three pixel signals Sig1, Sig2, Sig3 in the example shown in FIG. 2) sequentially output from the vertical signal line VL to the switches SW1, The pixel signals Sig1, Sig2, and Sig3 held in the capacitors C1, C2, and C3 are weighted and added to the capacitors C1, C2, and C3 via SW2 and SW3. That is, by adding the charges held in the capacitors C1, C2, and C3 (more precisely, redistributing the charges on the capacitors C1, C2, and C3), a voltage signal (weighted and added pixel signal) is generated on the node Na. ) Is generated. The weighted and added pixel signal is output to the PGA 11 via the switch SW4.

  The PGA 11 includes a differential amplifier (AM1), a switch PGA_AZ, a capacitor C11, and a variable capacitor C12. The reference voltage VREF is connected to the positive (+) input of the differential amplifier AM1, and the pixel signal input is connected to the negative (−) input via the capacitor C11. The output of the differential amplifier AM1 is connected to the negative feedback variable capacitor C12 and the switch PGA_AZ, and is also connected to the switch SPL (see FIG. 11) in the ADC 12. Further, the gain of the PGA 11 can be changed by the variable capacitor C12. The gain of the PGA 11 is switched according to the ISO sensitivity of the film (for example, ISO 100, 200, etc.).

As described above, the weighted addition circuit 10 includes the capacitors C1, C2, and C3 and the switches SW1, SW2, and SW3.
One end of the capacitor C1 is connected to the node Na via the switch SW1, and the other end of the capacitor C1 is connected to the circuit ground G. The switch SW1 is a switch for holding the pixel signal Sig1 output from the vertical signal line VL in the capacitor C1. For example, when the switch SW1 is turned on (the switches SW2, SW3, and SW4 are in the off state) at the timing (the output period of the signal Sig1) at which the pixel signal Sig1 is output to the vertical signal line VL (node Na), the switch SW1 is used. Charge is charged in the capacitor C1, and the pixel signal Sig1 is held in the capacitor C1.

  One end of the capacitor C2 is connected to the node Na via the switch SW2, and the other end of the capacitor C2 is connected to the circuit ground G. The switch SW2 is a switch for holding the pixel signal Sig2 in the capacitor C2. For example, when the switch SW2 is turned on (the switches SW1, SW3, and SW4 are in the off state) at the timing (the output period of the signal Sig2) when the pixel signal Sig2 is output to the vertical signal line VL (node Na), the switch SW2 is used. Charge is charged in the capacitor C2, and the pixel signal Sig2 is held in the capacitor C2.

One end of the capacitor C3 is connected to the node Na through the switch SW3, and the other end of the capacitor C3 is connected to the circuit ground G. The switch SW3 is a switch for holding the pixel signal Sig3 in the capacitor C3. For example, when the switch SW3 is turned on (the switches SW1, SW2, and SW4 are in the off state) at the timing (the output period of the signal Sig3) at which the pixel signal Sig3 is output to the vertical signal line VL (node Na), the switch SW3 is used. Charge is charged in the capacitor C3, and the pixel signal Sig3 is held in the capacitor C3.
In the circuit shown in FIG. 2, the switches SW1, SW2, SW3, and SW4 are indicated by contact symbols, but are actually MOS transistors, semiconductor switches, or the like. The same applies to the switch PGA_AZ in the PGA 11.

  The operation of the weighted addition circuit 10 is controlled by the weighted addition control unit 21. The weighted addition control unit 21 controls on / off of the switches SW1, SW2, and SW3 in the weighted addition circuit 10, and the switch SW4 inserted between the node Na and the input terminal (−) of the PGA11. ON / OFF (connection / release) (ie, switching between a conductive state and a non-conductive state) is controlled. In the weighted addition control unit 21, a pixel signal holding unit 22 and a pixel signal synthesis unit 23 are provided.

The pixel signal holding unit 22 controls the on / off of the switches SW1, SW2, and SW3 in accordance with the timings at which the pixel signals Sig1, Sig2, and Sig3 are output on the vertical signal line VL, whereby the pixel signal Sig1 , Sig2, and Sig3 are held in the capacitors C1, C2, and C3 corresponding to the pixel signals, respectively.
Further, the pixel signal combining unit 23 turns on the switches SW1, SW2, and SW3 in a lump after the pixel signals Sig1, Sig2, and Sig3 are held in the corresponding capacitors C1, C2, and C3, respectively. Charges charged in C1, C2, and C3 are added (more accurately, charges are redistributed on capacitors C1, C2, and C3), and a weighted and added pixel signal (voltage signal) is generated on node Na. . In addition, after the pixel signal subjected to the weighted addition on the node Na is generated, the pixel signal synthesis unit 23 turns on the switch SW4 and outputs the weighted and added pixel signal toward the PGA 11.

(Description of operation of weighted addition circuit 10)
As described above, in the weighted addition circuit 10, the capacitor C1 is charged with the signal Sig1, the capacitor C2 is charged with the signal Sig2, and the capacitor C3 is charged with the signal Sig3, and then the switches SW1, SW2, and SW3 are simultaneously turned on ( The switch SW4 is off), and potentials are generated on the node Na by the charges charged in the capacitors C1, C2, and C3, thereby performing weighted addition of the signals Sig1, Sig2, and Sig3. In this case, the weighting ratio for the signals Sig1, Sig2, and Sig3 is determined by the capacitance ratio of the capacitor C1, the capacitor C2, and the capacitor C3.

In this case, the charge Q1 held in the capacitor C1 by the signal Sig1 is
Q1 = C1 × Sig1,
The charge Q2 held in the capacitor C2 by the signal Sig2 is
Q2 = C2 × Sig2,
The charge Q3 held in the capacitor C3 by the signal Sig3 is
Q3 = C3 × Sig3.

Therefore, the total charge Qtotal held in the capacitors C1, C2, and C3 is
Qtotal = C1 × Sig1 + C2 × Sig2 + C3 × Sig3,
It becomes.
The total capacity Ctotal of the capacitors C1, C2, and C3 is
Ctotal = C1 + C2 + C3.

Therefore, when the potential of the node Na when the switches SW1, SW2 and SW3 are simultaneously turned on (the switch SW4 is turned off) is represented by VNa,
VNa = Qtotal / (C1 + C2 + C3).

Here, if C1: C2: C3 = a: b: c,
Qtotal = C1 * Sig1 + (b / a) * C1 * Sig2 + (c / a) * C1 * Sig3.
Therefore, since VNa = Qtotal / Ctotal,
VNa = {C1 × Sig1 + (b / a) × C1 × Sig2 + (c / a) × C1 × Sig3} / (C1 + C2 + C3),
It becomes.

Furthermore, as explained above, since C1: C2: C3 = a: b: c,
VNa = {C1 × Sig1 + (b / a) × C1 × Sig2 + (c / a) × C1 × Sig3} / (C1 + (b / a) C1 + (c / a) C1)
= {Sig1 + (b / a) * Sig2 + (c / a) * Sig3} / (1+ (b / a) + (c / a))
It becomes.

For example, if C1: C2: C3 = a: b: c = 1: 2: 1,
VNa = (Sig1 + (2/1) × Sig2 + (1/1) × Sig3) / (1+ (2/1) + (1/1)),
= (Sig1 + 2 × Sig2 + Sig3) / 4.
That is, a weighted addition of “1: 2: 1” can be performed on the signals Sig1, Sig2, and Sig3.

  As described above, the weighted addition circuit 10 shown in FIG. 2 generates the potential (voltage signal) at the node Na by weighting and adding the pixel signals Sig1, Sig2, and Sig3 output from the vertical signal line VL as analog signals. The potential generated at the node Na is amplified by the PGA 11 and output to the ADC 12. Therefore, when weighted addition is performed on the pixel signal output from the vertical signal line VL, noise generated in the PGA 11 or conversion error in the ADC 12 (for example, error or quantization error due to the effect of switch switching noise). The weighted addition can be performed with an analog signal without being affected by the above.

  In the above-described example, an example in which the highest weighting is given to the central pixel signal Sig2 with respect to the three pixel signals Sig1, Sig2, and Sig3 to be weighted (usually, with respect to the central pixel signal Sig2). However, the present invention is not limited to this, and the highest weight may be given to the pixel signals Sig1 and Sig3.

Further, the number of pixel signals to be subjected to weighted addition is not limited to three, and weighted addition can be performed on five pixel signals or seven pixel signals (basically an odd number of pixel signals). Basically, the weighted addition is performed on the odd number of pixel signals, but the weighted addition may be performed on the even number of pixel signals.
In addition, the pixel signals Sig1, Sig2, and Sig3 can be averaged by setting the capacitance ratio of the capacitors C1, C2, and C3 to “C1: C2: C3 = 1: 1: 1”. Furthermore, the solid-state imaging device 1 can be operated as a normal circuit without weighted addition (see FIG. 4 described later) by constantly turning off the switches SW1, SW2, and SW3.

(Description of the operation timing of the weighted addition circuit 10)
FIG. 3 is a time chart for explaining the operation of the weighted addition circuit 10. In the time chart shown in FIG. 3, FIG. 3A shows an on / off state (in the H state) of the selection transistor SEL1, the reset transistor RST1, and the transfer transistor TX1 in the red pixel R1 (see FIG. 10). ON). FIG. 3B shows the on / off state (on in the H state) of the selection transistor SEL2, the reset transistor RST2, and the transfer transistor TX2 in the red pixel R2 (see FIG. 10). 3 (C) shows the on / off state (on in the H state) of the selection transistor SEL3, the reset transistor RST3, and the transfer transistor TX3 in the red pixel R3 (see FIG. 10).

  FIG. 3D shows the ON / OFF state of each switch SW1, SW2, SW3 in the weighted addition circuit 10 (ON in the H state) and the ON / OFF state of the switch SW4 (ON in the H state). Is shown. FIG. 3E shows the on / off state of the switch PGA_AZ in the PGA 11 (on in the H state) and the output signal PGA_out of the PGA 11.

Hereinafter, the operation flow in the weighted addition circuit 10 will be described with reference to FIG.
First, before time T1, the transistors (SEL, RST, TX) shown in FIGS. 3A to 3C are all off, and the switches SW1, SW1 shown in FIG. It is assumed that SW2, SW3, and SW4 are all off. Further, as shown in FIG. 3E, it is assumed that the switch PGA_AZ in the PGA 11 is also off. In the state before this time T1, the switch SW4 is OFF, so the signal PGA_out is not output from the PGA 11.

  Then, the weighted addition process for the pixel signals Sig1, Sig2, and Sig3 is started from time T1. At the start of the weighted addition process, the switch SW4 is turned off, and the switch PGA_AZ in the PGA 11 is turned on (amplification gain is “0”), and the signal amplification operation in the PGA 11 is stopped.

Then, when the time T2 is reached, an operation of holding the pixel signal Sig1 of the pixel R1 in the capacitor C1 (charging operation of the capacitor C1) is started. In this case, as shown in FIG. 3A, at time T1, the selection transistor SEL1 in the pixel R1 is turned on, the reset transistor RST1 is turned off, and this state continues until time T4.
As shown in FIG. 3D, at time T1, the pixel signal holding unit 22 turns on the switch SW1 connected to the capacitor C1 in the weighted addition circuit 10, and this state is continued until time T4.

  Then, at time T3 between time T1 and time T4, as shown in FIG. 3A, the transfer transistor TX1 is turned on in the pixel R1 during the period t. As a result, the charge detected by the photodiode PD1 is transferred to the floating diffusion FD1 via the transfer transistor TX1, and a voltage signal is generated. A signal obtained by amplifying the voltage signal by the amplification transistor SF1 is vertically transmitted via the selection transistor SEL1. It is output to the signal line VL. The capacitor C1 is charged via the switch SW1 by a signal (pixel signal Sig1) output from the vertical signal line VL.

  At time T4, as shown in FIG. 3A, the selection transistor SEL1 is turned off and the reset transistor RST1 is turned on in the pixel R1, so that the pixel signal Sig1 is output to the vertical signal line VL. Stops. In the pixel signal holding unit 22, the holding of the pixel signal Sig1 by the capacitor C1 is completed by turning off the switch SW1 at time T4.

Subsequently, when the time T5 is reached, an operation of holding the pixel signal Sig2 of the pixel R2 in the capacitor C2 (charging operation of the capacitor C2) is started. In this case, as shown in FIG. 3B, at time T5, the selection transistor SEL2 in the pixel R2 is turned on, the reset transistor RST2 is turned off, and this state continues until time T7.
As shown in FIG. 3D, at time T5, the pixel signal holding unit 22 turns on the switch SW2 connected to the capacitor C2 in the weighted addition circuit 10, and this state is continued until time T7.

  Then, at time T6 between time T5 and time T7, as shown in FIG. 3B, the transfer transistor TX2 in the pixel R2 is turned on during the period t. As a result, the charge detected by the photodiode PD2 in the pixel R2 is transferred to the floating diffusion FD2 via the transfer transistor TX2 to generate a voltage signal, and the signal obtained by amplifying the voltage signal by the amplification transistor SF2 is the selection transistor SEL2. To the vertical signal line VL. The capacitor C2 is charged via the switch SW2 by a signal (pixel signal Sig2) output from the vertical signal line VL.

  At time T7, as shown in FIG. 3B, in the pixel R2, the selection transistor SEL2 is turned off and the reset transistor RST2 is turned on, so that the output of the pixel signal Sig2 to the vertical signal line VL is achieved. Stops. In the pixel signal holding unit 22, the holding of the pixel signal Sig2 by the capacitor C2 is completed by turning off the switch SW2 at time T7.

Subsequently, at time T8, an operation of holding the pixel signal Sig3 of the pixel R3 in the capacitor C3 (charging operation of the capacitor C3) is started. In this case, as shown in FIG. 3C, at time T8, the selection transistor SEL3 in the pixel R3 is turned on, the reset transistor RST3 is turned off, and this state continues until time T10.
As shown in FIG. 3D, at time T8, the pixel signal holding unit 22 turns on the switch SW3 connected to the capacitor C3 in the weighted addition circuit 10, and this state is continued until time T10.

  Then, at time T9 between time T8 and time T10, as shown in FIG. 3C, the transfer transistor TX3 is turned on in the pixel R3 during the period t. As a result, the charge detected by the photodiode PD3 in the pixel R3 is transferred to the floating diffusion FD3 via the transfer transistor TX3 to generate a voltage signal. A signal obtained by amplifying the voltage signal by the amplification transistor SF3 is the selection transistor SEL3. To the vertical signal line VL. The capacitor C3 is charged via the switch SW3 by a signal (pixel signal Sig3) output from the vertical signal line VL.

  At time T10, as shown in FIG. 3C, the selection transistor SEL3 is turned off and the reset transistor RST3 is turned on in the pixel R3, whereby the pixel signal Sig3 is output to the vertical signal line VL. Stops. In the pixel signal holding unit 22, the holding of the pixel signal Sig3 by the capacitor C3 is completed by turning off the switch SW3 at time T10.

  Then, at time T10, after the pixel signals Sig1, Sig2, and Sig3 are held in the capacitors C1, C2, and C3, respectively, at time T11, as shown in FIG. 3E, the switch PGA_AZ in the PGA 11 is displayed. Is turned off to start the amplification operation of the pixel signal in the PGA 11 after the time T11.

  Then, at time T12, weighted addition is started. That is, as shown in FIG. 3D, at time T12, the pixel signal synthesis unit 23 simultaneously turns on the switches SW1, SW2, and SW3, and this state is continued until time T13. As a result, the charges charged in the capacitors C1, C2, and C3 are added, and a voltage signal (pixel signal) weighted and added by the charges is generated on the node Na.

Thereafter, at time T14, as shown in FIG. 3D, the pixel signal synthesizing unit 23 turns on the switch SW4, and the switch SW4 is kept on until time T15. As a result, the voltage signal (weighted and added pixel signal) generated at the node Na is output to the PGA 11.
For this reason, as shown in FIG. 3D, after time T14, a signal PGA_out (a signal obtained by amplifying the weighted pixel signal) is output from the PGA 11. The signal PGA_out output from the PGA 11 is input to the ADC 12 (see FIG. 11). The signal level is held in the node Vcm in the ADC 12 and A / D conversion of the signal held in the node Vcm is performed. Is called.

FIG. 4 is a time chart for explaining the operation without weighted addition. As described above, the weighted addition circuit 10 can be operated as a circuit without weighted addition. When the weighted addition circuit 10 is operated as a circuit without weighted addition, as shown in FIG. 4, the pixel signal holding unit 22 includes switches SW1, SW2, and SW3 connected to capacitors C1, C2, and C3, respectively. Always off.
At time T1, the switch PGA_AZ in the PGA 11 is turned off, and after this time T1, the pixel signal amplification operation in the PGA 11 is started. Then, the pixel signal holding unit 22 turns on the switch SW4 during the period from time T2 to time T3, causes the pixel signal (not shown) output from the vertical signal line VL to be input to the PGA 11, and receives the pixel signal from the PGA 11 The amplified signal PGA_out is output.
In this way, the weighted addition circuit 10 can be operated as a circuit without weighted addition.

[Second Embodiment]
In the weighted addition circuit 10 of the first embodiment described above, in order to perform weighted addition of the signals Sig1, Sig2, and Sig3, the respective capacitances of the capacitors C1, C2, and C3 are set according to the weighting ratio. It was set to a different value. In contrast, as a second embodiment of the present invention, an example in which weighted addition is performed using capacitors having the same capacitance will be described.

FIG. 5 is a diagram showing a configuration of a weighted addition circuit 10A according to the second embodiment of the present invention. Compared with the weighted addition circuit 10 shown in FIG. 2, the weighted addition circuit 10A shown in FIG. 5A has the same capacitance for the capacitors C1, C2, C2 ′, C3, and two switches SW2 are connected to the switch SW2. The difference is that the capacitors C2 and C2 ′ are connected in parallel. Other configurations are the same as those of the weighted addition circuit 10 shown in FIG. For this reason, the same code | symbol is attached | subjected to a corresponding structure and the overlapping description is abbreviate | omitted.
In this way, by connecting the two capacitors C2, C2 ′ having the same capacitance in parallel, the pixel signals Sig1, Sig2, Sig3 using the capacitors C1, C2, C2 ′, C3 having the same capacitance. The weighting ratio for can be “1: 2: 1”.
In addition, since it is sufficient to form capacitor elements having the same capacitance without forming capacitor elements having different capacitances on the solid-state imaging device (chip), the manufacturing process of the solid-state imaging device can be simplified. .

  5A shows an example in which two capacitors C2 and C2 ′ are connected in parallel to one switch SW2. For example, as shown in FIG. 5B, two capacitors C2 and C2 ′ may be made independent and connected to the node Na individually using two switches SW2 and SW2 ′. When performing weighted addition, the two switches SW2 and SW2 'are simultaneously turned on / off.

Even in this case, the weighting ratio for the pixel signals Sig1, Sig2, and Sig3 can be set to “1: 2: 1” by using the capacitors C1, C2, C2 ′, and C3 having the same capacitance.
With this configuration, for example, the pixel signals Sig1, Sig2, and Sig3 can be averaged by controlling the switch SW2 to be always off. As shown in FIG. 6A, one end of the switch SW2 ′ connected to the capacitor C2 ′ can be connected to a connection point between the capacitor C2 and the switch SW1.

  Further, the number of capacitors connected to each of the switches SW1, SW2 and SW3 can be arbitrarily set. For example, by connecting one capacitor to the switch SW1, two capacitors to the switch SW2, and three capacitors to the switch SW3, the weighting ratio for the pixel signals Sig1, Sig2, and Sig3 is “1: 2: 3 ".

When a plurality of capacitors are connected to each switch SW1, SW2, SW3, a switch may be provided for each capacitor. For example, as shown in FIG. 6B, when two capacitors C2 and C2 ′ are connected to the switch SW2, a switch SW2 ′ is provided for the capacitor C2 ′, and three capacitors C3 and C3 are provided to the switch SW3. When connecting C3 ′ and C3 ″, switches SW3 ′ and SW3 ″ may be provided for the capacitors C3 ′ and C3 ″, respectively. In the example shown in FIG. 6B, weights are assigned by controlling on / off of the switches SW2 ′, SW3 ′, SW3 ″ provided in the capacitors C2 ′, C3 ′, C3 ″. It is possible to change the fit appropriately.
The number of switches SW1, SW2 and SW3 is not limited to three, and may be five or seven (basically an odd number), for example, and the number of capacitors connected to each switch. Is set, weighted addition can be performed at a desired ratio. That is, in the weighted addition circuit 10A, it is possible to set an arbitrary weighting for an arbitrary number of pixel signals by providing a switch for each of an arbitrary number of capacitors.

[Third Embodiment]
In the above-described weighted addition circuit 10 of the first embodiment and the weighted addition circuit 10A of the second embodiment, an example in which the weighted addition circuit is connected to the node Na that is a signal connection point between the vertical signal line VL and the PGA 11. However, the present invention is not limited to this, and a weighted addition circuit may be arranged on the output side of the PGA 11.

FIG. 7 is a diagram showing a configuration of a weighted addition circuit 10B according to the third embodiment of the present invention. The weighted addition circuit 10B shown in FIG. 7 has the same configuration as the weighted addition circuit 10 shown in FIG. 2, except that this weighted addition circuit 10B is connected to the node Nb on the output side of the PGA 11.
That is, the weighted addition circuit 10 illustrated in FIG. 2 performs weighted addition on the signal output from the vertical signal line VL, but the weighted addition circuit 10B illustrated in FIG. 7 performs weighted addition on the output signal PGA_out of the PGA 11. Is to do. The operation of the weighted addition circuit 10B shown in FIG. 7 is the same as that of the weighted addition circuit 10 shown in FIG.

Although the embodiment of the present invention has been described above, the correspondence relationship between the present invention and the above embodiment will be supplementarily described.
In the above embodiment, the solid-state imaging device 1 corresponds to the solid-state imaging device in the present invention, and the light-receiving pixels in the present invention correspond to the pixels PX shown in FIGS. The combining unit in the present invention corresponds to the weighted addition circuit 10, and the amplifier in the present invention corresponds to the PGA 11. In addition, the capacitors C1, C2, and C3 correspond to the capacitive element in the present invention, the switches SW1, SW2, and SW3 correspond to the first switch in the present invention, and the switch SW4 corresponds to the second switch in the present invention. .

The pixel signal holding means in the present invention corresponds to the pixel signal holding unit 22, the switches SW1, SW2, SW3 controlled by the pixel signal holding unit 22, and the capacitors C1, C2, C3 (“pixel signal”). Generically referred to as “holding part 22”).
In the pixel signal combining means in the present invention, the pixel signal combining unit 23, the switches SW1, SW2, SW3 controlled by the pixel signal combining unit 23, and the capacitors C1, C2, C3 correspond to each other (“pixel signal”). And is collectively referred to as a synthesis unit 23).

  (1) In the above embodiment, the solid-state imaging device 1 includes the vertical signal line VL that outputs the pixel signal of the selected row among the plurality of light receiving pixels PX arranged in a matrix for each column, and the vertical signal line VL. From the weighted addition circuit 10 that temporarily holds the pixel signals output from each of the plurality of pixel signals Sig1, Sig2, and Sig3 and outputs one synthesized pixel signal. PGA11 for amplifying the synthesized pixel signal to be output.

In the solid-state imaging device 1 having such a configuration, the weighted addition circuit 10 is disposed between the vertical signal line VL of the solid-state imaging device 1 and the PGA 11 that amplifies the pixel signal. The weighted addition circuit 10 temporarily holds a plurality of pixel signals Sig1, Sig2, and Sig3 that are sequentially output from the vertical signal line VL, and also outputs one pixel signal from the plurality of held pixel signals Sig1, Sig2, and Sig3. The synthesized pixel signal is output to the PGA 11.
As a result, when a plurality of pixel signals Sig1, Sig2, and Sig3 output from the vertical signal line VL of the solid-state imaging device 1 are weighted and added, errors (noise and response delays) generated when the pixel signals are amplified by the PGA 11 are added. The weighted addition can be performed without including errors caused by A / D conversion and error (conversion error due to noise or quantization error) generated when the pixel signal is A / D converted.

(2) In the above embodiment, the weighted addition circuit 10 is a capacitive element provided corresponding to each of a predetermined number of pixel signals Sig1, Sig2, Sig3, and each of the pixel signals Sig1, Sig2, Sig3 A plurality of capacitors C1, C2, and C3 for holding and a predetermined number of pixel signals Sig1, Sig2, and Sig3 are held in the capacitors C1, C2, and C3, respectively. Pixel signal holding unit 22 that holds pixel signals of a predetermined number of selected rows, and pixel signal synthesis that combines the pixel signals Sig1, Sig2, and Sig3 held in the plurality of capacitors C1, C2, and C3 into one pixel signal Unit 23.
The solid-state imaging device 1 having such a configuration includes a weighted addition circuit 10, and when the pixel signals Sig1, Sig2, and Sig3 are output from the vertical signal line VL, the weighted addition circuit 10 has a pixel signal holding unit. 22 controls the on / off of the switches SW1, SW2, and SW3, and holds the pixel signals Sig1, Sig2, and Sig3 in the capacitors C1, C2, and C3 corresponding to the pixel signals, respectively. Then, after each of the pixel signals Sig1, Sig2, and Sig3 is held in the capacitors C1, C2, and C3, the switches SW1, SW2, and SW3 are collectively turned on by the pixel signal synthesis unit 23, thereby a plurality of capacitors C1. , C2 and C3, the pixel signals Sig1, Sig2 and Sig3 are combined into one pixel signal.
Thus, when a plurality of pixel signals Sig1, Sig2, and Sig3 output from the vertical signal line VL of the solid-state imaging device 1 are weighted and added, the pixel signals Sig1, Sig1, and C3 are obtained by a simple method using the capacitors C1, C2, and C3. Sig2 and Sig3 can be weighted and added by analog signals on the output point (node Na) of the vertical signal line VL. For this reason, the weighted addition can be performed without including an error that occurs when the pixel signal is amplified by the PGA 11 or an error that occurs when the pixel signal is A / D converted.

(3) In the above embodiment, the weighted addition circuit 10 is the capacitors C1, C2, C3 provided corresponding to each of the predetermined number of pixel signals Sig1, Sig2, Sig3, and the capacitance thereof is the pixel. A plurality of capacitors C1, C2, and C3 set in accordance with respective weighting ratios of the signals Sig1, Sig2, and Sig3 are provided, and the pixel signal holding unit 22 applies the pixel signals Sig1, Sig2, and Sig3 to the pixel signal. The pixel signals synthesizer 23 holds all the pixel signals Sig1, Sig2, and Sig3 by the capacitors C1, C2, and C3 corresponding to the pixel signals. After that, the charges held in the plurality of capacitors C1, C2, C3 are transferred to the plurality of capacitors C1, C2. , Perform a plurality of pixel signals Sig1, Sig2, weighted addition of the Sig3 by redistributing over C3.
Thus, by setting the respective capacitances of the capacitors C1, C2, and C3 to desired values, it is possible to set the weighting ratio for the pixel signals Sig1, Sig2, and Sig3 to desired values.

  (4) In the above-described embodiment, the weighted addition circuit 10 includes a plurality of capacitors C1, C2, C2 ′, C3 having the same capacitance, and the pixel signal holding unit 22 includes the pixel signals Sig1, Sig2, Depending on the weighting ratio of Sig3, one or a plurality of capacitors out of a plurality of capacitors C1, C2, C2 ′, C3 are assigned to the respective pixel signals, and the respective pixel signals Sig1, Sig2, Sig3 are assigned. The capacitor assigned to the pixel signal is held by charging, and the pixel signal synthesizer 23 holds a plurality of pixel signals Sig1, Sig2, and Sig3 after all of the pixels are held by the capacitor assigned to the pixel signal. The electric charges charged in the capacitors C1, C2, C2 ′, C3 are converted into the plurality of capacitors C1, C2, C2 ′, C 3 is redistributed to perform weighted addition of a plurality of pixel signals Sig1, Sig2, and Sig3.

In the solid-state imaging device 1 having such a configuration, as shown in FIG. 5, the capacitances of the plurality of capacitors C1, C2, C2 ′, C3 are set to the same value, and the weighting ratio of the pixel signals Sig1, Sig2, Sig3. Accordingly, one or a plurality of capacitors out of the plurality of capacitors C1, C2, C2 ′, and C3 are assigned to the pixel signals Sig1, Sig2, and Sig3. Then, the pixel signal is held by charging one or a plurality of capacitors assigned to the pixel signal by the pixel signals Sig1, Sig2, and Sig3. Then, after all the pixel signals Sig1, Sig2, and Sig3 are held by the capacitors, the charges held in the capacitors C1, C2, C2 ′, and C3 are added on the capacitors C1, C2, C2 ′, and C3. Thus, the pixel signals Sig1, Sig2, and Sig3 are weighted and added.
Thereby, the weighted addition of the pixel signals Sig1, Sig2, and Sig3 can be performed using the capacitors C1, C2, C2 ′, and C3 having the same capacitance.

(5) In the above embodiment, the predetermined number of pixel signals is an odd number (for example, three or five) of pixel signals having three or more same color pixel signals.
Thereby, weighted addition by analog signals can be performed on the output point (node Na) of the vertical signal line VL with respect to an odd number of pixel signals such as three pixel signals or five pixel signals of the same color.

(6) In the above embodiment, the weighting ratio for the predetermined number of pixel signals Sig1, Sig2, and Sig3 is the middle of the plurality of pixel signals sequentially held in the capacitors C1, C2, and C3. The pixel signal is set to have the largest weight.
Thus, the pixel information of the central pixel signal Sig2 is emphasized, and the peripheral pixel signals Sig1 and Sig2 are weighted and added, thereby improving the dynamic range against noise.

  (7) In the above embodiment, the weighted addition circuit 10 includes the switches SW1, SW2, which selectively connect the node Na on the signal output side of the vertical signal line VL and each of the plurality of capacitors C1, C2, C3. When the pixel signal holding unit 22 holds the pixel signals Sig1, Sig2, and Sig3, the capacitor corresponding to the pixel signal and the node Na are connected by the switches SW1, SW2, and SW3, and the pixel signal Capacitors C1, C2, and C3 corresponding to the pixel signals are charged, and when the pixel signal combining unit 23 combines the pixel signals Sig1, Sig2, and Sig3, a plurality of capacitors C1, C2, and C3 and a node Na are respectively connected. By turning on the switches SW1, SW2 and SW3 to be connected together, a plurality of capacitors C1, C2, C 3 generates a pixel signal that is weighted and added on the node Na by the electric charge charged in the node 3.

In the solid-state imaging device 1 having such a configuration, when the pixel signal Sig1 is output to the vertical signal line VL, the switch SW1 is turned on, and the capacitor C1 is charged by the pixel signal Sig1, whereby the pixel signal Sig1 is converted to the capacitor C1. Hold on. When the pixel signal Sig2 is output to the vertical signal line VL, the switch SW2 is turned on and the capacitor C2 is charged with the pixel signal Sig2, thereby holding the pixel signal Sig2 in the capacitor C2. When the pixel signal Sig3 is output to the vertical signal line VL, the switch SW3 is turned on and the capacitor C3 is charged by the pixel signal Sig3, thereby holding the pixel signal Sig3 in the capacitor C3. Then, after the pixel signals Sig1, Sig2, and Sig3 are held in the capacitors C1, C2, and C3, the switches SW1, SW2, and SW3 that connect the capacitors C1, C2, and C3 and the node Na are turned on collectively. The pixel signals weighted and added onto the node Na are generated by the charges charged in the capacitors C1, C2, and C3.
Thus, the pixel signals Sig1, Sig2, and Sig3 output from the vertical signal line VL are held in the capacitors C1, C2, and C3 corresponding to the pixel signals by performing on / off control of the switches SW1, SW2, and SW3. be able to. Further, by performing on / off control of the switches SW1, SW2, and SW3, the charges charged in the capacitors C1, C2, and C3 can be added to generate a weighted pixel signal on the node Na.

  (8) In the above embodiment, the weighted addition circuit 10 includes the SW 4 that selectively connects the node Na and the PGA 11, and the pixel signal holding unit 22 receives a predetermined number of pixel signals Sig 1 from the vertical signal line VL. When each of Sig2 and Sig3 is output, the switches SW1, SW2, and SW3 corresponding to the pixel signal are turned on, and the capacitors C1, C2, and C3 corresponding to the pixel signal are charged by the pixel signal, and the pixel signal The combining unit 23 connects the plurality of capacitors C1, C2, C3 and the node Na after all the charging of the capacitors C1, C2, C3 by the predetermined number of pixel signals Sig1, Sig2, Sig3 is completed. The switches SW1, SW2, and SW3 are turned on all at once, and the charges charged in the plurality of capacitors C1, C2, and C3 In addition to generating a weighted addition pixel signal on the node Na, and generating a weighted addition pixel signal on the node Na, the switch SW4 that connects the node Na and the PGA 11 is turned on. The weighted and added pixel signal is output to the PGA 11.

In the solid-state imaging device 1 having such a configuration, when each of the plurality of pixel signals Sig1, Sig2, and Sig3 is output from the vertical signal line VL, the switch corresponding to the pixel signal is turned on, and the pixel signal A capacitor corresponding to the pixel signal is charged. Then, after all the charging of the capacitors C1, C2, and C3 by the plurality of pixel signals Sig1, Sig2, and Sig3 is completed, the switches SW1, SW2, and SW3 are turned on collectively, and the capacitors C1, C2, and C3 are charged. Charges are added (more precisely, charge is redistributed on the capacitors C1, C2, and C3) to generate a pixel signal weighted and added to the node Na. After the weighted pixel signal is generated on the node Na, the switch SW4 that connects the node Na and the PGA 11 is turned on to output the weighted pixel signal to the PGA 11.
As a result, the plurality of pixel signals Sig1, Sig2, and Sig3 output from the vertical signal line VL of the solid-state imaging device 1 are weighted and added on the output point (node Na) of the vertical signal line VL, and then the weighted and added pixels. The signal can be output toward the PGA 11. For this reason, the weighted addition circuit 10 is not affected by the PGA 11 when performing the weighted addition process. Further, it is possible to avoid unnecessary signals from being output from the PGA 11 during the weighted addition process.

  Although the embodiments of the present invention have been described above, the solid-state imaging device of the present invention is not limited to the illustrated examples described above, and various modifications can be made without departing from the scope of the present invention. Of course.

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 2 Pixel part 3 Vertical scanning circuit 4 Horizontal scanning circuit 10, 10A, 10B Weighting addition circuit 11 PGA
12 ADC (A / D conversion circuit)
20 Weighted addition control unit 21 Pixel signal holding unit 22 Pixel signal synthesis unit C1, c2, C3 Capacitors PX, R1, R2, R3 Pixel Sig1, Sig2, Sig3 Pixel signal Na node

Claims (29)

A signal line connected to a first pixel that generates a first signal by incident light and a second pixel that generates a second signal by incident light, the first line generated by the first pixel A signal line for outputting one signal and the second signal generated by the second pixel;
A first holding unit for holding the first signal output to the signal line; and holding the second signal output to the signal line in a state where the first signal is held in the first holding unit. A second holding unit different from the first holding unit, and the first signal held in the first holding unit and the second signal held in the second holding unit A signal processing unit for generating three signals;
An amplifying unit for amplifying the third signal generated by the signal processing unit;
An imaging device comprising:   The signal processing unit includes the first holding unit including a first capacitive element that holds the first signal output to the signal line, and the first holding the second signal output to the signal line. A second holding unit including a second capacitive element different from the capacitive element, the first signal held in the first capacitive element, and the second signal held in the second capacitive element The imaging device according to claim 1, wherein the third signal is generated.   The imaging device according to claim 2, wherein the first capacitive element has a capacitance different from that of the second capacitive element. The first holding unit includes the first capacitor element that holds the first signal output to the signal line,
The imaging device according to claim 2, wherein the second holding unit includes a plurality of the second capacitor elements that hold the second signal output to the signal line.   The imaging device according to claim 4, wherein the plurality of second capacitance elements are connected in parallel.   The imaging device according to claim 1, further comprising a conversion unit that converts the third signal amplified by the amplification unit into a digital signal. The first pixel has at least a first photoelectric conversion unit that converts light into electric charge,
The image sensor according to claim 1, wherein the second pixel includes at least a second photoelectric conversion unit that converts light into electric charge. The first pixel has a first output circuit that outputs the first signal generated by the charge photoelectrically converted by the first photoelectric conversion unit to the signal line,
The image sensor according to claim 7, wherein the second pixel includes a second output circuit that outputs the second signal generated by the charge photoelectrically converted by the second photoelectric conversion unit to the signal line. The signal line is connected to a third pixel that generates a fourth signal by incident light, and outputs the fourth signal generated by the third pixel;
The signal processing unit includes a third holding unit including a third capacitive element different from the first capacitive element and the second capacitive element that holds the fourth signal output to the signal line, and The third signal is generated from the first signal held in the first holding unit, the second signal held in the second holding unit, and the fourth signal held in the third holding unit. And
The second pixel, imaging device according to any one of the preceding claims 2, which is disposed between the first pixel and the third pixel to the signal line.   The imaging device according to claim 9, wherein the third capacitive element has a capacitance different from that of the second capacitive element. A first pixel that outputs a first signal generated by the photoelectrically converted charge to a signal line;
A second pixel that outputs a second signal generated by photoelectrically converted charges to the signal line;
An amplifying unit for amplifying the first signal output to the signal line and the second signal output to the signal line;
A first holding unit that holds the first signal amplified by the amplification unit; and the second signal that is amplified by the amplification unit while holding the first signal in the first holding unit. A second holding unit that is different from the first holding unit, and the third signal is held by the first signal held by the first holding unit and the second signal held by the second holding unit. A signal processing unit for generating a signal;
An imaging device comprising:   The signal processing unit includes a first holding unit including a first capacitive element that holds the first signal amplified by the amplification unit, and the first capacitor that holds the second signal amplified by the amplification unit. A second holding unit including a second capacitive element different from the element, the first signal held in the first capacitive element, and the second signal held in the second capacitive element; The imaging device according to claim 11, wherein the third signal is generated by the method.   The imaging device according to claim 12, wherein the first capacitive element has a capacitance different from that of the second capacitive element. The first holding unit includes the first capacitive element that holds the first signal amplified by the amplification unit,
The imaging device according to claim 12, wherein the second holding unit includes a plurality of the second capacitance elements that hold the second signal amplified by the amplification unit.   The imaging device according to claim 14, wherein the plurality of second capacitance elements are connected in parallel.   The imaging device according to claim 11, further comprising a conversion unit that converts the third signal generated by the signal processing unit into a digital signal. The first pixel has at least a first photoelectric conversion unit that converts light into electric charge,
The image sensor according to claim 11, wherein the second pixel includes at least a second photoelectric conversion unit that converts light into electric charge. The first pixel has a first output circuit that outputs the first signal generated by the charge photoelectrically converted by the first photoelectric conversion unit to the signal line,
The image sensor according to claim 17, wherein the second pixel has a second output circuit that outputs the second signal generated by the charge photoelectrically converted by the second photoelectric conversion unit to the signal line. A third pixel that outputs a fourth signal generated by the photoelectrically converted charge to the signal line;
The amplifying unit amplifies the fourth signal output to the signal line,
The signal processing unit includes a third holding unit including a third capacitive element different from the first capacitive element and the second capacitive element that holds the fourth signal amplified by the amplification unit, The third signal is generated by the first signal held in the first capacitive element, the second signal held in the second capacitive element, and the fourth signal held in the third capacitive element. And
The image sensor according to any one of claims 12 to 15 , wherein the second pixel is disposed between the first pixel and the third pixel with respect to the signal line.   The imaging device according to claim 19, wherein the third capacitive element has a capacitance different from that of the second capacitive element. A first pixel that outputs a first signal generated by the photoelectrically converted charge to a signal line;
A second pixel that outputs a second signal generated by photoelectrically converted charges to the signal line;
A first holding unit for holding the first signal output to the signal line; and holding the second signal output to the signal line in a state where the first signal is held in the first holding unit. A second holding unit different from the first holding unit, and the first signal held in the first holding unit and the second signal held in the second holding unit A signal processing unit for generating three signals;
A conversion unit that converts the third signal generated by the signal processing unit into a digital signal;
An imaging device comprising: The signal processing unit includes a first holding unit including a first capacitive element that holds the first signal, and a second holding unit that includes a second capacitive element different from the first capacitive element that holds the second signal. And having
The imaging device according to claim 21, wherein the third signal is generated by the first signal held in the first capacitive element and the second signal held in the second capacitive element.   The imaging device according to claim 22, wherein the first capacitor element has a capacitance different from that of the second capacitor element. The first holding unit includes the first capacitive element that holds the first signal,
The imaging device according to claim 22, wherein the second holding unit includes a plurality of the second capacitance elements that hold the second signal.   The imaging device according to claim 24, wherein the plurality of second capacitive elements are connected in parallel. The first pixel has at least a first photoelectric conversion unit that converts light into electric charge,
The imaging device according to any one of claims 21 to 25, wherein the second pixel includes at least a second photoelectric conversion unit that converts light into electric charge. The first pixel has a first output circuit that outputs the first signal generated by the charge photoelectrically converted by the first photoelectric conversion unit to the signal line,
27. The imaging device according to claim 26, wherein the second pixel includes a second output circuit that outputs the second signal generated by the charge photoelectrically converted by the second photoelectric conversion unit to the signal line. A third pixel that outputs a fourth signal generated by the photoelectrically converted charge to the signal line;
The signal processing unit includes a third holding unit including a third capacitive element different from the first capacitive element and the second capacitive element that holds the fourth signal output to the signal line, and The third signal is obtained by the first signal held in one capacitive element, the second signal held in the second capacitive element, and the fourth signal held in the third capacitive element. Generate and
The image sensor according to any one of claims 22 to 25 , wherein the second pixel is arranged between the first pixel and the third pixel with respect to the signal line.   The imaging device according to claim 28, wherein the third capacitive element has a capacitance different from that of the second capacitive element.

Images