JP4929075B2 - Solid-state imaging device, driving method thereof, and imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device, a camera system, and a driving method.

  In recent years, various signal readout methods for CMOS image sensors have been proposed. In general, a column parallel output type CMOS image sensor that selects pixels in one row in the pixel array and simultaneously reads signals generated in these pixels in the column direction is often used.

  Among them, a conventional CMOS image sensor disclosed in Patent Document 1 will be described with reference to FIG. FIG. 7 is a schematic configuration diagram of a conventional CMOS solid-state imaging device (CMOS image sensor) in which an AD converter is mounted on the same semiconductor substrate as the pixel unit.

  As shown in FIG. 7, the solid-state imaging device 1 includes a pixel unit (imaging unit) 10 in which a plurality of unit pixels 3 are arranged in rows and columns, and a drive control unit 7 provided outside the pixel unit 10. And a column processing unit 26 having a column AD circuit 25 arranged for each vertical column, and a DAC (Digital Analog Converter) that supplies a reference voltage for AD conversion to the column AD circuit 25 of the column processing unit 26. The reference signal generator 27 and the output circuit 28 are provided.

  The drive control unit 7 also includes a horizontal scanning circuit (column scanning circuit) 12 that controls column addresses and column scanning circuits, a vertical scanning circuit (row scanning circuit) 14 that controls row addresses and row scanning circuits, and a terminal 5a. The communication / timing control unit 20 is provided which receives the master clock CLK0 via the control circuit, generates various internal clocks, and controls the horizontal scanning circuit 12, the vertical scanning circuit 14, and the like.

  Each unit pixel 3 is connected to a row control line 15 controlled by the vertical scanning circuit 14 and a vertical signal line 19 that transmits a pixel signal to the column processing unit 26.

  Further, the column AD circuit 25 includes the reference voltage RAMP generated by the reference signal generator 27 and the vertical signal lines 19 (H0, H1,...) From the unit pixel 3 for each row control line 15 (V1, V2,...). The voltage comparison unit 252 for comparing with the analog pixel signal obtained via...) And the result of counting the time until the voltage comparison unit 252 completes the comparison process using the counter unit 254 is held. And a data storage unit 256 configured as a memory, and has an n-bit AD conversion function.

  Also, one input terminal RAMP of the voltage comparison unit 252 receives the stepped reference voltage RAMP generated by the reference signal generation unit 27 in common with the input terminal RAMP of the other voltage comparison unit 252 and the other input. The vertical signal lines 19 in the corresponding vertical columns are connected to the terminals, and pixel signal voltages are individually input from the pixel unit 10. Further, the output signal of the voltage comparison unit 252 is supplied to the counter unit 254.

  As for the circuit configuration of the ADC, the reference voltage RAMP is supplied to the comparator (voltage comparator), and at the same time, counting with the clock signal is started, and the analog pixel signal input via the vertical signal line 19 is referred to. The AD conversion is performed by counting until a pulse signal is obtained by comparing with the voltage RAMP.

  At this time, the signal level (noise level) immediately after the pixel reset and the true signal level (according to the amount of received light) with respect to the voltage mode pixel signal input through the vertical signal line 19 together with AD conversion. A process of taking a difference from Vsig is performed. As a result, noise signal components called fixed pattern noise (FPN) and reset noise can be removed. FIG. 7 shows a configuration in which only the true signal level Vsig is extracted by down-counting the noise level and up-counting the signal level.

  Further, the pixel data digitized by the column AD circuit 25 is transmitted to the horizontal signal line 18 via a horizontal selection switch (not shown) driven by a horizontal selection signal from the horizontal scanning circuit 12, and further to the output circuit 28. Entered.

  With the above configuration, pixel signals are sequentially output for each vertical column for each row from the pixel unit 10 in which light receiving elements as charge generation units are arranged in a matrix. Then, one image, that is, a frame image for the pixel unit 10 in which the light receiving elements are arranged on the matrix is shown as a set of pixel signals of the entire pixel unit 10.

  Next, detailed operations of the column AD circuit mounted on the solid-state imaging device shown in the prior art will be described with reference to timing charts of FIGS.

  First, for the first reading, the communication / timing control unit 20 first resets the count value of the counter unit 254 to the initial value “0” and sets the counter unit 254 to the down-count mode. Then, after the first reading from the unit pixel 3 in any row Hx to the vertical signal lines 19 (H1, H2,...) Is stabilized, the communication / timing control unit 20 goes to the reference signal generation unit 27. Then, the control data 4 for generating the reference voltage RAMP is supplied.

  In response to this, the reference signal generation unit 27 forms a stepped waveform (RAMP waveform) that is time-varying in a sawtooth shape (RAMP shape) as a whole as a comparison voltage to one input terminal RAMP of the voltage comparison unit 252. input. The voltage comparison unit 252 compares the comparison voltage of the RAMP waveform with the pixel signal voltage of an arbitrary vertical signal line 19 (Vx) supplied from the pixel unit 10.

  In addition, at the same time as the reference voltage RAMP input of the reference voltage RAMP waveform to the input terminal RAMP of the voltage comparison unit 252, the reference signal is used to measure the comparison time in the voltage comparison unit 252 with the counter unit 254 arranged for each row. In synchronization with the ramp waveform voltage generated from the generation unit 27 (t10), the count clock CK0 is input from the communication / timing control unit 20 to the clock terminal of the counter unit 254, and the initial value “0” is used as the first count operation. Start counting down.

  The voltage comparator 252 compares the ramp-shaped reference voltage RAMP from the reference signal generation unit 27 with the pixel signal voltage Vx input via the vertical signal line 19, and when both voltages become the same. The comparator output is inverted from the H level to the L level (t12).

  That is, the voltage signal corresponding to the reset component Vrst is compared with the reference voltage RAMP, and the magnitude is counted (counted) with the count clock CK0 in the time axis direction corresponding to the magnitude of the reset component Vrst, whereby the reset component Vrst. A count value corresponding to the size of is obtained. In other words, the counter unit 254 counts the magnitude of the reset component Vrst by counting the time from when the RAMP waveform change starts (that is, when the counter unit 254 starts counting) until the output of the voltage comparator 252 is inverted. A count value corresponding to is obtained.

  In addition, when a predetermined down-count period has elapsed (t14), the communication / timing control unit 20 stops the supply of control data to the voltage comparison unit 252 and the supply of the count clock CK0 to the count unit 254. As a result, the voltage comparison unit 252 stops generating the ramp-shaped reference voltage RAMP.

  At the time of the first reading, since the reset level Vrst in the pixel signal voltage Vx is detected by the voltage comparison unit 252 and the count operation is performed, the reset component ΔV of the unit pixel 3 is read out.

  Subsequently, in the second reading, in addition to the reset component ΔV, an operation of reading the signal component Vsig corresponding to the amount of incident light for each unit pixel 3 is performed. The difference from the first reading is that the counter unit 254 is set to the up-count mode. By performing the same reading as the first reading, a count value corresponding to the magnitude of the signal component Vsig is obtained.

In FIG. 7 and FIG. 9, the count operation in the counter unit 254 is down-counting at the first reading and up-counting at the second reading. On the other hand, only the Vsig signal component is extracted as a count value.
JP 2005-323331 A

  The conventional column-parallel output AD conversion configuration disclosed in Patent Document 1 needs to perform an AD conversion operation of a reset component during a period between pixel analog signal readout and reset readout. The first problem is that it is difficult to shorten the AD conversion period.

  Further, the AD conversion configuration has a second problem that it is difficult to shorten the AD conversion period shown in FIG. 9 because the analog reset readout of the pixel is performed after the AD conversion operation of the pixel signal component is completed. .

  Having the first and second problems increases the number of AD conversion bits, or if the AD conversion period required within one horizontal scanning period becomes longer due to a driving operation such as pixel mixing, the AD conversion period is output as a signal. It becomes longer than the period, and it becomes difficult to perform high-speed readout, which is a feature of a solid-state imaging device of column parallel output type and a solid-state imaging device provided with an AD conversion circuit for each column.

  Further, by having the first problem, the CDS (Correlated Double Sampling) period becomes longer by the AD conversion operation period of the reset component, compared to the solid-state imaging device having the conventional analog readout circuit without the column AD circuit. Thus, there is a third problem that the 1 / f noise of the pixel source follower circuit (pixel SF circuit) increases, and in particular, the fixed pattern noise (roughness) in the dark deteriorates.

  Further, since the CDS period becomes longer, the signal holding period in the pixel part charge holding FD (Floating Diffusion) part becomes longer at the time of reading out the signal component, the influence of the leakage in the FD part becomes larger, and the fixed pattern noise in the dark time. There is a fourth problem that (roughness, scratches) deteriorate.

  It is an object of the present invention to provide a solid-state imaging device having a column AD conversion unit, a driving method thereof, and a camera that shorten the CDS period and suppress the generation of noise.

  In order to solve the above problems, a solid-state imaging device according to the present invention is provided for each of a plurality of pixel units arranged in a two-dimensional matrix and for each column of the plurality of pixel units, and is output from the pixel unit in the corresponding column. Signal holding means for holding analog signals, and AD conversion means provided for each column of the plurality of pixel portions and for converting the analog signals held in the signal holding means into digital signals.

  According to this configuration, since the signal holding unit is provided between the plurality of pixel units and the AD conversion unit, the operation of the AD conversion unit converting into a digital signal and the operation of reading the analog signal from the plurality of pixel units are performed in parallel. Makes it possible to do. This parallelization can shorten the CDS period even when AD conversion is performed. By shortening the CDS period, the effect of suppressing the occurrence of 1 / f noise is enhanced, and in particular, rough components that occur in the dark can be suppressed.

  Here, the signal holding means is connected to the column signal line via the switch element connected to the column signal line for transmitting the analog signal output from the pixel portion in the corresponding column, A capacitor element that holds the analog signal may be included.

According to this configuration, the signal holding means can be configured with a simple circuit.
Here, the solid-state imaging device further maintains the switch element in an OFF state during the conversion operation by the AD conversion unit, and performs an analog signal from the pixel unit to the column signal line by the conversion operation by the AD conversion unit. A drive control means for driving in parallel with the operation of reading out may be provided.

  According to this configuration, the analog output unit of the pixel signal and the signal holding unit can be electrically cut off during the AD conversion period of the signal component of the pixel, and a leak component generated by the charge holding unit in the pixel unit is prevented. It can be prevented from being transmitted to the signal holding means.

  Here, each pixel unit includes photoelectric conversion means for converting light into signal charges, charge holding means for holding signal charges transferred from the photoelectric conversion means signals, and amplification for amplifying signal charges of the charge holding means. And a reset means for resetting a signal charge of the charge holding means, and the solid-state imaging device further comprises a drive control means for driving the plurality of pixel units, the signal holding means and the AD conversion means, The drive control unit drives each operation in the first to fourth periods, and in the first period, the reset component analog signal output from the amplifying unit is output in a state where the charge holding unit is reset. In the second period, read out from the pixel portion, the analog signal of the reset component held in the signal holding unit is converted into a digital signal. In the third period, the charge holding unit In the state where the signal charge transferred from the photoelectric conversion means signal is held, the analog signal of the signal component output from the amplification means is read from the pixel unit, and held in the signal holding means in the fourth period. An analog signal of a signal component is converted into a digital signal, and the drive control means includes a set of the second period and the third period, and a first period for the pixel period of the fourth period and other rows. You may make it drive so that the period of at least one set may overlap.

  Here, the drive control means may be driven so that the second period and the third period overlap.

  Here, the signal holding means is connected to the column signal line via the switch element connected to the column signal line for transmitting the analog signal output from the pixel portion in the corresponding column, A capacitive element that holds the analog signal, and the drive control unit causes the capacitive element to hold an analog signal of a reset component that is output in the first period by turning on the switch element. The switch element may be turned off during the conversion in the period 2.

  According to this configuration, since the second period and the third period overlap, the analog signal of the signal component is output from the pixel unit in parallel with the AD conversion unit converting the reset component of the pixel into a digital signal. It can be read out. In addition, it is possible to prevent leakage components generated in the charge holding means in the pixel portion from being transmitted to the signal holding means.

  Here, the drive control means may drive so that the fourth period overlaps with the first period for the pixel portions in other rows.

  Here, the signal holding means is connected to the column signal line via the switch element connected to the column signal line for transmitting the analog signal output from the pixel portion in the corresponding column, A capacitive element that holds the analog signal, and the drive control unit causes the capacitive element to hold an analog signal of a signal component that is output in the third period by turning on the switch element. The switch element may be maintained in the OFF state during the conversion in the period 4.

  According to this configuration, since the fourth period overlaps with the first period for the pixel portions in the other rows, the amplifying unit is parallel to the AD conversion unit converting the signal component of the pixel into a digital signal. However, it is possible to output the reset components of pixels in other rows in an analog manner. In addition, it is possible to prevent leakage components generated in the charge holding means in the pixel portion from being transmitted to the signal holding means.

  Here, the solid-state imaging device is further provided for each column of the plurality of pixel units, amplifies an analog signal output from the pixel unit in the corresponding column, and the capacitive element via the switch element You may make it provide the column amplifier connected to.

  According to this configuration, it is possible to amplify the voltage output of the analog signal from the pixel unit, and it is possible to improve the S / N and switch the gain.

  In addition, the driving method and the camera of the solid-state imaging device of the present invention have the same configuration and effects as the above-described solid-state imaging device.

  According to the solid-state imaging device of the present invention, the pixel analog signal readout operation and the AD conversion operation by the AD conversion means can be performed in parallel, and the CDS period for pixel readout can be shortened. By shortening the CDS period, it is possible to suppress the occurrence of the above-described 1 / f noise, and it is possible to suppress a rough component that occurs particularly in the dark.

  Further, the analog output portion of the pixel signal and the signal holding means can be electrically cut off during the AD conversion period of the signal component of the pixel, so that the leak component generated in the FD portion in the pixel is not transmitted to the signal holding means. Can be.

  Further, by making the analog readout period of the pixel reset component and the analog readout period of the pixel signal component equal, it is possible to make the pixel reset readout state and the pixel signal readout state the same, and noise removal in CDS The effect is increased. For example, even if there is a difference between the pixel central portion and the pixel peripheral portion regarding the period until the FD portion is stabilized, even if the variation value differs between the pixel central portion and the pixel peripheral portion, If it is the same at the time of signal readout, noise can be removed by CDS and shading defects of the image can be suppressed.

  Further, by shortening the CDS period, one horizontal scanning period can be shortened. In particular, when the number of AD conversion bits is large, the AD conversion period of the pixels becomes longer than the horizontal scanning period of the pixels when AD conversion operations of a large number of rows are required during one horizontal scanning period such as pixel mixing. The effect of speeding up by shortening the CDS period is increased.

  A solid-state imaging device and a driving method thereof according to an embodiment of the present invention, which will be described in detail below, and an imaging device are two-dimensionally arranged in a matrix having at least a photoelectric conversion unit, a signal charge storage unit, a reset unit, and an amplification unit A solid-state device including a plurality of pixels and an AD (analog / digital) conversion unit that is arranged for each of the plurality of pixels in a column and converts an analog signal output from the amplification unit of each pixel into a digital signal. In the imaging apparatus, a first period in which the amplifying unit provided in the plurality of pixels outputs the reset component of the pixel in analog, a second period in which the AD conversion unit provided for each column converts the pixel reset component into a digital signal, There is a third period in which the amplification means analogly outputs the signal component of the pixel, and a fourth period in which the AD conversion means converts the signal component of the pixel into a digital signal. Duplicate the period and the third period of.

  According to this configuration, since the amplifying unit can output the pixel signal component in analog during the period in which the AD conversion unit converts the pixel reset component into a digital signal, the pixel analog output and the digital conversion of the AD conversion unit can be performed. Can be performed in parallel.

  Also, a plurality of pixels arranged two-dimensionally in a matrix having at least a photoelectric conversion unit, a signal charge storage unit, a reset unit, and an amplification unit, and a plurality of pixels are arranged for each column, and amplification of each pixel AD conversion means for converting an analog signal output by the means into a digital signal, and a first period during which the amplification means provided in the plurality of pixels outputs the reset component of the pixel in analog, and AD conversion means provided for each column Includes a second period in which the reset component of the pixel is converted into a digital signal, a third period in which the amplifying unit outputs the signal component of the pixel in analog, and a fourth period in which the AD conversion unit converts the signal component of the pixel into a digital signal. And the first period overlaps the fourth period.

  According to this configuration, since the amplifying unit can analog-output the reset component of the pixel in the next row during the period in which the AD converting unit converts the signal component of the pixel into a digital signal, the pixel analog output and the AD converting unit Can be performed in parallel.

  Further, it is preferable to provide a signal holding means output by the amplifying means between the amplifying means and the AD converting means. For example, by holding the analog reset signal of the pixel in the signal holding unit, AD conversion of the reset component can be performed in parallel during the analog readout period of the signal component of the pixel. Further, by holding the analog signal of the signal component of the pixel in the signal holding unit, AD conversion of the signal component of the row can be performed in parallel during the analog readout period of the reset component of the pixel of the next row.

  The signal holding means is composed of a MOS transistor and a capacitive element, and the signal holding means connects one end of the source or drain terminal of the MOS transistor to the pixel output and connects the other end of the source or drain terminal to the capacitive element. It is preferable. According to this configuration, the analog signal is held in the capacitive element, and the pixel output unit and the signal holding unit are electrically connected and cut off using the MOS transistor, so that the analog signal reading of the pixel and AD conversion are performed in parallel. Can be done.

  Further, it is preferable that a means for controlling an analog signal holding timing is provided connected to the MOS transistor gate terminal constituting the signal holding means. According to this configuration, the gate terminal of the MOS transistor can be controlled at an arbitrary timing, and at the same timing for each driving mode even in different driving modes such as pixel mixing operation and thinning operation at the same time as full image reading. Can be controlled.

  A first step of turning on a MOS transistor constituting the signal holding means and holding an analog output of a reset component of a pixel in a signal holding capacitor; and turning off a MOS transistor constituting the signal holding means; A second step of cutting off the connection between the storage capacitor and the analog output unit of the pixel signal, and a second period in which the AD conversion means provided for each column converts the reset component of the pixel into a digital signal; Preferably, the amplifying unit overlaps with the third period in which the signal component of the pixel is analog-output.

  According to this configuration, after the pixel reset component is held in the signal holding capacitor, the signal holding capacitor and the pixel analog output are electrically cut off during a period in which the AD conversion unit converts the pixel reset component into a digital signal. Therefore, the amplifying unit can output the signal component of the pixel in analog, so that the pixel analog output and the digital conversion of the AD conversion unit can be performed in parallel.

  A third step of turning on a MOS transistor constituting the signal holding means, and holding an analog output of a signal component of a pixel in the signal holding capacitor; and turning off a MOS transistor constituting the signal holding means; And a fourth step of cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal, and a first period during which the amplifying means provided in the plurality of pixels outputs the reset component of the pixel in an analog manner, AD It is preferable that the fourth period in which the conversion means converts the signal component of the pixel into a digital signal overlaps.

  According to this configuration, after the pixel signal component is held in the signal holding capacitor, the signal holding capacitor and the pixel analog output are electrically cut off during a period in which the AD conversion unit converts the pixel signal component into a digital signal. Therefore, the amplifying unit can output the signal component of the pixel in the next row in analog, so that the pixel analog output and the digital conversion of the AD conversion unit can be performed in parallel.

  A first step of turning on a MOS transistor constituting the signal holding means, and holding an analog output of a reset component of a pixel in the signal holding capacitor; turning off a MOS transistor constituting the signal holding means; A second step of cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal, and after the second step, the fifth step in which the amplification means outputs the signal component of the pixel in an analog manner. It is preferable to have.

  According to this configuration, after holding the reset component of the pixel in the signal holding capacitor, the signal holding capacitor and the pixel analog output can be electrically cut off. The reset component held in the signal holding capacitor can be held.

  A first step of turning on a MOS transistor constituting the signal holding means, and holding an analog output of a reset component of a pixel in the signal holding capacitor; turning off a MOS transistor constituting the signal holding means; Second step of cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal, and turning on the MOS transistor constituting the signal holding means, and holding the analog output of the signal component of the pixel in the signal holding capacitor And a fourth step of turning off the MOS transistor that constitutes the signal holding means and cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal. Between the second step and the fourth step, the amplifying means has a fifth step for outputting the signal component of the pixel in an analog manner. It is preferable.

  According to this configuration, after the fourth step, the analog output unit of the pixel signal and the signal holding unit can be electrically cut off during the AD conversion period of the signal component of the pixel, and the FD generated in the pixel unit It is possible to prevent the influence of leakage from being transmitted to the signal holding means.

  A first step of turning on a MOS transistor constituting the signal holding means, and holding an analog output of a reset component of a pixel in the signal holding capacitor; turning off a MOS transistor constituting the signal holding means; A second step of cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal, and AD conversion means provided for each column after the second step converts the reset component of the pixel into a digital signal It is preferable to have a sixth step.

  According to this configuration, even if reading of the pixel signal component is started during the AD conversion period of the pixel reset signal, the pixel output unit and the signal holding unit are electrically disconnected, so that the pixel signal component Analog readout and AD conversion operation of the pixel reset component can be performed in parallel.

  A first step of turning on a MOS transistor constituting the signal holding means, and holding an analog output of a reset component of a pixel in the signal holding capacitor; turning off a MOS transistor constituting the signal holding means; Second step of cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal, and turning on the MOS transistor constituting the signal holding means, and holding the analog output of the signal component of the pixel in the signal holding capacitor And a fourth step of turning off the MOS transistor that constitutes the signal holding means and cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal. Between the step 2 and the third step, AD conversion means provided for each column converts pixel reset components into digital signals. It is preferred to have a sixth step that.

  According to this configuration, the AD conversion operation of the pixel signal component can be started immediately after the completion of the fourth step by performing the fourth step after converting the reset component of the pixel into the digital signal.

  A third step of turning on a MOS transistor constituting the signal holding means, and holding an analog output of a signal component of a pixel in the signal holding capacitor; and turning off a MOS transistor constituting the signal holding means; A fourth step of cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal, and after the fourth step, AD conversion means converts the signal component of the pixel into a digital signal. It is preferable to have a step.

  According to this configuration, after the fourth step, the analog output unit of the pixel signal and the signal holding unit can be electrically cut off during the AD conversion period of the signal component of the pixel, and the FD generated in the pixel unit It is possible to prevent the influence of leakage from being transmitted to the signal holding means.

  A first step of turning on a MOS transistor constituting the signal holding means, and holding an analog output of a reset component of a pixel in the signal holding capacitor; turning off a MOS transistor constituting the signal holding means; Second step of cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal, and turning on the MOS transistor constituting the signal holding means, and holding the analog output of the signal component of the pixel in the signal holding capacitor And a fourth step of turning off the MOS transistor that constitutes the signal holding unit and cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal. To the first step of the next row, AD conversion means converts the signal component of the pixel into a digital signal in a seventh step It is preferred to have.

  According to this configuration, since the analog output of the pixel reset component of the next row can be performed during the AD conversion period of the signal component of the pixel of the row, the analog readout of the pixel and the AD conversion operation can be performed in parallel. .

  In addition, the period from the analog output start point of the pixel reset component to the second step of cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal, and the signal holding from the analog output start point of the pixel signal component It is preferable that the period until the fourth step of disconnecting the connection between the capacitor and the analog output unit of the pixel signal is made equal.

  According to this configuration, it is possible to make the pixel reset readout state and the pixel signal readout state the same. Specifically, the voltage fluctuations of the FD portion, the vertical signal line, and the signal holding means until the output of the pixel SF is stabilized after the f characteristic of the pixel SF circuit or the pixel readout pulse is applied, at the time of resetting and at the time of signal readout Therefore, the noise removal effect in the CDS is increased. For example, even if there is a difference between the pixel central portion and the pixel peripheral portion regarding the period until the FD portion is stabilized, even if the variation value differs between the pixel central portion and the pixel peripheral portion, If it is the same at the time of signal readout, noise can be removed by CDS and shading defects of the image can be suppressed. In other words, it is preferable that the state at the time of reset reading and at the time of signal reading be as much as possible.

  The analog signal holding timing control means is preferably provided as a camera system. According to this configuration, the gate terminal of the MOS transistor can be controlled at an arbitrary timing, and at the same timing for each driving mode even in different driving modes such as pixel mixing operation and thinning operation at the same time as full image reading. Can be controlled.

  That is, the pixel analog signal readout operation and the AD conversion operation by the AD conversion means can be performed in parallel, and the CDS period for pixel readout can be shortened. By shortening the CDS period, it is possible to suppress the occurrence of the above-described 1 / f noise, and it is possible to suppress a rough component that occurs particularly in the dark.

  Further, the analog output portion of the pixel signal and the signal holding means can be electrically cut off during the AD conversion period of the signal component of the pixel, so that the leak component generated in the FD portion in the pixel is not transmitted to the signal holding means. Can be.

  Further, by making the analog readout period of the pixel reset component and the analog readout period of the pixel signal component equal, it is possible to make the pixel reset readout state and the pixel signal readout state the same, and noise removal in CDS The effect is increased. For example, even if there is a difference between the pixel central portion and the pixel peripheral portion regarding the period until the FD portion is stabilized, even if the variation value differs between the pixel central portion and the pixel peripheral portion, If it is the same at the time of signal readout, noise can be removed by CDS and shading defects of the image can be suppressed.

  Further, by shortening the CDS period, one horizontal scanning period can be shortened. In particular, when the number of AD conversion bits is large, the AD conversion period of the pixels becomes longer than the horizontal scanning period of the pixels when AD conversion operations of a large number of rows are required during one horizontal scanning period such as pixel mixing. The effect of speeding up by shortening the CDS period is increased.

  Details of the solid-state imaging device according to the embodiments (first and second embodiments) of the present invention will be described below.

(First embodiment)
Hereinafter, a solid-state imaging device and a driving method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a structural plan view showing an imaging device (camera equipment) and a solid-state imaging device according to the first embodiment of the present invention.

  As shown in FIG. 1, the imaging apparatus 100 includes a solid-state imaging apparatus 1, a pixel unit (imaging unit) 10 in which a plurality of unit pixels 3 are arranged in rows and columns, and a drive control unit 7 provided outside the pixel unit 10. A signal holding unit 41 arranged for each vertical column, a column processing unit 26 having a column AD (column analog / digital converter) circuit 25, and a reference voltage for AD conversion in the column AD circuit 25 of the column processing unit 26. A reference signal generation unit 27 configured to include a DAC (Digital Analog Converter) that supplies the output signal, and an output circuit 28.

  The drive control unit 7 also includes a horizontal scanning circuit (column scanning circuit) 12 that controls column addresses and column scanning circuits, a vertical scanning circuit (row scanning circuit) 14 that controls row addresses and row scanning circuits, and a terminal 5a. The communication / timing control unit 20 is provided which receives the master clock CLK0 via the control circuit, generates various internal clocks, and controls the horizontal scanning circuit 12, the vertical scanning circuit 14, and the like.

  Each unit pixel 3 is connected to a row control line 15 controlled by the vertical scanning circuit 14 and a vertical signal line 19 that transmits a pixel signal to the column processing unit 26.

  Further, the column AD circuit 25 includes the reference voltage RAMP generated by the reference signal generator 27 and the vertical signal lines 19 (H0, H1,...) From the unit pixel 3 for each row control line 15 (V1, V2,...). .., And the voltage comparison unit 252 that compares the analog pixel signals obtained via the output lines 40 (ADIN0, ADIN1,...) Of the signal holding unit 41 and the voltage comparison unit 252 complete the comparison process. And a data storage unit 256 configured as a memory for holding a count result using the counter unit 254, and has an n-bit AD conversion function.

  Also, one input terminal RAMP of the voltage comparison unit 252 receives the stepped reference voltage RAMP generated by the reference signal generation unit 27 in common with the input terminal RAMP of the other voltage comparison unit 252 and the other input. The output lines 40 of the corresponding vertical column signal holding units 41 are connected to the terminals, and pixel signal voltages are individually input from the pixel unit 10. The output signal of the voltage comparison unit 252 is supplied to the counter unit 254.

  Further, regarding the circuit configuration of the ADC (analog / digital converter), the reference voltage RAMP is supplied to the comparator (voltage comparator), and at the same time, counting with the clock signal is started, and the signal holding unit 41 is connected via the output line 40. The analog pixel signal inputted in this way is compared with the reference voltage RAMP to count until a pulse signal is obtained, thereby performing AD conversion.

  At this time, the signal level (noise level) immediately after the pixel reset and the true (according to the amount of received light) with respect to the voltage mode pixel signal input through the output line 40 of the signal holding unit 41 together with AD conversion. A) Processing for obtaining a difference from the signal level Vsig is performed. As a result, the solid-state imaging device according to the first embodiment of the present invention can remove noise signal components called fixed pattern noise (FPN) and reset noise.

  In FIG. 1, only the true signal level Vsig is extracted by down-counting the noise level and up-counting the signal level. The pixel data digitized by the column AD circuit 25 is the horizontal scanning circuit. The signal is transmitted to the horizontal signal line 18 via a horizontal selection switch (not shown) driven by a horizontal selection signal from 12 and further input to the output circuit 28.

  With this configuration, in the solid-state imaging device according to the first embodiment of the present invention, pixel signals are sequentially transmitted for each vertical column from the pixel unit 10 in which the light receiving elements as charge generation units are arranged in a matrix. Is output. Then, one image, that is, a frame image for the pixel unit 10 in which the light receiving elements are arranged on the matrix is shown as a set of pixel signals of the entire pixel unit 10.

  As described above, the solid-state imaging device according to the first embodiment of the present invention is different from the conventional example in FIG. 7 in that the signal holding capacitor 262 and the signal between the vertical signal line 19 and the voltage comparator 252 are different. The point is that a signal holding unit 41 including a holding switch 263 is provided.

  Next, FIG. 2 is a timing chart for explaining the driving method of the solid-state imaging device according to the first embodiment of the present invention. The detailed operation of the column AD circuit will be described with reference to FIG.

  First, for the first reading, the communication / timing control unit 20 first resets the count value of the counter unit 254 to the initial value “0” and sets the counter unit 254 to the down-count mode. Then, after the first reading from the unit pixel 3 in any row Hx to the vertical signal lines 19 (H1, H2,...) Is stabilized, the control signal CN11 of the signal holding switch 263 is applied at the timing t4. Then, the signal holding switch 263 is turned ON, and a pixel reset signal is input to the signal holding capacitor 262.

  In addition, after the signal input to the signal holding capacitor is stabilized, the application of the control signal CN11 of the signal holding switch 263 is canceled at the timing of t6, the signal holding switch 263 is turned OFF, and the pixel holding signal is reset to the signal holding capacitor 262. Hold.

  Further, the communication / timing control unit 20 supplies the control data 4 for generating the reference voltage RAMP to the reference signal generating unit 27. In response to this, the reference signal generation unit 27 forms a stepped waveform (RAMP waveform) that is time-varying in a sawtooth shape (RAMP shape) as a whole as a comparison voltage to one input terminal RAMP of the voltage comparison unit 252. input. The voltage comparison unit 252 compares the comparison voltage of the RAMP waveform with the signal voltage of the pixel reset component of the arbitrary ADC input line 40 (ADINx) held in the signal holding capacitor 262 of the signal holding unit 41.

  In addition, at the same time as the reference voltage RAMP input of the reference voltage RAMP waveform to the input terminal RAMP of the voltage comparison unit 252, the reference signal is used to measure the comparison time in the voltage comparison unit 252 with the counter unit 254 arranged for each row. In synchronization with the ramp waveform voltage generated from the generation unit 27 (t10), the count clock CK0 is input from the communication / timing control unit 20 to the clock terminal of the counter unit 254, and the initial value “0” is used as the first count operation. Start counting down.

  Further, the voltage comparator 252 compares the ramp-shaped reference voltage RAMP from the reference signal generator 27 with the signal holding voltage Vx of the pixel reset component input via the ADC input line 40, and both voltages are the same. The comparator output is inverted from the H level to the L level (t12). That is, the voltage signal corresponding to the reset component Vrst and the reference voltage RAMP are compared, and the magnitude in the time axis direction corresponding to the magnitude of the reset component Vrst is counted (counted) by the count clock CK0, whereby the reset component Vrst A count value corresponding to the size of is obtained. In other words, the counter unit 254 uses the start point of the change of the RAMP waveform as the down-count start point of the counter unit 254, and counts down until the output of the voltage comparator 252 is inverted, thereby corresponding to the magnitude of the reset component Vrst. Get the count value.

  In addition, when a predetermined down-count period has elapsed (t14), the communication / timing control unit 20 stops the supply of control data to the voltage comparison unit 252 and the supply of the count clock CK0 to the count unit 254. As a result, the voltage comparison unit 252 stops generating the ramp-shaped reference voltage RAMP.

  At the time of the first reading, since the reset level Vrst in the pixel signal voltage Vx is detected by the voltage comparison unit 252 and the count operation is performed, the reset component ΔV of the unit pixel 3 is read out.

  Therefore, in the prior art, the second read operation is started after the above-described reset level AD conversion is completed. However, in the solid-state imaging device and the driving method thereof according to the first embodiment of the present invention, the pixel signal The component analog readout operation and the AD conversion operation of the pixel reset component are performed in parallel to shorten the CDS period.

  Further, as shown in FIG. 2, down-counting is started at the timing t10, and AD conversion operation of the reset signal component ΔV is performed, and at the same time, a pixel readout pulse φTR that reads the signal component accumulated in the pixel is applied, The pixel signal component Vsig is output to the vertical signal line 19.

  At this time, the application of the control signal CN11 to the signal holding switch 263 is released, the signal holding switch 263 is in the OFF state, and the vertical signal line 19 from which the pixel signal component is read and the pixel reset component are held. The signal holding capacitor 262 is electrically cut off.

  Therefore, the solid-state imaging device and the driving method thereof according to the first embodiment of the present invention can hold the reset component of the pixel in the signal holding capacitor 262 even if the signal component of the pixel is read out to the vertical signal line 19. . Further, the pixel signal readout operation can be performed in parallel with the AD conversion operation of the pixel reset component.

  Further, when the pixel signal component readout operation and the pixel reset component AD conversion are completed, the second pixel signal readout operation is started. At the time of the second reading, in addition to the reset component ΔV, an operation of reading the signal component Vsig corresponding to the incident light amount for each unit pixel 3 is performed. The difference from the first reading is that the counter unit 254 is set to the up-count mode.

  For the second read operation, the count value of the counter unit 254 is first reset to the initial value “0” at the timing t14. Subsequently, after the second reading from the unit pixel 3 in any row Hx to the vertical signal line 19 (H1, H2,...) Is stabilized, the control signal CN11 of the signal holding switch 263 is sent at the timing t16. Then, the signal holding switch 263 is turned ON, and the pixel signal component Vsig is input to the signal holding capacitor 262. After the signal input to the signal holding capacitor is stabilized, at time t18, application of the control signal CN11 of the signal holding switch 263 is canceled, the signal holding switch 263 is turned OFF, and the signal component Vsig of the pixel is supplied to the signal holding capacitor 262. Hold.

  In addition, after the signal reading to the signal holding capacitor 262 is stabilized, the reference voltage RAMP that is time-changed stepwise so as to be substantially ramp-shaped is input by the reference signal generation unit 27, and is input via an arbitrary ADC input line 40. The voltage comparison unit 252 compares the pixel signal component inputted in this way with the signal holding voltage Vx.

  At this time, at the same time when the reference voltage RAMP is input to one input terminal RAMP of the voltage comparator 252, the reference signal generator 27 emits the comparison time in the voltage comparator 252 using the counter unit 254. In synchronization with the ramp waveform voltage (t20), the counter unit 254 starts up-counting from the initial value “0” as the second count operation.

  The comparison unit 252 compares the ramp-shaped reference voltage RAMP from the reference signal generation unit 27 with the signal holding voltage Vx of the pixel signal component input via the arbitrary ADC input line 40, and both voltages are When they become the same, the comparator output is inverted from the H level to the L level (t22).

  That is, the voltage signal corresponding to the signal component Vsig and the reference voltage RAMP are compared, and the magnitude in the time axis direction corresponding to the magnitude of the signal component Vsig is counted (counted) by the count clock CK0, whereby the signal component Vsig. A count value corresponding to the size of can be obtained. In other words, the counter unit 254 corresponds to the magnitude of the signal component Vsig by counting up until the output of the voltage comparator 252 is inverted with the start point of the RAMP waveform change as the up-counting start point of the counter unit 254. Get the count value.

  In the driving method of the solid-state imaging device according to the first embodiment of the present invention, the count operation in the counter unit 254 is down-counting at the first reading and up-counting at the second reading.

  Thereby, in the driving method of the solid-state imaging device according to the first embodiment of the present invention, subtraction is automatically performed in the counter unit 254, and only the Vsig signal component is extracted as the count value with respect to the counter value 0. I can do it.

  Furthermore, in the solid-state imaging device and the driving method thereof according to the first embodiment of the present invention, the column AD circuit 25 is not only used as a digital changing unit that converts an analog pixel signal into digital pixel signal data, but also as a CDS (Correlated). It can also be operated as a double sampling processing function unit.

  Further, the AD converted data is transferred and held in the data storage unit 256, so that before the operation of the counter unit 254 (t30), based on the memory transfer instruction pulse CN8 from the communication / timing control unit 20, the Hx of the previous row The count result of −1 is transferred to the data storage unit 256.

  Thereby, in the solid-state imaging device and the driving method thereof according to the first embodiment of the present invention, the signal output operation from the data storage unit 256 to the outside through the horizontal signal line 18 and the output circuit 28, the reading of the current Hx, The counting operation of the counter unit 254 can be performed in parallel.

  That is, the solid-state imaging device and the driving method thereof according to the first embodiment of the present invention are different from the second signal reading of the conventional example in the signal holding switch 263 during the AD conversion period of the second signal component. Is turned off to electrically cut off the vertical signal line 19 that outputs a pixel signal and the signal holding capacitor 262 that performs AD conversion.

  By doing so, the solid-state imaging device and the driving method thereof according to the first embodiment of the present invention prevent leakage components generated in the in-pixel FD unit from being transmitted to the signal holding capacitor 262 serving as an AD conversion input unit. can do.

  As described above, in the solid-state imaging device and the driving method thereof according to the first embodiment of the present invention, the pixel analog signal readout operation and the AD conversion operation by the AD conversion means can be performed in parallel. The CDS period can be shortened.

  Furthermore, by shortening the CDS period, it is possible to suppress the occurrence of the above-described 1 / f noise, and particularly, it is possible to suppress rough components that occur in the dark.

  Further, the analog output part of the pixel signal and the signal holding part 41 can be electrically cut off during the AD conversion period of the signal component of the pixel, and the leak component generated in the in-pixel FD part is not transmitted to the signal holding part 41. Can be.

  As a result, it is possible to suppress image defects such as dark roughness and scratches caused by FD leakage.

  Further, by shortening the CDS period, one horizontal scanning period can be shortened. In particular, when the number of AD conversion bits is large, the AD conversion period of the pixels becomes longer than the horizontal scanning period of the pixels when AD conversion operations of a large number of rows are required during one horizontal scanning period such as pixel mixing. The effect of speeding up by shortening the CDS period is increased.

  In the solid-state imaging device and the driving method thereof according to the first embodiment of the present invention, the connection between the signal holding capacitor and the analog output unit of the pixel signal is cut off from the analog output start point of the pixel reset component. And a period (t10 to t18) from the analog signal output start point of the pixel signal component to a fourth step of cutting off the connection between the signal holding capacitor and the analog output unit of the pixel signal. ) And are more preferably equal.

  According to this configuration, the pixel reset readout state and the pixel signal readout state can be made the same. Specifically, the voltage fluctuations of the FD unit, the vertical signal line, and the signal holding unit 41 until the output of the pixel SF becomes stable after the pixel SF circuit's f characteristics and the pixel readout pulse are applied, and the signal readout. The time can be made equal, and the noise removal effect in the CDS is increased.

  For example, even if there is a difference between the pixel central portion and the pixel peripheral portion regarding the period until the FD portion is stabilized, even if the variation value differs between the pixel central portion and the pixel peripheral portion, If it is the same at the time of signal readout, noise can be removed by CDS and shading defects of the image can be suppressed.

  The above is the reason why it is preferable to make the states at the time of reset reading and signal reading as much as possible.

(Second Embodiment)
Hereinafter, a solid-state imaging device and a driving method thereof according to a second embodiment of the present invention will be described with reference to the drawings.

  First, the device configuration of the imaging device and solid-state imaging device according to the second embodiment of the present invention is the same as that of the imaging device and solid-state imaging device according to the first embodiment of the present invention shown in FIG.

  Next, FIG. 3 is a timing chart for explaining a driving method of the solid-state imaging device according to the second embodiment of the present invention.

  3 is different from the driving method of the solid-state imaging device according to the second embodiment of the present invention shown in FIG. 3 and the driving method of the solid-state imaging device according to the first embodiment of the present invention shown in FIG. Is that the application position of the pixel reset signal φRS of the (x + 1) th row is applied during the AD conversion period of the signal component of the xth row.

  That is, in the driving method of the solid-state imaging device according to the second embodiment of the present invention, the pixel signal component in the x-th row is held in the signal holding capacitor 262 at the timing t18, and the vertical signal line 19 serving as the pixel output and the signal The storage capacitor 262 is electrically disconnected.

  Therefore, in the driving method of the solid-state imaging device according to the second embodiment of the present invention, the reset operation of the (x + 1) th row is performed during the AD conversion period of the pixel signal output, and the reset component of the (x + 1) th row is applied to the vertical signal line 19. Can be held in the signal holding capacitor 262 even when the signal component is read out.

  Further, from FIGS. 2 and 3, the driving method of the solid-state imaging device according to the second embodiment of the present invention is the analog readout of the reset component of the pixel in the x + 1th row and the AD conversion of the signal component of the pixel in the xth row. Can be performed in parallel, so that the AD conversion period can be shortened.

(Comparison between the solid-state imaging device of the first and second embodiments and the reference technology)
Hereinafter, in order to facilitate understanding of the present invention, a solid-state imaging device and a driving method thereof according to embodiments (first and second embodiments) of the present invention will be described with reference to reference techniques shown in FIGS. And compare.

  FIG. 10 is a solid-state imaging device showing a reference technique in which a column parallel output type analog circuit without a column ADC is mounted.

  FIG. 10 is different from FIG. 7 in that there is no voltage comparator 252 and counter 254 for AD conversion. Instead, there is a noise cancellation circuit and a signal holding unit 41, which are described as an analog CDS circuit 44.

Further, as shown in FIG. 11, the analog CDS circuit 44 has various circuit methods.
FIG. 12 is a configuration diagram of a pixel of the solid-state imaging device showing the reference technique.

  In FIG. 12, φRS is a pixel reset pulse. By resetting the pixel FD section to “HI”, the pixel SF composed of a current source common to the T12 amplification transistor and each column is activated, and the pixel is You can choose.

  ΦTR is a pulse for reading the signal charge accumulated in the photodiode in the pixel to the FD portion. Although the timing for the pixel non-selection operation is omitted, the power supply signal line φVDD is set to “LOW” and φRS is applied again to set the voltage of the FD portion to “LOW”. By setting the pixel SF to an inactive state, the pixel can be set to a non-selected state.

  FIG. 13A is a solid-state imaging device showing a reference technique, and is a timing chart showing a column parallel output type pixel readout timing constituted by an analog circuit.

  From FIG. 13A, φRSa is applied and the reset component of the pixel is read out. Further, after the reset component readout is stabilized, φTRa is applied to read out the signal component including the reset component of the pixel. The reset noise component is removed by the CDS circuit configured by the capacitive elements 281 and 284 shown in FIG. 11, and only the signal component is held in the capacitive element 284.

  On the other hand, FIG. 13B is a timing chart showing the pixel readout timing constituted by the AD circuit in the solid-state imaging device shown in FIG.

  As shown in FIG. 13B, since the column ADC operation is performed after φRSb is applied, the timing at which φTRb is applied is delayed with respect to the pixel readout timing constituted by the analog circuit of φTRa.

  From the above description, in the solid-state imaging device according to the reference technology, especially when the number of AD conversion bits increases, or when a necessary AD conversion period becomes longer within one horizontal scanning period due to a driving operation such as pixel mixing, 1 The horizontal scanning period becomes long and high-speed reading becomes difficult.

  However, in the solid-state imaging device and the driving method thereof according to the embodiments (first and second embodiments) of the present invention, the signal holding unit 41 for the reset component of the pixel is provided in the AD circuit input unit. High-speed readout can be realized by performing analog readout operation of the signal component and AD conversion operation of the reset component of the pixel in parallel.

  Furthermore, in the solid-state imaging device shown in FIG. 7, the timing constituted by the AD circuit cannot perform the reset operation for the next row until the AD operation of the signal component is completed. It becomes long and high-speed reading becomes difficult.

  However, in the solid-state imaging device and the driving method thereof according to the embodiments (first and second embodiments) of the present invention, the signal holding unit 41 of the signal component of the pixel is provided in the AD circuit input unit, and the reset component of the pixel By performing the analog readout operation and the AD conversion operation of the pixel signal component in parallel, high-speed readout can be realized.

  Furthermore, an increase in 1 / f noise and an increase in FD leakage in the solid-state imaging device shown in FIG. 7 will be described in detail with reference to FIG.

In the reference technology, 1 / f noise is a trap or discharge of channel charge due to the influence of an unbonded bond near the channel (Si / SiO 2 interface) through which electrons flow. For example, when electrons are captured, a Coulomb repulsive force acts between the captured electrons and electrons traveling through the channel, and the drain current is reduced. On the other hand, when the channel is released, the drain current increases in reverse. Thus, since the drain current changes discretely, this becomes noise of the drain current. 1 / f noise is expressed as noise power vn ² , frequency f, transistor width W, transistor length L, insulating oxide film dox, dielectric constant e, trap density nt, charge q,
vn ² / f = (q ² · dox ² · nt) / (e ² · W · L · f)
It becomes a function of 1 / f. That is, the influence of noise on the low frequency side becomes particularly large. As can be seen from the equation, when the CDS period becomes longer and the operation becomes low frequency, the probability that electrons are captured and emitted increases and 1 / f noise deteriorates. Further, since 1 / f noise is inversely proportional to the W · L of the transistor, the influence is particularly remarkable in a fine transistor used in a pixel.

  Next, the FD leak will be described. FIG. 14 is a timing chart when an FD leak occurs in the pixel FD portion. Assuming that the leakage component of the FD part is ΔVleak, the leakage component of the FD part that occurs at the time of reset reading is ΔVleak_r, and the leakage component of the FD part that occurs at the time of signal reading is ΔVleak_s, the reset reading period does not depend on the amount of light. Whereas the amount of light in ΔVleak_s increases as the amount of light increases, ΔVleak_s becomes longer than ΔVleak_r.

  That is, even if the difference between the leak component at the time of reset reading and signal reading is taken, it means that the ΔV leak component remains. Further, when a circuit for calculating the difference between the leak components is not newly provided, the FD leak component at the time of signal reading is ΔVleak_r + ΔVleak_s. Therefore, in the CDS configuration of the reference technique, ΔVleak_s appears as it is in the image as noise caused by the FD leak.

  Since ΔVleak takes a unique value for each pixel, an image defect that increases roughness and scratches at a fixed position occurs. In addition to the fixed roughness and scratches, the voltage of the FD section decreases due to leakage, so there is a problem that the dynamic range of the pixel SF circuit decreases, and the problem that the linearity with respect to the incident light amount deteriorates due to the difference in the leak component depending on the light amount. appear.

  However, in the solid-state imaging device and the driving method thereof according to the embodiments (first and second embodiments) of the present invention, the signal holding unit 41 of the pixel signal component is provided in the AD circuit input unit, and the signal component of the pixel is By electrically shutting off the analog signal output unit of the pixel and the signal holding unit 41 of the AD circuit input unit during the AD conversion operation, image defects that increase the roughness and scratches at the fixed position can be prevented. Not only the scratch but also the voltage of the FD section decreases due to leakage, so that it is possible to prevent the problem that the dynamic range of the pixel SF circuit decreases, and to solve the problem that the linearity with respect to the incident light amount deteriorates due to the difference in the leak component depending on the light amount. I can do it.

  In addition, as the circuit configuration diagram of the first embodiment and the second embodiment, the signal holding unit 41 is illustrated as a switch. However, as illustrated in FIG. 4, the signal holding unit 41 may be configured as a pair transistor of Nch and Pch. By configuring with Nch and Pch pair transistors, the output voltage of the vertical signal lines 19 (H0, H1,... Can be passed from the ground level to the power supply level without voltage drop.

  FIG. 4 shows a pair transistor of Nch and Pch. For example, when the output level of the vertical signal line 19 cannot swing from the ground level to the power supply level, even if only Nch is configured according to the output level, A configuration with only Pch may be used.

  In the first and second embodiments, the vertical signal line and the signal holding unit 41 are directly connected, but a column amplifier is provided between the vertical signal line and the signal holding unit 41 as shown in FIG. Also good. By providing the column amplifier, the voltage output of the pixel SF can be amplified, and the S / N can be improved and the gain can be switched.

  An example of the configuration of the column amplifier is shown in FIG. FIG. 6 shows a configuration in which the gain of the amplifier is determined by the ratio of the capacitive elements 276 and 277 in a common source amplifier.

  Note that FIG. 6 is an example of a circuit, and an analog amplifier that amplifies the voltage signal of the pixel SF can similarly obtain the effects of the present invention, and is not limited to this configuration.

  An example of the configuration of the voltage comparison unit 252 is shown in FIG. Although FIG. 8 shows a differential input type amplifier configuration, the effect of the present invention can be similarly obtained if the pixel signal section shown in FIG. 8 holds a voltage and AD converts the signal voltage. Therefore, it is not bound by this configuration.

  Further, in the solid-state imaging device according to each embodiment of the present invention, a counter is provided in the column unit as an AD conversion configuration. However, the effects of the present invention can be achieved regardless of the configuration in which a reset component and a signal component are read and AD converted. Can be obtained in the same manner, and is not limited to this configuration.

  For example, even in an AD conversion configuration including a latch circuit unit in a column and a counter unit common to all columns, which is described as the prior art (FIG. 9), a configuration in which a reset component and a signal component are read in time series, respectively. Therefore, by providing a signal holding unit between the vertical signal line and the voltage comparison unit, it is possible to obtain the same effect as the present invention.

  Further, in the solid-state imaging device of each embodiment of the present invention, the timing control is performed by the communication / timing control unit 20 shown in FIG. 1, but the DATA input shown in FIG. 1 is controlled as a system outside the solid-state imaging device. May be.

  Specifically, in FIG. 1, 45 external systems are described for the solid-state imaging device 1 surrounded by a dotted line in the imaging device 100, but the communication / timing control unit 20 in the solid-state imaging device surrounded by a dotted line is illustrated. This means that it may be taken out of the solid-state imaging device 1.

  This makes it possible to control the system as a system outside the solid-state imaging device, and to arbitrarily set the drive timing for any drive mode with different frame rates, such as full image readout mode, pixel mixing mode, and thinning mode. It becomes.

  The solid-state imaging device in each of the above embodiments is mounted on a digital camera or the like. This digital camera includes an optical system including a lens for imaging incident light from a subject on an imaging surface of a solid-state image sensor, a control unit that controls driving of the solid-state image sensor, and an output signal of the solid-state image sensor. And an image processing unit for performing various signal processing.

  As described above, the solid-state imaging device and the driving method thereof according to the present invention are useful for imaging devices such as digital cameras, video cameras, and camera-equipped mobile phones.

It is a specific example of a circuit block diagram which shows the solid-state imaging device which concerns on 1st Embodiment. It is a specific example of a timing chart of the solid-state imaging device according to the first embodiment. It is a specific example of a timing chart of the solid-state imaging device according to the second embodiment. It is a specific example of the circuit block diagram of the signal holding | maintenance part concerning 1st and 2nd embodiment. It is a specific example of a circuit configuration diagram showing an imaging device equipped with a column amplifier according to the first and second embodiments. It is a specific example of a circuit configuration diagram of a column amplifier. It is a specific example of a circuit block diagram which shows the conventional solid-state imaging device. It is a specific example of the circuit block diagram which shows the conventional solid-state imaging device and the voltage comparison part concerning embodiment of this invention. It is a specific example of the timing chart figure of the conventional solid-state imaging device. It is a specific example of the circuit block diagram which shows the solid-state imaging device which does not provide the column AD conversion means of reference technology. It is a specific example of the analog CDS circuit block diagram of the solid-state imaging device which does not provide the column AD conversion means of reference technology. It is the specific example of the solid-state imaging device of reference technology, and the pixel circuit block diagram concerning embodiment of this invention. (A) A specific example of a timing chart showing the FD leak problem of the solid-state imaging device of the reference technology, and (b) a specific example of a timing chart showing the FD leak problem of the solid-state imaging device of FIG. 4 shows a timing chart when an FD leak occurs in a pixel FD portion.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 3 Unit pixel 10 Pixel part 12 Horizontal scanning circuit 14 Vertical scanning circuit 18 Horizontal signal line 19 Vertical signal line 20 Communication / timing control part 25 Column AD circuit 26 Column processing part 27 Reference signal generation part 27a DA conversion part 28 Output circuit 41 Signal holding unit 42 Column amplifier 44 Analog CDS circuit 254 Counter unit 262 Signal holding capacitor 263 Signal holding switch

Claims (15)

A pixel portion in which a plurality of unit pixels are arranged in rows and columns ;
A signal holding unit that is provided for each column of the pixel unit and holds an analog signal output from a unit pixel in a corresponding column among the plurality of unit pixels ;
AD conversion means that is provided for each column of the pixel portion and converts an analog signal held in the signal holding means into a digital signal ;
Drive control means for driving the pixel portion, the signal holding means and the AD conversion means,
Each of the plurality of unit pixels is
Photoelectric conversion means for converting light into signal charge;
Charge holding means for holding signal charges transferred from the photoelectric conversion means;
Amplifying means for amplifying the signal charge of the charge holding means;
Resetting means for resetting the signal charge of the charge holding means,
The drive control means drives each operation in the first to fourth periods,
In the first period, an analog signal of a reset component output from the amplifying unit is read from the pixel unit in a state where the charge holding unit is reset by the reset unit,
In the second period, the analog signal of the reset component held in the signal holding unit is converted into a digital signal,
In the third period, in the state where the charge holding unit holds the signal charge transferred from the photoelectric conversion unit, the analog signal of the signal component output from the amplification unit is read from the pixel unit,
In the fourth period, the analog signal of the signal component held in the signal holding unit is converted into a digital signal,
The drive control unit is configured so that the second period for the unit pixels belonging to the first row of the plurality of unit pixels overlaps the third period for the unit pixels belonging to the first row. A solid-state imaging device that is driven . The signal holding means is
A switch element connected to a column signal line for transmitting an analog signal output from a unit pixel in a corresponding column among the plurality of unit pixels ;
The solid-state imaging device according to claim 1, further comprising: a capacitive element that is connected to the column signal line via the switch element and holds the analog signal. The drive control means includes
Maintaining the switch element in an OFF state during the conversion operation by the AD conversion means;
A conversion operation by the AD converting means, you drive in parallel and an operation of reading the analog signal to the column signal line from the pixel unit
The solid-state imaging device according to claim 2, wherein the this. The signal holding means is
A switch element connected to a column signal line for transmitting an analog signal output from a unit pixel in a corresponding column among the plurality of unit pixels ;
A capacitor element connected to the column signal line via the switch element and holding the analog signal;
Said drive control means, the analog signal of the reset component outputted by said first period by turning on the switching element is held in the capacitor element, the switching element in the conversion during the second period The solid-state imaging device according to claim 1 , wherein the solid-state imaging device is turned off. The drive control means includes
The said first period for the unit pixels belonging to a row other than the first row of the fourth period and the plurality of unit pixels for a unit pixel belonging to the first row is driven so as to overlap The solid-state imaging device according to claim 1 . The signal holding means is
A switch element connected to a column signal line for transmitting an analog signal output from a unit pixel in a corresponding column among the plurality of unit pixels ;
A capacitor element connected to the column signal line via the switch element and holding the analog signal;
The drive control means includes
Said analog signal of the signal component outputted by said third period by turning on the switch element is held in the capacitor element, for maintaining the switching element in the conversion during the fourth period of the OFF state The solid-state imaging device according to claim 5 . The signal holding means is
A switch element connected to a column signal line for transmitting an analog signal output from a unit pixel in a corresponding column among the plurality of unit pixels ;
A capacitor element connected to the column signal line via the switch element and holding the analog signal;
The drive control means includes
The analog signal of the reset component outputted by said first period by turning on the switch element is held in the capacitor element, the switching element in the conversion during the second period to the OFF state,
Said analog signal of the signal component outputted by said third period by turning on the switch element is held in the capacitor element, for maintaining the switching element in the conversion during the fourth period of the OFF state The solid-state imaging device according to claim 5 . The solid-state imaging device may further provided for each column of the pixel portion, corresponding to amplify the analog signal outputted from the unit pixel in a column, before Symbol capacity through the switching element of the plurality of unit pixels The solid-state imaging device according to claim 2, further comprising a column amplifier connected to the element. The drive control means includes
Maintaining the switch element in an OFF state during the conversion operation by the AD conversion means;
A conversion operation by the AD converting means, you drive in parallel and an operation of reading the analog signal to the column signal line from the pixel unit
The solid-state imaging device according to claim 8, wherein the this. Camera comprising the solid-state imaging device according to any one of claims 1-9. A pixel portion in which a plurality of unit pixels are arranged in rows and columns;
A signal holding unit that is provided for each column of the pixel unit and holds an analog signal output from a unit pixel in a corresponding column among the plurality of unit pixels;
AD conversion means that is provided for each column of the pixel portion and converts an analog signal held in the signal holding means into a digital signal;
Drive control means for driving the pixel portion, the signal holding means and the AD conversion means,
Each of the plurality of unit pixels is
Photoelectric conversion means for converting light into signal charge;
Charge holding means for holding signal charges transferred from the photoelectric conversion means;
Amplifying means for amplifying the signal charge of the charge holding means;
A solid-state imaging device driving method comprising: reset means for resetting signal charges of the charge holding means,
A first step of reading out an analog signal of a reset component output from the amplification unit from the pixel unit in a state where the charge holding unit is reset by the reset unit;
A second step of converting the analog signal of the reset component held in the signal holding means into a digital signal;
A third step of reading out an analog signal of a signal component output from the amplification unit from the pixel unit in a state where the charge holding unit holds the signal charge transferred from the photoelectric conversion unit;
A fourth step of converting the analog signal of the signal component held in the signal holding means into a digital signal,
The second step for the unit pixels belonging to the first row among the plurality of unit pixels and the third step for the unit pixels belonging to the first row are performed in parallel.
A method for driving a solid-state imaging device. The signal holding means is
A switch element connected to a column signal line for transmitting an analog signal output from a unit pixel in a corresponding column among the plurality of unit pixels;
A capacitor element connected to the column signal line via the switch element and holding the analog signal;
By turning on the switch element, the analog signal of the reset component output in the first step is held in the capacitor element, and the switch element is turned off during the conversion in the second step.
The method for driving a solid-state imaging device according to claim 11. The fourth step for the unit pixels belonging to the first row and the first step for the unit pixels belonging to rows other than the first row among the plurality of unit pixels are performed in parallel.
The method for driving a solid-state imaging device according to claim 11. The signal holding means is
A switch element connected to a column signal line for transmitting an analog signal output from a unit pixel in a corresponding column among the plurality of unit pixels;
A capacitor element connected to the column signal line via the switch element and holding the analog signal;
By turning on the switch element, the capacitor element holds the analog signal of the signal component output in the third step, and maintains the switch element in the off state during the conversion in the fourth step.
The method for driving a solid-state imaging device according to claim 13. The signal holding means is
A switch element connected to a column signal line for transmitting an analog signal output from a unit pixel in a corresponding column among the plurality of unit pixels;
A capacitor element connected to the column signal line via the switch element and holding the analog signal;
By turning on the switch element, the capacitor element holds the reset component analog signal output in the first step, and the switch element is turned off during the conversion in the second step,
By turning on the switch element, the capacitor element holds the analog signal of the signal component output in the third step, and maintains the switch element in the off state during the conversion in the fourth step.
The method for driving a solid-state imaging device according to claim 13.

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