JP2013197697A - Solid-state image pickup device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device which can be driven with lower electric power.SOLUTION: A solid-state image pickup device 1 has a pixel part 10 and an intermediate voltage generation circuit 16. The pixel part 10 has a photo-gate, an electric charge voltage conversion part, and a plurality of pixels 20 including a transfer transistor for transferring a signal electric charge accumulated in the photo-gate to the electric charge voltage conversion part. The intermediate voltage generation circuit 16 generates intermediate voltage to be applied to the gate of the transfer transistor, in an intermediate transfer operation at the time of reading the signal electric charge accumulated in the photo-gate by a predetermined number of the intermediate transfer operation and a full transfer operation. Furthermore, the intermediate voltage generation circuit 16 applies the intermediate voltage on a gate electrode of the photo-gate as drive voltage of the photo-gate.

Description

  The present disclosure relates to a solid-state imaging device and an electronic apparatus including the same.

  Conventionally, as a solid-state imaging device, a CMOS (Complementary MOS) image sensor that reads out signal charges accumulated in a photodiode, which is a photoelectric conversion element, through a MOS (Metal-Oxide-Semiconductor) transistor has been used in various applications. Yes. For such a CMOS image sensor, various signal charge readout methods have been proposed (see, for example, Patent Documents 1 and 2).

  Patent Document 1 proposes a method of reading a signal charge divided into a plurality of times when the signal charge is transferred from the photodiode to the floating diffusion portion by a transfer transistor. Note that in the reading method proposed in Patent Document 1, a voltage signal corresponding to the signal charge accumulated in the photodiode is generated by combining a plurality of signals read out divided into a plurality of times.

  In Patent Document 2, when a pixel signal is read, a digital CDS (Correlated Double Sampling) process is performed in parallel with a comparison process between a reference signal and a processing target signal performed by an AD (Analog to Digital) conversion unit. A method for removing noise has been proposed.

JP 2010-226679 A JP 2006-033453 A

  Conventionally, CMOS solid-state imaging devices having various configurations have been proposed. In these solid-state imaging devices, an analog power source for driving pixels and a digital power source for a logic unit that performs signal processing are usually used. These two power supplies are used. Of these two power supply voltages, the voltage of the digital power supply can be reduced with the miniaturization of the CMOS process, but the voltage of the analog power supply is currently difficult to reduce. That is, at present, it is difficult to drive the solid-state imaging device with lower power (low power consumption).

  The present disclosure has been made in view of the above situation, and an object of the present disclosure is to provide a solid-state imaging device that can be driven with lower power and an electronic apparatus including the solid-state imaging device.

  In order to solve the above problems, a solid-state imaging device of the present disclosure includes a pixel unit and an intermediate voltage generation circuit, and the configuration of each unit is as follows. The pixel portion includes a plurality of pixels including a photogate, a charge-voltage converter, and a transfer transistor that transfers signal charges accumulated in the photogate to the charge-voltage converter. The intermediate voltage generation circuit generates an intermediate voltage to be applied to the gate of the transfer transistor in the intermediate transfer operation when the signal charge accumulated in the photogate is read by a predetermined number of intermediate transfer operations and complete transfer operations. Furthermore, the intermediate voltage generation circuit applies the intermediate voltage to the gate electrode of the photogate as a drive voltage for the photogate.

  In addition, an electronic apparatus according to the present disclosure includes the solid-state imaging device according to the present disclosure and a signal processing circuit that performs predetermined processing on an output signal of the solid-state imaging device.

  In this specification, the “complete transfer operation” means that the signal charge accumulated in the photogate is divided into a plurality of times by the transfer transistor and transferred (read) to the charge-voltage conversion unit. This refers to the transfer operation (read operation) to be performed. In this specification, “intermediate transfer operation” refers to a series of operations in which a signal charge accumulated in a photogate is divided into a plurality of times by a transfer transistor and transferred to a charge-voltage converter before a complete transfer operation. This refers to the transfer operation performed. Furthermore, in this specification, the “intermediate voltage” is a voltage that is larger than a low level voltage applied to the gate of the transfer transistor and smaller than a high level voltage applied to the gate of the transfer transistor during the complete transfer operation. I mean.

  In the solid-state imaging device of the present disclosure, a photogate is used as a photoelectric conversion element in a pixel, and signal charges accumulated in the photogate are divided and read out multiple times. Furthermore, the solid-state imaging device of the present disclosure includes an intermediate voltage generation circuit that generates an intermediate voltage applied to the gate of the transfer transistor during the intermediate transfer operation, and drives the photogate with the intermediate voltage generated by the intermediate voltage generation circuit. To do. In the present disclosure, by adopting such a configuration, the solid-state imaging device can be driven by a single drive power supply.

  As described above, according to the present disclosure, since the solid-state imaging device can be driven by a single drive power supply, the solid-state imaging device can be driven with lower power.

It is a figure for demonstrating the difference with the solid-state imaging device of this indication, and the conventional one. 1 is a schematic block configuration diagram of a solid-state imaging device according to a first embodiment of the present disclosure. FIG. 3 is a schematic configuration diagram of each pixel of a solid-state imaging device according to a first embodiment of the present disclosure and a unit circuit in a column processing unit provided corresponding to each pixel. It is a timing chart of various signals for explaining operation of a unit circuit in a column processing part. 6 is a flowchart illustrating a procedure of a read operation of the solid-state imaging device according to the first embodiment. 6 is a timing chart of various signals for explaining a reading operation of the solid-state imaging device according to the first embodiment. It is a figure for demonstrating the intermediate transfer operation | movement of the solid-state imaging device which concerns on 1st Embodiment. It is a figure for demonstrating the complete transfer operation | movement of the solid-state imaging device which concerns on 1st Embodiment. It is a schematic block block diagram of the solid-state imaging device which concerns on 2nd Embodiment of this indication. It is a schematic block diagram of the measurement system for calculating | requiring the optimal intermediate voltage of the solid-state imaging device which concerns on 2nd Embodiment. It is a flowchart which shows the procedure of the setting operation | movement of the optimal intermediate voltage in the solid-state imaging device which concerns on 2nd Embodiment. It is a timing chart of various signals for explaining the setting operation of the optimal intermediate voltage in the solid-state imaging device according to the second embodiment. FIG. 10 is a diagram for explaining a method for obtaining an optimum value of an intermediate voltage of each pixel in the second embodiment. It is a schematic block block diagram of the solid-state imaging device which concerns on 3rd Embodiment of this indication. It is a figure for demonstrating the feedback control operation | movement of the intermediate voltage in the solid-state imaging device which concerns on 3rd Embodiment. It is a figure which shows an example of the electronic device to which the solid-state imaging device of this indication is applied.

Hereinafter, an example of a solid-state imaging device according to an embodiment of the present disclosure and an electronic apparatus including the solid-state imaging device will be described in the following order with reference to the drawings. However, the present disclosure is not limited to the following example.
1. 1. First embodiment: basic configuration of solid-state imaging device 2. Reading operation of pixel signal Second Embodiment: Configuration including a storage unit storing an optimum intermediate voltage 3. Third embodiment: Configuration for feedback control of intermediate voltage Various modifications 6. Configuration of electronic devices (application examples)

<1. First Embodiment: Basic Configuration of Solid-State Imaging Device>
In the first embodiment, a configuration example of a solid-state imaging device of a type in which a signal charge accumulated in a photoelectric conversion element is divided into a plurality of times by a transfer transistor and transferred to a floating diffusion portion (hereinafter referred to as an FD portion) will be described. To do. Hereinafter, such a method is referred to as a divided reading method. In this divided readout method, normally, a plurality of pixel signals (output data) read out in a divided manner are finally added and output. In this embodiment, a configuration example of a surface irradiation type solid-state imaging device in which light is irradiated from the surface on the wiring layer side of the substrate will be described.

[Outline of the principle of low power drive]
First, before describing the specific configuration of the solid-state imaging device of the divided readout method according to the first embodiment, an outline of the principle that enables low-power driving in the solid-state imaging device of the present disclosure will be briefly described.

  1A and 1B show schematic block configurations of a conventional and the solid-state imaging device of the present disclosure, respectively. 1A and 1B, the configuration of each solid-state imaging device is simplified and described in order to clarify the difference between the conventional solid-state imaging device 200 and the solid-state imaging device 1 of the present disclosure. Details of the internal configuration of the solid-state imaging device 1 of the present disclosure will be described later with reference to the drawings.

  The conventional solid-state imaging device 200 mainly includes a pixel unit 201 having a plurality of pixels including photodiodes (hereinafter referred to as PD), an analog circuit 202, and a digital circuit 203. The analog circuit 202 performs predetermined analog processing (for example, analog CDS processing, AD conversion processing, etc.) on the analog signal output from the pixel unit 201, and the digital circuit 203 is digitally converted by the analog circuit 202. The output data is subjected to predetermined processing.

  As shown in FIG. 1A, the conventional solid-state imaging device 200 includes an analog power source 204 for driving pixels and a digital power source 205 for driving the digital circuit 203 and the like. Used. Therefore, conventionally, in order to drive the solid-state imaging device 200, two power supplies are required, which increases the cost. Further, as described above, at present, it is difficult to reduce the power supply voltage DVDD of the analog power supply 204, so it is difficult to reduce the power consumption.

On the other hand, the solid-state imaging device 1 according to the present disclosure has the following characteristics (see FIG. 1B).
(1) A division readout method is adopted as a pixel signal readout method.
(2) A photoelectric conversion element included in each pixel in the pixel unit 10 is configured by a photogate (hereinafter referred to as PG).
(3) A one-row memory unit 3 is provided for temporarily storing data for one row output during the intermediate transfer operation and data for one row output during the complete transfer operation.
(4) A single drive power source 6 is used, and a part of the analog circuit 2 and the digital circuit 4 (various circuits provided after a vertical signal line VSL described later) and various pixel transistors in the pixel 20 6 to drive.
(5) An intermediate voltage generation circuit 5 that generates an intermediate voltage Vm (0 <Vm <VDD) to be applied to the gate of the transfer transistor during the intermediate transfer operation from the power supply voltage VDD output from the drive power supply 6 is provided.
(6) PG is driven by the intermediate voltage Vm generated by the intermediate voltage generation circuit 5.

  In FIG. 1B, the single-row memory unit 3 is illustrated separately from the analog circuit 2 in order to clarify the feature of the present disclosure (difference from the prior art). The unit 3 is included in the analog circuit 2 as described later. More specifically, the one-row memory unit 3 corresponds to an analog memory 32 and a digital memory 36 in the unit circuit 30 shown in FIG. 3 to be described later, and these memories are connected to the column processing unit 13 in the analog circuit 2. Provided.

  As described above, the solid-state imaging device 1 of the present disclosure employs the divided readout method, uses PG as a photoelectric conversion element, and generates a power supply voltage for driving the PG as an intermediate voltage provided inside the device. It is generated by the circuit 5. In the PG, the depth of the potential potential in the PG can be adjusted by the voltage applied to the gate thereof, so that an accurate read operation can be performed even with the intermediate voltage Vm.

  In the present disclosure, the solid-state imaging device 1 can be driven by a single drive power supply 6 by having the characteristics (1) to (6). Therefore, according to the present disclosure, it is possible to drive the solid-state imaging device 1 with low power, and further, it is possible to reduce the number of parts, thereby reducing the cost.

[Configuration of solid-state imaging device]
FIG. 2 shows a schematic configuration of the solid-state imaging device of the divided readout method according to the first embodiment of the present disclosure. FIG. 2 is a schematic block configuration diagram of the entire solid-state imaging device.

  The solid-state imaging device 1 is a CMOS image sensor, and includes a pixel unit 10, a sensor control circuit 11, a vertical scanning circuit 12, and a column processing unit 13. The solid-state imaging device 1 includes a digital processing circuit 14, a reference signal generation circuit 15 (DAC: Digital to Analog Converter), and an intermediate voltage generation circuit 16.

  The pixel unit 10 includes a plurality of unit pixels 20 (hereinafter simply referred to as pixels 20) that are two-dimensionally arranged in a matrix. The internal configuration of the pixel 20 will be described in detail later. In addition, the pixel unit 10 is formed along various column drive lines (not shown) formed along the row direction for each row of the pixels 20 two-dimensionally arranged in a matrix and along the column direction for each column. Vertical signal lines VSL. Various pixel drive lines are connected to the vertical scanning circuit 12 (not shown), and the vertical signal lines VSL are connected to the column processing unit 13.

  The sensor control circuit 11 includes, for example, a timing generator that generates timing signals for various operations of the solid-state imaging device 1. Various timing signals generated by the sensor control circuit 11 are supplied to the vertical scanning circuit 12, the column processing unit 13, and the like, and each unit is driven and controlled based on these timing signals.

  The vertical scanning circuit 12 is configured by, for example, circuit elements such as a shift register and an address decoder, and outputs various driving signals to each pixel 20 of the pixel unit 10 to drive each pixel 20, and outputs a signal from each pixel 20. read out.

  The column processing unit 13 includes a plurality of unit circuits 30 that perform a predetermined process on the analog pixel signal (voltage signal) output to the vertical signal line VSL. The unit circuit 30 is provided for each vertical signal line VSL.

  Each unit circuit 30 performs not only AD conversion processing but also CDS processing before and after the pixel signal (voltage signal) obtained through the corresponding vertical signal line VSL. That is, in the unit circuit 30, dual noise canceling signal processing is performed on the pixel signal obtained via the vertical signal line VSL. The internal configuration and operation of the unit circuit 30 will be described later in detail.

  The digital processing circuit 14 performs various signal processes on the digital pixel signal (count number) output from the column processing unit 13. For example, the digital processing circuit 14 converts the input count number into a corresponding output code.

  The reference signal generation circuit 15 generates a reference signal (reference voltage) used when AD converting the pixel signal, and supplies the reference signal to an AD conversion circuit 34 (comparator) described later in the column processing unit 13. As will be described later in Modification 6, the reference signal generation circuit 15 generates and outputs a reference signal not only during normal operation but also during the setting operation of the optimum value of the intermediate voltage performed before shipment. Also good.

  Although not shown, the intermediate voltage generation circuit 16 is connected to the drive power supply 6 in FIG. 1B and generates a predetermined intermediate voltage Vm based on the power supply voltage VDD output from the drive power supply 6. Although the value of the intermediate voltage Vm generated by the intermediate voltage generation circuit 16 is arbitrary, in this embodiment, the intermediate voltage Vm is set to VDD / 2.

  Although not shown, the intermediate voltage generation circuit 16 is connected to a gate of a transfer transistor 22 described later of each pixel 20 and supplies the generated intermediate voltage Vm to each gate of the transfer transistor 22 during an intermediate transfer operation. Further, although not shown, the intermediate voltage generation circuit 16 is connected to a gate electrode of a PG 21 described later of each pixel 20, and the PG 21 is driven by the intermediate voltage Vm output from the intermediate voltage generation circuit 16.

  As will be described later, the pixel transistors other than the transfer transistor 22 in the pixel 20 are driven by the power supply voltage VDD output from the external drive power supply 6 (see FIG. 3). Various circuits (including the reference signal generation circuit 15) provided after the vertical signal line VSL are driven by the power supply voltage VDD output from the drive power supply 6.

  Further, although not shown in FIG. 2, the solid-state imaging device 1 also includes a horizontal scanning circuit that sequentially and selectively scans the unit circuits 30 provided for each vertical signal line VSL in the column processing unit 13. By this selective scanning of the horizontal scanning circuit, the pixel signals subjected to signal processing by each unit circuit 30 of the column processing unit 13 are sequentially output to the digital processing circuit 14.

[Pixel configuration]
Next, the configuration of each pixel 20 will be briefly described with reference to FIG. FIG. 3 is a schematic configuration diagram of the pixel 20 and the unit circuit 30 connected thereto. FIG. 3 shows the configuration of the unit circuit 30 when the number of intermediate transfer operations is one.

  The pixel 20 includes one PG 21 (photogate), various active elements (pixel transistors) including MOS transistors provided for the one PG 21, and an FD unit 26 (charge-voltage conversion unit). In the example illustrated in FIG. 3, the pixel 20 includes a transfer transistor 22, an amplification transistor 23, a reset transistor 24, and a selection transistor 25 as various active elements.

  That is, here, an example in which the pixel 20 is a four-transistor pixel will be described. Note that the present disclosure is not limited to this, and the pixel 20 may be a three-transistor pixel that does not include the selection transistor 25. Furthermore, here, an example is shown in which various pixel transistors are composed of MOS transistors having an N-type carrier polarity. In this example, for one pixel 20, three signal wirings (not shown) including a transfer wiring, a reset wiring, and a selection wiring are provided in the row direction, and a vertical signal line VSL is provided in the column direction.

  The PG 21 is composed of a MOS diode, and converts incident light into an amount of electric charges (here, electrons) corresponding to the amount of incident light (photoelectric conversion). The PG 21 has a gate electrode, and the potential (potential) depth of the light receiving region can be changed by a voltage value applied to the gate electrode. In the present embodiment, the PG 21 has a characteristic that the potential depth of the light receiving region of the PG 21 becomes deep (large) when the voltage value applied to the gate electrode increases.

  Moreover, since the solid-state imaging device 1 of this embodiment is a surface irradiation type solid-state imaging device, a gate electrode is provided on the light receiving surface of the PG 21. Therefore, in this embodiment, since light is incident on the light receiving portion of the PG 21 via the gate electrode, the thickness of the gate electrode of the PG 21 is made as thin as possible, or the gate electrode is made of a transparent electrode. Is preferred.

  The transfer transistor 22 is provided between the PG 21 and the FD unit 26. The transfer transistor 22 is turned on when a high level signal is input from the vertical scanning circuit 12 to the gate of the transfer transistor 12 via the transfer wiring, and charges (electrons) photoelectrically converted by the PG 21 are transferred to the FD unit 26. Note that the charge transferred to the FD unit 26 is converted into a voltage (potential) in the FD unit 26.

  The gate of the amplification transistor 23 is connected to the FD unit 26. The drain of the amplification transistor 23 is connected to the supply terminal of the power supply voltage VDD, and the source of the amplification transistor 23 is connected to the vertical signal line VSL via the selection transistor 25. The amplification transistor 23 amplifies the potential (voltage signal) of the FD unit 26 and outputs the amplified voltage signal to the selection transistor 25 as a light accumulation signal (pixel signal).

  The reset transistor 24 is provided between the supply terminal of the power supply voltage VDD and the FD unit 26. The reset transistor 24 is turned on when a high level signal is input to the gate of the reset transistor 24 from the vertical scanning circuit 12 via the reset wiring, and the potential of the FD section 26 is reset to the power supply voltage VDD.

  The selection transistor 25 is provided between the amplification transistor 23 and the vertical signal line VSL. The selection transistor 25 is turned on when a high level signal is input to the gate thereof from the vertical scanning circuit 12 via the selection wiring, and the voltage signal (pixel signal) amplified by the amplification transistor 23 is applied to the vertical signal line VSL. Output to. That is, in the four-transistor type solid-state imaging device 1, the selection transistor 25 is controlled to switch between selection and non-selection of the pixel 20. The pixel signal of each pixel 20 output to the vertical signal line VSL is transferred to a corresponding analog CDS circuit 31 described later.

[Configuration of unit circuit]
Next, the internal configuration and operation of the unit circuit 30 in the column processing unit 13 provided for each vertical signal line VSL will be described with reference to FIGS.

FIG. 4 is a timing chart of various signals for explaining the operation of each unit in the unit circuit 30. Specifically, FIG. 4 shows a transfer signal (TRG) supplied to each pixel 20, a pixel signal (S _VSL ) output to the vertical signal line VSL, a comparator output signal (S _COM ), and a reference signal ( RAMP) and a signal (ΔV) timing chart after analog CDS processing. In FIG. 4, for convenience of explanation, the reference signal (RAMP) and the signal (ΔV) after the analog CDS processing are described in an overlapping manner.

  As shown in FIG. 3, the unit circuit 30 includes an analog CDS circuit 31, an analog memory 32, an analog addition / non-addition circuit 33, an AD conversion circuit 34, a digital CDS circuit 35, a digital memory 36, and a digital memory. And an addition / non-addition circuit 37. The analog CDS circuit 31, analog memory 32, analog addition / non-addition circuit 33, AD conversion circuit 34, digital CDS circuit 35, digital memory 36, and digital addition / non-addition circuit 37 are arranged in this order from the pixel unit 10 side. Connected in series.

The analog CDS circuit 31 performs correlated double sampling processing (analog CDS processing) on the pixel signal S _VSL (voltage signal) obtained via the corresponding vertical signal line VSL. Specifically, the analog CDS circuit 31 first detects the voltage level of the P phase at a predetermined timing T1 in the P phase period (reset period) in the pixel signal S _VSL output to the vertical signal line VSL (see FIG. 4). Next, the analog CDS circuit 31 stores the voltage level detected at the timing T1 in a memory (not shown) including a capacitor or the like with reference (for example, zero). Thereafter, the analog CDS circuit 31 detects the D-phase voltage level at a predetermined timing T5 in the D-phase period (signal transfer period) (see FIG. 4), and from the P-phase voltage level (reference level) of the voltage level. The potential difference is detected. Then, as shown in FIG. 4, the analog CDS circuit 31 outputs a potential difference signal ΔV using the P-phase voltage level as a reference level to the analog memory 32.

  By performing the above-described analog CDS processing, for example, fixed pattern noise unique to a pixel due to reset noise, variation in threshold values of amplification transistors, and the like can be removed. In this embodiment, since the pixel signal is read out by the divided reading method, the above-described analog CDS processing is performed for each intermediate transfer operation and for each complete transfer operation. The potential difference signal ΔV (output data: DataA0 and DataB0 in FIG. 3) obtained by each transfer operation is individually output to the analog memory 32.

  The analog memory 32 temporarily stores analog output data (potential difference signal ΔV) output from the analog CDS circuit 31. In the present embodiment, the analog memory 32 temporarily stores analog output data (DataA0 and DataB0) output from the analog CDS circuit 31 in each of the intermediate transfer operation and the complete transfer operation.

  The analog addition / non-addition circuit 33 stores the analog output data (DataA0: first analog output data) stored in the analog memory 32 during the intermediate transfer operation and the analog output data (DataB0: 2nd analog output data) is acquired. Next, the analog addition / non-addition circuit 33 determines the analog output data (DataA0) during the intermediate transfer operation and the analog output data (DataB0) during the complete transfer operation according to the level of the output data during each transfer operation. ) Is subjected to addition processing or non-addition processing. Then, the analog addition / non-addition circuit 33 outputs the data (DataC0) subjected to the addition process or the non-addition process to the AD conversion circuit 34. Note that the addition and non-addition processing of output data in the analog addition / non-addition circuit 33 can be performed in the same manner as the processing described later in the digital addition / non-addition circuit 37, but in this embodiment, analog addition / non-addition is performed. The circuit 33 performs only addition processing.

Although not shown, the AD conversion circuit 34 includes a comparator, and the voltage level of the signal (potential difference signal ΔV) output from the corresponding analog addition / non-addition circuit 33 and the reference signal input from the reference signal generation circuit 15 ( The voltage level of RAMP) is compared with a comparator. Then, as shown in FIG. 4, the AD conversion circuit 34 generates a signal (comparison result: S _COM ) whose signal level is inverted at times T2 and T6 when the output levels of both signals become the same.

In the present embodiment, analog CDS processing is performed before the AD conversion processing. Therefore, the AD conversion circuit 34 performs the above-described comparison processing on the analog CDS-processed P-phase and D-phase signals (potential difference signal ΔV) output from the analog addition / non-addition circuit 33. The AD conversion circuit 34 outputs the comparison result (S _COM ) between the P phase and the D phase obtained by the comparator to the digital CDS circuit 35 in each of the intermediate transfer operation and the complete transfer operation.

Although not shown, the digital CDS circuit 35 has a count unit. The count unit is a time until the voltage level of the output signal (potential difference signal ΔV) from the analog addition / non-addition circuit 33 becomes the same level as the voltage level of the reference signal (RAMP) output from the reference signal generation circuit 15 ( (Comparison period) is measured (counted). At this time, the count unit switches the count operation to either the up-count operation or the down-count operation based on the comparison result (S _COM ) in the comparator in the AD conversion circuit 34.

Specifically, the count unit, the output signal S period _COM is at the high level and the comparison period in the P phase (the period of time T0~T2 in FIG. 4) comparator performs the down-count operation. Further, the comparison period in the D phase (the period of time T4~T6 in FIG. 4) a and the output signal S period _COM is at the low level of the comparator performs the up-count operation. Thus, the count number obtained after the end of the up-count operation is a value obtained by subtracting the absolute value of the count number in the P-phase comparison period from the absolute value of the count number in the D-phase comparison period. That is, the count number finally obtained by the D-phase count operation is output data subjected to digital CDS processing. By this digital CDS processing, it is possible to cancel the influence of characteristic variations of the analog CDS circuit 31 and the AD conversion circuit 34.

  Then, the digital CDS circuit 35 outputs the finally obtained D-phase count number (output data after the digital CDS process) to the digital memory 36. In the present embodiment, since the pixel signal is read out by the divided reading method, the digital CDS circuit 35 counts the D-phase counts obtained in the intermediate transfer operation and the complete transfer operation (Data A and Data B in FIG. 3). ) Is output to the digital memory 36.

  The digital memory 36 temporarily stores the count number (digital output data) output from the digital CDS circuit 35. At this time, the analog memory 32 temporarily stores the count numbers (DataA and DataB) output from the digital CDS circuit 35 in each of the intermediate transfer operation and the complete transfer operation.

  The digital addition / non-addition circuit 37 stores the analog output data (Data A: first digital output data) stored in the digital memory 36 during the intermediate transfer operation and the analog output data (Data B: stored during the complete transfer operation). 2nd digital output data) is acquired. Then, the digital adder / non-adder circuit 37, according to the level of the output data at each transfer operation, digital output data (DataA) at the intermediate transfer operation and digital output data (DataB) at the complete transfer operation ) Is subjected to addition processing or non-addition processing. Then, the digital addition / non-addition circuit 37 outputs the output data (DataC) subjected to the addition process or the non-addition process to the digital processing circuit 14.

  Here, the contents of addition processing and non-addition processing performed by the digital addition / non-addition circuit 37 will be described in detail. The digital addition / non-addition circuit 37 performs addition processing in the following situations A and B. Here, a case where the intermediate transfer operation is performed once will be described.

(Situation A)
Digital addition / non-addition when the level of the output data (Data A) during the intermediate transfer operation and the level of the output data (Data B) during the complete transfer operation are values between a predetermined upper limit threshold ThH and a lower limit threshold ThL The circuit 37 adds both output data. Then, the digital addition / non-addition circuit 37 outputs the added data (DataC = DataA + DataB) to the digital processing circuit 14.

  Note that the upper limit threshold ThH and the lower limit threshold ThL of the output data can be arbitrarily set according to, for example, the assumed noise amount, the value of the intermediate voltage Vm, and the like. For example, the upper threshold value ThH of the output data can be set to output data corresponding to the charge amount (3Qfd / 4) that is 3/4 of the saturation charge amount Qfd of the FD unit 26. In addition, the lower limit threshold ThL can be set, for example, as output data corresponding to a charge amount (Qfd / 4) that is ¼ of the saturation charge amount Qfd of the FD unit 26.

(Situation B)
When the level of the output data (Data A) during the intermediate transfer operation is larger than the upper limit threshold ThH, the amount of charge transferred to the FD unit 26 during the complete transfer operation becomes very large. Therefore, the count number during the complete transfer operation is the full count value. become. Therefore, in this case, the digital addition / non-addition circuit 37 outputs data (DataC = DataA + full count value) obtained by adding the full count value to the output data (DataA) at the time of the intermediate transfer operation to the digital processing circuit 14. In this case, it is not necessary to read the output data (Data B) during the complete transfer operation.

  On the other hand, in the following situations C and D, the digital addition / non-addition circuit 37 performs non-addition processing.

(Situation C)
When the level of the output data (DataA) during the intermediate transfer operation is smaller than the lower limit threshold ThL, the output data (DataA) during the intermediate transfer operation is considered to be noise. Therefore, in this case, output data (Data A) during the intermediate transfer operation is not used. That is, in this case, the digital addition / non-addition circuit 37 does not add the output data (Data A) at the time of the intermediate transfer operation and the output data (Data B) at the time of the complete transfer operation, and outputs the data ( Only Data B) is output as output data (Data C).

(Situation D)
When the level of the output data (Data B) during the complete transfer operation is smaller than the lower limit threshold ThL, the output data (Data A) during the intermediate transfer operation is considered to be fake data. Therefore, in this case, output data (Data A) during the intermediate transfer operation is not used. That is, in this case, the digital addition / non-addition circuit 37 does not add the output data (Data A) at the time of the intermediate transfer operation and the output data (Data B) at the time of the complete transfer operation, and outputs the data ( Only Data B) is output as output data (Data C).

<2. Pixel signal readout operation>
Next, referring to FIG. 5, FIG. 6 (a) to (g), FIG. 7 (a) to (d), and FIG. 8 (a) to (c), the solid according to the first embodiment. A pixel signal reading operation in the imaging apparatus 1 will be described. However, here, an example in which the intermediate transfer operation is performed once will be described. However, the present disclosure is not limited to this, and the disclosed technology can also be applied when the intermediate transfer operation is performed twice or more.

  FIG. 5 is a flowchart illustrating the procedure of the pixel signal reading operation in the solid-state imaging device 1 according to the first embodiment. 6A to 6G are timing charts of various signals (control signals, output signals, etc.) during the read operation.

Specifically, FIG. 6A shows a signal waveform of a voltage signal (SEL) applied to the gate of the selection transistor 25, and FIG. 6B shows a voltage signal applied to the gate of the reset transistor 24. It is a signal waveform of (RST). FIG. 6C shows the signal waveform of the voltage signal (TRG) applied to the gate of the transfer transistor 22, and FIG. 6D shows the voltage signal (PGTG) applied to the gate electrode of PG21. It is a signal waveform. FIG. 6E is a signal waveform showing a temporal change in the potential (S _FD ) of the FD unit 26, and FIG. 6F is a diagram illustrating the pixel signal (S _VSL ) output to the vertical signal line VSL. It is a signal waveform which shows a time change of an electric potential level. FIG. 6G shows the signal waveform of the reference signal (RAMP) output from the reference signal generation circuit 15 and the signal waveform of the output signal (ΔV: potential difference signal) after analog CDS processing. . In FIG. 6G, the reference signal (RAMP) and the output signal (ΔV) after the analog CDS processing are described in an overlapping manner in order to clarify the state of the comparison processing in the AD conversion circuit 34.

  FIGS. 7A to 7D are diagrams showing the state of the charge transfer operation from the PG 21 to the FD unit 26 during the intermediate transfer operation. 8A to 8C are diagrams showing the state of the charge transfer operation from the PG 21 to the FD unit 26 during the complete transfer operation.

  First, the intermediate voltage generation circuit 16 of the solid-state imaging device 1 applies the intermediate voltage Vm (here, VDD / 2) to the gate electrodes of the PG 21 in all the pixels 20 (step S1), and the potential of the light receiving region of the PG 21. Make the depth deeper (larger). Then, the solid-state imaging device 1 performs exposure in this state (step S2). As a result, signal charges are accumulated in PG21. This intermediate voltage Vm (= VDD / 2) is continuously applied to the gate electrode of PG21 until the charge transfer start time (time t10) in the complete transfer period described later.

  Next, the solid-state imaging device 1 selects a predetermined PG 21 and starts an intermediate transfer process for the signal charge stored in the PG 21.

  Specifically, first, a high level voltage (VDD) is applied to the gates of the selection transistor 25 and the reset transistor 24 of the pixel 20 to be read at a predetermined time t1 (step S3), and both transistors are turned on. (See FIGS. 6A and 6B). As a result, the charge accumulation state of the FD unit 26 is reset, and the P-phase period process (step S4) in the intermediate transfer process is started. In the process of the P-phase period in step S4, as described in the operation of the unit circuit 30, the analog CDS process and AD conversion are performed on the analog pixel signal output to the vertical signal line VSL during the P-phase period. Processing (comparison processing) and digital CDS processing are performed.

As a result of the reset operation in step S3, a potential _SFD corresponding to the reset state is generated in the FD unit 26 (see FIG. 6E). Further, the pixel signal S _VSL corresponding to the reset state of the FD unit 26 is output to the vertical signal line VSL (see FIG. _6F ). After the intermediate transfer process is started, a high level voltage (VDD) is applied to the gate of the selection transistor 25 from time t1 to time t12 when the complete transfer process ends, as shown in FIG. 6A. .

Here, the relationship between the light receiving (gate) region of PG 21, the gate region of the transfer transistor 22, the gate region of the reset transistor 24, and the region of the FD portion 26 at the time immediately after time t 1 is shown in FIG. Shown in (a). The time t1 immediately after the time, by the reset operation of the FD section 26, reduces the potential barrier of the gate region of the reset transistor 24, the potential S _FD of the FD portion 26 is reset to a predetermined potential.

  Next, at time t2, the voltage applied to the gate of the reset transistor 24 is set to a low level (eg, ground level). Here, the relationship between the potential of the light receiving region of PG21, the gate region of the transfer transistor 22, the gate region of the reset transistor 24, and the region of the FD portion 26 at the time immediately after time t2 is shown in FIG. Shown in At the time immediately after time t2, as shown in FIG. 7B, the voltage level applied to the gate of the reset transistor 24 is low, so that the potential barrier in the gate region of the reset transistor 24 is as shown in FIG. ) Is in an elevated state from the state shown in FIG. In the state shown in FIG. 7B, the column processing unit 13 performs various processes (comparison process and count process) of the P phase (reset state) in the intermediate transfer process.

  Specifically, in the state shown in FIG. 7B, the column processing unit 13 (AD conversion circuit 34) performs the voltage level of the reference signal (RAMP) output from the reference signal generation circuit 15 and the analog CDS processing. The P level output signal (ΔV) is compared with the voltage level.

  The column processing unit 13 (digital CDS circuit 35) then waits for a time (comparison) from the start of the comparison process until the voltage level of the reference signal (RAMP) and the output signal (ΔV) after the analog CDS process become the same level. Count down). In the example shown in FIG. 6G, the level of both signals becomes the same at time t3, and the count number at this time becomes the count number corresponding to the P-phase (reset state) output signal at the time of intermediate transfer processing. Become.

  Next, at time t4, the intermediate voltage generation circuit 16 applies the intermediate voltage Vm (= VDD / 2) to the gate of the transfer transistor 22 (step S5). Thereby, the process (step S6) of the D phase period in the intermediate transfer process is started.

Here, the relationship between the light receiving region of PG21, the gate region of the transfer transistor 22, the gate region of the reset transistor 24, and the region of the FD portion 26 at the time immediately after time t4 is shown in FIG. Shown in By applying the intermediate voltage Vm in step S5, the potential barrier in the gate region of the transfer transistor 22 is lowered. As a result, as shown in FIG. 7C, among the amount of charge accumulated in the PG 21 by the exposure operation in step S2, the amount of charge corresponding to the lowered potential barrier is transferred to the FD unit 26. . As a result, a potential _SFD corresponding to the signal transfer state (D phase) is generated in the FD unit 26 (see FIG. 6E). Further, the pixel signal S _VSL corresponding to the signal transfer state of the FD unit 26 is output to the vertical signal line VSL (see FIG. _6F ).

  Next, at time t5, the voltage (TRG) applied to the gate of the transfer transistor 22 is set to a low level. Here, the relationship between the light receiving region of PG21, the gate region of the transfer transistor 22, the gate region of the reset transistor 24, and the region of the FD portion 26 at the time immediately after time t5 is shown in FIG. Shown in

  At the time immediately after time t5, as shown in FIG. 7D, the voltage level applied to the gate of the reset transistor 24 is at a low level. Therefore, the potential barrier in the gate region of the reset transistor 24 is as shown in FIG. ) Is in an elevated state from the state shown in FIG. Then, in the state shown in FIG. 7D, the column processing unit 13 performs various processes (comparison process and count process) of the D phase (signal transfer state) in the intermediate transfer process.

  Specifically, in the state shown in FIG. 7D, the column processing unit 13 (AD conversion circuit 34) performs the voltage level of the reference signal (RAMP) output from the reference signal generation circuit 15 and the analog CDS processing. The D-phase output signal (ΔV) is compared with the voltage level.

  The column processing unit 13 (digital CDS circuit) then waits until the voltage level of the reference signal (RAMP) and the output signal (ΔV) after the analog CDS processing become the same level from the start of the comparison processing (comparison time). ). In the example shown in FIG. 6G, the level of both signals becomes the same at time t6, and the count number at this time is the count number corresponding to the D-phase (signal transfer state) output signal during the intermediate transfer process. become.

  The AD conversion process and the digital CDS process are performed on the output signal (ΔV) after the analog CDS process by the series of processes in the P-phase period and the D-phase period during the intermediate transfer process described above. Therefore, the output data corresponding to the count number output at time t6 (Data A in FIG. 3) is output data that has been subjected to digital CDS processing and from which noise has been removed.

  Next, the digital memory 36 stores the digital output data (Data A) during the intermediate transfer process measured as described above (step S7).

  After the intermediate transfer process, at a predetermined time t7, a high level voltage (VDD) is applied to the gate of the reset transistor 24 of the pixel 20 to be read (step S8), and the reset transistor 24 is turned on (FIG. 6 (b)). As a result, the charge accumulation state of the FD unit 26 is reset, and the P-phase period process (step S9) in the complete transfer process is started. In the complete transfer process, analog CDS process and AD conversion process (comparison) are performed on the pixel signal output to the vertical signal line VSL in the unit circuit 30 (column processing unit 13) as in the intermediate transfer process. Processing) and digital CDS processing.

Here, the relationship between the light receiving (gate) region of PG 21, the gate region of the transfer transistor 22, the gate region of the reset transistor 24, and the region of the FD portion 26 at the time immediately after time t 7 is shown in FIG. Shown in (a). Time t7 in the time immediately following, by the reset operation of the FD section 26, reduces the potential barrier of the gate region of the reset transistor 24, the potential S _FD of the FD portion 26 is reset to a predetermined potential.

  Next, at time t8, the voltage applied to the gate of the reset transistor 24 is set to a low level (for example, the ground level). Here, the relationship between the potential of the light receiving region of PG21, the gate region of the transfer transistor 22, the gate region of the reset transistor 24, and the region of the FD portion 26 at the time immediately after time t8 is shown in FIG. Shown in At the time immediately after time t8, as shown in FIG. 8B, the voltage level applied to the gate of the reset transistor 24 is low, so that the potential barrier in the gate region of the reset transistor 24 is as shown in FIG. ) Is in an elevated state from the state shown in FIG. In the state shown in FIG. 8B, the column processing unit 13 performs various processes (comparison process and count process) in the P phase (reset state) in the complete transfer process.

  Specifically, in the state shown in FIG. 8B, the column processing unit 13 (AD conversion circuit 34) performs the voltage level of the reference signal (RAMP) output from the reference signal generation circuit 15 and the analog CDS processing. The P level output signal (ΔV) is compared with the voltage level.

  The column processing unit 13 (digital CDS circuit 35) then waits for a time (comparison) from the start of the comparison process until the voltage level of the reference signal (RAMP) and the output signal (ΔV) after the analog CDS process become the same level. Count down). In the example shown in FIG. 6G, the level of both signals becomes the same at time t9, and the count number at this time becomes the count number corresponding to the output signal of the P phase (reset state) at the time of complete transfer processing. Become.

  Next, at time t10, the solid-state imaging device 1 applies the power supply voltage VDD to the gate of the transfer transistor 22 by the drive power supply 6, and sets the potential of the gate electrode of PG21 to a low level (for example, ground level) (step S10: (Refer FIG.6 (c) and (d)). Thereby, the process (step S11) of the D phase period in the complete transfer process is started.

  In the present embodiment, the complete transfer voltage (= VDD) is continuously applied to the gate of the transfer transistor 22 until the complete transfer processing end time (time t12), and the potential of the gate electrode of PG21 is maintained at a low level. .

  Here, the relationship between the light receiving region of PG21, the gate region of the transfer transistor 22, the gate region of the reset transistor 24, and the region of the FD portion 26 at the time immediately after time t10 is shown in FIG. Shown in The potential barrier in the gate region of the transfer transistor 22 is further lowered by the application of the power supply voltage (VDD) from the potential barrier when the intermediate voltage Vm is applied (state in FIG. 8B). At this time, by setting the potential of the gate electrode of PG21 to a low level, the potential depth of the gate electrode region becomes shallow (small).

As a result, as shown in FIG. 8C, the bottom position of the potential of the gate electrode region of PG 21 is higher than the height position of the potential barrier of the gate region of the transfer transistor 22. In this case, all the charges remaining in the PG 21 after the intermediate transfer process are transferred to the FD unit 26. As a result, after time t10, a potential _SFD corresponding to the signal transfer state (D phase) is generated in the FD unit 26 (see FIG. 6E). Further, the pixel signal S _VSL corresponding to the signal transfer state of the FD unit 26 is output to the vertical signal line VSL (see FIG. _6F ).

  Next, in the state shown in FIG. 8C, the column processing unit 13 (AD conversion circuit 34) performs the voltage level of the reference signal (RAMP) output from the reference signal generation circuit 15 and the D phase after the analog CDS processing. Is compared with the voltage level of the output signal (ΔV).

  The column processing unit 13 (digital CDS circuit) then waits until the voltage level of the reference signal (RAMP) and the output signal (ΔV) after the analog CDS processing become the same level from the start of the comparison processing (comparison time). ). In the example shown in FIG. 6G, the level of both signals becomes the same at time t11, and the count number at this time is the count number corresponding to the output signal of the D phase (signal transfer state) during the complete transfer process. become.

  The AD conversion process and the digital CDS process are performed on the output signal (ΔV) after the analog CDS process by the series of processes in the P-phase period and the D-phase period during the complete transfer operation described above. Therefore, the output data corresponding to the count number output at time t11 (Data B in FIG. 3) is output data that has been subjected to digital CDS processing and from which noise has been removed.

  Next, the digital memory 36 stores the digital output data (Data B) during the complete transfer process measured as described above (step S12).

  Next, at a predetermined time t12, the potential levels of the selection transistor 25 and the transfer transistor 22 of the pixel 20 to be read are both set to a low level (ground level), and both transistors are turned off. At time t12, an intermediate voltage Vm (= VDD / 2) is applied to the gate electrode of PG21. In the present embodiment, the complete transfer process is thus completed.

  Next, the digital addition / non-addition circuit 37 corresponding to the pixel 20 to be read out outputs the output data (Data A) obtained by the intermediate transfer process and the output data (Data B) obtained by the complete transfer process to the digital memory. 36. Then, the digital addition / non-addition circuit 37 performs addition processing or non-addition processing on the two output data (Data A and Data B) based on the acquired level of each output data (step S13). Specifically, the digital addition / non-addition circuit 37 performs addition processing when the level of each output data is in the above-described situations A and B, and the level of each output data is in the above-described situations C and D. In some cases, non-addition processing is performed.

  In the present embodiment, as described above, the signal charge accumulated in PG 21 is read out by the divided reading method. Although not shown in FIG. 5, in the present embodiment, the above-described processing of steps S <b> 3 to S <b> 13 is performed on all the pixels 20.

  As described above, the solid-state imaging device 1 according to the present embodiment employs the division readout method and uses PG21 (photogate) as the photoelectric conversion element. In this embodiment, the PG 21 in each pixel 20 is driven by the intermediate voltage Vm output from the intermediate voltage generation circuit 16. In this embodiment, the transfer transistor 22 in each pixel 20 is driven with the intermediate voltage Vm during the intermediate transfer operation, and is driven with the power supply voltage VDD output from the external drive power supply 6 during the complete transfer operation. Furthermore, in this embodiment, the pixel transistors other than the transfer transistor 22 and various circuits after the vertical signal line VSL are driven by the power supply voltage VDD output from the drive power supply 6.

  Therefore, in the solid-state imaging device 1 of the present embodiment, the solid-state imaging device 1 can be driven by a single drive power supply 6, and the power consumption of the solid-state imaging device 1 can be reduced. Furthermore, in this embodiment, since the number of parts can be reduced, the cost can be reduced.

<3. Second Embodiment: Configuration including a storage unit storing an optimum intermediate voltage>
In the solid-state imaging device according to the present disclosure, as described above, the pixel signal is read by the division reading method. However, in this readout method, in order to accurately read out the data (pixel signal) corresponding to the amount of charge accumulated in PG21, the amount of charge Qc remaining in PG21 immediately before the complete transfer operation is calculated using the FD unit 26. The value must be equal to or less than the saturation charge amount Qfd.

That is, between the charge amount Qc remaining in the PG 21 immediately before the complete transfer operation, the charge amount Qm read for each intermediate transfer operation, the saturation charge amount Qs of the PG 21, and the saturation charge amount Qfd of the FD unit 26 The relationship of the following formula (1) must be satisfied. Note that “n” in the following equation (1) is the number of intermediate transfer operations.
Qs−n × Qm = Qc ≦ Qfd (1)

  The charge amount Qc remaining in PG 21 immediately before the complete transfer operation (hereinafter referred to as intermediate voltage holding charge amount Qc) is applied to the gate of the transfer transistor 22 during the intermediate transfer operation when the number of intermediate transfer operations is determined. It varies depending on the value of the applied intermediate voltage Vm. Therefore, in the divided readout method, in order to accurately read out the data (pixel signal) corresponding to the charge amount accumulated in PG21, the condition of the above formula (1) is satisfied for all the pixels 20 with the intermediate voltage Vm. It is necessary to set a value like this.

  In practice, however, the performance (electrical characteristics) of the transfer transistor 22 differs for each pixel 20 due to process problems. If there is such a performance variation of the transfer transistor 22, even if the same intermediate voltage Vm is applied to each pixel 20, the potential barrier height (potential) between the PG 21 and the FD unit 26 also varies. As a result, the charge amount Qm transferred during the intermediate transfer operation is different for each pixel 20, and finally, the intermediate voltage holding charge amount Qc is also different for each pixel 20.

  In this case, there is a possibility that the pixel 20 in which the intermediate voltage holding charge amount Qc of the PG 21 is larger than the saturation charge amount Qfd of the FD unit 26 is generated. In such a pixel 20, the FD unit 26 performs the complete transfer operation. Charges may overflow and image data may not be accurately reproduced.

  Therefore, in the divided readout method, even if there is a performance variation of the transfer transistor 22 as described above, the intermediate voltage Vm is set so that the condition of the above expression (1) is satisfied in all the pixels 20. It is preferable that it is set. Therefore, in the second embodiment, a configuration example of a solid-state imaging device that can be read with an intermediate voltage Vm that satisfies the condition of the above expression (1) in all the pixels 20 will be described.

[Configuration of solid-state imaging device]
FIG. 9 illustrates a schematic configuration of a solid-state imaging apparatus according to the second embodiment of the present disclosure. FIG. 9 is a schematic block configuration diagram of the entire solid-state imaging device. Moreover, in the solid-state imaging device 40 of this embodiment shown in FIG. 9, the same code | symbol is attached | subjected and shown to the structure similar to the solid-state imaging device 1 of the said 1st Embodiment shown in FIG.

  The solid-state imaging device 40 includes a pixel unit 10, a sensor control circuit 11, a vertical scanning circuit 12, and a column processing unit 13. The solid-state imaging device 40 includes a digital processing circuit 14, a reference signal generation circuit 15, an intermediate voltage generation circuit 16, and a storage unit 41.

  As is clear from a comparison between FIG. 9 and FIG. 2, the configuration of the solid-state imaging device 40 of the present embodiment is a configuration in which a storage unit 41 is further provided in the configuration of the solid-state imaging device 1 of the first embodiment. Other configurations are the same as the corresponding configurations of the first embodiment. Therefore, only the configuration of the storage unit 41 will be described here.

  The storage unit 41 includes a memory element such as an electrically programmable fuse (eFuse). From the viewpoint of ease of manufacturing the solid-state imaging device 40, it is preferable to use a memory element having a configuration that can be manufactured simultaneously with the formation process of the MOS transistor that forms the pixel 20 as the storage unit 41. From such a viewpoint, it is preferable that the storage unit 41 is configured by an electrically programmable fuse (eFuse).

  The storage unit 41 stores various information necessary for reading out pixel signals such as an optimum value of the intermediate voltage Vm and the number of intermediate transfer operations. In the present embodiment, even when the above-described performance variation of the transfer transistor 22 exists, the optimum value of the intermediate voltage Vm (hereinafter referred to as the optimum intermediate voltage Vmo) that satisfies the condition of the above expression (1) in all the pixels 20. Information) is stored.

  In the present embodiment, all of the optimum value (Vmd) of the intermediate voltage Vm for each pixel 20 may be stored in the storage unit 41 as various pieces of information necessary for reading. Further, in the solid-state imaging device 40, when the number of intermediate transfer operations is determined in advance, it is not necessary to store information on the number of intermediate transfer operations in the storage unit 41. The number of intermediate transfers is set in consideration of, for example, the design value of the saturation charge amount Qs of PG 21 and the saturation charge amount Qfd of the FD unit 26, the frame rate specification of the solid-state imaging device 40, and the like.

  Further, the storage unit 41 is connected to the intermediate voltage generation circuit 16, and information on the optimum intermediate voltage Vmo stored in the storage unit 41 is output to the intermediate voltage generation circuit 16 when reading out the pixel signal. The intermediate voltage generation circuit 16 generates the optimum intermediate voltage Vmo based on the acquired information about the optimum intermediate voltage Vmo and applies it to the pixel 20. Note that the optimum intermediate voltage Vmo is measured in advance using an external inspection device before shipment, as will be described later.

  Further, although not shown in FIG. 9, the solid-state imaging device 40 of the present embodiment acquires information on the optimum intermediate voltage Vmo measured by an external inspection device and writes the information in the storage unit 41. May be provided.

[Optimum intermediate voltage Vmo setting method]
Next, a method for setting the optimum intermediate voltage Vmo in the solid-state imaging device 40 of the present embodiment will be described.

(1) Configuration of Intermediate Voltage Setting System FIG. 10 shows a schematic block configuration of an intermediate voltage setting system for measuring and setting the optimum intermediate voltage Vmo of the solid-state imaging device 40. As shown in FIG. 10, the intermediate voltage setting system includes a solid-state imaging device 40 to be inspected and an inspection device 50 provided outside thereof.

  The inspection device 50 includes an intermediate voltage setting unit 51. Although not shown in FIG. 10, the inspection device 50 includes a control unit for controlling the setting operation of the optimum intermediate voltage Vmo. In the present embodiment, the inspection device 50 may include a uniform light inspection light source that irradiates the light receiving unit of the pixel unit 10 during the setting operation of the optimum intermediate voltage Vmo. 50 may be provided separately.

  The intermediate voltage setting unit 51 is connected to the digital processing circuit 14 in the solid-state imaging device 40, and output data obtained when various intermediate voltages Vm are applied to each pixel 20 during the setting operation of the optimum intermediate voltage Vmo. To get. Further, the intermediate voltage setting unit 51 obtains the optimum value Vmd of the intermediate voltage Vm of each pixel 20 based on the acquired various output data. As described above, since there is a performance variation in the transfer transistor 22 in each pixel 20, the optimum value Vmd of the intermediate voltage Vm of each pixel 20 also varies.

  Further, the intermediate voltage setting unit 51 selects an optimum intermediate voltage that satisfies the condition of the above formula (1) at the time of reading out from all the optimum values Vmd of the intermediate voltage Vm obtained for each pixel 20. Determine Vmo. In this example, the maximum value is selected from the optimum intermediate voltage Vmd obtained for each pixel 20, and the maximum value is set as the optimum intermediate voltage Vmo. The intermediate voltage setting unit 51 is connected to the storage unit 41 in the solid-state imaging device 40, and writes the obtained information about the optimum intermediate voltage Vmo into the storage unit 41.

(2) Setting Operation of Optimal Intermediate Voltage Vmo Next, the setting operation of the optimal intermediate voltage Vmo of the solid-state imaging device 40 will be described more specifically with reference to FIGS. FIG. 11 is a flowchart showing the procedure for setting the optimum intermediate voltage Vmo. FIG. 12 shows a reset signal (RST), a transfer signal (TRG), a pixel signal (S _VSL ) output to the vertical signal line VSL, a reference signal (RAMP), and an analog signal when the optimum intermediate voltage Vmo is set. It is a timing chart of the signal (ΔV) after CDS processing. In FIG. 12, the reference signal (RAMP) and the signal (ΔV) after the analog CDS process are described in an overlapping manner in order to clarify the state of the comparison process in the AD conversion circuit 34.

  The setting operation of the optimum intermediate voltage Vmo described below is controlled by a control unit (not shown) in the external inspection device 50.

  First, an operator or the like connects the solid-state imaging device 40 to be inspected to the inspection device 50. Specifically, the input terminal of the intermediate voltage setting unit 51 in the inspection device 50 is connected to the digital processing circuit 14 in the solid-state imaging device 40, and the output terminal of the intermediate voltage setting unit 51 is connected to the storage unit in the solid-state imaging device 40. 41 (see FIG. 10).

  Next, the inspection device 50 controls the intermediate voltage generation circuit 16 to set the intermediate voltage Vm applied to each pixel 20 in the pixel unit 10 to a predetermined initial value Vm_0 (step S21). Here, the initial value Vm_0 of the intermediate voltage Vm is the minimum value of the variable region (Vm_0 to Vm_max) of the intermediate voltage Vm.

  Next, the inspection device 50 irradiates the light receiving unit of the pixel unit 10 with uniform light to forcibly saturate each pixel 20 (step S22). At this time, a voltage corresponding to the saturation charge amount Qs is applied to the gate electrode of the PG 21 of each pixel 20. By this step S22, the PG 21 is in a state where charges of the saturation charge amount Qs are accumulated.

  Next, the inspection device 50 controls the solid-state imaging device 40 and performs the following intermediate transfer operation n times in the predetermined pixel 20 (step S23). In each intermediate transfer operation, analog CDS processing, AD conversion processing (comparison processing), and digital CDS processing are performed as described in the operation of the unit circuit 30. Here, an example in which the intermediate transfer operation is performed once (n = 1) will be described to simplify the description.

  Specifically, first, the inspection device 50 controls the sensor control circuit 11 and the vertical scanning circuit 12 of the solid-state imaging device 40 to reset the reset transistor of the pixel 20 to be measured at a predetermined time tb0 (see FIG. 12). A high level reset signal is supplied to 24 gates. By this reset operation, the potential of the FD unit 26 is reset to the power supply voltage VDD, and the electric charge accumulated in the FD unit 26 is discharged.

  Thereafter, the column processing unit 13 in the solid-state imaging device 40 compares both signals until the voltage level of the reference signal RAMP and the voltage level of the signal after the analog CDS processing (potential difference signal ΔV) become the same level. . In the example shown in FIG. 12, at time tb1, the voltage level of the reference signal RAMP and the voltage level of the signal (potential difference signal ΔV) after the analog CDS processing become the same level. Phase (reset state) output data is obtained. However, in the setting operation of the optimum intermediate voltage Vmo, the P-phase output data during the intermediate transfer operation is not read out.

  Next, at time tb2, the inspection device 50 controls the sensor control circuit 11, the vertical scanning circuit 12, and the intermediate voltage generation circuit 16 of the solid-state imaging device 40, and is updated in the initial value Vm_0 of the intermediate voltage Vm or step S29 described later. The intermediate voltage Vm thus applied is applied to the pixel 20 to be measured. By applying the intermediate voltage Vm, the potential barrier in the gate region of the transfer transistor 22 is lowered. As a result, of the amount of charge accumulated in PG 21 (saturated charge amount Qs), the amount of charge (charge amount Qm) corresponding to the potential barrier drop is transferred to the FD unit 26.

  Thereafter, the column processing unit 13 in the solid-state imaging device 40 compares both signals until the voltage level of the reference signal RAMP and the voltage level of the signal after the analog CDS processing (potential difference signal ΔV) become the same level. . In the example shown in FIG. 12, at time tb3, the voltage level of the reference signal RAMP and the voltage level of the signal after the analog CDS processing (potential difference signal ΔV) become the same level. Phase (signal transfer state) output data is obtained. However, in the setting operation of the optimum intermediate voltage Vmo, the D-phase output data during the intermediate transfer operation is not read out. In this embodiment, the intermediate transfer operation in step S23 is performed in this way. When the intermediate transfer operation is performed twice or more, the intermediate transfer operation is repeated twice or more.

  Next, the inspection device 50 controls the solid-state imaging device 40 and performs the following complete transfer operation on the predetermined pixel 20 (step S24). In the complete transfer operation, analog CDS processing, AD conversion processing (comparison processing), and digital CDS processing are performed in the same manner as in normal operation after shipment, and output data is acquired.

  Specifically, first, as shown in FIG. 12, the inspection device 50 controls the sensor control circuit 11 and the vertical scanning circuit 12 of the solid-state imaging device 40, and at the time tb4 (> tb3), the pixel to be measured. A high level reset signal is supplied to the gate of the 20 reset transistors 24. By this reset operation, the potential of the FD unit 26 is reset to the power supply voltage VDD, and the electric charge accumulated in the FD unit 26 is discharged.

  Thereafter, the column processing unit 13 in the solid-state imaging device 40 compares both signals until the voltage level of the reference signal RAMP and the voltage level of the signal after the analog CDS processing (potential difference signal ΔV) become the same level. . In the example shown in FIG. 12, at time tb5, the voltage level of the reference signal RAMP and the voltage level of the signal (potential difference signal ΔV) after the analog CDS processing become the same level. Phase (reset state) output data is obtained.

  Next, as shown in FIG. 12, at time tb6, the inspection device 50 controls the sensor control circuit 11 and the vertical scanning circuit 12 of the solid-state imaging device 40, and complete transfer voltage (complete transfer voltage Vc> Vm). Is supplied to the transfer transistor 22 of the pixel 20 to be measured. At this time, a low level (for example, ground level) voltage is applied to the gate electrode of PG 21 to reduce the potential depth of the gate electrode region.

  Note that the complete transfer voltage Vc is such that when the complete transfer voltage Vc is applied to the gate of the transfer transistor 22, the potential barrier of the gate region of the transfer transistor 22 is positioned at the bottom of the potential of the PG 21 or at a lower position. Set to the correct value. For example, the complete transfer voltage Vc can be set to the power supply voltage VDD of the solid-state imaging device 1 or the like.

  Due to the voltage application operation, all charges (intermediate voltage holding charge amount Qc = Qs−n × Qm) accumulated in PG 21 immediately before the complete transfer operation (after the last intermediate transfer operation) are transferred to the FD unit 26. (See FIG. 8C).

  Thereafter, the column processing unit 13 in the solid-state imaging device 40 compares both signals until the voltage level of the reference signal RAMP and the voltage level of the signal after the analog CDS processing (potential difference signal ΔV) become the same level. . In the example shown in FIG. 12, at time tb7, the voltage level of the reference signal RAMP and the voltage level of the signal (potential difference signal ΔV) after the analog CDS processing become the same level. Phase (signal transfer state) output data is obtained. That is, at time tb7, output data WDMOF corresponding to the charge amount (intermediate voltage holding charge amount Qc = Qs−n × Qm) stored in PG21 immediately before the complete transfer operation (after the last intermediate transfer operation) is obtained. It is done.

  In the present embodiment, the transfer operations in steps S23 and S24 are performed as described above, and output data WDMOF corresponding to the intermediate voltage holding charge amount Qc of PG21 immediately before the complete transfer operation (after the last intermediate transfer operation) is obtained. To do.

  Then, the solid-state imaging device 40 outputs the output data WDMOF corresponding to the intermediate voltage holding charge amount Qc obtained in step S24 to the intermediate voltage setting unit 51 in the inspection device 50 via the digital processing circuit 14 ( Step S25). Thereafter, during time tb8 to tb9, the inspection device 50 controls the sensor control circuit 11 and the vertical scanning circuit 12 of the solid-state imaging device 40, and each gate of the transfer transistor 22 and the reset transistor 24 of the pixel 20 to be measured. Supply a high level signal. At this time, although not shown in FIG. 12, the potential level of the gate electrode of PG21 is maintained at a low level. As a result, both the PG 21 and the FD unit 26 are in a reset state (the charge amount becomes zero), and the above-described intermediate transfer and complete transfer operations for the predetermined pixel 20 (column) are completed.

  Next, the inspection device 50 determines whether or not the above measurement has been performed on all the pixels 20 (step S26).

  If it is determined in step S26 that the processing in steps S23 to S25 described above has not been completed for all the pixels 20, the determination in step S26 is NO. In this case, the inspection device 50 changes the measurement target pixel 20 (step S27). Next, the process returns to the process of step S23, and thereafter, the processes of steps S23 to S27 described above are repeated until the measurement of all the pixels 20 is completed.

  On the other hand, in step S26, when the processes of steps S23 to S25 described above are completed for all the pixels 20, step S26 is YES. In this case, the inspection device 50 determines whether or not the intermediate voltage Vm currently applied to the transfer transistor 22 is the preset maximum value Vm_max of the intermediate voltage Vm (step S28).

  In step S28, if the current intermediate voltage Vm is not the maximum value Vm_max, step S28 is NO. In this case, the inspection device 50 controls the sensor control circuit 11, the vertical scanning circuit 12, and the intermediate voltage generation circuit 16 of the solid-state imaging device 40 to update the intermediate voltage Vm applied to the transfer transistor 22 (step S29). ). For example, the intermediate voltage Vm is increased by a predetermined amount ΔVm (set to Vm = Vm + ΔVm). The increase (ΔVm) of the intermediate voltage Vm may be constant over the entire variable range (Vm_0 to Vm_max) of the intermediate voltage Vm, or an increase in the region near the optimum value Vmd of the intermediate voltage Vm ( ΔVm) may be smaller than that of other regions.

  After the intermediate voltage Vm is updated in step S29, the process returns to step S22, and thereafter, the processes in steps S22 to S29 described above are repeated until the intermediate voltage Vm reaches its maximum value Vm_max.

  On the other hand, if the current intermediate voltage Vm is the maximum value Vm_max in step S28, step S28 is YES. In this case, the intermediate voltage setting unit 51 determines each pixel 20 based on various output data WDMOF corresponding to various intermediate voltages Vm (Vm_0 to Vm_max) obtained by the various processes in each pixel 20. An optimum value Vmd of the intermediate voltage Vm is calculated (step S30). Specifically, the optimum value Vmd of the intermediate voltage Vm of each pixel 20 is obtained as follows.

  In FIG. 13, in each pixel 20, various intermediate voltages Vm (Vm_0 to Vm_max) obtained by the processing in steps S21 to S29 and output data WDMOF (intermediate voltage holding charge amount Qc) corresponding to each intermediate voltage Vm are obtained. The corresponding output data). In the characteristics shown in FIG. 13, the horizontal axis represents the intermediate voltage Vm, and the vertical axis represents the output data WDMOF.

  As shown in FIG. 13, the output data WDMOF becomes the minimum value WDMOF_0 when the intermediate voltage Vm is the maximum value Vm_max. This is because, when the intermediate voltage Vm is maximum, the amount of charge Qm transferred from the PG 21 to the FD unit 26 in the intermediate transfer operation is maximum, so that the intermediate voltage holding charge amount Qc of the PG 21 immediately before the complete transfer operation is minimized. It is to become.

  Further, when the intermediate voltage Vm becomes smaller than the maximum value Vm_max, the output data WDMOF increases linearly. In this change region, as the intermediate voltage Vm decreases, the charge amount Qm transferred from the PG 21 to the FD unit 26 in the intermediate transfer operation decreases, and the intermediate voltage holding charge amount Qc of the PG 21 immediately before the complete transfer operation increases. .

  The value of the output data WDMOF is constant in the vicinity of the intermediate voltage (Vm_s) where the charge amount (Qc) transferred during the complete transfer operation is equal to the saturation charge amount Qfd of the FD section 26 and in the region of the intermediate voltage Vm smaller than that. (Maximum value WDMOF_max). In this constant output region, the charge amount (Qc) transferred to the FD unit 26 during the complete transfer operation is equal to or greater than the saturation charge amount Qfd, so that the output data WDMOF is saturated and constant at the maximum value WDMOF_max. It becomes.

  As described above, in the vicinity of the intermediate voltage Vm_s in FIG. 13 where the output data WDMOF is saturated, the intermediate voltage holding charge amount Qc of PG 21 immediately before the complete transfer operation is substantially the same as the saturated charge amount Qfd of the FD section 26. That is, the state in the vicinity of the intermediate voltage Vm_s corresponds to the lower limit (Qc = Qm) of the above equation (1), and the range of the intermediate voltages Vm_s to Vm_max having the characteristics shown in FIG. A suitable intermediate voltage Vm range that satisfies the conditions is obtained.

  Therefore, in step S30, the intermediate voltage setting unit 51 selects a predetermined intermediate voltage Vm from the range of the intermediate voltages Vm_s to Vm_max based on the relationship between the intermediate voltage Vm and the output data WDMOF shown in FIG. The optimum value Vmd of the intermediate voltage Vm of the pixel 20 is assumed. In the present embodiment, the intermediate voltage Vm_s at which the intermediate voltage holding charge amount Qc of PG 21 becomes substantially the same as the saturation charge amount Qfd of the FD unit 26 is set as the optimum value Vmd of the intermediate voltage Vm of the pixel 20.

  Here, returning to FIG. 11 again, the processing after step S30 will be described. After step S30, the intermediate voltage setting unit 51 satisfies the condition of the above expression (1) in all the pixels 20 based on the optimum value Vmd of the intermediate voltage Vm of each pixel 20 obtained in step S30. The optimum intermediate voltage Vmo is determined (step S31).

  Specifically, in this example, the maximum value is selected from the optimum value Vmd of the intermediate voltage Vm obtained for each pixel 20, and the maximum value is set as the intermediate voltage setting value Vmo. The intermediate voltage setting value Vmo selected in this way becomes a value in the range of the intermediate voltages Vm_s to Vm_max having the characteristics shown in FIG. 13 in all the pixels 20, and the condition of the above expression (1) is satisfied. . In this case, in the complete transfer operation during the normal read operation, the FD unit 26 does not overflow, and the data (pixel signal) corresponding to the charge amount accumulated in the PG 21 can be read accurately.

  Next, the intermediate voltage setting unit 51 records information on the optimum intermediate voltage Vmo determined in step S31 in the storage unit 41 of the solid-state imaging device 40 (step S32). In this embodiment, in this way, the optimum intermediate voltage Vmo at the time of reading is written in the storage unit 41 of the solid-state imaging device 40 before shipment.

  As described above, in the solid-state imaging device 40 of this embodiment, the value of the optimum intermediate voltage Vmo stored in the storage unit 41 is a value that satisfies the condition of the above expression (1) in all the pixels 20. . Therefore, in the present embodiment, in the divided readout type solid-state imaging device 40, the influence of the performance variation of the transfer transistor 22 described above can be reduced, and the image data can be accurately reproduced.

  In addition, since the configuration other than the storage unit 41 of the solid-state imaging device 40 of the present embodiment is the same as the corresponding configuration of the solid-state imaging device 1 of the first embodiment as described above, in the present embodiment, The same effect as the first embodiment can be obtained.

  Note that the method of setting the optimum intermediate voltage Vmo is not limited to the method described above. As shown in FIG. 13, the relationship between the information (output data WDMOF) regarding the intermediate voltage holding charge amount Qc of the PG 21 immediately before the complete transfer operation and the intermediate voltage Vm is obtained, and the optimum intermediate voltage Vmo is obtained based on the relationship. Any technique can be used.

  For example, in the setting method of the optimum intermediate voltage Vmo of this embodiment, an example in which analog CDS processing, AD conversion processing (comparison processing), and digital CDS processing are performed in the intermediate transfer operation (step S23) has been described. It is not limited to this. As described above, the output data is not read in the intermediate transfer operation of the method for setting the optimum intermediate voltage Vmo. Therefore, in the intermediate transfer operation of step S23, after transferring a part of the charge of PG21 to the FD unit 26, the analog CDS processing, AD conversion processing (comparison processing), and digital CDS processing are not performed, and the complete transfer operation (step You may transfer to S24).

  In the setting method of the optimum intermediate voltage Vmo of this embodiment, the initial value of the intermediate voltage Vm is set to the minimum value (Vm_0) of the variable region (step S21), and the intermediate voltage Vm is updated (step S29). Although the example which increases the voltage Vm was demonstrated, this indication is not limited to this. The initial value of the intermediate voltage Vm may be set to the maximum value (Vm_max) of the variable region, and the intermediate voltage Vm may be decreased when the intermediate voltage Vm is updated.

  In the present embodiment, the example in which the intermediate voltage Vm_s corresponding to the lower limit (Qc = Qm) of the above formula (1) is set to the optimum value Vmd of the intermediate voltage Vm of each pixel 20 has been described. It is not limited. For example, a margin may be included in advance in the optimum value Vmd of the intermediate voltage Vm of each pixel 20 in consideration of a change in performance of the transfer transistor 22 due to a change in use environment of the solid-state imaging device 40 or the like. For example, the optimum value Vmd of the intermediate voltage Vm of each pixel 20 may be set to a value higher than Vm_s by the amount corresponding to the performance change of the transfer transistor 22 assumed due to the environmental change or the like. In addition, a margin may be included in advance in the optimum intermediate voltage Vmo of the solid-state imaging device 1 finally obtained in consideration of a change in performance of the transfer transistor 22 due to a change in usage environment of the solid-state imaging device 40 or the like.

  Further, in the present embodiment, the example in which the output data WDMOF obtained during the complete transfer operation is used as the information regarding the intermediate voltage holding charge amount Qc of the PG 21 has been described, but the present disclosure is not limited thereto. For example, the intermediate voltage holding charge amount Qc of PG21 may be calculated from the output data WDMOF obtained during the complete transfer operation, and the optimum intermediate voltage Vmo may be obtained based on the intermediate voltage holding charge amount Qc.

<4. Third Embodiment: Configuration for Feedback Control of Intermediate Voltage>
In the second embodiment, the example in which the optimal intermediate voltage Vmo is measured in advance before shipment and the information is stored in the storage unit 41 of the solid-state imaging device 40 has been described, but the present disclosure is not limited thereto. For example, the intermediate voltage Vm may be optimally controlled in the solid-state imaging device. In the third embodiment, an example of the configuration will be described.

  FIG. 14 illustrates a schematic configuration of a solid-state imaging device according to the third embodiment of the present disclosure. FIG. 14 is a schematic block configuration diagram of the entire solid-state imaging device. Further, in the solid-state imaging device 60 of the present embodiment shown in FIG. 14, the same reference numerals are given to the same configurations as those of the solid-state imaging device 1 of the first embodiment shown in FIG.

  The solid-state imaging device 60 includes a pixel unit 10, a sensor control circuit 11, a vertical scanning circuit 12, and a column processing unit 13. The solid-state imaging device 60 includes a digital processing circuit 14, a reference signal generation circuit 15, an intermediate voltage generation circuit 16, an intermediate voltage measurement pixel unit 61, and an intermediate voltage optimization circuit 62.

  As is clear from a comparison between FIG. 14 and FIG. 2, the configuration of the solid-state imaging device 60 of the present embodiment is the same as that of the solid-state imaging device 1 of the first embodiment, but further includes an intermediate voltage measurement pixel unit 61. The intermediate voltage optimizing circuit 62 is provided. The other configuration is the same as the corresponding configuration in the first embodiment. Therefore, only the configuration of the intermediate voltage measurement pixel unit 61 and the intermediate voltage optimization circuit 62 will be described here.

  The intermediate voltage measuring pixel unit 61 includes a plurality of dedicated pixels (not shown) for feedback control of the intermediate voltage Vm. This dedicated pixel has the same configuration as the normal readout pixel 20.

  The intermediate voltage optimization circuit 62 is a circuit that optimally controls the intermediate voltage Vm. Specifically, the intermediate voltage optimization circuit 62 acquires output data corresponding to the intermediate voltage holding charge amount Qc in the dedicated pixel for feedback control via the digital processing circuit 14. Then, the intermediate voltage optimization circuit 62 performs feedback control on the intermediate voltage Vm so that the output data corresponding to the acquired intermediate voltage holding charge amount Qc becomes a predetermined expected value.

  Note that the configuration for optimally controlling the intermediate voltage Vm in the solid-state imaging device 60 has been proposed in Japanese Patent Application Laid-Open No. 2010-109677 filed by the proposers of the present disclosure prior to the present disclosure. In the present embodiment, feedback control of the intermediate voltage Vm is performed in the same manner as the method proposed in Japanese Patent Laid-Open No. 2010-109677. Here, an outline of the method will be described with reference to FIG. FIG. 15 is a diagram illustrating the data during the feedback control of the intermediate voltage Vm and the flow state of the intermediate voltage Vm. The white arrow in FIG. 15 indicates the flow of control information, and the black arrow indicates the intermediate voltage Vm. The flow of is shown.

  In the solid-state imaging device 60 of this embodiment, first, a predetermined intermediate voltage Vm is applied from the intermediate voltage generation circuit 16 to a predetermined pixel in the intermediate voltage measurement pixel unit 61 via the vertical scanning circuit 12. In this pixel, the intermediate transfer operation and the complete transfer operation are performed in the same manner as the intermediate voltage setting operation described in the second embodiment, and output data corresponding to the intermediate voltage holding charge amount Qc is measured.

  Next, the intermediate voltage optimization circuit 62 acquires output data corresponding to the intermediate voltage holding charge amount Qc measured by the transfer operation via the digital processing circuit 14. Next, the intermediate voltage optimization circuit 62 compares the output data corresponding to the acquired intermediate voltage holding charge amount Qc with a predetermined expected value. Then, based on the comparison result, the intermediate voltage optimization circuit 62 controls the intermediate voltage generation circuit 16 so that the output data corresponding to the intermediate voltage holding charge amount Qc approaches a predetermined expected value. The intermediate voltage Vm applied to a predetermined pixel in the measurement pixel unit 61 is adjusted.

  In the present embodiment, the above-described adjustment operation of the intermediate voltage Vm is repeatedly performed, and feedback control is performed so that the intermediate voltage Vm becomes an optimum value (expected value).

  In the solid-state imaging device 60 of the present embodiment, the intermediate voltage Vm can be optimally controlled by the solid-state imaging device 60 itself even after shipment. Therefore, in the present embodiment, not only the influence of the performance variation of the transfer transistor 22 that occurs in the manufacturing stage, but also the influence of the performance change of the transfer transistor 22 due to a change in use environment or the like can be reduced.

  In addition, the configuration other than the intermediate voltage measurement pixel unit 61 and the intermediate voltage optimization circuit 62 of the solid-state imaging device 60 of the present embodiment corresponds to the configuration of the solid-state imaging device 1 of the first embodiment as described above. Therefore, in this embodiment, the same effect as that of the first embodiment can be obtained.

<5. Various modifications>
The configuration of the solid-state imaging device of the present disclosure is not limited to the configuration described in the above-described various embodiments, and for example, the following various modifications can be considered.

[Modification 1]
In the various embodiments, the example in which the solid-state imaging device 1 is a surface irradiation type solid-state imaging device has been described, but the present disclosure is not limited thereto. The technique of the present disclosure can also be applied to a back-illuminated solid-state imaging device in which light is irradiated from the surface (back surface) opposite to the wiring layer side of the substrate.

  In this case, since the light is incident on the light receiving portion of the PG without passing through the gate electrode, the thickness of the gate electrode of the PG is made as thin as possible as in the above embodiment, or the gate electrode is configured with a transparent electrode. There is no need to do.

[Modification 2]
In the various embodiments described above, an example in which the dual noise canceling method is used as the signal processing method at the time of reading the pixel signal has been described, but the present disclosure is not limited thereto. The technique of the present disclosure can be applied to a solid-state imaging device that performs one of analog CDS processing and digital CDS processing, and similar effects can be obtained.

[Modification 3]
In the above-described various embodiments, the example in which the potential of the gate electrode of PG21 is set to the ground level during complete transfer has been described, but the present disclosure is not limited to this. At the time of complete transfer, any potential can be set as long as the bottom position of the potential of the gate region of PG 21 is a height position of the potential barrier of the transfer transistor 22 or a higher position. That is, the potential of the gate electrode of PG21 at the time of complete transfer is set to an arbitrary potential as long as all charges remaining in PG21 after the intermediate transfer can be transferred to the FD unit 26 at the time of complete transfer. be able to.

  For example, at the time of complete transfer, a small positive potential may be applied to the gate electrode of PG21, or a negative potential may be applied to the gate electrode of PG21.

  When a negative potential is applied to the gate electrode of PG21 at the time of complete transfer, the potential depth of the gate region of PG21 at the time of complete transfer can be made shallower, and all charges remaining in PG21 after intermediate transfer can be more reliably The data can be transferred to the FD unit 26 during complete transfer. That is, in this case, the pixel signal can be read more reliably. In this case, it is necessary to separately provide a negative voltage generation circuit for applying a negative potential to the gate electrode of PG21 in the solid-state imaging device.

[Modification 4]
In the configuration of the solid-state imaging device of the various embodiments, the gate potential of the transfer transistor 22 in each pixel 20 may be set to a negative potential during the blanking period. In this case, for example, the influence of noise generated from the transfer transistor 22 can be reduced. In this case as well, as in Modification 3, it is necessary to separately provide a negative voltage generation circuit for applying a negative voltage to the gate of the transfer transistor 22 in the solid-state imaging device.

[Modification 5]
The technique of the present disclosure described above selects not only the solid-state imaging device that sequentially scans the pixels in the pixel unit in units of rows and reads out the pixel signal from each pixel, but also selects any pixel in the pixel unit. The present invention can also be applied to a solid-state imaging device that reads XY addresses. In addition, the solid-state imaging device described in the above embodiment may be configured as a single chip, or may be configured as an imaging module packaged integrally with a signal processing circuit, an optical system, or the like. .

<6. Configuration of electronic device (application example)>
The solid-state imaging device according to the present disclosure can be applied to various electronic devices. For example, the solid-state imaging device described in the above-described various embodiments and various modifications is an electronic device such as a camera system such as a digital still camera or a digital video camera, a mobile phone having an imaging function, or another device having an imaging function. It can be applied to equipment. Here, a digital video camera will be described as an example of the configuration of the electronic device.

  FIG. 16 shows a schematic configuration of a digital video camera (hereinafter simply referred to as a camera) to which the solid-state imaging device described in the above embodiment is applied.

  The camera 100 includes a solid-state imaging device 101, an optical system 102 that guides incident light to a light receiving unit (not shown) of the solid-state imaging device 101, a shutter device 103 provided between the solid-state imaging device 101 and the optical system 102, And a drive circuit 104 that drives the imaging apparatus 101. The camera 100 further includes a signal processing circuit 105 that processes an output signal of the solid-state imaging device 101.

  The solid-state imaging device 101 is a divided readout type solid-state imaging device, and can be configured by, for example, the solid-state imaging device described in any of the above-described various embodiments and various modifications. Configurations and functions of other parts are as follows.

  The optical system (optical lens) 102 forms image light (incident light) from a subject on an imaging surface (not shown) of the solid-state imaging device 101. Thereby, signal charges are accumulated in the solid-state imaging device 101 for a certain period. The optical system 102 may be configured by an optical lens group including a plurality of optical lenses. Further, the shutter device 103 controls a period during which light is incident on the solid-state imaging device 101 (light irradiation period) and a period during which light incident on the solid-state imaging device 101 is shielded (light-shielding period).

  The drive circuit 104 supplies drive signals to the solid-state imaging device 101 and the shutter device 103. Then, the drive circuit 104 controls the signal transfer operation to the signal processing circuit 105 of the solid-state imaging device 101 and the shutter operation of the shutter device 103 by the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state imaging device 101 to the signal processing circuit 105 is performed by a drive signal (timing signal) supplied from the drive circuit 104.

  The signal processing circuit 105 performs various signal processing on the signal transferred from the solid-state imaging device 101. The signal (video signal) that has been subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or is output to a monitor (not shown).

  In the camera 100 of this embodiment, since the solid-state imaging device described in the above various embodiments or various modifications is used, the influence on the readout performance due to the performance variation of the transfer transistor 22 described above can be reduced, and high image quality can be achieved. Imaging becomes possible.

In addition, this indication can also take the following structures.
(1)
A pixel unit having a plurality of pixels including a photogate, a charge-voltage conversion unit, and a transfer transistor that transfers signal charges accumulated in the photogate to the charge-voltage conversion unit;
In the intermediate transfer operation when the signal charge accumulated in the photogate is read by a predetermined number of intermediate transfer operations and complete transfer operations, an intermediate voltage to be applied to the gate of the transfer transistor is generated, and the intermediate voltage is A solid-state imaging device comprising: an intermediate voltage generation circuit that is applied to a gate electrode of the photogate as a drive voltage for the photogate.
(2)
Furthermore, an analog-digital conversion circuit that converts an analog signal output from the pixel into a digital signal;
First digital output data provided at a subsequent stage of the digital-analog conversion circuit and converted by the analog-digital conversion circuit during the intermediate transfer operation, and second digital data converted by the analog-digital conversion circuit during the complete transfer operation The solid-state imaging device according to (1), further comprising: a digital addition / non-addition circuit that acquires output data and performs addition processing or non-addition processing on the first digital output data and the second digital output data.
(3)
The digital addition / non-addition circuit adds a full count value to the first digital output data and outputs the first digital output data when the first digital output data is larger than a predetermined upper limit threshold value. .
(4)
When at least one of the first digital output data and the first digital output data is smaller than a predetermined lower threshold value, the digital addition / non-addition circuit includes the first digital output data and the first digital output data. The solid-state imaging device according to (2) or (3), wherein the second digital output data is output without adding.
(5)
Further, the first analog output data output from the pixel during the intermediate transfer operation and the second analog output data output from the pixel during the complete transfer operation are provided in a stage preceding the analog-digital conversion circuit. And an analog addition / non-addition circuit that performs addition processing or non-addition processing on the first analog output data and the second analog output data. (2) to (4) Imaging device.
(6)
The solid-state imaging device according to any one of (1) to (5), further including a storage unit that stores information on an optimum value of an intermediate voltage applied to a gate of the transfer transistor during the intermediate transfer operation.
(7)
Furthermore, an intermediate voltage measurement pixel unit including a plurality of pixels for obtaining an optimum value of the intermediate voltage applied to the gate of the transfer transistor during the intermediate transfer operation;
An intermediate voltage optimization circuit that performs feedback control based on output data of the pixel in the intermediate voltage measurement pixel unit so that the intermediate voltage becomes the optimum value. The solid-state imaging device according to item.
(8)
The solid-state imaging device according to any one of (1) to (7), wherein the voltage applied to the gate of the transfer transistor during the blanking period is a negative voltage.
(9)
The solid-state imaging device according to any one of (1) to (8), wherein a gate electrode of the photogate is provided on a surface opposite to a light incident surface of the photogate.
(10)
A pixel portion having a plurality of pixels including a photogate, a charge-voltage converter, and a transfer transistor that transfers the signal charge accumulated in the photogate to the charge-voltage converter; and the signal charge accumulated in the photogate In the intermediate transfer operation at the time of reading by a predetermined number of intermediate transfer operations and complete transfer operations, an intermediate voltage to be applied to the gate of the transfer transistor is generated, and the intermediate voltage is used as a drive voltage for the photogate. A solid-state imaging device having an intermediate voltage generation circuit to be applied to the gate electrode;
An electronic apparatus comprising: a signal processing circuit that performs predetermined processing on an output signal of the solid-state imaging device.

  DESCRIPTION OF SYMBOLS 1,40,60 ... Solid-state imaging device, 10 ... Pixel part, 11 ... Sensor control circuit, 12 ... Vertical scanning circuit, 13 ... Column processing part, 14 ... Digital processing circuit, 15 ... Reference signal generation circuit, 16 ... Intermediate signal Generation circuit, 20... Pixel, 21... Photogate (PG), 22... Transfer transistor, 23... Amplification transistor, 24 .. reset transistor, 25 .. selection transistor, 26 ... floating diffusion (FD) section, 30. DESCRIPTION OF SYMBOLS ... Analog CDS circuit, 41 ... Memory | storage part, 50 ... Inspection apparatus, 51 ... Intermediate voltage setting part, 61 ... Pixel part for intermediate voltage measurement, 62 ... Intermediate voltage optimization circuit

Claims (10)

A pixel unit having a plurality of pixels including a photogate, a charge-voltage conversion unit, and a transfer transistor that transfers signal charges accumulated in the photogate to the charge-voltage conversion unit;
In the intermediate transfer operation when the signal charge accumulated in the photogate is read by a predetermined number of intermediate transfer operations and complete transfer operations, an intermediate voltage to be applied to the gate of the transfer transistor is generated, and the intermediate voltage is A solid-state imaging device comprising: an intermediate voltage generation circuit that applies a photogate drive voltage to the gate electrode of the photogate. Furthermore, an analog-digital conversion circuit that converts an analog signal output from the pixel into a digital signal;
First digital output data provided at a subsequent stage of the digital-analog conversion circuit and converted by the analog-digital conversion circuit during the intermediate transfer operation, and second digital data converted by the analog-digital conversion circuit during the complete transfer operation The solid-state imaging device according to claim 1, further comprising: a digital addition / non-addition circuit that acquires output data and performs addition processing or non-addition processing on the first digital output data and the second digital output data. The solid-state imaging device according to claim 2, wherein the digital addition / non-addition circuit adds a full count value to the first digital output data when the first digital output data is greater than a predetermined upper limit threshold value. . When at least one of the first digital output data and the first digital output data is smaller than a predetermined lower threshold value, the digital addition / non-addition circuit includes the first digital output data and the first digital output data. The solid-state imaging device according to claim 2, wherein the second digital output data is output without adding. Further, the first analog output data output from the pixel during the intermediate transfer operation and the second analog output data output from the pixel during the complete transfer operation are provided in a stage preceding the analog-digital conversion circuit. The solid-state imaging device according to claim 2, further comprising an analog addition / non-addition circuit that performs addition processing or non-addition processing on the first analog output data and the second analog output data. The solid-state imaging device according to claim 1, further comprising a storage unit storing information on an optimum value of an intermediate voltage applied to a gate of the transfer transistor during the intermediate transfer operation. Furthermore, an intermediate voltage measurement pixel unit including a plurality of pixels for obtaining an optimum value of the intermediate voltage applied to the gate of the transfer transistor during the intermediate transfer operation;
The solid-state imaging device according to claim 1, further comprising: an intermediate voltage optimization circuit that performs feedback control so that the intermediate voltage becomes an optimum value based on output data of the pixel in the intermediate voltage measurement pixel unit. The solid-state imaging device according to claim 1, wherein a voltage applied to the gate of the transfer transistor during a blanking period is a negative voltage. The solid-state imaging device according to claim 1, wherein a gate electrode of the photogate is provided on a surface opposite to a light incident surface of the photogate. A pixel portion having a plurality of pixels including a photogate, a charge-voltage converter, and a transfer transistor that transfers the signal charge accumulated in the photogate to the charge-voltage converter; and the signal charge accumulated in the photogate In the intermediate transfer operation at the time of reading by a predetermined number of intermediate transfer operations and complete transfer operations, an intermediate voltage to be applied to the gate of the transfer transistor is generated, and the intermediate voltage is used as a drive voltage for the photogate. A solid-state imaging device having an intermediate voltage generation circuit to be applied to the gate electrode;
An electronic apparatus comprising: a signal processing circuit that performs predetermined processing on an output signal of the solid-state imaging device.

Images