JP6413401B2 - Solid-state image sensor - Google Patents

Description

The present invention relates to a solid-state imaging element

  In Patent Document 1 below, a plurality of pixels, each of which includes at least two pixels including (a) a photodetector, (b) a charge-voltage conversion region that forms a floating capacitance section, and (c) an input section to an amplifier. And a solid-state imaging device including a connection switch that selectively connects the charge-voltage conversion regions.

Special table 2008-546313 gazette

  In the conventional solid-state imaging device, by turning on the connection switch and connecting the charge-voltage conversion regions to each other, the number of saturated electrons in the entire connected charge-voltage conversion region is expanded, so that the dynamic range is increased. Can be enlarged.

  In the conventional solid-state imaging device, the charge-voltage conversion capacity is reduced and the charge-voltage conversion coefficient is increased by turning off the connection switch and separating the charge-voltage conversion region from other charge-voltage conversion regions. Therefore, the SN ratio at the time of high sensitivity reading becomes high.

  However, in the conventional solid-state imaging device, even when the connection switch is turned off, the SN ratio at the time of high-sensitivity readout cannot be increased so much.

  The present invention has been made in view of such circumstances, a solid-state imaging device capable of expanding the dynamic range and improving the SN ratio at the time of high-sensitivity reading, and imaging using the same. An object is to provide an apparatus.

The solid-state imaging device according to the first aspect of the present invention is provided corresponding to one photoelectric conversion unit, a node, and one photoelectric conversion unit, and one transfer that transfers charges from the photoelectric conversion unit to the node. A plurality of pixel blocks each including a switch and a reset switch that resets the potential of the node; and an electrical circuit provided between the node of one pixel block and the node of the other pixel block And a plurality of connection switches per one pixel block provided in the connection portion.
A solid-state imaging device according to a second aspect of the present invention, a plurality of photoelectric conversion units, nodes, and, provided corresponding to said plurality of photoelectric conversion unit, the charge to the node from the previous SL photoelectric conversion unit transfers A plurality of transfer switches , an amplifier connected to the node and outputting a signal corresponding to the potential of the node, and a selector connected to the amplifier and outputting the signal to a signal line. And a plurality of connection switches provided between the nodes of the two pixel blocks among the plurality of pixel blocks .

  ADVANTAGE OF THE INVENTION According to this invention, while being able to expand a dynamic range, the solid-state image sensor which can improve the S / N ratio at the time of highly sensitive reading, and an imaging device using the same can be provided.

1 is a schematic block diagram schematically showing an electronic camera according to a first embodiment of the present invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor in FIG. FIG. 3 is an enlarged circuit diagram illustrating the vicinity of three pixel blocks in FIG. 2. FIG. 4 is a schematic plan view schematically showing the vicinity of three pixel blocks shown in FIG. 3. FIG. 5 is an enlarged schematic plan view showing the vicinity of one pixel block in FIG. 4. 3 is a timing chart showing a predetermined operation mode of the solid-state imaging device shown in FIG. 2. 3 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 2. 6 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2. It is a circuit diagram which shows the vicinity of three pixel blocks of the solid-state image sensor by a comparative example. FIG. 10 is a schematic plan view schematically showing the vicinity of three pixel blocks shown in FIG. 9. It is a circuit diagram which shows the vicinity of three pixel blocks of the solid-state image sensor of the electronic camera by the 2nd Embodiment of this invention. FIG. 12 is a schematic plan view schematically showing the vicinity of three pixel blocks shown in FIG. 11. It is a circuit diagram which shows schematic structure of the solid-state image sensor of the electronic camera by the 3rd Embodiment of this invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor of the electronic camera by the 4th Embodiment of this invention. It is a circuit diagram which expands and shows the vicinity of the four pixel blocks in FIG. It is a timing chart which shows the predetermined operation mode of the solid-state image sensor shown in FIG. 15 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 15 is a timing chart showing still another operation mode of the solid-state imaging element shown in FIG. 15 is a timing chart showing still another operation mode of the solid-state imaging element shown in FIG. 15 is a timing chart showing still another operation mode of the solid-state imaging element shown in FIG. It is a circuit diagram which shows schematic structure of the solid-state image sensor of the electronic camera by the 5th Embodiment of this invention. It is a circuit diagram which shows the vicinity of three pixel blocks of the solid-state image sensor of the electronic camera by the 6th Embodiment of this invention. It is a circuit diagram which expands and shows the vicinity of the four pixel blocks in FIG. It is a timing chart which illustrates a mode that the electric potential of node P (n) is reset. It is a circuit diagram which shows the vicinity of three pixel blocks of the solid-state image sensor of the electronic camera by the 7th Embodiment of this invention. FIG. 26 is a schematic plan view schematically showing the vicinity of three pixel blocks BL shown in FIG. 25. It is a timing chart which shows the 1st operation mode of the solid-state image sensor of the electronic camera by the 7th Embodiment of this invention. It is a timing chart which shows 2A operation mode of the solid-state image sensor of the electronic camera by the 7th Embodiment of this invention. It is a timing chart which shows the 2B operation mode of the solid-state image sensor of the electronic camera by the 7th Embodiment of this invention. It is a timing chart which illustrates a mode that the electric potential of node P (n) is reset.

  Hereinafter, a solid-state imaging device and an imaging apparatus according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic block diagram schematically showing the electronic camera 1 according to the first embodiment of the present invention.

  The electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera. However, the imaging apparatus according to the present invention is not limited to this, and is mounted on another electronic camera such as a compact camera or a mobile phone. The present invention can be applied to various imaging devices such as an electronic camera and an electronic camera such as a video camera that captures moving images.

  A photographing lens 2 is attached to the electronic camera 1. The photographing lens 2 is driven by a lens control unit 3 for focus and diaphragm. In the image space of the photographic lens 2, the imaging surface of the solid-state imaging device 4 is arranged.

  The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. In normal main shooting (during still image shooting) or the like, the imaging control unit 5 performs a predetermined readout operation after exposure with a mechanical shutter (not shown) after, for example, a so-called global reset that resets all pixels simultaneously. The solid-state image sensor 4 is controlled. In the electronic viewfinder mode or moving image shooting, the imaging control unit 5 controls the solid-state imaging device 4 so as to perform a predetermined reading operation while performing a so-called rolling electronic shutter, for example. At these times, as will be described later, the imaging controller 5 controls the solid-state imaging device 4 so as to perform a read operation in each operation mode described later according to the ISO sensitivity setting value. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on the digital image signal output from the solid-state imaging device 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 is also connected with a lens control unit 3, an imaging control unit 5, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12 and an image processing unit 13. An operation unit 14 such as a release button is connected to the CPU 9. The ISO sensitivity can be set by the operation unit 14. A recording medium 11a is detachably attached to the recording unit 11.

  When the CPU 9 in the electronic camera 1 is instructed by the operation unit 14 to operate in the electronic viewfinder mode, moving image shooting, normal normal shooting (still image shooting), or the like, the CPU 9 drives the imaging control unit 5 accordingly. At this time, the lens controller 3 appropriately adjusts the focus and the aperture. The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. A digital image signal from the solid-state imaging device 4 is processed by the digital signal processing unit 6 and then stored in the memory 7. The CPU 9 displays the image signal on the display unit 10 in the electronic viewfinder mode, and records the image signal in the recording medium 11a during moving image shooting. In the case of normal main shooting (during still image shooting) or the like, the CPU 9 processes the digital image signal from the solid-state imaging device 4 by the digital signal processing unit 6 and stores it in the memory 7, and then the operation unit 14. The image processing unit 13 or the image compression unit 12 performs a desired process based on the above command, outputs the processed signal to the recording unit 11 and records it on the recording medium 11a.

  FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 4 in FIG. FIG. 3 is an enlarged circuit diagram showing the vicinity of three pixel blocks BL sequentially arranged in the column direction in FIG. FIG. 4 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. FIG. 5 is an enlarged schematic plan view showing the vicinity of one pixel block BL in FIG. In the present embodiment, the solid-state imaging device 4 is configured as a CMOS type solid-state imaging device, but is not limited thereto, and may be configured as, for example, another XY address type solid-state imaging device.

  As shown in FIGS. 2 to 4, the solid-state imaging device 4 includes a pixel block BL arranged in a two-dimensional matrix in N rows and M columns, each having two pixels PX (PXA, PXB), and one of the pixel blocks BL. The connection transistors SWa and SWb as a plurality of connection switches, the vertical scanning circuit 21, the control lines 22 to 27 provided for each row of the pixel block BL, and the column of the pixel PX (the column of the pixel block BL) A plurality of (M) vertical signal lines 28 that receive signals from the pixels PX (pixel blocks BL) in the corresponding columns provided, and constant current sources 29 provided on the vertical signal lines 28, A column amplifier 30, a CDS circuit (correlated double sampling circuit) 31, an A / D converter 32, and a horizontal readout circuit 33 provided corresponding to the vertical signal line 28 are included.

  The column amplifier 30 may be an analog amplifier or a so-called switched capacitor amplifier. Further, the column amplifier 30 is not necessarily provided.

  For convenience of drawing, FIG. 2 shows M = 2, but the number of columns M is actually a larger arbitrary number. Further, the number N of rows is not limited. When distinguishing the pixel block BL for each row, the pixel block BL in the j-th row is indicated by a symbol BL (j). This also applies to other elements and control signals described later. 2 and 3 show pixel blocks BL (n−1) to BL (n + 1) in the (n−1) th to n + 1th rows over three rows.

  In the drawing, the pixel of the pixel block BL is distinguished from the lower pixel in FIGS. 2 and 3 by PXA and the upper pixel in FIGS. 2 and 3 is PXB. When the description is made without distinction, the description may be made with the reference numeral PX attached to both. In the drawings, the photodiode of the pixel PXA is identified by PDA, and the photodiode of the pixel PXB is identified by PDB. However, when the description is made without distinguishing both, the PD is denoted by PD. May explain. Similarly, the transfer transistor of the pixel PXA is denoted by TXA and the transfer transistor of the pixel PXB is denoted by TXB. The two are distinguished from each other. There is a case. In the present embodiment, the photodiodes PD of the pixels PX are arranged in 2N rows and M columns in a two-dimensional matrix.

  In the present embodiment, each pixel PX includes a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and a transfer transistor as a transfer switch that transfers charges from the photodiode PD to the node P. TX.

  In the present embodiment, the plurality of pixels PX form a pixel block BL for every two pixels PX (PXA, PXB) in which the photodiodes PD are sequentially arranged in the column direction. As shown in FIG. 2 and FIG. 3, for each pixel block BL, two pixels PX (PXA, PXB) belonging to the pixel block BL include one set of node P, amplification transistor AMP, reset transistor RST, and selection. The transistor SEL is shared. A capacitance (charge-voltage conversion capacitance) is formed between the node P and the reference potential, and the electric charge transferred to the node P is converted into a voltage by the capacitance. The amplification transistor AMP constitutes an amplification unit that outputs a signal corresponding to the potential of the node P. The reset transistor RST constitutes a reset switch that resets the potential of the node P. The selection transistor SEL constitutes a selection unit for selecting the pixel block BL. The photodiode PD and the transfer transistor TX are provided for each pixel PX without being shared by the two pixels PX (PXA, PXB). 2 and 3, n indicates a row of the pixel block BL. For example, a pixel block BL in the first row is constituted by the pixel PX (PXA) in the first row and the pixel PX (PXB) in the second row, and the pixel PX (PXA) in the third row and the pixel PX in the fourth row. (PXB) constitutes the pixel block BL in the second row.

  In the present invention, for example, the pixel block BL may be configured for each of three or more pixels PX in which the photodiodes PD are sequentially arranged in the column direction.

  Although not shown in the drawings, in the present embodiment, a plurality of types of color filters that transmit light of different color components are arranged in a predetermined color array on the light incident side of the photodiode PD of each pixel PX. (For example, a Bayer array). The pixel PX outputs an electrical signal corresponding to each color by color separation with a color filter.

  An electrical connection path provided between the node P of one pixel block BL and the node P of the other pixel block BL for each of the two pixel blocks BL adjacent to each other in the column direction among the pixel blocks BL Two connection transistors SWa and SWb as two connection switches are provided in series in a connection path (connection section) that is a connection section (connection section). Thus, in the present embodiment, the nodes P of three or more pixel blocks BL are connected in a daisy chain by the plurality of connection paths (connection portions). Of these two connection transistors SWa and SWb, the connection transistor SWa is arranged on the node P side of the lower pixel block BL in FIGS. 2 and 3, and the connection transistor SWb is the same as FIG. 3 is arranged on the node P side of the upper pixel block BL in FIG.

  For example, an electrical connection path between a node P (n) of the pixel block BL (n) in the nth row and a node P (n + 1) of the pixel block BL in the n + 1th row, and a unique connection path therebetween Inside, two connection transistors SWa (n) and SWb (n) are provided in series. As shown in FIG. 4, the connection transistor SWa (n) is formed in the region of the pixel block BL (n), while the connection transistor SWb (n) is formed in the region of the pixel block BL (n + 1). However, to indicate that these connection transistors SWa (n) and SWb (n) are provided in series in the same unique connection path, the same (n) is appended to the end of the reference numeral. . In the present invention, three or more connection switches may be provided in series in each unique connection path. However, in order to simplify the structure, each unique connection as in the present embodiment. It is preferable to provide two connection transistors SWa and SWb in series in the path.

  2 and 3, VDD is a power supply potential. In the present embodiment, the transistors TXA, TXB, AMP, RST, SEL, SWa, and SWb are all nMOS transistors.

  The gate of the transfer transistor TXA is commonly connected to the control line 26 for each row, and a control signal φTXA is supplied from the vertical scanning circuit 21 to the gate. The gate of the transfer transistor TXB is commonly connected to the control line 25 for each row, and a control signal φTXB is supplied from the vertical scanning circuit 21 to the gate. The gates of the reset transistors RST are commonly connected to the control line 24 for each row, and a control signal φRST is supplied from the vertical scanning circuit 21 there. The gates of the selection transistors SEL are connected in common to the control line 23 for each row, and a control signal φSEL is supplied from the vertical scanning circuit 21 there. The gates of the connection transistors SWa are commonly connected to the control line 22 for each row, and a control signal φSWa is supplied from the vertical scanning circuit 21 there. The gates of the connection transistors SWb are commonly connected to the control line 27 for each row, and a control signal φSWb is supplied from the vertical scanning circuit 21 there. For example, the control signal φTXA (n) is supplied to the gate of the transfer transistor TXA (n), the control signal φTXB (n) is supplied to the gate of the transfer transistor TXB (n), and the gate of the reset transistor RST (n). Is supplied with the control signal φRST (n), the gate of the selection transistor SEL (n) is supplied with the control signal φSEL (n), and the gate of the connection transistor SWa (n) is supplied with the control signal φSWa (n). The control signal φSWb (n) is supplied to the gate of the connection transistor SWb (n).

  Each transistor TXA, TXB, RST, SEL, SWa, SWb is turned on when the corresponding control signal φTXA, φTXB, φRST, φSEL, φSWa, φSWb is at a high level (H), and is at a low level (L). Turn off.

  The vertical scanning circuit 21 outputs control signals φTXA, φTXB, φRST, φSEL, φSWa, and φSWb for each row of the pixel block BL under the control of the imaging control unit 5 in FIG. The transistors SWa and SWb are controlled to realize a still image reading operation, a moving image reading operation, and the like. In this control, for example, a read operation in each operation mode, which will be described later, is performed according to the set value of the ISO sensitivity. By this control, the signal (analog signal) of the pixel PX in the corresponding column is supplied to each vertical signal line 28.

  In the present embodiment, the vertical scanning circuit 21 constitutes a control unit that switches each operation mode to be described later according to a command (control signal) from the imaging control unit 5 in FIG.

  The signal read out to the vertical signal line 28 is amplified by the column amplifier 30 for each column, and further optical signals (signals including optical information photoelectrically converted by the pixels PX) and dark signals (light After being subjected to processing for obtaining a difference from the signal (difference signal including a noise component to be subtracted from the signal), it is converted into a digital signal by the A / D converter 32, and the digital signal is held in the A / D converter 32. Is done. The digital image signal held in each A / D converter 32 is horizontally scanned by a horizontal readout circuit 33, converted into a predetermined signal format as necessary, and externally (digital signal processing unit 6 in FIG. 1). ).

  The CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in FIG. 1, and when φDARKC is at a high level (H), The output signal is sampled as a dark signal, and the optical signal sampling signal φSIGC is received from the timing generation circuit under the control of the imaging control unit 5 in FIG. 1. When φSIGC is H, the output signal of the column amplifier 30 is converted into an optical signal. Sampling as Then, the CDS circuit 31 outputs a signal corresponding to the difference between the sampled dark signal and optical signal based on the clock and pulse from the timing generation circuit. As the configuration of the CDS circuit 31, a known configuration can be adopted.

  Here, the structure of the pixel block BL will be described with reference to FIGS. In practice, a color filter, a microlens, and the like are disposed above the photodiode PD, but are omitted in FIGS. 4 and 5, the layout of the power supply line, the ground line, the control lines 22 to 27, etc. is omitted.

  In the present embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and each element in the pixel block BL such as a photodiode PD is arranged in the P-type well. Yes. In FIG. 5, reference numerals 41 to 49 denote N-type impurity diffusion regions that are part of the above-described transistors. Reference numerals 61 to 67 denote gate electrodes of the respective transistors made of polysilicon. The diffusion regions 42 and 45 are regions to which the power supply voltage VDD is applied by a power supply line (not shown).

  The photodiodes PDA (n) and PDB (n) include an N-type charge storage layer (not shown) provided in the P-type well and a P-type depletion prevention layer (see FIG. It is an embedded photodiode made of (not shown). The photodiodes PDA (n) and PDB (n) photoelectrically convert incident light and store the generated charges in the charge storage layer.

  The transfer transistor TXA (n) is an nMOS transistor having a charge storage layer of the photodiode PDA (n) as a source, a diffusion region 41 as a drain, and a gate electrode 61 as a gate. The transfer transistor TXB (n) is an nMOS transistor having the charge storage layer of the photodiode PDB (n) as a source, the diffusion region 41 as a drain, and the gate electrode 62 as a gate. The diffusion region 41 is provided between the photodiode PDA (n) and the photodiode PDB (n). The diffusion region 41 is also used as a diffusion region serving as the drain of the transfer transistor TXA (n) and a diffusion region serving as the drain of the transfer transistor TXB (n). The gate electrode 61 of the transfer transistor TXA (n) is disposed on the photodiode PDA (n) side of the diffusion region 41. The gate electrode 62 of the transfer transistor TXB (n) is disposed on the photodiode PDB (n) side of the diffusion region 41.

  The amplification transistor AMP (n) is an nMOS transistor having the diffusion region 42 as a drain, the diffusion region 43 as a source, and the gate electrode 63 as a gate. The selection transistor SEL (n) is an nMOS transistor having the diffusion region 43 as a drain, the diffusion region 44 as a source, and the gate electrode 64 as a gate. The diffusion region 44 is connected to the vertical signal line 28. The reset transistor RST (n) is an nMOS transistor having the diffusion region 45 as a drain, the diffusion region 46 as a source, and the gate electrode 65 as a gate.

  The connection transistor SWa (n) is an nMOS transistor having the diffusion region 46 as a source, the diffusion region 47 as a drain, and the gate electrode 66 as a gate. The connection transistor SWb (n−1) is an nMOS transistor having the diffusion region 48 as a drain, the diffusion region 49 as a source, and the gate electrode 67 as a gate.

  The gate electrode 63 and the diffusion regions 41 and 46 of the pixel block BL (n) and the diffusion region 48 of the connection transistor SWb (n−1) are electrically connected to each other by the wiring 71 (n) to be conductive. In this embodiment mode, the node P (n) corresponds to the wiring 71 (n) and the entire portion that is electrically connected to and conductive with the wiring 71 (n).

  The structure of the pixel block BL other than the nth row is the same as the structure of the pixel block BL (n) in the nth row. The structure of the connection transistors SWa other than the connection transistor SWa (n) is the same as that of the connection transistor SWa (n) described above. The structure of the connection transistor SWb other than the connection transistor SWb (n) is the same as the structure of the connection transistor SWb (n) described above.

  And about two connection transistor SWa, SWb provided in series in each said intrinsic | native connection path, between the diffusion region 47 of connection transistor SWa and the diffusion region 49 of connection transistor SWb is connected by the wiring 72. Has been. For example, the diffusion region 47 of the connection transistor SWa (n−1) and the diffusion region 49 of the connection transistor SWb (n−1) are electrically connected by the wiring 72 (n−1). The wiring 72 (n−1) is a connection portion between the connection transistors SWa (n−1) and SWb (n−1) when the connection transistors SWa (n−1) and SWb (n−1) are off. It is composed. The diffusion region 47 of the connection transistor SWa (n) and the diffusion region 49 of the connection transistor SWb (n) are electrically connected by the wiring 72 (n). The wiring 72 (n) forms a connection portion between the connection transistors SWa (n) and SWb (n) when the connection transistors SWa (n) and SWb (n) are off.

  Here, as shown in FIG. 4, the amount of misalignment in the column direction between two connection transistors SWa and SWb provided in series in each of the unique connection paths is Ls, and the column direction of the photodiode PD Is Pg. In the present invention, the relationship between the pitch Pg and the positional deviation Ls is not limited. However, in order to reduce the capacitance value Cfd1 of the capacitance CA described later, it is preferable that pg <Ls <2 × Pg. In the present embodiment, for example, the connection transistor SWb (n−1) is disposed in the vicinity of the connection transistor SWa (n), and the misregistration amount Ls is set to be slightly less than 2 × Pg. The length of (n) is shortened as much as possible, and the capacity value Cfd1 of the capacity CA (n) described later is as small as possible.

  2 to 5, CA (n) is a capacitance between the node P (n) and the reference potential when the connection transistors SWa (n) and SWb (n−1) are off. The capacitance value of the capacitor CA (n) is Cfd1. CB (n) indicates a capacitance between the wiring 72 (n) and the reference potential when the connection transistors SWa (n) and SWb (n) are off. The capacitance value of the capacitor CB (n) is Cfd2. The same applies to the rows of other pixel blocks BL.

  The capacitance CA (n) includes the capacitance of the drain diffusion region 41 of the transfer transistors TXA (n) and TXB (n), the capacitance of the source diffusion region 46 of the reset transistor RST (n), and the source of the connection transistor SWa (n). The capacitance of the diffusion region 46, the capacitance of the drain diffusion region 48 of the connection transistor SWb (n-1), the capacitance of the gate electrode 63 of the amplification transistor AMP (n), and the wiring capacitance of the wiring 71 (n). The sum of these capacitance values is the capacitance value Cfd1 of the capacitance CA (n). The same applies to the rows of other pixel blocks BL.

  Here, the value of the channel capacitance when the connection transistor SWa is on and the value of the channel capacitance when the connection transistor SWb is on are both Csw. Usually, the capacitance value Csw is smaller than the capacitance values Cfd1 and Cfd2.

  Now, paying attention to the pixel block BL (n), both the connection transistors SWa (n) and SWb (n−1) are turned off (that is, the on-state connection transistor of the connection transistors SWa and SWb is a node). P (n) is not electrically connected, and the connection path provided with the connecting transistors SWa and SWb is not electrically connected to the node P (n)). The capacitance (charge voltage conversion capacitance) between the node P (n) and the reference potential is a capacitance CA (n). Therefore, the capacitance value of the charge-voltage conversion capacitor at the node P (n) is Cfd1. This state corresponds to a state of a period T2 in FIG. 6 showing a first operation mode described later.

  Further, focusing on the pixel block BL (n), when the connection transistor SWa (n) is turned on, an on-state connection transistor other than the connection transistor SWa (n) among the connection transistors SWa and SWb is connected to the node P (n). (In this case, specifically, when the coupling transistors SWb (n−1) and SWb (n) are off), the node P (n) and the reference The capacitance between the potential (charge-voltage conversion capacitance) is obtained by adding the capacitance CB (n) and the channel capacitance when the connection transistor SWa (n) is on to the capacitance CA (n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the node P (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2. This state corresponds to a state of a period T2 in FIG. 7 showing a 2A operation mode to be described later.

  Further, paying attention to the pixel block BL (n), when both of the connection transistors SWa (n) and SWb (n) are turned on, of the connection transistors SWa and SWb, other than the connection transistors SWa (n) and SWb (n). If the connected transistors in the ON state are not electrically connected to the node P (n) (here, specifically, the connected transistors SWb (n−1) and SWa (n + 1) are turned off) If so, the charge-voltage conversion capacity of the node P (n) is the capacity CB (n), the channel capacity when the connection transistors SWa (n) and SWb (n) are on, and the capacity CA (n) A capacitor CA (n + 1) is added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the node P (n) is 2 × Cfd1 + Cfd2 + 2 × Csw≈2 × Cfd1 + Cfd2. This state corresponds to a state of a period T2 in FIG. 8 showing a 2B operation mode to be described later.

  Thus, if there is no on-state connected transistor electrically connected to the node P (n) among the connected transistors SWa and SWb, the capacitance value of the charge-voltage conversion capacitance at the node P (n) is minimum. Thus, since the charge-voltage conversion coefficient due to the charge-voltage conversion capacity is increased, reading with the highest S / N ratio is possible.

  On the other hand, if the number of on-state connected transistors electrically connected to the node P (n) among the connected transistors SWa and SWb is increased to one or more desired numbers, the node P (n) Since the capacitance value of the charge-voltage conversion capacitor can be increased to a desired value and a large signal charge amount can be handled, the number of saturated electrons can be increased. Thereby, the dynamic range can be expanded.

  The node P (n) of the pixel block BL (n) has been described above, but the same applies to the nodes P of other pixel blocks BL.

  FIG. 6 is a timing chart showing a first operation mode of the solid-state imaging device 4 shown in FIG. In the first operation mode, each pixel block BL is sequentially selected for each row, and is in an ON state electrically connected to the node P of the selected pixel block BL among the connection transistors SWa and SWb. The transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on sequentially in a state where there is no connected transistor (a state where the charge-voltage conversion capacitance of the node P is minimum), and the selected pixel block BL This is an example of an operation of sequentially reading out the signals of the photodiodes PDA and PDB for each row. In the example illustrated in FIG. 6, signals of all the pixels PXA and PXB are read out. However, the present invention is not limited to this. For example, thinning out reading that reads out pixel rows may be performed. This also applies to each example shown in FIGS. 7 and 8 described later.

  In FIG. 6, the pixel block BL (n-1) in the (n-1) th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the pixels in the (n + 1) th row in the period T3. This shows a situation where the block BL (n + 1) is selected. Since the operation when the pixel block BL of any row is selected is the same, only the operation when the pixel block BL (n) of the n-th row is selected will be described here.

  The exposure of the photodiodes PDA (n) and PDB (n) has already been completed in the predetermined exposure period before the start of the period T2. This exposure is performed by a mechanical shutter (not shown) after a so-called global reset that resets all pixels at the same time during normal main shooting (still image shooting), and during electronic viewfinder mode or movie shooting. This is performed by a so-called rolling electronic shutter operation. Immediately before the start of the period T2, all the transistors SEL, RST, TXA, TXB, SWa, and SWb are turned off.

  In the period T2, φSEL (n) in the nth row is set to H, the selection transistor SEL (n) in the pixel block BL (n) in the nth row is turned on, and the pixel block BL (n) in the nth row is turned on. Selected.

  In the period T2, φSWa (n) and φSWb (n−1) are set to L, and the connection transistors SWa (n) and SWb (n−1) are turned off. Accordingly, in the period T2, there is no on-state coupled transistor electrically connected to the node P (n) of the selected pixel block BL (n) among the coupled transistors SWa and SWb. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor at the node P (n) is Cfd1, which is the minimum.

  For a certain period immediately after the start of the period T2, φRST (n) is set to H, the reset transistor RST (n) in the nth row is once turned on, and the potential of the node P (n) is once reset to the power supply potential VDD. The

  After the time point t1 in the period T2, the dark signal sampling signal φDARKC is set to H for a certain period and the potential appearing at the node P (n) is amplified by the amplification transistor AMP (n) in the nth row, and then the selection transistor The signal amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

  ΦTXA (n) is set to H and the transfer transistor TXA (n) in the n-th row is turned on for a certain period from time t2 thereafter in period T2. As a result, the signal charge accumulated in the photodiode PDA (n) of the pixel block BL (n) in the n-th row is transferred to the charge-voltage conversion capacitor at the node P (n). When the noise component is excluded, the potential of the node P (n) becomes a value proportional to the amount of the signal charge and the inverse of the capacitance value of the charge-voltage conversion capacitor of the node P (n).

  At a subsequent time t3 in the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the node P (n) is amplified by the amplification transistor AMP (n) in the nth row, and then the selection transistor SEL (n ) And the signal further amplified by the column amplifier 30 via the vertical signal line 28 is sampled by the CDS circuit 31 as an optical signal.

  Thereafter, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from time t1 and the optical signal sampled in a certain time from time t3. . The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital signal image signal.

  Then, φRST (n) is set to H for a certain period from the time point t4 in the period T2, the reset transistor RST (n) in the nth row is once turned on, and the potential of the node P (n) is once set to the power supply potential VDD. Reset to.

  After the time t5 in the period T2, the dark signal sampling signal φDARKC is set to H for a certain period, and the potential appearing at the node P (n) is amplified by the n-th amplification transistor AMP (n) and then the selection transistor The signal amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

  ΦTXB (n) is set to H and the transfer transistor TXB (n) in the n-th row is turned on for a certain period from time t6 thereafter in period T2. As a result, the signal charge accumulated in the photodiode PDB (n) of the pixel block BL (n) in the n-th row is transferred to the charge-voltage conversion capacitor at the node P (n). When the noise component is excluded, the potential of the node P (n) becomes a value proportional to the amount of the signal charge and the inverse of the capacitance value of the charge-voltage conversion capacitor of the node P (n).

  At a subsequent time t7 in the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the node P (n) is amplified by the n-th amplification transistor AMP (n) and then the selection transistor SEL (n ) And the signal further amplified by the column amplifier 30 via the vertical signal line 28 is sampled by the CDS circuit 31 as an optical signal.

  Thereafter, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from time t5 and the optical signal sampled in a certain time from time t7. . The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital signal image signal.

  As described above, in the first operation mode, there is no on-state connected transistor electrically connected to the node P of the selected pixel block BL among the connected transistors SWa and SWb. Since the capacitance value of the charge-voltage conversion capacitor at the node P of the pixel block BL is minimized and the charge-voltage conversion coefficient by the charge-voltage conversion capacitor is increased, reading with the highest SN ratio is possible. For example, when the ISO sensitivity setting value is the highest, the imaging control unit 5 instructs to perform the first operation mode.

  FIG. 7 is a timing chart showing the 2A operation mode of the solid-state imaging device 4 shown in FIG. The second A operation mode is one of the second operation modes. In the second operation mode, each pixel block BL is sequentially selected for each row, and one or more predetermined number of on-state connected transistors among the respective connected transistors SWa and SWb are selected. In a state of being electrically connected to the node P of BL, the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on sequentially, and the photodiodes PDA and PDB of the selected pixel block BL are sequentially turned on. It is an example of the operation | movement which reads sequentially this signal for every line. The second A operation mode is an example of an operation in which the predetermined number is one in the second operation mode.

  In FIG. 7, similarly to FIG. 6, the pixel block BL (n−1) in the n−1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the period T3 FIG. 9 shows a situation where the pixel block BL (n + 1) in the (n + 1) th row is selected. The operation mode 2A shown in FIG. 7 is different from the first operation mode shown in FIG. 6 in the following point.

  In the operation mode 2A shown in FIG. 7, in a period T2 in which the pixel block BL (n) in the n-th row is selected, φSWa (n) is set to H and φSWb (n−1) is set to L, The connection transistor SWa (n) is turned on and the connection transistor SWb (n−1) is turned off. As a result, in the period T2, one of the connection transistors SWa and SWb, which is in the on state (here, the connection transistor SWa (n)), is connected to the node P (n ) To be electrically connected. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor at the node P (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2, which is one step larger than that in the first operation mode shown in FIG.

  Here, the period T2 in which the pixel block BL (n) in the n-th row is selected has been described, but the same applies to the period in which another pixel block BL is selected.

  As described above, in the second A operation mode, one of the connection transistors SWa and SWb is electrically connected to the node P of the selected pixel block BL. The capacitance value of the charge-voltage conversion capacitance at the node P of the selected pixel block BL is increased by one level, and the number of saturated electrons in the charge-voltage conversion capacitance at the node P can be increased by one level. Thereby, the dynamic range can be expanded by one step. For example, when the ISO sensitivity setting value is one step smaller than the highest value, the imaging control unit 5 instructs to perform the second A operation mode.

  FIG. 8 is a timing chart showing the 2B operation mode of the solid-state imaging device 4 shown in FIG. The second B operation mode is another operation mode of the second operation modes, and is an operation example in which the predetermined number is two.

  In FIG. 8, similarly to FIGS. 6 and 7, the pixel block BL (n−1) in the n−1th row is selected in the period T1, and the pixel block BL (n) in the nth row is selected in the period T2. In the period T3, the pixel block BL (n + 1) in the (n + 1) th row is selected. The operation mode 2B shown in FIG. 8 is different from the operation mode shown in FIG. 6 and the operation mode shown in FIG.

  In the second B operation mode shown in FIG. 8, φSWa (n) and φSWb (n) are set to H and φSWb (n−1) in the period T2 during which the pixel block BL (n) in the n-th row is selected. , ΦSWa (n + 1) are set to L, the connecting transistors SWa (n) and SWb (n) are turned on, and the connecting transistors SWb (n−1) and SWa (n + 1) are turned off. As a result, in the period T2, two of the connection transistors SWa and SWb in the on state (here, the connection transistors SWa (n) and SWb (n)) are selected by the selected pixel block BL (n). The node P (n) is electrically connected. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor at the node P (n) is 2 × Cfd1 + Cfd2 + 2Csw≈2 × Cfd1 + Cfd2, which is two steps larger than that in the first operation mode shown in FIG.

  Here, the period T2 in which the pixel block BL (n) in the n-th row is selected has been described, but the same applies to the period in which another pixel block BL is selected.

  As described above, in the second B operation mode, two of the connection transistors SWa and SWb are electrically connected to the node P of the selected pixel block BL. The capacitance value of the charge-voltage conversion capacitance at the node P of the selected pixel block BL is increased by two levels, and the number of saturated electrons in the charge-voltage conversion capacitance at the node P can be increased by two levels. Thereby, the dynamic range can be expanded by two stages. For example, when the ISO sensitivity setting value is a value that is two steps smaller than the highest value, the imaging control unit 5 instructs to perform the second B operation mode.

  In the second operation mode, the predetermined number may be three or more.

  Here, a solid-state image sensor according to a comparative example compared with the solid-state image sensor 4 in the present embodiment will be described. FIG. 9 is a circuit diagram showing the vicinity of the three pixel blocks BL of the solid-state imaging device according to this comparative example, and corresponds to FIG. FIG. 10 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 9, and corresponds to FIG. 4 and FIG. 9 and 10, elements that are the same as or correspond to those in FIGS. 3, 4, and 5 are assigned the same reference numerals, and redundant descriptions thereof are omitted. In FIG. 10, reference numerals are not assigned to the diffusion regions and the gate electrodes. However, since these reference numerals are the same as those in FIG. 5, refer to FIG.

  This comparative example is different from the present embodiment in that each connection transistor SWb is removed, and the removed connection transistor SWb is short-circuited by the wiring 171 including the wirings 71 and 72. . For example, in this embodiment, the connection transistor SWb (n−1) is removed, and the gate electrode of the pixel block BL (n) is formed by the wiring 171 (n) including the wirings 71 (n) and 72 (n−1). 63, the diffusion regions 41 and 46, and the diffusion region 47 of the connection transistor SWa (n-1) are electrically connected to each other and are conductive.

  9 and 10, CAB (n) is a capacitance between the node P (n) and the reference potential when the connection transistors SWa (n) and SWa (n−1) are off. Let Cfd be the capacitance value of the capacitor CAB (n). The same applies to the rows of other pixel blocks BL.

  The capacitor CAB (n) includes the capacitance of the drain diffusion region 41 of the transfer transistors TXA (n) and TXB (n), the source diffusion region 46 of the reset transistor RST (n), and the source diffusion region of the connection transistor SWa (n). 46, the capacitance of the drain diffusion region 47 of the connection transistor SWa (n-1), the capacitance of the gate electrode 63 of the amplification transistor AMP (n), and the wiring capacitance of the wiring 171 (n). The sum of the values becomes the capacitance value Cfd of the capacitor CAB (n). The same applies to the rows of other pixel blocks BL.

  The wiring capacity of the wiring 171 (n) is substantially equal to the sum of the wiring capacity (floating capacity) of the wiring 71 (n) and the wiring capacity of the wiring 171 (n). Therefore, the capacitance value Cfd of the capacitance CAB (n) is substantially equal to the sum of the capacitance value Cfd1 of the capacitance CA (n) and the capacitance value Cfd2 of the capacitance CB (n) in the present embodiment, and Cfd≈Cfd1 + Cfd2 It becomes.

  In this comparative example, paying attention to the pixel block BL (n), when both of the coupling transistors SWa (n) and SWa (n−1) are turned off, the charge-voltage conversion capacitance of the node P (n) is the capacitance CAB ( n). Therefore, the capacitance value of the charge-voltage conversion capacitor at the node P (n) is Cfd, which is the minimum in the comparative example, and the charge-voltage conversion coefficient due to the charge-voltage conversion capacitor is large. Can be read.

  In this comparative example, paying attention to the pixel block BL (n), one or more predetermined number of connected transistors of each of the connected transistors SWa are electrically connected to the node P (n). In this state, the capacitance value of the charge-voltage conversion capacitor at the node P (n) increases in accordance with the number of connected transistors in the on state, and the number of saturated electrons can be increased. Thereby, the dynamic range can be expanded.

  However, in this comparative example, the capacitance value of the charge-voltage conversion capacitor at the node P (n) cannot be made smaller than Cfd≈Cfd1 + Cfd2. Therefore, according to this comparative example, the charge-voltage conversion coefficient cannot be increased so much and cannot be read out with a very high SN ratio.

  On the other hand, according to the present embodiment, since the connection transistor SWb is added, as described above, the minimum capacitance value of the charge-voltage conversion capacitance of the node P (n) is set to Cfd1≈Cfd−Cfd2. And can be made smaller than the comparative example.

  Therefore, according to the present embodiment, the dynamic range can be expanded, and the SN ratio at the time of high-sensitivity reading can be improved as compared with the comparative example.

  In the present embodiment, the connection transistors SWa and SWb are provided between all two nodes P that are sequentially adjacent in the column direction. However, the present invention is not limited to this. For example, the connection transistors SWa and SWb are not provided between every q nodes (q is an integer of 2 or more) arranged in the column direction and a node P adjacent to the lower side in the figure with respect to the node P. You may always leave it open. In this case, the smaller the number of q, the smaller the maximum number of the predetermined number in the second operation mode and the degree of expansion of the dynamic range decreases. However, the SN at the time of high-sensitivity reading compared to the comparative example is reduced. The ratio can be improved.

  Each of the operation examples described with reference to FIGS. 6 to 8 is an example of an operation of reading the signal charge of the photodiode PD of each pixel PX without mixing with the signal charge of the photodiode PD of another pixel PX. Met. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be mixed and read with the signal charge of the photodiode PD of another pixel PX of the same color.

  For example, the connection transistors SWa (n−1), SWb (n−1), SWa (n), and SWb (n) are turned on to connect the nodes P (n−1), P (n), and P (n + 1) to each other. When connected and TXA (n−1), TXA (n), TXA (n + 1) are turned on at the same time, three pixels PXA (n−1), PXA (n) of the same color when a Bayer array or the like is assumed , PXA (n−1) photodiodes PDA (n−1), PDA (n), PDA (n−1) signal charges of nodes P (n−1), P (n), P It is averaged by (n + 1), and the same color three-pixel mixed readout function can be realized. At this time, the coupling transistors SWb (n−2) and SWa (n + 1) are turned off, and the on-state coupling is electrically connected to the nodes P (n−1), P (n) and P (n + 1). By minimizing the number of transistors, the charge-voltage conversion capacitance values at the connected nodes P (n−1), P (n), and P (n + 1) are minimized, and the same color three-pixel mixing is performed with the highest SN ratio. Reading can be performed. On the other hand, in addition to the connected transistors SWa (n−1), SWb (n−1), SWa (n), and SWb (n), one or more connected transistors are connected to the nodes P (n−1), P When electrically connected to (n) and P (n + 1), the charges at the connected nodes P (n−1), P (n), and P (n + 1) according to the number thereof The voltage conversion capacitance value increases, and the dynamic range of the same color three-pixel mixed readout can be expanded.

[Second Embodiment]
FIG. 11 is a circuit diagram showing the vicinity of the three pixel blocks BL of the solid-state imaging device of the electronic camera according to the second embodiment of the present invention, and corresponds to FIG. FIG. 12 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 9 and corresponds to FIG. 4 and FIG. 11 and 12, elements that are the same as or correspond to those in FIGS. 3, 4, and 5 are denoted by the same reference numerals, and redundant description thereof is omitted.

  The present embodiment differs from the first embodiment in that an adjustment capacitor CB ′ having a capacitance value Cfd3 is added to each wiring 72. Since the capacitor CB (n) is a capacitor between the wiring 72 (n) and the reference potential when the coupling transistors SWa (n) and SWb (n) are off, the adjustment capacitor CB ′ (n) Is included in the capacitance CB (n), but the adjustment capacitance CB ′ adds a capacitance value Cfd3 to the configuration forming the capacitance value Cfd2 of the capacitance CB (n) in the first embodiment. In order to clearly indicate that it is a component, in FIG. 11 and FIG. 12, the adjustment capacitor CB ′ is shown separately from the capacitor CB (n). In the first embodiment, the capacitance value of the capacitor CB (n) is Cfd2, whereas in this embodiment, the capacitance value of the capacitor CB (n) is Cfd2 + Cfd3. The same applies to the other capacitors CB, the wiring 72, and the adjustment capacitor CB '.

  According to the present embodiment, the same advantages as those of the first embodiment can be obtained, and the capacitance value of the capacitor CB can be set to an arbitrary desired capacitance value by providing the adjustment capacitor CB ′. it can.

  Specifically, the adjustment capacitor CB ′ has, for example, (i) the area of the wiring 72 by making at least a part of the wiring width of the wiring 72 wider than the wiring width of the other wiring in the pixel block BL. To be larger than the area of the wiring 72 in the first embodiment, (ii) connecting a MOS capacitor to the wiring 72, (iii) connecting a diffusion capacitor that does not constitute the coupling transistors SWa and SWb, (Iv) making the area of the drain diffusion region 47 of the coupling transistor SWa larger than the area of the drain diffusion region 47 in the first embodiment, and (v) making the area of the source diffusion region 49 of the coupling transistor SWb the first. The area of the source diffusion region 49 in one embodiment may be larger than that of the source diffusion region 49, or one or more of them may be combined.

  Here, an example of setting the capacitance value Cfd3 of the adjustment capacitor CB 'will be described. It is desirable that the capacitance value of the charge-voltage conversion capacitance of the node P is an integral multiple of the reference capacitance value. However, in the structure of the first embodiment described above, when the adjustment capacitor CB ′ is not added, the capacitance value Cfd2 of the capacitor CB is generally smaller than the capacitance value Cfd1 of the capacitor CA. Therefore, for example, in order to double the capacitance value of the charge-voltage conversion capacitance of the node P (n) to the reference capacitance value, the connection transistors SWa (n) and SWb (n) are turned on and the node P (n ) Is set to 2 × Cfd1 + Cfd2 + 2 × Csw, and two pixel blocks BL (n) and BL (n + 1) are used.

  On the other hand, in the present embodiment, when the adjustment capacitor CB ′ is formed so that the capacitance value Cfd3 of the adjustment capacitor CB ′ becomes Cfd1−Cfd2, the capacitance value of the capacitor CB becomes cfd2 + Cfd3 = Cfd1. Therefore, in order to make the capacitance value of the charge-voltage conversion capacitance of the node P (n) twice the reference capacitance value, it is only necessary to turn on the connection transistor SWa (n), and one pixel block BL (n) Just use it. Further, when handling a larger amount of saturated charge, the number of connected pixel blocks BL can be greatly reduced.

  Such a setting example of the capacitance value Cfd3 of the adjustment capacitor CB 'is merely an example, and is not limited thereto.

  In order to bring the capacitance value of the charge-voltage conversion capacitance of the node P closer to an integral multiple of the reference dose value, the capacitance value of the capacitance CB is a value within a range of ± 20% with respect to the capacitance value of the capacitance CA. Preferably, the value is within a range of ± 10% with respect to the capacity value of the capacity CA.

[Third Embodiment]
FIG. 13 is a circuit diagram showing a schematic configuration of the solid-state imaging device 84 of the electronic camera according to the third embodiment of the present invention, and corresponds to FIG. 13, elements that are the same as or correspond to those in FIG. 2 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The present embodiment is different from the first embodiment in that the photodiode PDB and the transfer transistor TXB are removed from each pixel block BL in the first embodiment. The pixel block BL is a pixel PXA. However, in the present embodiment, the density in the column direction of the photodiode PDA is set to be twice the density in the column direction of the photodiode PDA in the first embodiment, and the photodiode in the first embodiment. The density in the column direction of the entire PDA and PDB is the same. In the present embodiment, n indicates the row of the pixel block BL and simultaneously indicates the row of the pixel PXA.

  In other words, in the first embodiment, each pixel block BL is composed of two pixels PX (PXA, PXB), whereas in this embodiment, each pixel block BL is one. Pixel PX (PXA). In the first embodiment, two pixels PX (PXA, PXB) belonging to the pixel block BL share one set of node P, amplification transistor AMP, reset transistor RST, and selection transistor SEL. On the other hand, in the present embodiment, each pixel PX (in the present embodiment, only PXA) has one set of node P, amplification transistor AMP, reset transistor RST, and selection transistor SEL.

  Basically, the description of the first embodiment is applicable as the description of the present embodiment by replacing the pixel block BL with the pixel PXA. Therefore, detailed description of this embodiment is omitted here.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained.

  In the present invention, a modification similar to that obtained by modifying the first embodiment may be applied to the second embodiment.

[Fourth Embodiment]
FIG. 14 is a circuit diagram showing a schematic configuration of a solid-state image sensor 94 of an electronic camera according to the fourth embodiment of the present invention, and corresponds to FIG. FIG. 15 is an enlarged circuit diagram showing the vicinity of four pixel blocks BL sequentially arranged in the column direction in FIG. 14, and corresponds to FIG. 14 and 15, elements that are the same as or correspond to those in FIGS. 2 and 3 are given the same reference numerals, and redundant descriptions thereof are omitted. This embodiment is different from the first embodiment in the points described below.

  In the present embodiment, in the first embodiment, the first connection transistor SWa, the second connection transistor SWb, and the wirings 71 and 72 are removed, and instead, the first node Pa and the corresponding one. The first switch SWA as a first switch unit that electrically connects and disconnects between the second node Pb and the second switch that electrically connects and disconnects between the two second nodes Pb A second transistor SWB as a part and wirings 97 and 98 are provided.

  The first node Pa (n) of the pixel block BL (n) corresponds to the node P (n) in the first embodiment. The transfer transistor TXA (n) transfers charges from the photodiode PDA (n) to the first node Pa (n), and the transfer transistor TXB (n) transfers from the photodiode PDB (n) to the first node Pa (n). ) To transfer the charge. A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa (n) and the reference potential, and the charge transferred to the first node Pa (n) is converted into a voltage by the capacitance. The The amplification transistor AMP (n) outputs a signal corresponding to the potential of the first node Pa (n). The reset transistor RST (n) resets the potential of the first node Pa (n). The same applies to the rows of other pixel blocks BL.

  The first transistor SWA (n) constitutes a first switch unit that electrically connects and disconnects between the first node Pa (n) and the corresponding second node Pb (n). ing. Such a first switch unit can be configured by combining a plurality of switches such as transistors, but in order to simplify the structure, a single first transistor SWA is used as in the present embodiment. (N) is preferable. The same applies to the other first transistors SWA.

  Each second transistor SWB includes a second node Pb corresponding to the first node Pa of the one pixel block BL and the other of the two pixel blocks BL adjacent to each other in the column direction among the pixel blocks BL. The second switch unit is configured to be electrically connected to and disconnected from the second node Pb corresponding to the first node Pa of the pixel block BL. Thus, in the present embodiment, the first nodes Pa of three or more pixel blocks BL are connected in a daisy chain by a plurality of the second switch portions. The second switch portion as described above can be configured by combining a plurality of switches such as a plurality of transistors. However, in order to simplify the structure, a single second transistor is used as in the present embodiment. It is preferable to use SWB.

  For example, the second transistor SWB (n) includes the second node Pb (n) corresponding to the first node Pa (n) of the pixel block BL (n) in the nth row and the pixel in the n−1th row. The block BL (n−1) is provided so as to be electrically connected to and disconnected from the second node Pb (n−1) corresponding to the first node Pa (n−1) of the block BL (n−1). This also applies to the other second transistors SWB.

  The gate electrode of the amplification transistor AMP (n) of the pixel block BL (n), the source region of the reset transistor RST (n), the drain diffusion region of the transfer transistors TXA (n) and TXB (n), and the first transistor SWA The source diffusion regions (n) are electrically connected to each other by the wiring 97 (n) to be conductive. The first node Pa (n) corresponds to the wiring 97 (n) and the entire portion that is electrically connected to and conductive with the wiring 97 (n). The same applies to the rows of other pixel blocks BL.

  The wiring 98 (n) electrically connects the drain diffusion region of the first transistor SWA (n), the drain diffusion region of the second transistor SWB (n), and the source diffusion region of the second transistor SWB (n + 1). Connected and conducting. The second node Pb (n) corresponds to the wiring 98 (n) and the entire portion that is electrically connected to and conductive with the wiring 98 (n). The same applies to other first transistors SWA and other second transistors SWB.

  The gate of the first transistor SWA is commonly connected to the control line 95 for each row, and a control signal φSWA is supplied from the vertical scanning circuit 21 to the gate. The gates of the second transistors SWB are commonly connected to the control line 96 for each row, and a control signal φSWB is supplied from the vertical scanning circuit 21 there.

  14 and 15, CC (n) is a capacitance between the first node Pa (n) and the reference potential when the first transistor SWA (n) is off. Let Cfd1 'be the capacitance value of the capacitor CC (n). CD (n) is a capacitance between the wiring 98 (n) and the reference potential when the first transistor SWA (n) and the second transistors SWB (n) and SWB (n + 1) are off. is there. The capacitance value of the capacitor CD (n) is Cfd2 '. The same applies to other first transistors SWA and other second transistors SWB.

  The capacitance CC (n) includes the capacitance of the drain diffusion region of the transfer transistors TXA (n) and TXB (n), the capacitance of the source diffusion region of the reset transistor RST (n), and the source of the first transistor SWA (n). The capacitance of the diffusion region, the capacitance of the gate electrode of the amplification transistor AMP (n), and the wiring capacitance of the wiring 97 (n) are composed of the capacitance value Cfd1 ′ of the capacitance CC (n). Become. The same applies to the rows of other pixel blocks BL.

  Note that the capacitance of the source diffusion region of the second transistor SWB (n) does not become a component of the capacitor CC (n), and accordingly, the capacitance value Cfd1 'of the capacitor CC (n) is reduced. In this regard, in the first embodiment, not only the capacitance of the source diffusion region 46 of the coupling transistor SWa (n) but also the capacitance of the drain diffusion region 48 of the coupling transistor SWb (n−1) is a component of the capacitance CB. Therefore, the capacitance value Cfd1 of the capacitor CB increases accordingly. That is, the capacitance value Cfd1 'in this embodiment is smaller than the capacitance value Cfd1 in the first embodiment by one transistor diffusion capacitor.

  Here, the value of the channel capacitance when the first transistor SWA is on and the value of the channel capacitance when the second transistor SWB is on are both Csw. Usually, the capacitance value Csw is smaller than the capacitance values Cfd1 'and Cfd2'.

  Now, paying attention to the pixel block BL (n), the first transistor SWA (n) is turned off (that is, the on-state transistor among the first transistors SWA and the second transistors SWB is the first one). And a capacitance (charge-voltage conversion capacitance) between the first node Pa (n) and the reference potential is a capacitance CC (n). It becomes. Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa (n) is Cfd1 ′. This state corresponds to a state of a period T2 in FIG. 16 showing a first operation mode described later.

  When the first transistor SWA (n) is turned on by focusing on the pixel block BL (n), the first transistor SWA and the second transistor SWB other than the first transistor SWA (n) are turned on. Are not electrically connected to the first node Pa (n) (here, specifically, the second transistors SWB (n), SWB (n + 1) Is off), the capacitance (charge-voltage conversion capacitance) between the first node Pa (n) and the reference potential is the capacitance CD (n) and the first transistor with respect to the capacitance CC (n). The channel capacity when SWA (n) is turned on is added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 ′ + Cfd2 ′ + Csw≈Cfd1 ′ + Cfd2 ′. This state corresponds to a state of a period T2 in FIG. 17 showing a 2A operation mode to be described later.

  Further, paying attention to the pixel block BL (n), when the first transistor SWA (n) and the second transistor SWB (n + 1) are turned on, among the first transistors SWA and the second transistors SWB, If the transistors other than the transistors SWA (n) and SWB (n + 1) are not electrically connected to the first node Pa (n) (here, specifically, the transistor SWB). (If (n), SWA (n + 1), SWB (n + 2) are off), the charge-voltage conversion capacitance of the first node Pa (n) is the capacitance CD (n), The capacitance CD (n + 1) and the channel capacitance when the transistors SWA (n) and SWB (n + 1) are turned on are added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 ′ + 2 × Cfd2 ′ + 2 × Csw≈Cfd1 ′ + 2 × Cfd2 ′. This state corresponds to a state of a period T2 in FIG. 18 showing a second B operation mode described later.

  Furthermore, paying attention to the pixel block BL (n), when the first transistors SWA (n), SWA (n + 1) and the second transistor SWB (n + 1) are turned on, the first transistors SWA and the second transistors SWA (n + 1) are turned on. Of the transistors SWB, transistors other than the transistors SWA (n), SWA (n + 1), and SWB (n + 1) must be in an electrically connected state with respect to the first node Pa (n). Here, specifically, if the transistors SWB (n) and SWB (n + 2) are off), the charge-voltage conversion capacitance of the first node Pa (n) is relative to the capacitance CC (n). Capacitance CD (n), capacitance CD (n + 1), capacitance CC (n + 1) and channel capacitance when the transistors SWA (n), SWA (n + 1) and SWB (n + 1) are turned on are added. The things. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is 2 × Cfd1 ′ + 2 × Cfd2 ′ + 3 × Csw≈2 × Cfd1 ′ + 2 × Cfd2 ′. This state corresponds to a state of a period T2 in FIG. 19 showing a 2C operation mode described later.

  Further, focusing on the pixel block BL (n), when the first transistor SWA (n) and the second transistors SWB (n + 1) and SWB (n + 2) are turned on, the first transistors SWA and the second transistors SWB (n + 1) and SWB (n + 2) are turned on. Of the transistors SWB, transistors in the on state other than the transistors SWA (n), SWB (n + 1), and SWB (n + 2) are not electrically connected to the first node Pa (n) ( Here, specifically, if the transistors SWA (n + 1), SWA (n + 2), SWB (n), and SWB (n + 3) are off), the charge-voltage conversion capacity of the first node Pa (n) is For the capacitor CC (n), the capacitor CD (n), the capacitor CD (n + 1), the capacitor CD (n + 2), and the transistors SWA (n), SWB (n + 1), SWB (n + 2) The obtained by adding the channel capacity when on. Accordingly, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 ′ + 3 × Cfd2 ′ + 3 × Csw≈Cfd1 ′ + 3 × Cfd2 ′. This state corresponds to a state of a period T2 in FIG. 20 showing a 2C operation mode to be described later.

  As described above, if there is no on-state transistor electrically connected to the first node Pa (n) among the first transistors SWA and the second transistors SWB, the first node Pa ( The capacitance value of the charge-voltage conversion capacitor in (n) becomes the minimum capacitance value Cfd1 ′, and the charge-voltage conversion coefficient by the charge-voltage conversion capacitor increases, so that reading with the highest SN ratio becomes possible. As described above, since the capacitance value Cfd1 ′ is smaller than the minimum capacitance value Cfd1 in the first embodiment by one transistor diffusion capacitor, according to this embodiment, the first value Compared to the embodiment, the charge-voltage conversion coefficient is further increased, and reading at a higher SN ratio is possible.

  On the other hand, among the first transistors SWA and the second transistors SWB, the number of ON-state transistors electrically connected to the first node Pa (n) is increased to one or more desired numbers. If so, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) can be increased to a desired value and a large amount of signal charge can be handled, so that the number of saturated electrons can be increased. it can. Thereby, the dynamic range can be expanded.

  The first node Pa (n) of the pixel block BL (n) has been described above, but the same applies to the first nodes Pa of other pixel blocks BL.

  FIG. 16 is a timing chart showing a first operation mode of the solid-state imaging element 94 shown in FIG. In the first operation mode, each pixel block BL is sequentially selected for each row, and the first node Pa of the selected pixel block BL among the first transistors SWA and the second transistors SWB is applied to the first node Pa. The transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected in a state where there is no on-state transistor electrically connected to the transistor (a state where the charge-voltage conversion capacitance of the first node Pa is minimum). This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read for each row. In the example illustrated in FIG. 16, signals of all the pixels PXA and PXB are read out. However, the present invention is not limited to this. For example, thinning out reading that reads out pixel rows may be performed. This also applies to each example shown in FIGS. 17 to 20 described later.

  Since the operation in the first operation mode shown in FIG. 16 is clear from the above description, the detailed description thereof is omitted.

  FIG. 17 is a timing chart showing the 2A operation mode of the solid-state imaging device 94 shown in FIG. The second A operation mode is one of the second operation modes. In the second operation mode, each pixel block BL is sequentially selected for each row, and one or more predetermined numbers of ON transistors among the first transistors SWA and the second transistors SWB are provided. The transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on in order while being electrically connected to the first node Pa of the selected pixel block BL. This is an example of the operation of sequentially reading out the signals of the photodiodes PDA and PDB of the block BL for each row. The second A operation mode is an example of an operation in which the predetermined number is one (one of the first transistors SWA) in the second operation mode.

  Since the operation in the operation mode 2A shown in FIG. 17 is clear from the above description, the detailed description thereof is omitted.

  FIG. 18 is a timing chart showing the 2B operation mode of the solid-state imaging element 94 shown in FIG. The second B operation mode is another operation mode of the second operation mode, and the predetermined number is two (one first transistor SWA and one second transistor SWB). This is an example of operation. Since the operation in the operation mode 2B shown in FIG. 18 is clear from the above description, the detailed description thereof is omitted.

  FIG. 19 is a timing chart showing the 2C operation mode of the solid-state imaging device 94 shown in FIG. The second C operation mode is another one of the second operation modes, and the predetermined number is three (two of the first transistors SWA and one of the second transistors SWB). This is an example of operation. Since the operation in the operation mode 2C shown in FIG. 19 is apparent from the above description, the detailed description thereof is omitted.

  FIG. 20 is a timing chart showing a 2D operation mode of the solid-state imaging device 94 shown in FIG. The second D operation mode is another one of the second operation modes, and the predetermined number is three (one of the first transistor SWA and two of the second transistors SWB). This is an example of operation. Since the operation in the 2D operation mode shown in FIG. 20 is apparent from the above description, the detailed description thereof is omitted.

  According to the present embodiment, the dynamic range can be expanded as in the first embodiment, and the SN ratio at the time of high-sensitivity reading can be improved as compared with the comparative example. In addition, according to the present embodiment, the charge-voltage conversion coefficient is further increased as compared with the first embodiment, and high-sensitivity readout with an even higher SN ratio is possible.

  In the present embodiment, the second transistor SWB is provided between all the two second nodes Pb sequentially adjacent in the column direction. However, the present invention is not necessarily limited to this. For example, between r second nodes Pb arranged in the column direction (r is an integer of 2 or more) and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb, The second transistor SWB may be left open without being provided. In this case, the smaller the number of r, the smaller the maximum number of the predetermined number in the second operation mode and the degree of expansion of the dynamic range decreases. However, the SN at the time of high-sensitivity reading compared to the comparative example is reduced. The ratio can be improved. Further, for example, between s second nodes Pb arranged in the column direction (s is an integer of 1 or more) and a second node Pb adjacent to the second node Pb on the lower side in the figure. May be short-circuited electrically without providing the second transistor SWB. Further, for example, between u second nodes Pb arranged in the column direction (u is an integer of 1 or more) and a second node Pb adjacent to the second node Pb on the lower side in the figure. Only the second transistor SWB is provided, while the second node Pb other than u pieces arranged in the column direction and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb are provided. You may short-circuit electrically.

  As in the second embodiment, an adjustment capacitor may be provided for the wiring 98 in this embodiment. Also in the present embodiment, the capacitance value of the capacitor CD may be a value within a range of ± 20% with respect to the capacitance value of the capacitor CC, or ± 10% with respect to the capacitance value of the capacitor CC. It may be a value within the range. These points are the same in the fifth embodiment described later.

  Each of the operation examples illustrated in FIGS. 16 to 20 is an example of an operation of reading the signal charge of the photodiode PD of each pixel PX without mixing with the signal charge of the photodiode PD of the other pixel PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be mixed and read with the signal charge of the photodiode PD of another pixel PX of the same color.

  For example, the first transistor SWA (n−1), SWA (n), SWA (n + 1) and the second transistor SWB (n), SWB (n + 1) are turned on and the first node Pa (n−1) is turned on. , Pa (n), Pa (n + 1) are connected to each other, and TXA (n-1), TXA (n), TXA (n + 1) are turned on at the same time, the three of the same color in the case of assuming the Bayer arrangement etc. First signal charges of the photodiodes PDA (n−1), PDA (n), and PDA (n−1) of the pixels PXA (n−1), PXA (n), and PXA (n−1) are connected to each other. The nodes Pa (n−1), Pa (n), and Pa (n + 1) are averaged, and the same color three-pixel mixed readout function can be realized. At this time, the second transistors SWB (n−2) and SWB (n + 2) are turned off and are electrically connected to the first nodes Pa (n−1), Pa (n) and Pa (n + 1). The charge-voltage conversion capacitance value at the connected first nodes Pa (n−1), Pa (n), Pa (n + 1) by minimizing the number of first or second transistors in the ON state And the same color three-pixel mixed readout can be performed with the highest SN ratio. On the other hand, in addition to the first transistors SWA (n−1), SWA (n), SWA (n + 1) and the second transistors SWB (n), SWB (n + 1), each first transistor SWA and each second transistor If one or more of the transistors SWB are electrically connected to the first nodes Pa (n−1), Pa (n), Pa (n + 1), Depending on the number, the charge-voltage conversion capacitance value at the connected first nodes Pa (n−1), Pa (n), Pa (n + 1) increases, and the dynamic range of the same color three-pixel mixed readout is expanded. Can do.

[Fifth Embodiment]
FIG. 21 is a circuit diagram showing a schematic configuration of the solid-state imaging device 104 of the electronic camera according to the fifth embodiment of the present invention, and corresponds to FIG. In FIG. 21, elements that are the same as or correspond to elements in FIG. 14 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The difference between the present embodiment and the fourth embodiment is that, in the present embodiment, the photodiode PDB and the transfer transistor TXB are removed from each pixel block BL in the fourth embodiment. The pixel block BL is a pixel PXA. However, in the present embodiment, the density in the column direction of the photodiode PDA is twice the density in the column direction of the photodiode PDA in the fourth embodiment, and the photodiode in the fourth embodiment is The density in the column direction of the entire PDA and PDB is the same. In the present embodiment, n indicates the row of the pixel block BL and simultaneously indicates the row of the pixel PXA.

  In other words, in the fourth embodiment, each pixel block BL is composed of two pixels PX (PXA, PXB), whereas in this embodiment, each pixel block BL is one. Pixel PX (PXA). In the fourth embodiment, two pixels PX (PXA, PXB) belonging to the pixel block BL share one set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL. On the other hand, in the present embodiment, each pixel PX (in this embodiment, only PXA) has a set of first node Pa, amplification transistor AMP, reset transistor RST, and selection transistor SEL. doing.

  Basically, the description of the fourth embodiment is applicable as the description of the present embodiment by replacing the pixel block BL with the pixel PXA. Therefore, detailed description of this embodiment is omitted here.

  Also in this embodiment, the same advantages as in the fourth embodiment can be obtained.

[Sixth Embodiment]
FIG. 22 is a circuit diagram showing the vicinity of the three pixel blocks BL of the solid-state imaging device of the electronic camera according to the sixth embodiment of the present invention, and corresponds to FIG. FIG. 23 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 22, and corresponds to FIG. 4 and FIG. 22 and 23, elements that are the same as or correspond to those in FIGS. 3, 4, and 5 are given the same reference numerals, and redundant descriptions thereof are omitted.

  In FIG. 23, the control line 24 (n) not shown in FIGS. 4 and 5 is clearly shown, but the control line 24 (n) is not newly added in the present embodiment. . In other words, although the control line 24 (n) exists in other embodiments, the illustration is omitted.

  As described with reference to FIG. 3 in the first embodiment, the control line 24 (n) is a control line through which the control signal φRST (n) is transmitted. The gates of the reset transistors RST (n) are commonly connected to the control line 24 (n) for each row, and a control signal φRST (n) is supplied from the vertical scanning circuit 21 thereto. As shown in FIG. 23, the control line 24 (n) is arranged so as to be substantially parallel to the node P (n), and between the control line 24 (n) and the node P (n). A coupling capacitor CRSTA (n) is formed. In the following description, the capacitance value of the coupling capacitor CRSTA (n) is Cra.

  This embodiment is different from the first embodiment in the points described below. In the present embodiment, the dummy wiring DP (n) is arranged substantially parallel to the wiring 72 (n) in each pixel block BL (n). The dummy wiring DP (n) is a wiring pattern in which a part of the control line 24 (n) is extended. That is, one end of the dummy wiring DP (n) is connected to the control line 24 (n), but the other end extending between the pixel blocks BL is not connected anywhere, and is particularly useful for circuit control. It can be said that this is a dummy wiring pattern having no meaning. Since the dummy wiring DP (n) is arranged substantially parallel to the wiring 72 (n), the coupling between the wiring 72 (n) and the dummy wiring DP (n) is performed as shown in FIGS. A capacitor CRSTB (n) is formed. In the following description, the capacitance value of the coupling capacitor CRSTB (n) is Crb. In the first embodiment, the control line 24 (n) and the wiring 72 (n) are hardly coupled, and Crb is extremely small. In this embodiment, since the dummy wiring DP (n) is provided, Crb takes a larger value than that in the first embodiment.

  The shape of the dummy wiring DP (n) may be different from that described above. For example, only a portion parallel to the wiring 72 (n) may be provided, and a portion extending between the pixel blocks BL may be omitted. In order to increase the coupling capacitance CRSTB (n), it is desirable that the pattern of the dummy wiring DP (n) be as thick as possible. Further, the coupling capacitance between the control line 24 (n) and the wiring 72 (n) may be increased by a method different from that provided with the dummy wiring DP (n).

  FIG. 24 is a timing chart illustrating how the potential of the node P (n) is reset. At time t0, the control signal φRST (n) is set to H, the reset transistor RST (n) in the n-th row is once turned on, and the potential of the node P (n) is once reset to the power supply potential VDD. Thereafter, when the control signal φRST (n) is set to L, the reset transistor RST (n) is turned off. At this time, the potential of the node P (n) decreases from the power supply potential VDD by the feedthrough amount ΔV and becomes the potential VDARK.

  When the connection transistors SWa (n), SWb (n), and SWb (n−1) are off, the feedthrough amount ΔV is (Cra / Cfd1) × Vrst. Here, Vrst is the amplitude of the control signal φRST (n). As described above, Cfd1 is the capacitance value of the capacitor CA (n), and Cra is the capacitance value of the coupling capacitor CRSTA (n).

  On the other hand, when the connection transistor SWa (n) is on, the feedthrough amount ΔV is ((Cra + Crb) / (Cfd1 + Cfd2)) × Vrst. As described above, Cfd2 is the capacitance value of the capacitor CB (n), and Crb is the capacitance value of the coupling capacitor CRSTB (n).

  In the first embodiment, Crb is extremely small. If Crb is 0, the feedthrough amount ΔV when the connection transistor SWa (n) is on is (Cra / (Cfd1 + Cfd2)). Here, the capacitance value Cra is constant regardless of whether the connection transistor SWa (n) is on or off. Therefore, in the first embodiment, the feedthrough amount ΔV decreases when the connection transistor SWa (n) is turned on. Therefore, the potential VDARK is higher than that when the connection transistor SWa (n) is off.

  On the other hand, in the present embodiment, Crb is larger than that in the first embodiment. Therefore, the feedthrough amount ΔV becomes larger than that in the first embodiment, and the potential VDARK can be lowered.

  In order to keep the linearity of the output from the amplification transistor AMP (n) good, it is necessary to operate the amplification transistor AMP (n) in the saturation region. That is, it is necessary to make the drain-source voltage Vds larger than the saturation voltage Vdsat. The drain-source voltage Vds is a difference between the drain voltage Vd and the source voltage Vs and is expressed as Vd−Vs. Here, from FIG. 22, the drain voltage Vd is the power supply voltage Vdd. The source voltage Vs is Vg−Vth−√ (2 × Id / β). Vg is a gate voltage, Vth is a threshold value of the amplification transistor AMP (n), Id is a drain current, and β is an element parameter.

  From this, it can be seen that as the gate voltage Vg increases, the source voltage Vs increases, that is, the drain-source voltage Vds decreases. At this time, the amplification transistor AMP (n) may not be able to operate in the saturation region. Therefore, it is necessary to keep the potential VDARK after resetting the node P (n) low. In addition, there is a technique of making the amplification transistor AMP (n) a buried channel type in order to reduce noise. However, when such a technique is applied, the threshold voltage Vth decreases, and the source voltage Vs further increases. Therefore, it is more important to keep the potential VDARK low.

  In this embodiment, even when the connection transistor SWa (n) is on, the feedthrough amount ΔV can be increased, and the amplification transistor AMP (n) can be reliably operated in the saturation region. Compared with the first embodiment, the linearity of the output of the amplification transistor AMP (n) is improved.

  Further, the capacitance values of Cfd2 and Crb can be adjusted, and the feedthrough amount ΔV can be made substantially the same regardless of whether the coupling transistor SWa (n) is turned on or off by appropriately adjusting the capacitance values. In this way, the operation can be performed with the potential VDARK after the reset of the node P (n) being substantially the same regardless of whether the connection transistor SWa (n) is turned on or off.

[Seventh Embodiment]
FIG. 25 is a circuit diagram showing the vicinity of the three pixel blocks BL of the solid-state imaging device of the electronic camera according to the sixth embodiment of the present invention, and corresponds to FIG. FIG. 26 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 25, and corresponds to FIG. 4 and FIG. 25 and 26, the same or corresponding elements as those in FIGS. 3, 4 and 5 are denoted by the same reference numerals, and redundant description thereof will be omitted.

  26 clearly shows three control lines 22 (n), 24 (n), and 27 (n) that are not shown in FIGS. 4 and 5, these three control lines 22 ( n), 24 (n), and 27 (n) are not newly added in the present embodiment. That is, in the other embodiments, these three control lines 22 (n), 24 (n), and 27 (n) exist, but are not shown.

  As described with reference to FIG. 3 in the first embodiment, the control line 22 (n) is a control line through which the control signal φSWa (n) is transmitted. The gates of the connection transistors SWa (n) are commonly connected to the control line 22 (n) for each row, and a control signal φSWa (n) is supplied from the vertical scanning circuit 21 thereto.

  As described with reference to FIG. 3 in the first embodiment, the control line 24 (n) is a control line through which the control signal φRST (n) is transmitted. The gates of the reset transistors RST (n) are commonly connected to the control line 24 (n) for each row, and a control signal φRST (n) is supplied from the vertical scanning circuit 21 thereto.

  As described with reference to FIG. 3 in the first embodiment, the control line 27 (n) is a control line through which the control signal φSWb (n) is transmitted. The gates of the connection transistors SWb (n) are commonly connected to the control line 27 (n) for each row, and a control signal φSWb (n) is supplied from the vertical scanning circuit 21 thereto.

  As shown in FIGS. 25 and 26, a coupling capacitor CRSTA (n) is formed between the node P (n) and the control line 24 (n). Similarly, a coupling capacitance CSWa (n) is formed between the wiring 72 (n) and the control line 22 (n), and a coupling is formed between the wiring 72 (n) and the control line 27 (n). A capacitor CSWb (n) is formed.

  This embodiment is different from the first embodiment in the points described below. In the present embodiment, the circuit configuration of the solid-state imaging device is the same as that of the first embodiment. In the present embodiment, the operations of the connection transistors SWa (n) and SWb (n) in each operation mode are different from those in the first embodiment. Hereinafter, focusing on the pixel block BL (n), the operation of the connection transistors SWa (n) and SWb (n) in each operation mode will be described.

  FIG. 27 is a timing chart showing a first operation mode of the solid-state imaging device of the electronic camera according to the seventh embodiment of the present invention, and corresponds to FIG. The difference from the first embodiment is that when the control signal φRST (n) is set to H and the reset transistor RST (n) is turned on, the control signal φSWa (n) is set to H and the connection transistor SWa ( n) is turned on (immediately before time t1). Thereafter, the vertical scanning circuit 21 first sets the control signal φRST (n) to L to turn off the reset transistor RST (n), and then sets the control signal φSWa (n) to L to turn off the connection transistor SWa (n). To. Since other points are the same as those of the first embodiment, description thereof is omitted.

  FIG. 28 is a timing chart showing a 2A operation mode of the solid-state imaging device of the electronic camera according to the seventh embodiment of the present invention, and corresponds to FIG. The difference from the first embodiment is that when the control signal φRST (n) is set to H and the reset transistor RST (n) is turned on, the control signal φSWb (n) is set to H and the connection transistor SWb is substantially at the same time. (N) is turned on (immediately before time t1). Thereafter, the vertical scanning circuit 21 first sets the control signal φRST (n) to L to turn off the reset transistor RST (n), and then sets the control signal φSWb (n) to L to turn off the connection transistor SWb (n). To. Since other points are the same as those of the first embodiment, description thereof is omitted.

  FIG. 29 is a timing chart showing the 2B operation mode of the solid-state imaging device of the electronic camera according to the seventh embodiment of the present invention, and corresponds to FIG. The difference from the first embodiment is that when the control signal φRST (n) is set to H and the reset transistor RST (n) is turned on, the control signal φSWa (n + 1) is set to H and the connection transistor SWa ( n + 1) is turned on (immediately before time t1). Thereafter, the vertical scanning circuit 21 first sets the control signal φRST (n) to L to turn off the reset transistor RST (n), and then sets the control signal φSWa (n + 1) to L to turn off the connection transistor SWa (n + 1). To. Since other points are the same as those of the first embodiment, description thereof is omitted.

  As described above, in the present embodiment, when the node P (n) is reset, the outermost connected transistor is turned on substantially temporarily. Here, the outermost connected transistor is a connected transistor located at the outermost end of the pixel block BL to be connected. For example, when the pixel block BL (n) is not connected, the outermost connected transistor is one of the connected transistors SWa (n) and SWb (n−1). Further, when the pixel block BL (n) and the pixel block BL (n + 1) are connected, the outermost connected transistor is one of the connected transistors SWa (n + 1) and SWb (n−1).

  FIG. 30 is a timing chart illustrating how the potential of the node P (n) is reset. In FIG. 30, the control signal φSW is a control signal supplied to the gate of the outermost connected transistor. For example, when the outermost connection transistor is the connection transistor SWb (n−1), the control signal φSW is the control signal φSWb (n−1).

  At time t0, the control signal φSW and the control signal φRST (n) supplied to the gates of the outermost coupled transistors are set to H substantially simultaneously. As a result, the reset transistor RST (n) in the n-th row is once turned on and the pixel block BL is once connected. At this time, the potential of the node P (n) is once reset to the power supply potential VDD. Thereafter, when the control signal φRST (n) is set to L, the reset transistor RST (n) is turned off. At this time, the potential of the node P (n) decreases from the power supply potential VDD by the feedthrough amount ΔV1 according to the coupling capacitance by the control line 24 (n). Subsequently, when the control signal φSW is set to L, the outermost connected transistor is turned off. At this time, the potential of the node P (n) is further lowered by the feedthrough amount ΔV2 and becomes the potential VDARK.

  As described above, in this embodiment, when the potential of the node P (n) is reset, the connection switch at the outermost end is turned on / off, thereby further reducing the potential of the node P (n) by the feedthrough amount ΔV2. I am letting. As a result, the potential VDARK can be further reduced as compared with the first embodiment. Therefore, the same effects as those described in the sixth embodiment can be obtained.

  As mentioned above, although each embodiment and modification of this invention were demonstrated, this invention is not limited to these.

4 Solid-state imaging device BL Pixel block PX Pixel PD Photodiode TXA, TXB Transfer transistor P node AMP Amplification transistor SWa, SWb Linked transistor

Claims (18)

One photoelectric conversion unit, a node, one transfer switch provided corresponding to the one photoelectric conversion unit, and transferring a charge from the photoelectric conversion unit to the node; and a reset switch for resetting the potential of the node; a plurality of pixel blocks having,
An electrical connection provided between the node of one of the pixel blocks and the node of another one of the pixel blocks;
A plurality of connection switches per one pixel block provided in the connection portion;
A solid-state imaging device comprising: The solid-state imaging device according to claim 1,
A solid-state imaging device including a wiring that is arranged substantially parallel to the wiring configuring the connection portion and has one end electrically connected to the reset switch . The solid-state imaging device according to claim 1 or 2 ,
Wherein the reset switch is turned on, one of the connecting switch that is electrically connected to the node solid-state image pickup device is turned on. The solid-state imaging device according to claim 1,
A control unit for controlling the connection switch;
The control unit controls the connection switch so that the connection unit is electrically disconnected from the node of the pixel block in the first operation mode;
In the second operation mode, the control unit controls the connection switch so that the connection unit is electrically connected to the node of the pixel block. The solid-state imaging device according to claim 4 ,
In the second operation mode, the control unit is in a state in which one or more of the connection switches of the connection switches are electrically connected to the node of the pixel block. A solid-state imaging device that controls the connection switch so that The solid-state imaging device according to claim 1,
A solid-state imaging device in which the nodes of three or more pixel blocks of the plurality of pixel blocks are connected in a daisy chain by a plurality of the connection portions. The solid-state imaging device according to claim 6 ,
A control unit for controlling the connection switch;
In the first operation mode, the control unit is configured to connect the connection unit so that the connection unit is electrically disconnected from the node of one pixel block of the three or more pixel blocks. Control the switch,
In the second operation mode, the control unit is configured so that the connection unit is electrically connected to the node of the one pixel block among the three or more pixel blocks. A solid-state image sensor that controls a connection switch. The solid-state imaging device according to claim 7 ,
In the second operation mode, the control unit is configured such that one or more of the connection switches in the predetermined number of on-state connection switches are connected to the one pixel block of the three or more pixel blocks. A solid-state imaging device that controls the connection switch so as to be electrically connected to the node. In the solid-state image sensing device according to any one of claims 1 to 8 ,
Each of the pixel blocks has a plurality of the photoelectric conversion units and the transfer switches, respectively. A plurality of photoelectric conversion units, nodes, and said plurality of respectively provided corresponding to the photoelectric conversion unit, and a plurality of transfer switches for transferring charges to said node before Symbol photoelectric conversion unit, connected to said node, A plurality of pixel blocks including: an amplification unit that outputs a signal corresponding to the potential of the node; and a selection unit that is connected to the amplification unit and outputs the signal to a signal line ;
Among the plurality of pixel blocks, a plurality of connection switches provided between the nodes of the two pixel blocks;
A solid-state imaging device. The solid-state imaging device according to claim 10 ,
A control unit for controlling the connection switch;
In the first operation mode, the control unit is configured such that an on-state connection switch of the connection switches is electrically connected to the node of one pixel block of the two pixel blocks. Control the connection switch so that it does not become a state,
In the second operation mode, the control unit is configured such that one or more of the connection switches of the connection switches are electrically connected to the node of the one pixel block. A solid-state imaging device that controls the connection switch so as to be in a state. The solid-state imaging device according to claim 10 ,
A solid-state imaging device in which the nodes of three or more pixel blocks of the plurality of pixel blocks are connected in a daisy chain by two or more sets of the plurality of connection switches. The solid-state imaging device according to claim 12 ,
A control unit for controlling the connection switch;
In the first operation mode, the controller is configured such that an on-state coupling switch among the coupling switches is electrically connected to one of the three or more pixel blocks. The connection switch is controlled so that
In the second operation mode, the control unit is configured such that one or more of the connection switches of the connection switches are electrically connected to the node of the one pixel block. A solid-state imaging device that controls the connection switch so as to be in a state. In the solid-state image sensing device according to any one of claims 9 to 13 ,
The transfer switch comprises a transistor;
In each of the pixel blocks, a diffusion region that becomes a source or drain of one transfer switch of the transfer switches, and a diffusion region that becomes a source or drain of another transfer switch of the transfer switches , One diffusion region provided between one photoelectric conversion unit of each photoelectric conversion unit and the other one photoelectric conversion unit of each photoelectric conversion unit,
In each pixel block, the gate electrode of the one transfer switch is disposed on the one photoelectric conversion unit side of the one diffusion region,
In each of the pixel blocks, the gate electrode of the other one transfer switch is a solid-state imaging device arranged on the one other photoelectric conversion unit side of the one diffusion region. In the solid-state image sensing device according to any one of claims 9 to 14 ,
The solid-state imaging device in which the number of the plurality of photoelectric conversion units and the number of the plurality of transfer switches are two, respectively. The solid-state imaging device according to claim 15 ,
The number of the plurality of connection switches is two;
A positional deviation amount in a predetermined direction between one connection switch of the plurality of connection switches and another connection switch of the plurality of connection switches is determined by a pitch in the predetermined direction of the plurality of photoelectric conversion units. A solid-state imaging device which is larger and smaller than twice the pitch. In the solid-state image sensing device according to any one of claims 9 to 16 ,
The number of the plurality of connection switches is two;
The value of the capacitance between the connection between the plurality of connection switches and the reference potential when the plurality of connection switches are off is the value of the node and the reference potential when the plurality of connection switches are off. A solid-state imaging device having a value within a range of ± 20% with respect to a capacitance value between. In the solid-state image sensing device according to any one of claims 1 to 17 ,
The number of the plurality of connection switches is two;
A width of at least a part of a wiring configuring a connection portion between the plurality of connection switches when the plurality of connection switches are off, is wider than a width of another wiring in the pixel block; A solid-state imaging device satisfying any one or more of a MOS capacitor being connected and a diffusion capacitor that does not constitute each of the connection switches being connected to the connection part.

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