JP6579186B2 - Imaging device and imaging apparatus - Google Patents

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus using the same.

  In Patent Document 1 below, a plurality of pixels, each of which includes at least two pixels including (a) a photodetector, (b) a charge-voltage conversion region that forms a floating capacitance section, and (c) an input section to an amplifier. And a solid-state imaging device including a connection switch that selectively connects the charge-voltage conversion regions.

Special table 2008-546313 gazette

  In the conventional solid-state imaging device, by turning on the connection switch and connecting the charge-voltage conversion regions to each other, the number of saturated electrons in the entire connected charge-voltage conversion region is expanded, so that the dynamic range is increased. Can be enlarged.

  In the conventional solid-state imaging device, the charge-voltage conversion capacity is reduced and the charge-voltage conversion coefficient is increased by turning off the connection switch and separating the charge-voltage conversion region from other charge-voltage conversion regions. Therefore, the SN ratio at the time of high sensitivity reading becomes high.

  However, in the conventional solid-state imaging device, even when the connection switch is turned off, the SN ratio at the time of high-sensitivity readout cannot be increased so much.

  The present invention has been made in view of such circumstances, a solid-state imaging device capable of expanding the dynamic range and improving the SN ratio at the time of high-sensitivity reading, and imaging using the same. An object is to provide an apparatus.

  The following aspects are presented as means for solving the problems. The solid-state imaging device according to the first aspect is provided corresponding to two photoelectric conversion units, nodes, and the two photoelectric conversion units arranged in a predetermined direction, and transfers electric charges from the two photoelectric conversion units to the node, respectively. A plurality of pixel blocks each having two transfer transistors, a reset transistor for resetting the potential of the node, and a connection transistor, and each one of the two transfer transistors, the reset transistor, and the connection transistor in each pixel block Source / drain diffusion regions are shared by one diffusion region, and the other source / drain diffusion regions of the coupling transistors of two or more pixel blocks are electrically connected to each other.

  In the solid-state imaging device according to the second aspect, in the first aspect, in each pixel block, the gate electrodes of the two transfer transistors are on one side and the other side in the predetermined direction of the one diffusion region. In each of the pixel blocks, the gate electrodes of the reset transistor and the connection transistor are arranged on one side and the other side in a direction intersecting the predetermined direction of the one diffusion region.

  In the solid-state imaging device according to the third aspect, in the first or second aspect, each of the two photoelectric conversion units of the plurality of pixel blocks is arranged in a lattice shape as a whole, and The two pairs of the photoelectric conversion units are adjacent to each other in a direction crossing the predetermined direction, and the two rows of the pair arranged in the predetermined direction are in the predetermined direction by one pitch of the photoelectric conversion unit with respect to each other. They are arranged in a staggered pattern so as to be displaced.

  The solid-state imaging device according to a fourth aspect is the solid state imaging device according to the third aspect, wherein the position of the two photoelectric conversion units in one pixel block of the two or more pixel blocks in the predetermined direction and the two or more The position of the two photoelectric conversion units in the other one of the pixel blocks in the predetermined direction is the same, and the two of the two or more pixel blocks are the 2 of the one pixel block. The position in the intersecting direction of two photoelectric conversion units and the position in the intersecting direction of the two photoelectric conversion units in the other one pixel block of the two or more pixel blocks are the photoelectric conversion unit Is shifted by two pitches.

  A solid-state imaging device according to a fifth aspect is provided corresponding to a group of pixel blocks having the same position in the predetermined direction of the pair of the plurality of pixel blocks in the third or fourth aspect. A signal line for receiving the output signal of the pixel block of the group is provided.

  The solid-state imaging device according to a sixth aspect is the gate of one transfer transistor of the two transfer transistors of each pixel block in which the pair forms the two columns in any of the third to fifth aspects. The electrode is electrically connected in common, and the gate electrode of the other transfer transistor of the two transfer transistors of each pixel block in which the pair forms the two columns is electrically connected in common It is.

  A solid-state imaging device according to a seventh aspect is the solid-state imaging device according to any one of the first to sixth aspects, wherein each of the pixel blocks includes an amplification transistor that outputs a signal according to the potential of the node, the one diffusion region, The gate electrode of the amplification transistor is electrically connected to each other and has a wiring composed of a lowermost wiring layer.

  A solid-state imaging device according to an eighth aspect includes, in any one of the first to seventh aspects, a signal line that receives an output signal of the pixel block, and each pixel block has a signal corresponding to the potential of the node. And a wiring line adjacent to the signal line that electrically connects the one diffusion region and the gate electrode of the amplification transistor and receives an output signal of the pixel block. .

  In a solid-state imaging device according to a ninth aspect, in any one of the first to eighth aspects, in the first operation mode, the connection transistor of one pixel block of the two or more pixel blocks is off. In the second operation mode, at least one of the two transfer transistors of the one pixel block is turned on, and the connection transistor of the one pixel block is turned on in the second operation mode. At least one of the two transfer transistors of one pixel block is turned on.

  An imaging apparatus according to a tenth aspect includes the solid-state imaging element according to any one of the first to ninth aspects.

  An image pickup apparatus according to an eleventh aspect includes the solid-state image pickup element according to the ninth aspect, and switches the operation modes according to a set value of ISO sensitivity.

  ADVANTAGE OF THE INVENTION According to this invention, while being able to expand a dynamic range, the solid-state image sensor which can improve the S / N ratio at the time of highly sensitive reading, and an imaging device using the same can be provided.

1 is a schematic block diagram schematically showing an electronic camera according to a first embodiment of the present invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor in FIG. FIG. 3 is an enlarged circuit diagram illustrating the vicinity of four pixel blocks in FIG. 2. It is a figure which shows typically the relationship between the pixel block of the solid-state image sensor shown in FIG. 2, and a photodiode. FIG. 4 is a schematic plan view schematically showing the vicinity of four pixel blocks shown in FIG. 3. FIG. 6 is a schematic plan view showing an enlarged vicinity of two pixel blocks in FIG. 5 with some wirings omitted. 3 is a timing chart showing a predetermined operation mode of the solid-state imaging device shown in FIG. 2. 3 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 2. It is a circuit diagram which shows schematic structure of the solid-state image sensor by a comparative example. It is a figure which shows typically the relationship between the pixel block of the solid-state image sensor shown in FIG. 9, and a photodiode. FIG. 11 is a schematic plan view schematically showing the vicinity of four pixel blocks in FIG. 10.

  Hereinafter, a solid-state imaging device and an imaging apparatus according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a schematic block diagram schematically showing the electronic camera 1 according to the first embodiment of the present invention.

  The electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera. However, the imaging apparatus according to the present invention is not limited to this, and is mounted on another electronic camera such as a compact camera or a mobile phone. The present invention can be applied to various imaging devices such as an electronic camera and an electronic camera such as a video camera that captures moving images.

  A photographing lens 2 is attached to the electronic camera 1. The photographing lens 2 is driven by a lens control unit 3 for focus and diaphragm. In the image space of the photographic lens 2, the imaging surface of the solid-state imaging device 4 is arranged.

  The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. In normal main shooting (during still image shooting) or the like, the imaging control unit 5 performs a predetermined readout operation after exposure with a mechanical shutter (not shown) after, for example, a so-called global reset that resets all pixels simultaneously. The solid-state image sensor 4 is controlled. In the electronic viewfinder mode or moving image shooting, the imaging control unit 5 controls the solid-state imaging device 4 so as to perform a predetermined reading operation while performing a so-called rolling electronic shutter, for example. At these times, as will be described later, the imaging controller 5 controls the solid-state imaging device 4 so as to perform a read operation in each operation mode described later according to the ISO sensitivity setting value. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on the digital image signal output from the solid-state imaging device 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 is also connected with a lens control unit 3, an imaging control unit 5, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12 and an image processing unit 13. An operation unit 14 such as a release button is connected to the CPU 9. The ISO sensitivity can be set by the operation unit 14. A recording medium 11a is detachably attached to the recording unit 11.

  When the CPU 9 in the electronic camera 1 is instructed by the operation unit 14 to operate in the electronic viewfinder mode, moving image shooting, normal normal shooting (still image shooting), or the like, the CPU 9 drives the imaging control unit 5 accordingly. At this time, the lens controller 3 appropriately adjusts the focus and the aperture. The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. A digital image signal from the solid-state imaging device 4 is processed by the digital signal processing unit 6 and then stored in the memory 7. The CPU 9 displays the image signal on the display unit 10 in the electronic viewfinder mode, and records the image signal in the recording medium 11a during moving image shooting. In the case of normal main shooting (during still image shooting) or the like, the CPU 9 processes the digital image signal from the solid-state imaging device 4 by the digital signal processing unit 6 and stores it in the memory 7, and then the operation unit 14. The image processing unit 13 or the image compression unit 12 performs a desired process based on the above command, outputs the processed signal to the recording unit 11 and records it on the recording medium 11a.

  FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 4 in FIG. FIG. 3 is an enlarged circuit diagram showing the vicinity of the four pixel blocks BL in FIG. FIG. 4 is a diagram schematically showing the relationship between the pixel block BL and the photodiode PD of the solid-state imaging device 4 shown in FIG. FIG. 5 is a schematic plan view schematically showing the vicinity of the four pixel blocks BL shown in FIG. FIG. 6 is a schematic plan view showing an enlarged view of the vicinity of two pixel blocks BL in FIG. 5 by omitting some of the wirings 23 to 27. In the present embodiment, the solid-state imaging device 4 is configured as a CMOS type solid-state imaging device, but is not limited thereto, and may be configured as, for example, another XY address type solid-state imaging device.

  As shown in FIGS. 2 to 6, the solid-state imaging device 4 is provided for every two rows of a plurality of pixel blocks BL each having two pixels PX (PXA, PXB), the vertical scanning circuit 21, and the pixel blocks BL. Control lines 23 to 27, a plurality of vertical signal lines 28 that are provided for each column of the pixel block BL and receive an output signal from the pixel block BL of a corresponding column, and a constant signal line 28 that is provided for each vertical signal line 28. A current source 29, a column amplifier 30 provided corresponding to each vertical signal line 28, a CDS circuit (correlated double sampling circuit) 31, an A / D converter 32, and a horizontal readout circuit 33 are provided. . Each pixel PX (PXA, PXB) has a photodiode PD (PDA, PDB) as one photoelectric conversion unit.

  The column amplifier 30 may be an analog amplifier or a so-called switched capacitor amplifier. Further, the column amplifier 30 is not necessarily provided.

  As shown in FIGS. 4 to 6, each of the photodiodes PD of the two pixels PX of the plurality of pixel blocks BL is arranged in a two-dimensional matrix in N rows and M columns and in a grid. FIG. 4 shows the relationship between the pixel block BL and 6 × 6 photodiodes PD from the (n−2) th row to the (n + 3) th row and from the (m−2) th column to the (m + 3) th row. The number of rows N and the number of columns M are not limited.

  Each pixel block BL has two photodiodes PD that are sequentially arranged in the row direction (left-right direction in FIGS. 4 to 6). In the drawing, the left photodiode in FIG. 4 to FIG. 6 in the pixel block BL is identified as PDA, and the right photodiode in FIG. 4 to 6 is identified as PDB. When the description is made without distinguishing between them, there is a case where both are described with the reference sign PD. 2 and 3, the pixel having the photodiode PDA is denoted by PXA, and the pixel having the photodiode PDB is denoted by PXB. The two are distinguished from each other. A description may be given with the reference numeral PX. Similarly, in FIGS. 2 to 6, the transfer transistor of the pixel PXA is denoted by TXA and the transfer transistor of the pixel PXB is denoted by TXB. The two are distinguished from each other. In some cases, TX is used for explanation.

  When the pixel block BL is distinguished by a row and a column, the pixel block BL in the j-th row and the k-th column is indicated by a symbol BL (j, k). Here, the matrix of the pixel block BL is defined by the matrix of the left photodiode PDA included in the pixel block BL, and the pixel block BL including the photodiode PDA in the j-th row and the k-th column is denoted by a symbol BL (j, k). When the pixel block BL is distinguished for each row without particularly distinguishing the column, the pixel block BL in the j-th row is indicated by a symbol BL (j). This also applies to components such as the photodiodes PDA and PDB of the pixel block BL and control signals described later. When distinguishing the vertical signal line 28, the vertical signal line provided corresponding to the pixel block BL (j) and receiving the output signal from the pixel block BL (j) is denoted by reference numeral 28 (j).

  A pair of two photodiodes PD (PDA, PDB) of a plurality of pixel blocks BL are arranged in the row direction adjacent to each other in the column direction (vertical direction in FIGS. 4 to 6) that intersects the row direction. The two columns of the pair (here, two rows) are staggered so as to be shifted in the row direction by one pitch of the photodiode PD with respect to each other. For example, the row of the nth pixel block BL and the row of the (n + 1) th pixel block BL are shifted in the row direction by one pitch of the photodiode PD with respect to each other.

  In the present embodiment, each pixel PX includes a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and charges from the photodiode PD to the node P provided corresponding to the photodiode PD. And a transfer transistor TX. As shown in FIGS. 2 and 3, for each pixel block BL, two pixels PX (PXA, PXB) belonging to the pixel block BL include one set of node P, amplification transistor AMP, reset transistor RST, and selection. The transistor SEL and the connection transistor SW are shared. A capacitance (charge-voltage conversion capacitance) is formed between the node P and the reference potential, and the electric charge transferred to the node P is converted into a voltage by the capacitance. The amplification transistor AMP constitutes an amplification unit that outputs a signal corresponding to the potential of the node P. The amplification transistor AMP has a drain connected to the power supply voltage VDD, a gate connected to the node P, a source connected to the drain of the selection transistor SEL, and a source follower circuit having the constant current source 29 as a load. ing. The reset transistor RST constitutes a reset unit that resets the potential of the node P to a predetermined potential (in this embodiment, the power supply voltage VDD). The selection transistor SEL constitutes a selection unit for selecting the pixel block BL. The source of the connection transistor SW is electrically connected to the node P. The photodiode PD and the transfer transistor TX are provided for each pixel PX without being shared by the two pixels PX (PXA, PXB).

  For example, the transfer transistor TXA (n) of the pixel block BL (n, m) transfers charge from the photodiode PDA (n) to the node P (n), and the transfer transistor TXB (n) is the photodiode PDB (n). The charge is transferred from node to node P (n). A capacitance (charge-voltage conversion capacitance) is formed between the node P (n) and the reference potential, and the electric charge transferred to the node P (n) is converted into a voltage by the capacitance. The amplification transistor AMP (n) outputs a signal corresponding to the potential of the node P (n). The reset transistor RST (n) resets the potential of the node P (n) to the power supply voltage VDD. One source / drain (source in the present embodiment) of the connection transistor SW (n) is electrically connected to the node P (n). The same applies to the other pixel blocks BL.

  Although not shown in the drawings, in the present embodiment, a plurality of types of color filters that transmit light of different color components are arranged in a predetermined color array on the light incident side of the photodiode PD of each pixel PX. (For example, a Bayer array). The pixel PX outputs an electrical signal corresponding to each color by color separation with a color filter.

  In the present embodiment, for each of the two pixel blocks BL, the other source / drain (drain in this embodiment) of the connection transistor SW of the two pixel blocks BL is electrically connected to each other. More specifically, in this embodiment, the columns are the same (that is, the positions in the row direction are the same) and the rows are different by two rows (that is, the positions in the column direction are shifted by two pitches of the photodiode PD). For each of the two pixel blocks BL, the drains of the connection transistors SW of the two pixel blocks BL are electrically connected to each other. Here, the position of the pixel block BL is defined by the position of the photodiode PDA included in the pixel block BL.

  For example, the drain of the connection transistor SW (n) of the pixel block BL (n, m) and the drain of the connection transistor SW (n + 2) of the pixel block BL (n + 2, m) are electrically connected. The drain of the connection transistor SW (n−1) of the pixel block BL (n−1, m + 1) and the drain of the connection transistor SW (n + 1) of the pixel block BL (n + 1, m + 1) are electrically connected. The same applies to the other pixel blocks BL.

  2 and 3, VDD is a power supply potential. In the present embodiment, the transistors TXA, TXB, AMP, RST, SEL, SW are all nMOS transistors.

  The gates of the transfer transistors TXA are commonly connected to the control line 26 every two rows, and a control signal φTXA is supplied thereto from the vertical scanning circuit 21. For example, the gates of the transfer transistors TXA (n) and TXA (n−1) are commonly connected to the control line 26, and the same control signals φTXA (n) and φTXA (n−1) are connected to the vertical scanning circuit. 21.

  The gates of the transfer transistors TXB are commonly connected to the control line 25 every two rows, and a control signal φTXB is supplied from the vertical scanning circuit 21 there. For example, the gates of the transfer transistors TXB (n) and TXB (n−1) are commonly connected to the control line 25, and the same control signals φTXB (n) and φTXB (n−1) are connected to the vertical scanning circuit. 21.

  The gates of the reset transistors RST are commonly connected to the control line 24 every two rows, and a control signal φRST is supplied from the vertical scanning circuit 21 thereto. For example, the gates of the reset transistors RST (n) and RST (n−1) are commonly connected to the control line 24, and the same control signals φRST (n) and φRST (n−1) are connected to the vertical scanning circuit. 21.

  The gates of the selection transistors SEL are commonly connected to the control line 23 every two rows, and a control signal φSEL is supplied thereto from the vertical scanning circuit 21. For example, the gates of the selection transistors SEL (n) and SEL (n−1) are commonly connected to the control line 23, and the same control signals φSEL (n) and φSEL (n−1) are connected to the vertical scanning circuit. 21.

  The gates of the connecting transistors SW are commonly connected to the control line 27 every two rows, and a control signal φSW is supplied thereto from the vertical scanning circuit 21. For example, the gates of the connection transistors SW (n) and SW (n + 1) are commonly connected to the control line 27, and the same control signals φSW (n) and φSW (n + 1) are supplied from the vertical scanning circuit 21 there. The

  Each transistor TXA, TXB, RST, SEL, SW is turned on when the corresponding control signal φTXA, φTXB, φRST, φSEL, φSW is at a high level (H), and is turned off when it is at a low level (L).

  The vertical scanning circuit 21 outputs the control signals φTXA, φTXB, φRST, φSEL, and φSW for every two rows of the pixel block BL under the control of the imaging control unit 5 in FIG. 1 to control the pixel block BL. Realize still image reading operation, moving image reading operation, and the like. In this control, for example, a read operation in each operation mode, which will be described later, is performed according to the set value of the ISO sensitivity. By this control, each vertical signal line 28 is supplied with an output signal (analog signal) of the pixel block BL in the corresponding column.

  In the present embodiment, the vertical scanning circuit 21 constitutes a control unit that switches each operation mode to be described later according to a command (control signal) from the imaging control unit 5 in FIG.

  The signal read out to the vertical signal line 28 is amplified by the column amplifier 30 for each column, and further optical signals (signals including optical information photoelectrically converted by the pixels PX) and dark signals (light After being subjected to processing for obtaining a difference from the signal (difference signal including a noise component to be subtracted from the signal), it is converted into a digital signal by the A / D converter 32, and the digital signal is held in the A / D converter 32. Is done. The digital image signal held in each A / D converter 32 is horizontally scanned by a horizontal readout circuit 33, converted into a predetermined signal format as necessary, and externally (digital signal processing unit 6 in FIG. 1). ).

  The CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in FIG. 1, and when φDARKC is at a high level (H), The output signal is sampled as a dark signal, and the optical signal sampling signal φSIGC is received from the timing generation circuit under the control of the imaging control unit 5 in FIG. 1. When φSIGC is H, the output signal of the column amplifier 30 is converted into an optical signal. Sampling as Then, the CDS circuit 31 outputs a signal corresponding to the difference between the sampled dark signal and optical signal based on the clock and pulse from the timing generation circuit. As the configuration of the CDS circuit 31, a known configuration can be adopted.

  Here, the structure of the pixel block BL will be described with reference to FIGS. 5 and 6. In practice, a color filter, a microlens, and the like are disposed above the photodiode PD, but are omitted in FIGS. In FIGS. 5 and 6, the layout of power supply lines, ground lines, and the like is omitted. In FIG. 6, the layout of the control lines 23 to 27 in FIG. 5 is also omitted. In FIGS. 5 and 6, a thick solid line indicates the first wiring layer (the lowest layer closest to the substrate) made of metal such as aluminum. In FIG. 6, a broken line indicates a second wiring layer made of a metal such as aluminum. In FIG. 5 and FIG. 6, white circles indicate connection portions between the first wiring layer and the gate electrode or the diffusion region. In FIG. 6, gray circles indicate connection portions between the first wiring layer and the second wiring layer.

  In the present embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and each element in the pixel block BL such as a photodiode PD is arranged in the P-type well. Yes. In FIG. 6, reference numerals 41 to 45 denote N-type impurity diffusion regions which are part of the above-described transistors. Reference numerals 61 to 65 denote gate electrodes of the respective transistors made of polysilicon. The diffusion region 42 is a region to which the power supply voltage VDD is applied by a power supply line (not shown).

  The photodiodes PDA (n) and PDB (n) of the pixel block BL (n, m) are arranged on the surface side of an N-type charge storage layer (not shown) provided in the P-type well. This is a buried photodiode composed of a P-type depletion prevention layer (not shown). The photodiodes PDA (n) and PDB (n) photoelectrically convert incident light and store the generated charges in the charge storage layer.

  The transfer transistor TXA (n) of the pixel block BL (n, m) is an nMOS transistor having the charge storage layer of the photodiode PDA (n) as a source, the diffusion region 41 as a drain, and the gate electrode 61 as a gate. The transfer transistor TXB (n) of the pixel block BL (n, m) is an nMOS transistor having the charge storage layer of the photodiode PDB (n) as a source, the diffusion region 41 as a drain, and the gate electrode 62 as a gate. The diffusion region 41 is provided between the photodiode PDA (n) and the photodiode PDB (n).

  The amplification transistor AMP (n) of the pixel block BL (n, m) is an nMOS transistor having the diffusion region 42 as a drain, the diffusion region 43 as a source, and the gate electrode 64 as a gate. The gate electrode 64 and the diffusion region 4 are electrically connected by a wiring 71 composed of the lowermost wiring layer. The reset transistor RST (n) of the pixel block BL (n, m) is an nMOS transistor having the diffusion region 41 as a source, the diffusion region 42 as a drain, and the gate electrode 63 as a gate. The selection transistor SEL (n) of the pixel block BL (n, m) is an nMOS transistor having the diffusion region 43 as a drain, the diffusion region 44 as a source, and the gate electrode 65 as a gate. The diffusion region 44 is connected to the vertical signal line 28 (m). The connection transistor SW (n) of the pixel block BL (n, m) is an nMOS transistor having the diffusion region 41 as a source, the diffusion region 45 as a drain, and the gate electrode 66 as a gate. The diffusion region 45 serving as the drain of the connection transistor SW (n) of the pixel block BL (n, m) is connected to the diffusion region 45 serving as the drain of the connection transistor SW (n + 2) of the pixel block BL (n + 2, m). It is connected to the.

  As can be seen from the above description, the diffusion region 41 includes the diffusion region that becomes the drain of the transfer transistor TXA (n), the diffusion region that becomes the drain of the transfer transistor TXB (n), and the diffusion region that becomes the source of the reset transistor RST (n). And it is also used as a diffusion region that becomes the source of the connection transistor SW (n). The gate electrode 61 of the transfer transistor TXA (n) and the gate electrode 62 of the transfer transistor TXB (n) are disposed on one side and the other side of the diffusion region 41 in the row direction. The gate electrode 63 of the reset transistor RST (n) and the gate electrode 66 of the connection transistor SW (n) are arranged on one side and the other side of the diffusion region 41 in the column direction.

  In the present embodiment, the node P (n) of the pixel block BL (n, m) is connected to the wiring 71 of the pixel block BL (n, m) and the entire portion that is electrically connected to and conductive therewith. It corresponds to.

  The structure of the pixel block BL other than the n-th row and the m-th column is the same as the structure of the pixel block BL (n, m) in the n-th row and the m-th column.

  As shown in FIG. 5, each of the control lines 23 to 27 for each two rows is composed of a combination of a second wiring layer indicated by a broken line and a lowermost wiring layer indicated by a thick solid line. .

  2 and 3, FC (n) is a capacitance between the node P (n) and the reference potential when the connection transistor SW (n) is off. The capacity value of the capacity FC (n) is Cfd1. The same applies to the rows of other pixel blocks BL.

  The capacitance FC (n) includes the capacitance of the diffusion regions 41 of the transfer transistors TXA (n), TXB (n), the reset transistor RST (n) and the connection transistor SW (n), and the gate electrode 64 of the amplification transistor AMP (n). And the wiring capacitance of the wiring 71, and the total of those capacitance values is the capacitance value Cfd1 of the capacitance FC (n). The same applies to the rows of other pixel blocks BL.

  Here, the value of the channel capacitance when the connection transistor SW is on is Csw. Usually, the capacitance value Csw is smaller than the capacitance value Cfd1. The capacitance value of the capacitance of the diffusion region 45 of the connection transistor SW is Cfd2, and the capacitance value of the wiring capacitance of the wiring 72 is Cfd3.

  Now, paying attention to the pixel block BL (n), when the connection transistor SW (n) is turned off, the capacitance (charge-voltage conversion capacitance) between the node P (n) and the reference potential is the capacitance FC (n). Become. Therefore, the capacitance value of the charge-voltage conversion capacitor at the node P (n) is Cfd1. This state corresponds to the state of the period T2 in FIG. 7 showing a first operation mode to be described later and other periods.

  Further, paying attention to the pixel block BL (n), when the connection transistors SW (n) and SW (n + 2) are turned on, the capacitance value of the charge-voltage conversion capacitance of the node P (n) is 2 × Cfd1 + 2 × Csw + 2 × Cfd2 + Cfd3. It becomes. This state corresponds to a state of a period T2 in FIG. 8 showing a second operation mode described later and other periods.

  As described above, when the connection transistor SW (n) is turned off, the capacitance value of the charge-voltage conversion capacitor at the node P (n) is minimized, and the charge-voltage conversion coefficient due to the charge-voltage conversion capacitor is increased. Can be read.

  On the other hand, when the connection transistors SW (n) and SW (n + 2) are turned on, the capacitance value of the charge-voltage conversion capacitance of the node P (n) increases, and a large signal charge amount can be handled, so the number of saturated electrons is increased. can do. Thereby, the dynamic range can be expanded.

  The node P (n) of the pixel block BL (n) has been described above, but the same applies to the nodes P of other pixel blocks BL.

  FIG. 7 is a timing chart showing a first operation mode of the solid-state imaging device 4 shown in FIG. In the first operation mode, each pixel block BL is sequentially selected every two rows, and the connection transistor SW of the selected two pixel blocks BL is turned off (charge-voltage conversion of the node P). The transfer transistors TXA and TXB of the selected two rows of pixel blocks BL are sequentially turned on sequentially in a state where the capacitance is minimum), and the photodiodes PDA and PDB of the selected two rows of pixel blocks BL are sequentially turned on. It is an example of the operation | movement which reads a signal sequentially for every 2 rows. In the example illustrated in FIG. 7, signals of all the pixels PXA and PXB are read out. However, the present invention is not limited to this. For example, thinning out reading that reads out pixel rows may be performed. This also applies to the example shown in FIG.

  In the example shown in FIG. 7, in this first operation mode, φSW of all rows is set to L over the entire period, and the connection transistors SW of all rows are turned off.

  FIG. 7 shows that pixel blocks BL (n−2) and BL (n−3) in the n−2 and n−3th rows are selected in the period T1, and the nth and n−1th rows are selected in the period T2. Pixel blocks BL (n) and BL (n−1) are selected, and the pixel blocks BL (n + 2) and BL (n + 1) in the n + 2 and n + 1 rows are selected in the period T3. . Since the operation when any two rows of pixel blocks BL are selected is the same, the pixel blocks BL (n) and BL (n-1) of the nth row and the (n-1) th row are selected here. Only the operation in the case of failure will be described.

  The exposure of the photodiodes PDA (n), PDB (n), PDA (n−1), and PDB (n−1) has already been completed in a predetermined exposure period before the start of the period T2. This exposure is performed by a mechanical shutter (not shown) after a so-called global reset that resets all pixels at the same time during normal main shooting (still image shooting), and during electronic viewfinder mode or movie shooting. This is performed by a so-called rolling electronic shutter operation. Immediately before the start of the period T2, the transistors SEL, RST, TXA, and TXB in all rows are turned off.

  In the period T2, φSEL (n) and φSEL (n−1) in the nth and n−1th rows are set to H, and the pixel blocks BL (n) and BL (n (n) in the nth and n−1th rows are set. -1) selection transistors SEL (n) and SEL (n-1) are turned on, and pixel blocks BL (n) and BL (n-1) in the nth and n-1th rows are selected.

  In period T2, φSW (n) and φSW (n−1) are set to L, and the n-th and n−1-th row connecting transistors SW (n) and SW (n−1) are turned off. As described above, the capacitance values of the charge-voltage conversion capacitors at the nodes P (n) and P (n−1) are Cfd1, which is the minimum.

  ΦRST (n) and φRST (n−1) are set to H only for a certain period immediately after the start of the period T2, and the reset transistors RST (n) and RST (n−1) in the nth and n−1th rows are set. Once turned on, the potentials of the nodes P (n) and P (n−1) are once reset to the power supply potential VDD.

  After the time point t1 in the period T2, the dark signal sampling signal φDARKC is set to H for a certain period and the potential appearing at the node P (n) is amplified by the amplification transistor AMP (n) in the nth row, and then the selection transistor A signal amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 (m) is further sampled by the CDS circuit 31 as a dark signal. At the same time, after the potential appearing at the node P (n−1) is amplified by the amplification transistor AMP (n−1) in the n−1th row, the selection transistor SEL (n−1), the vertical signal line 28 (m + 1), etc. The signal further amplified by the column amplifier 30 is sampled by the CDS circuit 31 as a dark signal.

  ΦTXA (n) and φTXA (n−1) are set to H for a certain period from the subsequent time t2 in the period T2, and the transfer transistors TXA (n) and TXA (n−) in the nth and n−1th rows are set to H. 1) is turned on. As a result, the signal charge accumulated in the photodiode PDA (n) of the pixel block BL (n) in the n-th row is transferred to the charge-voltage conversion capacitor at the node P (n). When the noise component is excluded, the potential of the node P (n) becomes a value proportional to the amount of the signal charge and the inverse of the capacitance value of the charge-voltage conversion capacitor of the node P (n). At the same time, the signal charge accumulated in the photodiode PDA (n−1) of the pixel block BL (n−1) in the n−1th row is transferred to the charge-voltage conversion capacitor of the node P (n−1). . The potential of the node P (n−1) is a value proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge voltage conversion capacitor of the node P (n−1), excluding the noise component.

  At a subsequent time t3 in the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the node P (n) is amplified by the amplification transistor AMP (n) in the nth row, and then the selection transistor SEL (n ) And the vertical signal line 28 (m) and the like, and the signal further amplified by the column amplifier 30 is sampled by the CDS circuit 31 as an optical signal. At the same time, after the potential appearing at the node P (n−1) is amplified by the amplification transistor AMP (n−1) in the n−1th row, the selection transistor SEL (n−1), the vertical signal line 28 (m + 1), etc. The signal further amplified by the column amplifier 30 is sampled by the CDS circuit 31 as an optical signal.

  Thereafter, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from time t1 and the optical signal sampled in a certain time from time t3. . The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital signal image signal.

  Then, φRST (n) and φRST (n−1) are set to H for a certain period from the time point t4 in the period T2, and the reset transistors RST (n) and RST (n− in the n-th and n−1-th rows are set. 1) is once turned on, and the potentials of the nodes P (n) and P (n−1) are once reset to the power supply potential VDD.

  After the time t5 in the period T2, the dark signal sampling signal φDARKC is set to H for a certain period, and the potential appearing at the node P (n) is amplified by the n-th amplification transistor AMP (n) and then the selection transistor A signal amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 (m) is further sampled by the CDS circuit 31 as a dark signal. At the same time, after the potential appearing at the node P (n−1) is amplified by the amplification transistor AMP (n−1) in the n−1th row, the selection transistor SEL (n−1), the vertical signal line 28 (m + 1), etc. The signal further amplified by the column amplifier 30 is sampled by the CDS circuit 31 as a dark signal.

  ΦTXB (n) and φTXB (n−1) are set to H for a certain period from the subsequent time point t6 in the period T2, and the transfer transistors TXB (n) and TXB (n−) in the nth and n−1th rows are set to H. 1) is turned on. As a result, the signal charge accumulated in the photodiode PDB (n) of the pixel block BL (n) in the n-th row is transferred to the charge-voltage conversion capacitor at the node P (n). When the noise component is excluded, the potential of the node P (n) becomes a value proportional to the amount of the signal charge and the inverse of the capacitance value of the charge-voltage conversion capacitor of the node P (n). At the same time, the signal charge accumulated in the photodiode PDB (n−1) of the pixel block BL (n−1) in the n−1th row is transferred to the charge-voltage conversion capacitor of the node P (n−1). . The potential of the node P (n−1) is a value proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge voltage conversion capacitor of the node P (n−1), excluding the noise component.

  At a subsequent time t7 in the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the node P (n) is amplified by the n-th amplification transistor AMP (n) and then the selection transistor SEL (n ) And the vertical signal line 28 (m) and the like, and the signal further amplified by the column amplifier 30 is sampled by the CDS circuit 31 as an optical signal. At the same time, after the potential appearing at the node P (n−1) is amplified by the amplification transistor AMP (n−1) in the n−1th row, the selection transistor SEL (n−1), the vertical signal line 28 (m + 1), etc. The signal further amplified by the column amplifier 30 is sampled by the CDS circuit 31 as an optical signal.

  Thereafter, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from time t5 and the optical signal sampled in a certain time from time t7. . The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital signal image signal.

  In this way, in the first operation mode, since the connection transistors SW (n) and SW (n−1) are turned off, the charge-voltage conversion capacitors at the nodes P of the selected two rows of pixel blocks BL. , And the charge-voltage conversion coefficient due to the charge-voltage conversion capacitor becomes large, so that reading with the highest SN ratio becomes possible. For example, when the ISO sensitivity setting value is high, the imaging control unit 5 instructs to perform the first operation mode.

  FIG. 8 is a timing chart showing a second operation mode of the solid-state imaging device 4 shown in FIG. In the second operation mode, each pixel block BL is sequentially selected every two rows, and the connected transistors SW of the selected pixel blocks BL in the two rows and the wiring transistors 71 connected thereto are connected to each other. In a state where the connected transistor SW is turned on (a state where the charge-voltage conversion capacity of the node P is large), the transfer transistors TXA and TXB of the selected pixel blocks BL in the two rows are sequentially turned on and selected. This is an example of an operation of sequentially reading out the signals of the photodiodes PDA and PDB of the pixel blocks BL in the two rows that are read out every two rows.

  In FIG. 8, similarly to FIG. 7, the pixel blocks BL (n−2) and BL (n−3) in the n−2 and n−3th rows are selected in the period T1, and the n th row is selected in the period T2. The pixel blocks BL (n) and BL (n−1) in the (n−1) th row are selected, and the pixel blocks BL (n + 2) and BL (n + 1) in the (n + 2) th row and the (n + 1) th row are selected in the period T3. Shows the situation. The second operation mode shown in FIG. 8 is different from the first operation mode shown in FIG. 7 in the following points.

  In the example shown in FIG. 8, in this second operation mode, φSW of all rows is set to H and all the connecting transistors SW of all rows are turned on over the entire period. Thereby, in the period T2, φSW (n), φSW (n−1), φSW (n + 2), and φSW (n + 1) are set to H, and the nth, n−1th, n + 2th, and n + 1th rows. The connected transistors SW (n), SW (n−1), SW (n + 2), and SW (n + 1) are turned on. Therefore, as described above, the capacitance values of the charge-voltage conversion capacitors of the nodes P (n) and P (n−1) are 2 × Cfd1 + 2 × Csw + 2 × Cfd2 + Cfd3, which is compared with the first operation mode shown in FIG. Become bigger.

  Here, the period T2 in which the pixel blocks BL (n) and BL (n-1) in the n-th row and the (n-1) -th row are selected has been described, but the same applies to the period in which other pixel blocks BL are selected. It is.

  As described above, in the second operation mode, the capacitance value of the charge-voltage conversion capacitor at the node P of the selected pixel block BL is increased, and the number of saturated electrons in the charge-voltage conversion capacitor at the node P can be increased. it can. Thereby, the dynamic range can be expanded. For example, when the ISO sensitivity setting value is small, the imaging control unit 5 instructs to perform the second operation mode.

  For example, the control signal φSW is configured to be supplied independently for each row, and φSW (n) and φSW (n + 1) are set to H in the period T2, while φSW (n + 2) and φSW (n -1) is set to L, and the connection transistors SW (n) and SW (n + 1) in the nth and n + 1th rows are turned on, while the connection transistors SW (n + 2) in the n + 2th and n−1th rows are turned on. SW (n-1) may be turned off and the same may be done for other periods. In this case, the capacitance values of the charge-voltage conversion capacitors of the nodes P (n) and P (n−1) are Cfd1 + Csw + 2 × Cfd2 + Cfd3, which is larger than that in the first operation mode shown in FIG. 8 and shown in FIG. It becomes smaller than the second operation mode.

  Here, a solid-state image sensor 94 according to a comparative example compared with the solid-state image sensor 4 in the present embodiment will be described. FIG. 9 is a circuit diagram showing a schematic configuration of the solid-state imaging device 94 according to this comparative example, and corresponds to FIG. FIG. 10 is a diagram schematically showing the relationship between the pixel block BL and the photodiode PD of the solid-state imaging device 94 shown in FIG. 9, and corresponds to FIG. FIG. 11 is a schematic plan view schematically showing the vicinity of the four pixel blocks BL in FIG. 10, and corresponds to FIG. 9 to 11, elements that are the same as or correspond to those in FIGS. 2, 4, and 5 are given the same reference numerals, and redundant descriptions thereof are omitted. This comparative example is different from the present embodiment mainly in the points described below.

  In this comparative example, each pixel block BL has two photodiodes PD (PDA, PDB) sequentially arranged in the column direction, and is arranged in a two-dimensional matrix. In this comparative example, the matrix of the pixel block BL is defined as it is as the matrix of the pixel block BL itself, and two rows of the photodiodes PD correspond to one row of the pixel block BL, and n is a row of the pixel block BL. M represents a column of the pixel block BL.

  In this comparative example, the drain of the connection transistor SW of each pixel block BL is electrically connected to the node P of the pixel block BL adjacent on one side in the column direction.

  In this comparative example, the gate of the transfer transistor TXA is commonly connected to the control line 26 for each row, and a control signal φTXA is supplied from the vertical scanning circuit 21 to the gate. The gate of the transfer transistor TXB is commonly connected to the control line 25 for each row, and a control signal φTXB is supplied from the vertical scanning circuit 21 to the gate. The gates of the reset transistors RST are commonly connected to the control line 24 for each row, and a control signal φRST is supplied from the vertical scanning circuit 21 there. The gates of the selection transistors SEL are connected in common to the control line 23 for each row, and a control signal φSEL is supplied from the vertical scanning circuit 21 there. The gates of the connection transistors SW are commonly connected to the control line 27 for each row, and a control signal φSW is supplied thereto from the vertical scanning circuit 21.

  Also in this comparative example, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and each element in the pixel block BL such as the photodiode PD is arranged in the P-type well. Yes. In FIG. 11, reference numerals 101 to 108 denote N-type impurity diffusion regions that are part of each transistor. Reference numerals 111 to 116 denote gate electrodes of the respective transistors made of polysilicon. The diffusion region 105 is a region to which the power supply voltage VDD is applied by a power supply line (not shown).

  In this comparative example, the transfer transistor TXA (n) of the pixel block BL (n, m) is an nMOS transistor having the charge storage layer of the photodiode PDA (n) as the source, the diffusion region 101 as the drain, and the gate electrode 111 as the gate. It is. The transfer transistor TXB (n) of the pixel block BL (n, m) is an nMOS transistor having the charge storage layer of the photodiode PDB (n) as a source, the diffusion region 102 as a drain, and the gate electrode 112 as a gate.

  In this comparative example, the amplification transistor AMP (n) of the pixel block BL (n, m) is an nMOS transistor having the diffusion region 105 as a drain, the diffusion region 104 as a source, and the gate electrode 114 as a gate. The reset transistor RST (n) of the pixel block BL (n, m) is an nMOS transistor having the diffusion region 106 as a source, the diffusion region 105 as a drain, and the gate electrode 115 as a gate. The selection transistor SEL (n) of the pixel block BL (n, m) is an nMOS transistor having the diffusion region 104 as a drain, the diffusion region 103 as a source, and the gate electrode 113 as a gate. The diffusion region 103 is connected to the vertical signal line 28 (m). The connection transistor SW (n) of the pixel block BL (n, m) is an nMOS transistor having the diffusion region 107 as a source, the diffusion region 108 as a drain, and the gate electrode 116 as a gate. The diffusion regions 101, 102, 106, 107 and the gate electrode 114 of the pixel block BL (n, m) and the diffusion region 108 of the pixel block BL (n−1, m) are electrically connected to each other by the wiring 121. Yes. The diffusion region 108 of the pixel block BL (n, m) is electrically connected to the diffusion regions 101, 102, 106, 107 and the gate electrode 114 of the pixel block BL (n + 1, m) by the wiring 121.

  In this comparative example, the structure of the pixel block BL other than the n-th row and the m-th column is the same as the structure of the pixel block BL (n, m) in the n-th row and the m-th column.

  In FIG. 9, FC (n) is a capacitance between the node P (n) and the reference potential when the connection transistors SW (n) and SW (n−1) are off. Let Cfd1 'be the capacitance value of the capacitor FC (n). The same applies to the rows of other pixel blocks BL.

  The capacitance FC (n) in this comparative example is the capacitance of the diffusion region 101 of the transfer transistor TXA (n), the capacitance of the diffusion region 102 of the transfer transistor TXB (n), and the diffusion region 106 of the reset transistor RST (n). The capacitance of the diffusion region 107 of the coupling transistor SW (n), the capacitance of the diffusion region 108 of the coupling transistor SW (n−1), the capacitance of the gate electrode 114 of the amplification transistor AMP (n), and the wiring 121 The total of these capacitance values is the capacitance value Cfd1 ′ of the capacitance FC (n). The same applies to the rows of other pixel blocks BL. Since the length of the wiring 121 in FIG. 11 must be considerably longer than the length of the wiring 71 in FIG. 5, the wiring capacity of the wiring 121 is considerably larger than the wiring capacity of the wiring 71.

  On the other hand, the capacitance FC (n) in the present embodiment is the diffusion region 41 of the transfer transistors TXA (n), TXB (n), the reset transistor RST (n), and the connection transistor SW (n) as described above. , The capacitance of the gate electrode 64 of the amplification transistor AMP (n), and the wiring capacitance of the wiring 71, and the total of these capacitance values is the capacitance value Cfd1 of the capacitance FC (n).

  Accordingly, the capacitance value Cfd1 of the capacitance FC (n) in the present embodiment is equivalent to the capacitance of the capacitance corresponding to four diffusion regions and the wiring than the capacitance value Cfd1 ′ of the capacitance FC (n) in this comparative example. It becomes smaller by subtracting the wiring capacity of the wiring 71 from the wiring capacity of 121.

  In this comparative example, paying attention to the pixel block BL (n), when both of the connection transistors SW (n) and SW (n−1) are turned off, the capacitance (charge) between the node P (n) and the reference potential. The voltage conversion capacity) is the capacity FC (n), the capacitance value of the charge voltage conversion capacity of the node P (n) is the minimum Cfd1 ′, and the charge voltage conversion coefficient by the charge voltage conversion capacity is increased, so that the highest SN The ratio can be read out. Further, in this comparative example, when one or both of the connection transistors SW (n) and SW (n−1) are turned on, the capacitance value of the charge-voltage conversion capacitance at the node P (n) increases, and a large signal charge is generated. Since the quantity can be handled, the number of saturated electrons can be increased. Thereby, the dynamic range can be expanded.

  As described above, the minimum capacitance value Cfd1 of the charge-voltage conversion capacitance of the node P (n) in this embodiment is smaller than the minimum capacitance value Cfd1 ′ of the charge-voltage conversion capacitance of the node P (n) in this comparative example. Also, the size is reduced by the amount corresponding to the four transistor diffusion capacitors and the wiring capacity of the wiring 121 minus the wiring capacity of the wiring 71. Therefore, according to the present embodiment, the charge-voltage conversion coefficient is further increased as compared with this comparative example, and reading at a higher SN ratio is possible.

  Further, in the present embodiment, since the wiring 71 is composed of the lowermost wiring layer, the wiring capacity of the wiring 71 is smaller than when the wiring is composed of two or more wiring layers. Therefore, according to the present embodiment, also from this point, the charge-voltage conversion coefficient is further increased, and reading at a higher SN ratio is possible.

  Furthermore, in the present embodiment, as shown in FIGS. 5 and 6, the wiring 71 is adjacent to the vertical signal line 28. Parasitic capacitance is generated between the wiring 71 and surrounding wiring, and the wiring capacity of the wiring 71 is approximately expressed by the following equation.

  [Wiring capacitance of wiring 71 = parasitic capacitance with wiring supplying control signal φTXA + parasitic capacitance with wiring supplying control signal φTXB + parasitic capacitance with wiring supplying control signal φRST + wiring supplying control signal φSW Parasitic capacitance with power supply line + parasitic capacitance with ground line + (1-G) × parasitic capacitance with vertical signal line 28]

  The capacitance value Cfd1 of the capacitor FC in the present embodiment appears to be small due to the gain G of the source follower circuit formed by the amplification transistor AMP. Therefore, according to the present embodiment, from this point as well, the charge-voltage conversion coefficient is further increased, and reading at a higher SN ratio is possible.

  Each operation example described with reference to FIGS. 7 and 8 is an example of an operation of reading the signal charge of the photodiode PD of each pixel PX without mixing with the signal charge of the photodiode PD of the other pixel PX. Met. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be mixed and read with the signal charge of the photodiode PD of another pixel PX of the same color. In this case, two or more transfer transistors TX are simultaneously turned on during charge mixing.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to this embodiment.

  For example, in the embodiment, as described above, for each of the two pixel blocks BL, the other source / drain (drain in this embodiment) of the connection transistor SW of the two pixel blocks BL is electrically connected to each other. It is connected to the. However, in the present invention, for each of the three or more pixel blocks BL, the other source / drain of the connection transistor SW of the three or more pixel blocks BL may be electrically connected to each other. In this case, for example, the drain of the connection transistor SW (n) of the pixel block BL (n, m), the drain of the connection transistor SW (n + 2) of the pixel block BL (n + 2, m), and the pixel block BL (n + 4, m). The drains of the connection transistor SW (n + 4) are electrically connected to each other, the drain of the connection transistor SW (n−1) of the pixel block BL (n−1, m + 1), and the connection transistor SW of the pixel block BL (n + 1, m + 1). The drain of (n + 1) and the drain of the connection transistor SW (n + 1) of the pixel block BL (n + 3, m + 1) may be electrically connected to each other.

4 Solid-state imaging device BL Pixel block PXA, PXB Pixel PDA, PDB Photodiode TXA, TXB Transfer transistor P node AMP Amplification transistor SW Link transistor RST Reset transistor

Claims (9)

A first photoelectric conversion unit and a second photoelectric conversion unit that generate charge by converting light into a charge;
A first node to which charges generated by the first photoelectric conversion unit are transferred;
A second node to which the charge generated by the second photoelectric conversion unit is transferred;
A first transfer transistor that transfers the charge generated by the first photoelectric conversion unit to the first node;
A first connection transistor capable of connecting the first node and the second node;
A second connection transistor capable of connecting the first node and the second node ;
A drain of the first transfer transistor and a source of the first connection transistor are shared ;
Before Symbol The first node and the second node, the first connection transistor and the second coupling transistor and the imaging device that will be connected through. The imaging device according to claim 1,
A third photoelectric conversion unit for generating charge by converting light into charge;
A third transfer transistor that transfers the charge generated by the third photoelectric conversion unit to the first node;
An image sensor in which a drain of the third transfer transistor and a source of the first connection transistor are shared. The image sensor according to claim 1 or 2,
A reset transistor for resetting the potential of the first node to a predetermined potential;
An imaging device in which a drain of the first transfer transistor and a source of the reset transistor are shared. The imaging device according to any one of claims 1 to 3 ,
A second transfer transistor configured to transfer the charge generated by the second photoelectric conversion unit to the second node;
An imaging device in which a drain of the second transfer transistor and a source of the second connection transistor are shared. The imaging device according to any one of claims 1 to 4 ,
The first photoelectric conversion unit and the second photoelectric conversion unit are arranged in a first direction,
The first transfer transistor and the first connection transistor are image sensors arranged in the first direction. The imaging device according to claim 2,
The first photoelectric conversion unit and the third photoelectric conversion unit are arranged in a first direction,
The imaging device, wherein the first transfer transistor and the first connection transistor are arranged in a second direction intersecting the first direction. The imaging device according to claim 3,
The first photoelectric conversion unit and the second photoelectric conversion unit are arranged in a first direction,
The imaging device in which the first transfer transistor and the reset transistor are arranged in the first direction. The image pickup device according to claim 7 ,
The imaging device in which the first connection transistor, the first transfer transistor, and the reset transistor are sequentially arranged in the first direction. Imaging apparatus including an imaging device according to any one of claims 1-8.

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