JP6825675B2 - Image sensor and image sensor - Google Patents

Description

The present invention relates to a solid-state image pickup device and an image pickup device using the same.

The following Patent Document 1 describes a plurality of pixels including a plurality of pixels, each of which includes (a) a photodetector, (b) a charge-voltage conversion region forming a floating capacitance portion, and (c) an input portion to an amplifier. And a solid-state image sensor including a connection switch that selectively connects the charge-voltage conversion regions to each other are disclosed.

Japanese Patent Publication No. 2008-546313

In the conventional solid-state image sensor, by turning on the connection switch and connecting the charge-voltage conversion regions to each other, the number of saturated electrons in the entire connected charge-voltage conversion regions is expanded, so that the dynamic range is increased. It can be expanded.

Further, in the conventional solid-state imaging device, by turning off the connection switch and separating the charge-voltage conversion region from the other charge-voltage conversion region, the charge-voltage conversion capacity becomes smaller and the charge-voltage conversion coefficient becomes larger. Therefore, the SN ratio at the time of high-sensitivity reading becomes high.

However, in the conventional solid-state image sensor, even if the connection switch is turned off, the SN ratio at the time of high-sensitivity reading cannot be increased so much.

The present invention has been made in view of such circumstances, and is a solid-state image sensor capable of expanding the dynamic range and improving the SN ratio at the time of high-sensitivity reading, and imaging using the solid-state image sensor. The purpose is to provide the device.

The following aspects are presented as means for solving the above problems. The solid-state imaging device according to the first aspect is provided corresponding to one photoelectric conversion unit, the first node, and the one photoelectric conversion unit, and transfers charges from the photoelectric conversion unit to the first node. A plurality of pixel blocks having one transfer switch, two second nodes corresponding to the first node of the pixel block and the first node of the other pixel block, and the above. Two first nodes that electrically connect and disconnect between the first node of one pixel block and the first node of the other one pixel block and the two second nodes, respectively. A switch unit, a second switch unit that electrically connects and disconnects between the two second nodes, and two third switch units that supply predetermined potentials to the two second nodes, respectively. It is equipped with.

The pixel block may have only one photoelectric conversion unit and be composed of one pixel, or may have two or more photoelectric conversion units and be composed of a plurality of pixels. Good. This point is the same for each aspect described later.

In the solid-state image sensor according to the second aspect, in the first aspect, each pixel block has a plurality of the photoelectric conversion unit and the transfer switch.

In the first or second aspect, the solid-state image sensor according to the third aspect has the first node of the one pixel block and the corresponding second node in the first operation mode. The first switch unit that electrically connects and disconnects the space is turned on only when the potential of the first node of the one pixel block is reset, and the first switch unit of the one pixel block is turned on. Each of the first switches so that the third switch unit that supplies the predetermined potential to the second node corresponding to the node is turned on at least when the potential of the first node of the one pixel block is reset. The switch unit and the control unit that controls each of the third switch units are provided.

In the third aspect, the solid-state image sensor according to the fourth aspect has the control unit, in the second operation mode, the first node of the one pixel block and the corresponding second node. The first switch unit that electrically connects and disconnects from the first switch unit is turned on, the second switch unit is turned off, and the second switch unit corresponding to the first node of the one pixel block is turned on. The first switch unit, the second switch unit, so that the third switch unit that supplies the predetermined potential to the node is turned on only when the potential of the first node of the one pixel block is reset. The switch unit and each of the third switch units are controlled.

In the third or fourth aspect of the solid-state image sensor according to the fifth aspect, the control unit performs the first node of the one pixel block and the corresponding first node in the third operation mode. The first switch unit that electrically connects and disconnects from the two nodes is turned on, the second switch unit is turned on, and corresponds to the first node of the one pixel block. Each of the first switch units, such that the third switch unit that supplies the predetermined potential to the second node is turned on only when the potential of the first node of the one pixel block is reset. It controls the second switch unit and each of the third switch units.

In the first or second aspect, the solid-state image sensor according to the sixth aspect includes the first node of three or more pixel blocks of the plurality of pixel blocks and the three or more of the first nodes thereof. The three or more first switch portions are provided, respectively, for electrically connecting and disconnecting the electrical connection between the three or more second nodes corresponding to one node. The second node is connected in a string by a plurality of the second switch portions, and the three or more third switch portions that supply the predetermined potential to the three or more second nodes are provided. It is prepared.

In the sixth aspect, the solid-state image sensor according to the seventh aspect corresponds to the first node of one pixel block of the three or more pixel blocks in the first operation mode. Only when the first switch unit that electrically connects and disconnects from the second node resets the potential of the first node of the one pixel block among the three or more pixel blocks. The third switch unit, which is turned on once and supplies the predetermined potential to the second node corresponding to the first node of the one pixel block among the three or more pixel blocks, The first switch unit and the third switch unit are controlled so as to be turned on at least when the potential of the first node of the one pixel block among the three or more pixel blocks is reset. It is equipped with a control unit.

The solid-state imaging device according to the eighth aspect has the same control unit as the first node of one of the three or more pixel blocks in the second operation mode in the seventh aspect. The first switch unit that electrically connects and disconnects from the second node corresponding to this is turned on, and the first of the one pixel block among the three or more pixel blocks is turned on. The first switch unit of the one pixel block of the three or more pixel blocks is turned off and the second switch unit electrically connected to the second node corresponding to the node is turned off. When the third switch unit that supplies the predetermined potential to the second node corresponding to the node resets the potential of the first node of the one pixel block among the three or more pixel blocks. It controls the first switch unit, the second switch unit, and the third switch unit so that only the first switch unit is turned on.

In the seventh or eighth aspect of the solid-state imaging device according to the ninth aspect, the control unit has the first pixel block of one of the three or more pixel blocks in the third operation mode. The first switch unit that electrically connects and disconnects between the node and the corresponding second node is turned on, and the pixel block of the one pixel block among the three or more pixel blocks is turned on. The second switch unit electrically connected to the second node corresponding to the first node is turned on, and the pixel block of the one pixel block among the three or more pixel blocks is said. The third switch unit that supplies the predetermined potential to the second node corresponding to the first node is the potential of the first node of the one pixel block among the three or more pixel blocks. The first switch unit, the second switch unit, and the third switch unit are controlled so as to be turned on only at the time of resetting.

The image pickup device according to the tenth aspect includes the solid-state image pickup device according to any one of the first to ninth aspects.

The image pickup device according to the eleventh aspect is a control that switches between the solid-state image pickup device according to the third, fourth, fifth, seventh, eighth, or ninth aspect and each of the operation modes according to the ISO sensitivity setting value. It is equipped with means.
The following aspects are also presented as means for solving the above problems. The image pickup element based on the first surface is an image pickup element including a plurality of pixel blocks arranged side by side in the column direction, and the pixel blocks include a plurality of photoelectric conversion units that convert light into charges and the plurality of pixel blocks. A first node unit to which charges from the photoelectric conversion unit are transferred, a second node unit different from the first node unit, and a second node unit that controls the connection between the first node unit and the second node unit. The first switch unit, the second switch unit that controls the connection between the second node unit and the second node unit of the other pixel blocks arranged adjacent to the plurality of pixel blocks, and the above. It has a third switch unit that controls the connection between the second node unit and the supply unit to which a predetermined voltage is supplied.
The image sensor with the second surface is the image sensor with the first surface, in which the first node unit is connected to the supply unit via the first switch unit and the third switch unit. ..
The image sensor with the third surface is the image sensor with the first or second surface, and the second node portion has wiring connected to the first switch portion and the second switch portion. ..
The image sensor using the fourth surface is the image sensor using any of the first to third surfaces, and the first switch unit outputs a control signal for controlling the first switch unit. The second switch unit is connected to a control line, the second switch unit is connected to a second control line from which a control signal for controlling the second switch unit is output, and the third switch unit connects the third switch unit. It is connected to a third control line from which a control signal for control is output.
The image pickup element based on the fifth surface is the image pickup element based on the fourth surface, wherein the first node section has a diffusion region to which charges from the plurality of photoelectric conversion sections are transferred, and the first switch section. Has a first transistor including a gate electrode connected to the first control line, and the second switch unit has a second transistor including a gate electrode connected to the second control line. The gate electrode of the first transistor is arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the second transistor to the diffusion region.
The image sensor with the sixth surface is the image sensor with the fifth surface, wherein the third switch unit has a third transistor including a gate electrode connected to the third control line, and the first transistor. The gate electrode of the above is arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the third transistor to the diffusion region.
The image pickup device based on the seventh surface is the image pickup device based on the fifth or sixth surface, wherein the pixel block has an amplification transistor including a gate electrode connected to the first node portion, and the first transistor. The gate electrode of the above is arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the amplification transistor to the diffusion region.
The image sensor with the eighth surface is the image sensor with any of the fifth to seventh surfaces, and the pixel block is connected to a signal line that outputs a signal based on the charge of the first node portion. The gate electrode of the first transistor is arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the selection transistor to the diffusion region. ..
The image pickup element based on the ninth surface is the image pickup element based on the fourth surface, wherein the first node section has a diffusion region to which charges from the plurality of photoelectric conversion sections are transferred, and the first switch section. Has a first transistor including a gate electrode connected to the first control line, and the third switch unit has a third transistor including a gate electrode connected to the third control line. The gate electrode of the first transistor is arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the third transistor to the diffusion region.
The image sensor with the tenth surface is the image sensor with the ninth surface, wherein the pixel block has an amplification transistor including a gate electrode connected to the first node portion, and the gate electrode of the first transistor. Is arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the amplification transistor to the diffusion region.
The image sensor using the eleventh surface controls the connection between the pixel block and the signal line that outputs a signal based on the charge of the first node portion in the image sensor using the ninth or tenth surface. The gate electrode of the first transistor having a selection transistor is arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the selection transistor to the diffusion region.
The image pickup element based on the twelfth surface is the image pickup element based on the fourth surface, wherein the pixel block has an amplification transistor including a gate electrode connected to the first node portion, and the first node portion includes an amplification transistor. The first switch unit has a diffusion region to which charges from the plurality of photoelectric conversion units are transferred, and the first switch unit has a first transistor including a gate electrode connected to the first control line, and the first transistor. The gate electrode of the above is arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the amplification transistor to the diffusion region.
The image sensor with the thirteenth surface is the image sensor with the twelfth surface, and the pixel block is a selection transistor that controls a connection with a signal line that outputs a signal based on the charge of the first node portion. The gate electrode of the first transistor is arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the selection transistor to the diffusion region.
The image pickup element by the fourteenth plane is the image pickup element by the fourth plane, in which the pixel block controls the connection with the signal line which outputs the signal based on the charge of the first node portion. The first node unit has a diffusion region to which charges from the plurality of photoelectric conversion units are transferred, and the first switch unit includes a gate electrode connected to the first control line. The gate electrode of the first transistor having one transistor is arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the selection transistor to the diffusion region.
The image pickup device using the fifteenth surface includes an image pickup device using any of the first to fourteenth surfaces.

According to the present invention, it is possible to provide a solid-state image sensor capable of expanding the dynamic range and improving the SN ratio at the time of high-sensitivity reading, and an image pickup device using the solid-state image sensor.

It is a schematic block diagram which shows typically the electronic camera by 1st Embodiment of this invention. It is a circuit diagram which shows the schematic structure of the solid-state image pickup device in FIG. It is a circuit diagram which enlarges and shows the vicinity of four pixel blocks in FIG. It is a schematic plan view which shows typically the vicinity of three pixel blocks in FIG. It is a schematic plan view which shows the vicinity of one pixel block in FIG. 4 enlarged. It is a timing chart which shows the predetermined operation mode of the solid-state image sensor shown in FIG. It is a timing chart which shows other operation modes of the solid-state image sensor shown in FIG. It is a timing chart which shows the other operation mode of the solid-state image sensor shown in FIG. It is a timing chart which shows the other operation mode of the solid-state image sensor shown in FIG. It is a timing chart which shows the other operation mode of the solid-state image sensor shown in FIG. It is a circuit diagram which shows the vicinity of three pixel blocks of the solid-state image pickup device by a comparative example. 9 is a schematic plan view schematically showing the vicinity of the three pixel blocks shown in FIG. It is a circuit diagram which shows the schematic structure of the solid-state image sensor of the electronic camera by the 2nd Embodiment of this invention.

Hereinafter, the solid-state image pickup device and the image pickup apparatus according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic block diagram schematically showing an electronic camera 1 according to the first embodiment of the present invention.

The electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera, but the imaging device according to the present invention is not limited to this, and is mounted on other electronic cameras such as compact cameras and mobile phones. It can be applied to various imaging devices such as electronic cameras and electronic cameras such as video cameras that capture moving images.

A photographing lens 2 is attached to the electronic camera 1. The focus and aperture of the photographing lens 2 are driven by the lens control unit 3. The image pickup surface of the solid-state image pickup device 4 is arranged in the image space of the photographing lens 2.

The solid-state image sensor 4 is driven by a command from the image pickup control unit 5 and outputs a digital image signal. During normal main shooting (still image shooting), for example, the image sensor 5 performs a predetermined readout operation after exposure with a mechanical shutter (not shown) after a so-called global reset that resets all pixels at the same time. The solid-state image sensor 4 is controlled. Further, in the electronic viewfinder mode or when shooting a moving image, the image pickup control unit 5 controls the solid-state image sensor 4 so as to perform a predetermined readout operation while performing, for example, a so-called rolling electronic shutter. At these times, the image pickup control unit 5 controls the solid-state image sensor 4 so as to perform the read operation of each operation mode described later according to the setting value of the ISO sensitivity, as will be described later. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on the digital image signal output from the solid-state image sensor 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. A lens control unit 3, an imaging control unit 5, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like are also connected to the bus 8. An operation unit 14 such as a release button is connected to the CPU 9. The ISO sensitivity can be set by the operation unit 14. A recording medium 11a is detachably attached to the recording unit 11.

The CPU 9 in the electronic camera 1 drives the image pickup control unit 5 in accordance with an instruction such as an electronic viewfinder mode, moving image shooting, or normal main shooting (still image shooting) by the operation of the operation unit 14. At this time, the lens control unit 3 appropriately adjusts the focus and the aperture. The solid-state image sensor 4 is driven by a command from the image pickup control unit 5 and outputs a digital image signal. The digital image signal from the solid-state image sensor 4 is processed by the digital signal processing unit 6 and then stored in the memory 7. The CPU 9 causes the display unit 10 to display the image signal in the electronic viewfinder mode, and records the image signal in the recording medium 11a when shooting a moving image. In the case of normal main shooting (still image shooting) or the like, the CPU 9 performs the operation unit 14 after the digital image signal from the solid-state image sensor 4 is processed by the digital signal processing unit 6 and stored in the memory 7. The image processing unit 13 and the image compression unit 12 perform desired processing as necessary, and the recording unit 11 outputs the processed signal and records the processed signal on the recording medium 11a.

FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state image sensor 4 in FIG. FIG. 3 is an enlarged circuit diagram showing the vicinity of the four pixel blocks BL sequentially arranged in the column direction in FIG. FIG. 4 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL in FIG. FIG. 5 is a schematic plan view showing the vicinity of one pixel block BL in FIG. 4 in an enlarged manner. In the present embodiment, the solid-state image sensor 4 is configured as a CMOS-type solid-state image sensor, but is not limited to this, and may be configured as, for example, another XY address-type solid-state image sensor.

As shown in FIGS. 2 to 4, the solid-state imaging device 4 has a pixel block BL arranged in N rows and M columns in a two-dimensional matrix and each having two pixels PX (PXA, PXB), and a first described later. The first transistor SWA as a first switch unit that electrically connects and disconnects between the node Pa and the corresponding second node Pb and the two second nodes Pb are electrically connected. A second transistor SWB as a second switch unit to be disconnected, a reset transistor RST as a third switch unit that supplies a power supply voltage VDD as a predetermined potential to the second node Pb, and a vertical scanning circuit 21. , Signals from the control lines 22 to 27 provided for each row of the pixel block BL and the pixels PX (pixel block BL) of the corresponding columns provided for each column of the pixel PX (for each column of the pixel block BL). A plurality of (M) vertical signal lines 28 to be received, a constant current source 29 provided in each vertical signal line 28, a column amplifier 30 provided corresponding to each vertical signal line 28, and a CDS circuit (correlation 2). It has a heavy sampling circuit) 31 and an A / D converter 32, and a horizontal readout circuit 33.

As the column amplifier 30, an analog amplifier may be used, or a so-called switched capacitor amplifier may be used. Further, the column amplifier 30 does not necessarily have to be provided.

For convenience of drawing notation, although it is shown as M = 2 in FIG. 2, the number of columns M is actually a larger arbitrary number. Further, the number of lines N is not limited. When the pixel block BL is distinguished for each row, the pixel block BL on the jth row is indicated by the reference numeral BL (j). This point also applies to other elements and control signals described later. 2 and 3 show pixel blocks BL (n-1) to BL (n + 2) in the n-1th row to the n + 2nd row over four rows.

In the drawings, the reference numerals of the lower pixels in FIGS. 2 and 3 of the pixel block BL are referred to as PXA, and the reference numerals of the upper pixels in FIGS. 2 and 3 are referred to as PXB. When the explanation is made without distinction, both may be described by adding a reference numeral PX. Further, in the drawings, the code of the photodiode of the pixel PXA is PDA, and the code of the photodiode of the pixel PXB is PDB, and the two are distinguished. However, when the explanation is made without distinguishing between the two, the code PD is added to both. May be explained. Similarly, the code of the transfer transistor of the pixel PXA is TXA, and the code of the transfer transistor of the pixel PXB is TXB, and the two are distinguished. However, when the description is made without distinguishing between the two, the code TX is added to both. In some cases. In the present embodiment, the photodiode PDs of the pixels PX are arranged in a 2N row and M column in a two-dimensional matrix.

In the present embodiment, each pixel PX has a photodiode PD as a photoelectric conversion unit that generates and stores a signal charge according to the incident light, and a transfer switch that transfers the charge from the photodiode PD to the first node Pa. It has a transfer transistor TX of.

In the present embodiment, the plurality of pixels PX form a pixel block BL for each of two pixel PXs (PXA, PXB) in which photodiode PDs are sequentially arranged in the column direction. As shown in FIGS. 2 and 3, for each pixel block BL, two pixels PX (PXA, PXB) belonging to the pixel block BL form a set of a first node Pa, an amplification transistor AMP, and a selection transistor. Sharing SEL. A capacitance (charge-voltage conversion capacitance) is formed in the first node Pa with the reference potential, and the charge transferred to the first node Pa is converted into a voltage by the capacitance. The amplification transistor AMP constitutes an amplification unit that outputs a signal corresponding to the potential of the first node Pa. The selection transistor SEL constitutes a selection unit for selecting the pixel block BL. The photodiode PD and the transfer transistor TX are provided for each pixel PX without being shared by the two pixels PX (PXA, PXB). In FIGS. 2 and 3, n indicates a row of pixel block BL. For example, the pixel block BL in the first row is composed of the pixel PX (PXA) in the first row and the pixel PX (PXB) in the second row, and the pixel PX (PXA) in the third row and the pixel PX in the fourth row. (PXB) and the pixel block BL of the second row are configured.

For example, the transfer transistor TXA (n) of the pixel block BL (n) transfers an electric charge from the photodiode PDA (n) to the first node Pa (n), and the transfer transistor TXB (n) is the photodiode PDB (n). ) To the first node Pa (n). A capacitance (charge-voltage conversion capacitance) is formed in the first node Pa (n) with the reference potential, and the charge transferred to the first node Pa (n) is converted into a voltage by the capacitance. To. The amplification transistor AMP (n) outputs a signal corresponding to the potential of the first node Pa (n). These points are the same for the rows of other pixel blocks BL.

In the present invention, for example, the pixel block BL may be configured for each of three or more pixel PXs in which the photodiode PDs are sequentially arranged in the column direction.

Although not shown in the drawings, in the present embodiment, a plurality of types of color filters that transmit light having different color components are arranged in a predetermined color arrangement on the light incident side of the photodiode PD of each pixel PX. (For example, Bayer arrangement). The pixel PX outputs an electric signal corresponding to each color by color separation by a color filter.

The first transistor SWA (n) constitutes a first switch unit that electrically connects and disconnects between the first node Pa (n) and the corresponding second node Pb (n). ing. Such a first switch unit can be configured by combining switches such as a plurality of transistors, but in order to simplify the structure, a single first transistor SWA as in the present embodiment. It is preferably composed of (n). These points are the same for the other first transistor SWA.

Each second transistor SWB is a second node Pb corresponding to the first node Pa of one pixel block BL and the other for each of two pixel blocks BL adjacent to each other in the column direction of each pixel block BL. A second switch unit is configured so as to electrically connect and disconnect from the second node Pb corresponding to the first node Pa of the pixel block BL of the above. As a result, in the present embodiment, the first node Pa of the three or more pixel blocks BL is connected in a string by the plurality of second switch portions. The second switch unit as described above can be configured by combining switches such as a plurality of transistors, but in order to simplify the structure, a single second transistor as in the present embodiment. It is preferably composed of SWB.

For example, the second transistor SWB (n) is the second node Pb (n) corresponding to the first node Pa (n) of the pixel block BL (n) in the nth row and the pixels in the n-1th row. It is provided so as to electrically connect and disconnect from the second node Pb (n-1) corresponding to the first node Pa (n-1) of the block BL (n-1). This point is the same for the other second transistor SWB.

The reset transistor RST (n) constitutes a third switch unit that supplies the power supply voltage VDD as a predetermined potential to the second node Pb (n). Such a third switch unit can be configured by combining switches such as a plurality of transistors, but in order to simplify the structure, a single reset transistor RST (n) as in the present embodiment. ) Is preferable. These points are the same for other reset transistors RST.

In FIGS. 2 and 3, VDD is the power supply potential. In the present embodiment, the transistors TXA, TXB, AMP, RST, SEL, SWA, and SWB are all nMOS transistors.

The gate of the transfer transistor TXA is commonly connected to the control line 26 line by line, to which the control signal φTXA is supplied from the vertical scanning circuit 21. The gate of the transfer transistor TXB is commonly connected to the control line 25 line by line, to which the control signal φTXB is supplied from the vertical scanning circuit 21. The gate of the reset transistor RST is commonly connected to the control line 24 line by line, to which the control signal φRST is supplied from the vertical scanning circuit 21. The gate of the selection transistor SEL is commonly connected to the control line 23 line by row, to which the control signal φSEL is supplied from the vertical scanning circuit 21. The gate of the first transistor SWA is commonly connected to the control line 22 for each row, and the control signal φSWA is supplied to the control line 22 from the vertical scanning circuit 21. The gate of the second transistor SWB is commonly connected to the control line 27 line by line, to which the control signal φSWB is supplied from the vertical scanning circuit 21. For example, the control signal φTXA (n) is supplied to the gate of the transfer transistor TXA (n), the control signal φTXB (n) is supplied to the gate of the transfer transistor TXB (n), and the gate of the reset transistor RST (n). The control signal φRST (n) is supplied to the gate, the control signal φSEL (n) is supplied to the gate of the selection transistor SEL (n), and the control signal φSWA (n) is supplied to the gate of the first transistor SWA (n). Is supplied, and the control signal φSWB (n) is supplied to the gate of the second transistor SWB (n).

Each transistor TXA, TXB, RST, SEL, SWA, SWB is turned on when the corresponding control signals φTXA, φTXB, φRST, φSEL, φSWA, φSWB are high level (H), and when the corresponding control signals are low level (L). Turn off.

Under the control of the image pickup control unit 5 in FIG. 1, the vertical scanning circuit 21 outputs control signals φTXA, φTXB, φRST, φSEL, φSWA, and φSWB for each row of the pixel block BL, and outputs the pixel block BL and φSWB, respectively. The transistor SWA of 1 and the transistor SWB of the second transistor are controlled to realize a still image reading operation, a moving image reading operation, and the like. In this control, for example, a read operation of each operation mode described later is performed according to a set value of ISO sensitivity. By this control, each vertical signal line 28 is supplied with a signal (analog signal) of the pixel PX in the corresponding row.

In the present embodiment, the vertical scanning circuit 21 constitutes a control unit that switches each operation mode described later according to a command (control signal) from the imaging control unit 5 in FIG.

The signal read out on the vertical signal line 28 is amplified by the column amplifier 30 in each column and further amplified by the CDS circuit 31 as an optical signal (a signal including optical information photoelectrically converted by the pixel PX) and a dark signal (light). After processing to obtain the difference from the signal for difference including the noise component to be subtracted from the signal), it is converted into a digital signal by the A / D converter 32, and the digital signal is held in the A / D converter 32. Will be done. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33, converted into a predetermined signal format as necessary, and externally (digital signal processing unit 6 in FIG. 1). ) Is output.

The CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in FIG. 1, and when φDARKC is high level (H), the column amplifier 30 The output signal is sampled as a dark signal, and the optical signal sampling signal φSIGC is received from the timing generation circuit under the control of the imaging control unit 5 in FIG. 1. When φSIGC is H, the output signal of the column amplifier 30 is an optical signal. Sampling as. Then, the CDS circuit 31 outputs a signal corresponding to the difference between the sampled dark signal and the optical signal based on the clock or pulse from the timing generation circuit. As the configuration of such a CDS circuit 31, a known configuration can be adopted.

Here, the structure of the pixel block BL will be described with reference to FIGS. 4 and 5. Actually, a color filter, a microlens, etc. are arranged on the upper part of the photodiode PD, but they are omitted in FIGS. 4 and 5. In addition, in FIGS. 4 and 5, the layout of the power supply line, the ground line, the control lines 22 to 27, etc. is omitted.

In the present embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and each element in the pixel block BL such as a photodiode PD is arranged in the P-type well. There is. In FIG. 5, reference numerals 41 to 50 are N-type impurity diffusion regions that are a part of each of the above-mentioned transistors. Reference numerals 61 to 67 are gate electrodes of each transistor made of polysilicon. The diffusion regions 42 and 50 are regions in which the power supply voltage VDD is applied by a power supply line (not shown).

The photodiodes PDA (n) and PDB (n) are an N-type charge storage layer (not shown) provided in the P-type well and a P-type depletion prevention layer (not shown) arranged on the surface side thereof (FIG.). It is an embedded photodiode consisting of (not shown). The photodiodes PDA (n) and PDB (n) photoelectrically convert incident light and accumulate the generated charge in the charge storage layer.

The transfer transistor TXA (n) is an nMOS transistor having the charge storage layer of the photodiode PDA (n) as the source, the diffusion region 41 as the drain, and the gate electrode 61 as the gate. The transfer transistor TXB (n) is an nMOS transistor having the charge storage layer of the photodiode PDB (n) as the source, the diffusion region 41 as the drain, and the gate electrode 62 as the gate. The diffusion region 41 is provided between the photodiode PDA (n) and the photodiode PDB (n). The diffusion region 41 is also used as a diffusion region serving as a drain of the transfer transistor TXA (n) and a diffusion region serving as a drain of the transfer transistor TXB (n). The gate electrode 61 of the transfer transistor TXA (n) is arranged on the photodiode PDA (n) side of the diffusion region 41. The gate electrode 62 of the transfer transistor TXB (n) is arranged on the photodiode PDB (n) side of the diffusion region 41.

The amplification transistor AMP (n) is an nMOS transistor having a diffusion region 42 as a drain, a diffusion region 43 as a source, and a gate electrode 63 as a gate. The selection transistor SEL (n) is an nMOS transistor having a diffusion region 43 as a drain, a diffusion region 44 as a source, and a gate electrode 64 as a gate. The diffusion region 44 is connected to the vertical signal line 28.

The first transistor SWA (n) is an nMOS transistor having a diffusion region 45 as a source, a diffusion region 46 as a drain, and a gate electrode 65 as a gate. The second transistor SWB (n) is an nMOS transistor having a diffusion region 47 as a drain, a diffusion region 48 as a source, and a gate electrode 66 as a gate. The reset transistor RST (n) is an nMOS transistor having a diffusion region 49 as a source, a diffusion region 50 as a drain, and a gate electrode 67 as a gate.

The gate electrode 63 of the pixel block BL (n) and the diffusion regions 41 and 45 are electrically connected to each other by the wiring 71 (n) to conduct electricity. In the present embodiment, the first node Pa (n) corresponds to the wiring 71 (n) and the entire portion electrically connected to and conducting the wiring 71 (n).

Drain diffusion region 46 of the first transistor SWA (n), drain diffusion region 47 of the second transistor SWB (n), source diffusion region 49 of the reset transistor RST (n), and source of the second transistor SWB (n + 1). The diffusion regions 48 are electrically connected to each other by the wiring 72 (n) to conduct electricity. The second node Pb (n) corresponds to the wiring 72 (n) and the entire portion electrically connected and conducting with the wiring 72 (n). These points are the same for the other first transistor SWA, the other second transistor SWB, and the other reset transistor RST.

The structure of the pixel block BL other than the nth row is the same as the structure of the pixel block BL (n) of the nth row described above. The structure of the first transistor SWA other than the first transistor SWA (n) is the same as the structure of the first transistor SWA (n) described above. The structure of the connected transistor SWB other than the second transistor SWB (n) is the same as the structure of the connected transistor SWB (n) described above. The structure of the reset transistor RST other than the reset transistor RST (n) is the same as the structure of the reset transistor RST (n) described above.

In FIGS. 2 to 5, CC (n) is the capacitance between the first node Pa (n) and the reference potential when the first transistor SWA (n) is off. Let the capacitance value of the capacitance CC (n) be Cfd1. The CD (n) is the wiring 72 (n) and the reference when the first transistor SWA (n), the second transistor SWB (n), SWB (n + 1) and the reset transistor RST (n) are off. The capacitance between the potential. The capacity value of the capacity CD (n) is Cfd2. These points are the same for the other first transistor SWA, the other second transistor SWB, and the other reset transistor RST.

The capacitance CC (n) is the capacitance of the drain diffusion region 41 of the transfer transistors TXA (n) and TXB (n), the capacitance of the source diffusion region of the first transistor SWA (n), and the amplification transistor AMP (n). It is composed of the capacitance of the gate electrode 63 and the wiring capacitance of the wiring 71 (n), and the sum of these capacitance values is the capacitance value Cfd1 of the capacitance CC (n). This point is the same for the rows of other pixel blocks BL. Since the drain diffusion region 47 of the second transistor SWB (n) and the source diffusion region 49 of the reset transistor RST (n) are not components of the capacitance CC (n), the capacitance of the capacitance CC (n) is increased accordingly. The value Cfd1 becomes smaller.

Here, the value of the channel capacitance when the first transistor SWA is ON and the value of the channel capacitance when the second transistor SWB is ON are both set to Csw. Usually, the capacitance value Csw is a small value with respect to the capacitance values Cfd1 and Cfd2.

Now, focusing on the pixel block BL (n), the first transistor SWA (n) is turned off (that is, the on-state transistor of each first transistor SWA and each second transistor SWB is the first. The capacitance (charge-voltage conversion capacitance) between the first node Pa (n) and the reference potential is the capacitance CC (n). It becomes. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1. This state is a state other than the time when the first node Pa (n) in the period T2 in FIG. 6 showing the first operation mode described later is reset (φSWA (n) is L in the period T2 in FIG. 6). It corresponds to the state of the period).

Further, paying attention to the pixel block BL (n), when the first transistor SWA (n) is turned on, among the first transistor SWA and each second transistor SWB, other than the first transistor SWA (n). Unless the on-state transistor is electrically connected to the first node Pa (n) (specifically, here, the second transistors SWB (n), SWB (n + 1)). (If is off), the capacitance (charge-voltage conversion capacitance) between the first node Pa (n) and the reference potential is the capacitance CD (n) and the first transistor with respect to the capacitance CC (n). The channel capacitance when SWA (n) is on is added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2. This state corresponds to the state of the period T2 in FIG. 7 showing the second operation mode described later.

Further, focusing on the pixel block BL (n), when the first transistor SWA (n) and the second transistor SWB (n + 1) are turned on, among the first transistor SWA and each second transistor SWB, Unless the on-state transistors other than the transistors SWA (n) and SWB (n + 1) are electrically connected to the first node Pa (n) (here, specifically, the transistor SWB). (If (n), SWA (n + 1), SWB (n + 2) are off), the charge-voltage conversion capacitance of the first node Pa (n) is the capacitance CD (n) with respect to the capacitance CC (n). The channel capacitance when the capacitance CD (n + 1) and the transistors SWA (n) and SWB (n + 1) are on is added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + 2 × Cfd2 + 2 × Csw≈Cfd1 + 2 × Cfd2. This state corresponds to the state of the period T2 in FIG. 8 showing the operation mode of the third A described later.

Furthermore, focusing on the pixel block BL (n), when the first transistors SWA (n), SWA (n + 1) and the second transistor SWB (n + 1) are turned on, each first transistor SWA and each second transistor are turned on. Among the transistors SWB in the above, unless the on-state transistors other than the transistors SWA (n), SWA (n + 1), and SWB (n + 1) are electrically connected to the first node Pa (n). (Specifically, if the transistors SWB (n) and SWB (n + 2) are off), the charge-voltage conversion capacitance of the first node Pa (n) is relative to the capacitance CC (n). The channel capacitances of the capacitance CD (n), the capacitance CD (n + 1), the capacitance CC (n + 1), and the transistors SWA (n), SWA (n + 1), and SWB (n + 1) at the time of on are added. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is 2 × Cfd1 + 2 × Cfd2 + 3 × Csw≈2 × Cfd1 + 2 × Cfd2. This state corresponds to the state of the period T2 in FIG. 9, which shows the operation mode of the third B described later.

Further, paying attention to the pixel block BL (n), when the first transistor SWA (n) and the second transistors SWB (n + 1) and SWB (n + 2) are turned on, each of the first transistor SWA and each second transistor is turned on. Of the transistors SWB, on-state transistors other than the transistors SWA (n), SWB (n + 1), and SWB (n + 2) must be electrically connected to the first node Pa (n) ( Here, specifically, if the transistors SWA (n + 1), SWA (n + 2), SWB (n), and SWB (n + 3) are off), the charge-voltage conversion capacitance of the first node Pa (n) is Addition of channel capacitance when the capacitance CD (n), capacitance CD (n + 1), capacitance CD (n + 2) and transistors SWA (n), SWB (n + 1), SWB (n + 2) are turned on to the capacitance CC (n). It will be the one that was done. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + 3 × Cfd2 + 3 × Csw≈Cfd1 + 3 × Cfd2. This state corresponds to the state of the period T2 in FIG. 10 showing the operation mode of the third C described later.

As described above, if there is no on-state transistor electrically connected to the first node Pa (n) among the first transistor SWA and each second transistor SWB, the first node Pa ( Since the capacity value of the charge-voltage conversion capacity of n) becomes the minimum capacity value Cfd1 and the charge-voltage conversion coefficient due to the charge-voltage conversion capacity becomes large, it is possible to read at the highest SN ratio.

On the other hand, among the first transistor SWA and each second transistor SWB, the number of on-state transistors electrically connected to the first node Pa (n) is increased to one or more desired number. As a result, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) can be increased to a desired value, and a large signal charge amount can be handled, so that the number of saturated electrons can be increased. it can. As a result, the dynamic range can be expanded.

The first node Pa (n) of the pixel block BL (n) has been described above, but the same applies to the first node Pa (n) of the other pixel block BL.

FIG. 6 is a timing chart showing the first operation mode of the solid-state image sensor 4 shown in FIG. In this first operation mode, each pixel block BL is sequentially selected row by row, and the first node Pa of the selected pixel block BL among the first transistor SWA and each second transistor SWB is selected. On the other hand, in the state where there is no on-state transistor electrically connected (the state in which the charge-voltage conversion capacity of the first node Pa is the minimum), the transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected. This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read out row by row. In the example shown in FIG. 6, the signals of all pixels PXA and PXB are read, but the present invention is not limited to this, and for example, thinning-out reading may be performed by thinning out the pixel rows. This point is the same for each of the examples shown in FIGS. 7 to 10 described later.

In FIG. 6, the pixel block BL (n-1) in the n-1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the pixels in the n + 1th row in the period T3. It shows the situation where the block BL (n + 1) is selected. Since the operation when the pixel block BL of any row is selected is the same, only the operation when the pixel block BL (n) of the nth row is selected will be described here.

The exposure of the photodiodes PDA (n) and PDB (n) has already been completed in the predetermined exposure period before the start of the period T2. This exposure is performed by a mechanical shutter (not shown) after a so-called global reset that resets all pixels at the same time during normal main shooting (still image shooting), and in electronic viewfinder mode or movie shooting. , So-called rolling electronic shutter operation. Immediately before the start of period T2, all transistors SEL, RST, TXA, TXB, SWA, and SWB are turned off.

In the period T2, φSEL (n) in the nth row is set to H, the selection transistor SEL (n) in the pixel block BL (n) in the nth row is turned on, and the pixel block BL (n) in the nth row is changed. Be selected. Further, in the period T2, φRST (n) on the nth row is set to H, and the reset transistor RST (n) is turned on. However, the reset transistor RST (n) does not necessarily have to be turned on for the entire period T2, and φRST (n) is when the first node Pa (n) is reset (that is, φSWA (that is, φSWA) in FIG. Only the H period) of n) may be set to H.

ΦSWA (n) is set to H and the first transistor SWA (n) on the nth row is temporarily turned on for a certain period (when the first node Pa (n) is reset) immediately after the start of the period T2. .. At this time, since φRST (n) is set to H and the reset transistor RST (n) is on, the reset transistor RST (n) in the on state and the first transistor SWA (n) in the on state are passed through. Then, the potential of the first node Pa (n) is once reset to the power supply potential VDD.

After that, when the first transistor SWA (n) is turned off, it is electrically connected to the first node Pa (n) of the pixel block BL (n) selected from the transistors SWA and SWB. There is no transistor in the on state. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1, which is the minimum.

The dark signal sampling signal φDARKC was set to H for a certain period from the subsequent time point t1 during the period T2, and the potential appearing at the first node Pa (n) was amplified by the amplification transistor AMP (n) on the nth row. Later, the signal further amplified by the column amplifier 30 via the selection transistor SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

For a certain period from the subsequent time point t2 in the period T2, φTXA (n) is set to H and the transfer transistor TXA (n) on the nth row is turned on. As a result, the signal charge stored in the photodiode PDA (n) of the pixel block BL (n) on the nth row is transferred to the charge-voltage conversion capacitance of the first node Pa (n). The potential of the first node Pa (n) is a value proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge voltage conversion capacitance of the first node Pa (n), excluding the noise component.

At the subsequent time point t3 during the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa (n) is amplified by the amplification transistor AMP (n) in the nth row, and then the selection transistor. The signal further amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as an optical signal.

After that, after the time when φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from the time point t1 and the optical signal sampled in a certain time from the time point t3. .. The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output as a digital signal image signal to the outside (digital signal processing unit 6 in FIG. 1).

Then, φSWA (n) is set to H and the first transistor SWA (n) on the nth row is turned on once for a certain period (when the first node Pa (n) is reset) from the time point t4 in the period T2. To be reset. At this time, since φSEL (n) is set to H and the reset transistor RST (n) is on, the reset transistor RST (n) in the on state and the first transistor SWA (n) in the on state are passed through. Then, the potential of the first node Pa (n) is once reset to the power supply potential VDD.

After that, when the first transistor SWA (n) is turned off, it is electrically connected to the first node Pa (n) of the pixel block BL (n) selected from the transistors SWA and SWB. There is no transistor in the on state. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1, which is the minimum.

The dark signal sampling signal φDARKC was set to H for a certain period from the subsequent time point t5 in the period T2, and the potential appearing at the first node Pa (n) was amplified by the amplification transistor AMP (n) on the nth row. Later, the signal further amplified by the column amplifier 30 via the selection transistor SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

ΦTXB (n) is set to H and the transfer transistor TXB (n) on the nth row is turned on for a certain period from the subsequent time point t6 in the period T2. As a result, the signal charge stored in the photodiode PDB (n) of the pixel block BL (n) on the nth row is transferred to the charge-voltage conversion capacitance of the first node Pa (n). The potential of the first node Pa (n) is a value proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge voltage conversion capacitance of the first node Pa (n), excluding the noise component.

At the subsequent time point t7 during the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa (n) is amplified by the amplification transistor AMP (n) in the nth row, and then the selection transistor. The signal further amplified by the column amplifier 30 via the SEL (n) and the vertical signal line 28 is sampled by the CDS circuit 31 as an optical signal.

After that, after the time when φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from the time point t5 and the optical signal sampled in a certain time from the time point t7. .. The A / D converter 32 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output as a digital signal image signal to the outside (digital signal processing unit 6 in FIG. 1).

As described above, in the first operation mode, there is no on-state transistor electrically connected to the first node Pa of the selected pixel block BL among the transistors SWA and SWB, so that the transistor is selected. Since the capacity value of the charge-voltage conversion capacity of the first node Pa of the pixel block BL is minimized and the charge-voltage conversion coefficient due to the charge-voltage conversion capacity is large, reading with the highest SN ratio is possible. For example, when the ISO sensitivity setting value is the highest, the imaging control unit 5 is instructed to perform the first operation mode.

FIG. 7 is a timing chart showing a second operation mode of the solid-state image sensor 4 shown in FIG. In this second operation mode, each pixel block BL is sequentially selected row by row, and one of the first transistor SWA and each second transistor SWB in the on state transistor SWA is selected. In a state of being electrically connected to the first node Pa of the pixel block BL, the transfer transistors TXA and TXB of the selected pixel block BL are sequentially and selectively turned on, and each of the selected pixel block BL This is an example of an operation of sequentially reading the signals of the photodiodes PDA and PDB line by line.

In FIG. 7, similarly to FIG. 6, the pixel block BL (n-1) in the n-1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the pixel block BL (n) in the nth row is selected in the period T3. Shows the situation in which the pixel block BL (n + 1) on the n + 1th row is selected. The difference between the second operation mode shown in FIG. 7 and the first operation mode shown in FIG. 6 is described below.

In the second operation mode shown in FIG. 7, φSWA (n) is set to H and φSWB (n) and φSWB (n + 1) are set to L during the period T2 in which the pixel block BL (n) in the nth row is selected. The first transistor SWA (n) is turned on and the second transistors SWB (n) and φSWB (n + 1) are turned off. As a result, in the period T2, one of the transistors SWA and SWB in the on state, the first transistor SW (here, the first transistor SWA (n)) is of the selected pixel block BL (n). It is in a state of being electrically connected to the first node Pa (n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2, which is one step larger than that of the first operation mode shown in FIG.

Then, in the second operation mode shown in FIG. 7, while φSWA (n) is set to H and the first transistor SWA (n) is turned on, the first node Pa (n) is reset. Only at the time (a certain period immediately after the start of the period T2 and a certain period from the time point t4 during the period T2), φRST (n) is set to H and the reset transistor RST (n) is turned on. As a result, the potential of the first node Pa (n) is properly reset.

Here, the period T2 in which the pixel block BL (n) in the nth row is selected has been described, but the same applies to the period in which the other pixel block BL is selected.

As described above, in the second operation mode, one of the transistors SWA and SWB, the first transistor SWA in the on state, electrically relates to the first node Pa of the selected pixel block BL. Since they are connected, the capacity value of the charge-voltage conversion capacity of the first node Pa of the selected pixel block BL increases by one step, and the number of saturated electrons in the charge-voltage conversion capacity of the first node Pa increases by one step. Can be expanded. As a result, the dynamic range can be expanded by one step. For example, when the ISO sensitivity setting value is one step smaller than the highest value, the imaging control unit 5 is instructed to perform the second operation mode.

FIG. 8 is a timing chart showing the operation mode of the third A of the solid-state image sensor 4 shown in FIG. The operation mode of the third A is one of the operation modes of the third operation mode. In this third operation mode, each pixel block BL is sequentially selected row by row, and electrical is performed between the first node Pa of the selected pixel block BL and the corresponding second node Pb. The first transistor SWA that connects to and disconnects from is turned on, and the second transistor SWB that is electrically connected to the second node Pb corresponding to the first node Pa of the selected pixel block BL is turned on. The reset transistor RST that supplies the power supply potential VDD to the second node Pb corresponding to the first node Pa of the selected pixel block BL resets the first node Pa of the selected pixel block BL. An operation in which the transfer transistors TXA and TXB of the selected pixel block BL are sequentially and selectively turned on in a state of being turned on only at the time, and the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read line by line. Is an example of. The operation mode of the third A is one first transistor SWA in the ON state and one second transistor in the ON state with respect to the first node Pa of the selected pixel block BL in the third operation mode. This is an example of the operation in which the transistor SWB of the above is electrically connected.

In FIG. 8, similarly to FIG. 6, the pixel block BL (n-1) in the n-1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the period T3 Shows the situation in which the pixel block BL (n + 1) on the n + 1th row is selected. The difference between the operation mode of the third A shown in FIG. 8 and the operation mode of the first operation mode shown in FIG. 6 is described below.

In the operation mode of the third A shown in FIG. 8, φSWA (n) and φSWB (n + 1) are set to H and φSWA (n + 1) and φSWB are set to H in the period T2 in which the pixel block BL (n) in the nth row is selected. (N), φSWB (n + 2) is set to L, the first transistor SWA (n) and the second transistor SWB (n + 1) are turned on, and the first transistor SWA (n + 1) and the second transistor SWB are turned on. (N), SWB (n + 2) is turned off. As a result, in the period T2, one on-state first transistor SWA (here, the first transistor SWA (n)) and one on-state second transistor SWB (here, the first transistor SWA (n)) of the respective transistors SWA and SWB ( Here, the second transistor SWB (n + 1)) is electrically connected to the first node Pa (n) of the selected pixel block BL (n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + Cfd2 + Csw≈Cfd1 + Cfd2, which is two steps larger than that of the first operation mode shown in FIG.

Then, in the operation mode of the third A shown in FIG. 8, while φSWA (n) is set to H and the first transistor SWA (n) is turned on, the first node Pa (n) is reset. Only at the time (a certain period immediately after the start of the period T2 and a certain period from the time point t4 during the period T2), φRST (n) is set to H and the reset transistor RST (n) is turned on. As a result, the potential of the first node Pa (n) is properly reset. This point is the same for the operation mode of the third B shown in FIG. 9 and the operation mode of the third C shown in FIG. 10, which will be described later.

Here, the period T2 in which the pixel block BL (n) in the nth row is selected has been described, but the same applies to the period in which the other pixel block BL is selected.

As described above, in the third operation mode, one on-state first transistor SWA and one on-state second transistor SWB of the respective transistors SWA and SWB are included in the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL is increased by two steps, so to speak, and the charge of the first node Pa is increased. The number of saturated electrons in the voltage conversion capacitance can be increased by two steps. As a result, the dynamic range can be expanded by two steps. For example, when the ISO sensitivity setting value is two steps smaller than the highest value, the imaging control unit 5 is instructed to perform the operation mode of the third A.

FIG. 9 is a timing chart showing the operation mode of the third B of the solid-state image sensor 4 shown in FIG. In the third operation mode, the third operation mode includes two first transistors SWA in the ON state and one second transistor in the ON state with respect to the first node Pa of the selected pixel block BL. This is an example of the operation in which the transistor SWB of the above is electrically connected.

In FIG. 9, similarly to FIG. 4, the pixel block BL (n-1) in the n-1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the period T3 Shows the situation in which the pixel block BL (n + 1) on the n + 1th row is selected. The difference between the operation mode of the third B shown in FIG. 9 and the operation mode of the first operation mode shown in FIG. 4 is described below.

In the operation mode of the third B shown in FIG. 9, φSWA (n), φSWA (n + 1) and φSWB (n + 1) are set to H and φSWB is set to H in the period T2 in which the pixel block BL (n) in the nth row is selected. (N), φSWB (n + 2) is set to L, the first transistor SWA (n), SWA (n + 1) and the second transistor SWB (n + 1) are turned on, and the second transistor SWB (n), SWB (n + 2) is turned off. As a result, in the period T2, two ON-state first transistors SWA (here, first transistors SWA (n), SWA (n + 1)) and one ON-state first transistor SWA and SWB of each transistor SWA and SWB. The second transistor SWB (here, the second transistor SWB (n + 1)) is in a state of being electrically connected to the first node Pa (n) of the selected pixel block BL (n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is 2 × Cfd1 + 2 × Cfd2 + 3 × Csw≈2 × Cfd1 + 2 × Cfd2, and the first operation mode shown in FIG. It is three steps larger than the above.

Here, the period T2 in which the pixel block BL (n) in the nth row is selected has been described, but the same applies to the period in which the other pixel block BL is selected.

As described above, in the operation mode of the third B, the first transistor SWA in the on state and the second transistor SWB in the on state of each of the transistors SWA and SWB are in the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL is increased by three steps, so to speak, and the charge of the first node Pa is increased. The number of saturated electrons in the voltage conversion capacitance can be increased by three steps. As a result, the dynamic range can be expanded by three steps. For example, when the ISO sensitivity setting value is three steps smaller than the highest value, the imaging control unit 5 is instructed to perform the operation mode of the third B.

FIG. 10 is a timing chart showing the operation mode of the third C of the solid-state image sensor 4 shown in FIG. In the operation mode of the third C, each pixel block BL is sequentially selected row by row, and one of the first transistor SWA and each second transistor SWB in the ON state, the first transistor SWA and 2 The transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected in a state where the second on-state second transistor SWB is electrically connected to the first node Pa of the selected pixel block BL. This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read out row by row.

In FIG. 10, similarly to FIG. 6, the pixel block BL (n-1) in the n-1th row is selected in the period T1, the pixel block BL (n) in the nth row is selected in the period T2, and the pixel block BL (n) in the nth row is selected in the period T3. Shows the situation in which the pixel block BL (n + 1) on the n + 1th row is selected. The difference between the operation mode of the third C shown in FIG. 10 and the operation mode of the first operation mode shown in FIG. 4 is described below.

In the operation mode of the third C shown in FIG. 10, φSWA (n), φSWB (n + 1), and φSWB (n + 2) are set to H and φSWA is set to H in the period T2 in which the pixel block BL (n) in the nth row is selected. (N + 1), φSWA (n + 2), φSWB (n), φSWB (n + 3) are set to L, and the first transistor SWA (n) and the second transistor SWB (n + 1), SWB (n + 2) are turned on. At the same time, the first transistors SWA (n + 1) and SWA (n + 2) and the second transistors SWB (n) and SWB (n + 3) are turned off. As a result, in the period T2, one of the transistors SWA and SWB in the on state, the first transistor SWA (here, the first transistor SWA (n)) and the two transistors SWB in the on state (here, the second transistor SWB in the on state) ( Here, the second transistors SWB (n + 1) and SWB (n + 2)) are electrically connected to the first node Pa (n) of the selected pixel block BL (n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa (n) is Cfd1 + 3 × Cfd2 + 3 × Csw≈Cfd1 + 3 × Cfd2, which is different from the first operation mode shown in FIG. It will be 3 steps larger.

Here, the period T2 in which the pixel block BL (n) in the nth row is selected has been described, but the same applies to the period in which the other pixel block BL is selected.

As described above, in the operation mode of the third C, one of the first transistor SWA in the on state and the second transistor SWB in the on state of the transistors SWA and SWB are in the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacity value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by three steps, so to speak, and the charge of the first node Pa. The number of saturated electrons in the voltage conversion capacity can be increased by three steps. As a result, the dynamic range can be expanded by three steps. For example, when the ISO sensitivity setting value is three steps smaller than the highest value, the imaging control unit 5 is instructed to perform the second operation mode.

Here, a solid-state image sensor according to a comparative example compared with the solid-state image sensor 4 in the present embodiment will be described. FIG. 11 is a circuit diagram showing the vicinity of the three pixel blocks BL of the solid-state image sensor according to this comparative example, and corresponds to FIG. FIG. 12 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 11, and corresponds to FIGS. 4 and 5. In FIGS. 11 and 12, the same or corresponding elements as those in FIGS. 3, 4 and 5 are designated by the same reference numerals, and duplicate description thereof will be omitted. Although the diffusion region and the gate electrode are not designated in FIG. 12, their codes are the same as those in FIG. 5, so refer to FIG. 5 as necessary.

The difference between this comparative example and the present embodiment is that it will be described below. In this comparative example, the first and second transistors SWA and SWB and the wirings 71 and 72 are removed, and instead, the first connecting transistor SWa, the second connecting transistor SWb and the wirings 97 and 98 are provided. There is. Further, in this comparative example, the node P corresponding to the first node Pa exists, but the node corresponding to the second node Pb does not exist. Further, in the present embodiment, the source of the reset transistor RST is not connected to the first node Pa but is connected to the second node Pb, whereas in this comparative example, the source of the reset transistor RST is a node. It is connected to P.

In this comparative example, for each of the two pixel block BLs adjacent to each other in the column direction of each pixel block BL, the first pixel block BL is located between the node P of one pixel block BL and the node P of the other pixel block BL. The connection transistor SWa and the second connection transistor SWb of the above are provided in series. For example, between the node P (n) of the pixel block BL (n) on the nth row and the node P (n + 1) of the pixel block BL on the n + 1th row, the first connecting transistor SWa (n) and the second connection transistor SWa (n) The connecting transistor SWb (n) is provided in series.

In this comparative example, the gate electrode of the amplification transistor AMP (n) of the pixel block BL (n), the drain diffusion region of the transfer transistors TXA (n) and TXB (n), and the source diffusion of the first connected transistor SWa (n). The region, the drain diffusion region of the second connecting transistor SWb (n-1), and the source diffusion region of the reset transistor RST (n) are electrically connected to each other by the wiring 97 (n) to conduct electricity. The node P (n) corresponds to the wiring 97 (n) and the entire portion electrically connected and conductive to the wiring 97 (n). This point is the same for other pixel blocks BL.

Further, in this comparative example, the two connecting transistors SWa and SWb provided in series between the two nodes P are connected by the wiring 98. For example, the drain diffusion region of the first connection transistor SWa (n) and the source diffusion region of the second connection transistor SWb (n) are electrically connected by wiring 98 (n).

In FIGS. 11 and 12, CA (n) is the capacitance between the node P (n) and the reference potential when the connected transistors SWa (n) and SWb (n-1) are off. Let the capacity value of the capacity CA (n) be Cfd1'. CB (n) indicates the capacitance between the wiring 72 (n) and the reference potential when the connected transistors SWa (n) and SWb (n) are off. These points are the same for the rows of other pixel blocks BL.

The capacitance CA (n) is the capacitance of the drain diffusion region of the transfer transistors TXA (n) and TXB (n), the capacitance of the source diffusion region of the reset transistor RST (n), and the capacitance of the first connection transistor SWa (n). It is composed of the capacitance of the source diffusion region, the capacitance of the drain diffusion region of the second connecting transistor SWb (n-1), the capacitance of the gate electrode of the amplification transistor AMP (n), and the wiring capacitance of the wiring 97 (n). The sum of these capacity values is the capacity value Cfd1'of the capacity CA (n). This point is the same for the rows of other pixel blocks BL.

On the other hand, the capacitance CC (n) in the present embodiment is the capacitance of the drain diffusion region 41 of the transfer transistors TXA (n) and TXB (n) and the capacitance of the first transistor SWA (n) as described above. It is composed of the capacitance of the source diffusion region, the capacitance of the gate electrode of the amplification transistor AMP (n), and the wiring capacitance of the wiring 71 (n), and the total of these capacitance values is the capacitance value Cfd1 of the capacitance CC (n). It has become.

Therefore, the capacitance value Cfd1 of the capacitance CC (n) in the present embodiment is a drain diffusion region of the second connected transistor SWb (n-1) than the capacitance value Cfd1'of the capacitance CA (n) in this comparative example. And the capacity of the source diffusion region of the reset transistor RST (n) (that is, two transistor diffusion capacities).

In this comparative example, focusing on the pixel block BL (n), when both the connected transistors SWa (n) and SWb (n-1) are turned off, the capacitance (charge) between the node P (n) and the reference potential is reached. The voltage conversion capacity) is the capacity CA (n), the capacity value of the charge-voltage conversion capacity of the node P (n) is the minimum Cfd1', and the charge-voltage conversion coefficient due to the charge-voltage conversion capacity is large, so that the highest SN It is possible to read by ratio. Further, in this comparative example, if the number of connected transistors in the on state electrically connected to the node P (n) among the connected transistors SWa and SWb is increased to one or more desired number. Since the capacitance value of the charge-voltage conversion capacitance of the node P (n) can be increased to a desired value and a large amount of signal charge can be handled, the number of saturated electrons can be increased. As a result, the dynamic range can be expanded.

As described above, the minimum capacity value Cfd1 of the charge-voltage conversion capacity of the first node Pa (n) in the present embodiment is the minimum capacity value of the charge-voltage conversion capacity of the node P (n) in this comparative example. It is smaller than Cfd1'by two transistor diffusion capacities. Therefore, according to the present embodiment, the charge-voltage conversion coefficient is further increased as compared with this comparative example, and reading with a higher SN ratio becomes possible.

In the present embodiment, the second transistor SWB is provided between all the two second nodes Pb sequentially adjacent to each other in the column direction, but the present invention is not necessarily limited to this. For example, between the second node Pb every r (r is an integer of 2 or more) arranged in the column direction and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb, The second transistor SWB may not be provided and the space between them may be always open. In this case, as the number of r is smaller, the maximum number of the predetermined number in the second operation mode becomes smaller and the degree of expansion of the dynamic range decreases, but the SN at the time of high-sensitivity reading is compared with the comparative example. The ratio can be improved. Further, for example, between the second node Pb every s (s is an integer of 1 or more) arranged in the column direction and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb. May not be provided with the second transistor SWB and may be electrically short-circuited between them. Further, for example, between the second node Pb every u (u is an integer of 1 or more) arranged in the column direction and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb. While providing only the second transistor SWB, between the second node Pb other than every u node arranged in the column direction and the second node Pb adjacent to the lower side in the figure with respect to the second node Pb. It may be electrically short-circuited.

In the present embodiment, the capacity value of the capacity CD may be set to a value within ± 20% of the capacity value of the capacity CC by providing an adjustment capacity in the wiring 72 or the like. The value may be within the range of ± 10% with respect to the capacitance value. These points are the same for the second embodiment described later.

In addition, each operation example shown in FIGS. 6 to 10 was an example of the operation which reads out the signal charge of the photodiode PD of each pixel PX without mixing with the signal charge of the photodiode PD of another pixel PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be mixed with the signal charge of the photodiode PD of another pixel PX of the same color and read out.

For example, the first transistor SWA (n-1), SWA (n), SWA (n + 1) and the second transistor SWB (n), SWB (n + 1) are turned on to turn on the first node Pa (n-1). , Pa (n), Pa (n + 1) are connected to each other, and when TXA (n-1), TXA (n), TXA (n + 1) are turned on at the same time, three of the same color in the case of Bayer arrangement etc. A first in which the signal charges of the photodiodes PDA (n-1), PDA (n), and PDA (n-1) of the pixels PXA (n-1), PXA (n), and PXA (n-1) are connected to each other. It is averaged by the nodes Pa (n-1), Pa (n), and Pa (n + 1) of the above, and the function of the same color 3-pixel mixed reading can be realized. At this time, the second transistors SWB (n-2) and SWB (n + 2) are turned off and electrically connected to the first nodes Pa (n-1), Pa (n), Pa (n + 1). Charge-voltage conversion capacitance values at the connected first nodes Pa (n-1), Pa (n), Pa (n + 1) by minimizing the number of on-state first or second transistors. Is the minimum, and the same color 3-pixel mixed reading can be performed with the highest SN ratio. On the other hand, in addition to the first transistors SWA (n-1), SWA (n), SWA (n + 1) and the second transistors SWB (n), SWB (n + 1), each first transistor SWA and each second transistor If one or more on-state transistors of the transistors SWB of the above are electrically connected to the first nodes Pa (n-1), Pa (n), Pa (n + 1), the transistor is used. Depending on the number, the charge-voltage conversion capacitance values at the first connected nodes Pa (n-1), Pa (n), and Pa (n + 1) increase, and the dynamic range of the same color 3-pixel mixed readout is expanded. Can be done.

[Second Embodiment]
FIG. 13 is a circuit diagram showing a schematic configuration of the solid-state image sensor 84 of the electronic camera according to the second embodiment of the present invention, and corresponds to FIG. In FIG. 13, elements that are the same as or correspond to the elements in FIG. 2 are designated by the same reference numerals, and duplicate description thereof will be omitted.

The difference between the present embodiment and the first embodiment is that in the first embodiment, the photodiode PDB and the transfer transistor TXB are removed in each pixel block BL in the first embodiment. The point is that the pixel block BL is a pixel PXA. However, in the present embodiment, the density in the row direction of the photodiode PDA is doubled the density in the row direction of the photodiode PDA in the first embodiment, and the photodiode in the fourth embodiment is used. It is the same as the density in the column direction of the entire PDA and PDB. In the present embodiment, n indicates the row of the pixel block BL and at the same time indicates the row of the pixel PXA.

In other words, in the first embodiment, each pixel block BL is composed of two pixel PXs (PXA, PXB), whereas in the present embodiment, each pixel block BL is one. It is composed of the pixels PX (PXA) of. Then, in the first embodiment, the two pixels PX (PXA, PXB) belonging to the pixel block BL share a set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL. On the other hand, in the present embodiment, each pixel PX (in the present embodiment, only the PXA) has a set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL. doing.

Basically, the description of the first embodiment fits as the description of the present embodiment by replacing the pixel block BL with the pixel PXA. Therefore, a detailed description of the present embodiment will be omitted here.

The present embodiment also provides the same advantages as those of the first embodiment.

Although the embodiments and modifications of the present invention have been described above, the present invention is not limited thereto.

4 Solid-state imaging element BL pixel block PX pixel PD photodiode TXA, TXB transfer transistor Pa 1st node Pb 2nd node AMP amplification transistor SWA 1st transistor SWB 2nd transistor RST reset transistor (3rd transistor)

Claims (15)

An image sensor having a plurality of pixel blocks arranged side by side in the column direction.
The pixel block includes a plurality of photoelectric conversion units that convert light into electric charges, a first node unit to which charges from the plurality of photoelectric conversion units are transferred, and a second node unit that is different from the first node unit. , The first switch unit that controls the connection between the first node unit and the second node unit, and the other pixel block arranged adjacent to the second node unit and the plurality of pixel blocks. It has a second switch unit that controls the connection between the second node unit and the third switch unit that controls the connection between the second node unit and the supply unit to which a predetermined voltage is supplied. Imaging element. In the image pickup device according to claim 1,
The first node unit is an image sensor connected to the supply unit via the first switch unit and the third switch unit. In the image pickup device according to claim 1 or 2.
The second node unit is an image sensor having wiring connected to the first switch unit and the second switch unit. The image sensor according to any one of claims 1 to 3.
The first switch unit is connected to a first control line to which a control signal for controlling the first switch unit is output.
The second switch unit is connected to a second control line from which a control signal for controlling the second switch unit is output.
The third switch unit is an image sensor connected to a third control line from which a control signal for controlling the third switch unit is output. In the image pickup device according to claim 4,
The first node unit has a diffusion region to which charges from the plurality of photoelectric conversion units are transferred.
The first switch unit has a first transistor including a gate electrode connected to the first control line.
The second switch unit has a second transistor including a gate electrode connected to the second control line.
The gate electrode of the first transistor is an image pickup device arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the second transistor to the diffusion region. In the image pickup device according to claim 5,
The third switch unit has a third transistor including a gate electrode connected to the third control line.
The gate electrode of the first transistor is an image pickup device arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the third transistor to the diffusion region. In the image pickup device according to claim 5 or 6.
The pixel block has an amplification transistor including a gate electrode connected to the first node portion.
The gate electrode of the first transistor is an image pickup device arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the amplification transistor to the diffusion region. The image sensor according to any one of claims 5 to 7.
The pixel block has a selection transistor that controls a connection with a signal line that outputs a signal based on the charge of the first node portion.
The gate electrode of the first transistor is an image pickup device arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the selection transistor to the diffusion region. In the image pickup device according to claim 4,
The first node unit has a diffusion region to which charges from the plurality of photoelectric conversion units are transferred.
The first switch unit has a first transistor including a gate electrode connected to the first control line.
The third switch unit has a third transistor including a gate electrode connected to the third control line.
The gate electrode of the first transistor is an image pickup device arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the third transistor to the diffusion region. In the image pickup device according to claim 9,
The pixel block has an amplification transistor including a gate electrode connected to the first node portion.
The gate electrode of the first transistor is an image pickup device arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the amplification transistor to the diffusion region. In the image pickup device according to claim 9 or 10.
The pixel block has a selection transistor that controls a connection with a signal line that outputs a signal based on the charge of the first node portion.
The gate electrode of the first transistor is an image pickup device arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the selection transistor to the diffusion region. In the image pickup device according to claim 4,
The pixel block has an amplification transistor including a gate electrode connected to the first node portion.
The first node unit has a diffusion region to which charges from the plurality of photoelectric conversion units are transferred.
The first switch unit has a first transistor including a gate electrode connected to the first control line.
The gate electrode of the first transistor is an image pickup device arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the amplification transistor to the diffusion region. In the image pickup device according to claim 12,
The pixel block has a selection transistor that controls a connection with a signal line that outputs a signal based on the charge of the first node portion.
The gate electrode of the first transistor is an image pickup device arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the selection transistor to the diffusion region. In the image pickup device according to claim 4,
The pixel block has a selection transistor that controls a connection with a signal line that outputs a signal based on the charge of the first node portion.
The first node unit has a diffusion region to which charges from the plurality of photoelectric conversion units are transferred.
The first switch unit has a first transistor including a gate electrode connected to the first control line.
The gate electrode of the first transistor is an image pickup device arranged at a position where the distance to the diffusion region is shorter than the distance from the gate electrode of the selection transistor to the diffusion region. An image pickup apparatus comprising the image pickup device according to any one of claims 1 to 14.

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