JP2024040400A - Solid-state imaging device and imaging device - Google Patents

Abstract

[Problem] To improve the signal-to-noise ratio during high-sensitivity readout while enabling an expansion of the dynamic range. [Solution] An element 4 includes a plurality of pixel blocks BL each having one photoelectric conversion unit PD, a first node Pa, and one transfer switch provided corresponding to the one photoelectric conversion unit PD and transferring charges from the photoelectric conversion unit PD to the first node Pa, two first switch units SWA that electrically connect and disconnect the first node Pa of one pixel block BL and the first node Pa of the other pixel block BL to two second nodes Pb that respectively correspond to these two first nodes Pa, a second switch unit SWB that electrically connects and disconnects the two second nodes Pb, and two third switch units RST that supply a predetermined potential VDD to the two second nodes Pb. [Selected Figure] FIG.

Description

The present invention relates to a solid-state imaging device and an imaging device using the same.

Patent Document 1 below describes a plurality of pixels, each of which includes at least two pixels (a) a photodetector, (b) a charge-voltage conversion region forming a floating capacitance section, and (c) an input section to an amplifier. A solid-state imaging device is disclosed, which includes: and a connection switch that selectively connects the charge-voltage conversion regions.

Special Publication No. 2008-546313

In the conventional solid-state image sensor, by turning on the connection switch and connecting the charge-voltage conversion regions, the number of saturated electrons in the entire connected charge-voltage conversion regions is expanded, so the dynamic range can be increased. It can be expanded.

Further, in the conventional solid-state image sensor, by turning off the connection switch and separating the charge-voltage conversion region from other charge-voltage conversion regions, the charge-voltage conversion capacity becomes smaller and its charge-voltage conversion coefficient becomes larger. Therefore, the SN ratio during high-sensitivity reading increases.

However, in the conventional solid-state image sensor, even if the connection switch is turned off, the SN ratio during high-sensitivity readout cannot be made very high.

The present invention has been made in view of the above circumstances, and provides a solid-state imaging device that can expand the dynamic range and improve the SN ratio during high-sensitivity readout, and an imaging device using the same. The purpose is to provide equipment.

The following aspects are presented as means for solving the above problems. The solid-state image sensor according to the first aspect is provided with one photoelectric conversion section, a first node, and corresponding to the one photoelectric conversion section, and transfers charges from the photoelectric conversion section to the first node. a plurality of pixel blocks having one transfer switch; two second nodes respectively corresponding to the first node of one of the pixel blocks and the first node of another one of the pixel blocks; two first nodes that electrically connect and disconnect between the first node of one pixel block and the first node and the two second nodes of the other pixel block; a switch section, a second switch section that electrically connects and disconnects the two second nodes, and two third switch sections that supply predetermined potentials to the two second nodes, respectively; It is equipped with the following.

The pixel block may have only one photoelectric conversion section and be composed of one pixel, or may have two or more photoelectric conversion sections and be composed of a plurality of pixels. good. This point also applies to each aspect described below.

In the solid-state imaging device according to a second aspect, in the first aspect, each of the pixel blocks has a plurality of the photoelectric conversion sections and a plurality of the transfer switches.

In the solid-state imaging device according to the third aspect, in the first or second aspect, in the first operation mode, the first node of the one pixel block and the corresponding second node are connected to each other. The first switch unit that electrically connects and disconnects the first node of the one pixel block is turned on only when the potential of the first node of the one pixel block is reset, and Each of the first and second switches is configured such that the third switch unit that supplies the predetermined potential to the second node corresponding to the node is turned on at least when the potential of the first node of the one pixel block is reset. and a control section that controls each of the third switch sections.

In the solid-state imaging device according to a fourth aspect, in the third aspect, the control unit controls the first node of the one pixel block and the second node corresponding to the first node of the one pixel block in the second operation mode. The first switch section that electrically connects and disconnects the pixel block is turned on, the second switch section is turned off, and the second The respective first switch sections, the second and the respective third switch sections.

In the solid-state image sensing device according to a fifth aspect, in the third or fourth aspect, the control unit controls the first node of the one pixel block and the corresponding node of the one pixel block in the third operation mode. The first switch section that electrically connects and disconnects between the two nodes is turned on, and the second switch section is turned on and corresponds to the first node of the one pixel block. each of the first switch units, such that the third switch unit that supplies the predetermined potential to the second node is turned on only when resetting the potential of the first node of the one pixel block; The second switch section and each third switch section are controlled.

In the solid-state imaging device according to a sixth aspect, in the first or second aspect, the first nodes of three or more pixel blocks among the plurality of pixel blocks and the first nodes of these three or more pixel blocks are provided. 1 node and three or more of the second nodes, each of which electrically connects and disconnects the three or more of the second nodes, The above second nodes are connected in a daisy-chain manner by a plurality of the second switch sections, and the three or more third switch sections each supply the predetermined potential to the three or more second nodes. It is prepared.

In the solid-state imaging device according to a seventh aspect, in the sixth aspect, in the first operation mode, the first node of one pixel block among the three or more pixel blocks and the corresponding The first switch unit that electrically connects and disconnects between the second node and the second node only when resetting the potential of the first node of the one pixel block among the three or more pixel blocks. the third switch section is once turned on and supplies the predetermined potential to the second node corresponding to the first node of the one pixel block among the three or more pixel blocks; controlling each of the first switch units and each of the third switch units to turn on at least when resetting the potential of the first node of the one pixel block of the three or more pixel blocks; It is equipped with a control section.

In the solid-state imaging device according to an eighth aspect, in the seventh aspect, the control unit, in the second operation mode, connects the first node of one pixel block among the three or more pixel blocks. The first switch unit that electrically connects and disconnects the corresponding second node is turned on, and the first switch unit of the one pixel block among the three or more pixel blocks is turned on. The second switch section electrically connected to the second node corresponding to the node is turned off, and the first switch section of the one pixel block among the three or more pixel blocks is turned off. The third switch unit supplies the predetermined potential to the second node corresponding to the node, when resetting the potential of the first node of the one pixel block among the three or more pixel blocks. The first switch section, the second switch section, and the third switch section are controlled so that only the first switch section, the second switch section, and the third switch section are turned on.

In the solid-state imaging device according to a ninth aspect, in the seventh or eighth aspect, the control unit controls the first pixel block of one pixel block among the three or more pixel blocks in the third operation mode. The first switch unit that electrically connects and disconnects between the node and the corresponding second node is turned on, and the The second switch unit electrically connected to the second node corresponding to the first node is turned on, and the one pixel block of the three or more pixel blocks The third switch unit supplies the predetermined potential to the second node corresponding to the first node, and the third switch unit supplies the predetermined potential to the second node corresponding to the first node, The first switch section, the second switch section, and the third switch section are controlled so that they are turned on only when resetting the switch section.

An imaging device according to a tenth aspect includes the solid-state imaging device according to any one of the first to ninth aspects.

An imaging device according to an eleventh aspect includes the solid-state imaging device according to the third, fourth, fifth, seventh, eighth, or ninth aspect, and control for switching each of the operation modes according to a set value of ISO sensitivity. It is equipped with the means and.

According to the present invention, it is possible to provide a solid-state imaging device that can expand the dynamic range and improve the SN ratio during high-sensitivity readout, and an imaging device using the same.

FIG. 1 is a schematic block diagram schematically showing an electronic camera according to a first embodiment of the present invention. 2 is a circuit diagram showing a schematic configuration of a solid-state image sensor in FIG. 1. FIG. FIG. 2 is a circuit diagram showing an enlarged view of the vicinity of four pixel blocks in FIG. 1. FIG. 4 is a schematic plan view schematically showing the vicinity of three pixel blocks in FIG. 3. FIG. 5 is a schematic plan view showing an enlarged view of the vicinity of one pixel block in FIG. 4. FIG. 3 is a timing chart showing a predetermined operation mode of the solid-state image sensor shown in FIG. 2. FIG. 3 is a timing chart showing another operation mode of the solid-state image sensor shown in FIG. 2. FIG. 3 is a timing chart showing still another operation mode of the solid-state image sensor shown in FIG. 2. FIG. 3 is a timing chart showing still another operation mode of the solid-state image sensor shown in FIG. 2. FIG. 3 is a timing chart showing still another operation mode of the solid-state image sensor shown in FIG. 2. FIG. FIG. 3 is a circuit diagram showing the vicinity of three pixel blocks of a solid-state image sensor according to a comparative example. 10 is a schematic plan view schematically showing the vicinity of three pixel blocks shown in FIG. 9. FIG. FIG. 2 is a circuit diagram showing a schematic configuration of a solid-state image sensor of an electronic camera according to a second embodiment of the present invention.

Hereinafter, a solid-state imaging device and an imaging device according to the present invention will be described with reference to the drawings.

[First embodiment]
FIG. 1 is a schematic block diagram schematically showing an electronic camera 1 according to a first embodiment of the present invention.

Although the electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera, the imaging device according to the present invention is not limited to this, and can be installed in other electronic cameras such as compact cameras or mobile phones. It can be applied to various imaging devices such as electronic cameras and electronic cameras such as video cameras that capture moving images.

A photographing lens 2 is attached to the electronic camera 1. The focus and aperture of this photographic lens 2 are driven by a lens control section 3. In the image space of this photographic lens 2, an imaging surface of a solid-state image sensor 4 is arranged.

The solid-state imaging device 4 is driven by a command from the imaging control section 5 and outputs a digital image signal. During normal actual shooting (still image shooting), the imaging control unit 5 performs a predetermined readout operation, for example, after a so-called global reset in which all pixels are reset at the same time, and after exposure using a mechanical shutter (not shown). The solid-state image sensor 4 is controlled. Further, in the electronic viewfinder mode or when shooting a moving image, the imaging control unit 5 controls the solid-state imaging device 4 to perform a predetermined readout operation, for example, while performing a so-called rolling electronic shutter. At these times, the imaging control unit 5 controls the solid-state imaging device 4 to perform a readout operation in each operation mode, which will be described later, according to the ISO sensitivity setting value, as described later. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, white balance processing, etc. on the digital image signal output from the solid-state image sensor 4. The image signal processed by the digital signal processing section 6 is temporarily stored in the memory 7. Memory 7 is connected to bus 8 . Also connected to the bus 8 are a lens control section 3, an imaging control section 5, a CPU 9, a display section 10 such as a liquid crystal display panel, a recording section 11, an image compression section 12, an image processing section 13, and the like. An operation unit 14 such as a release button is connected to the CPU 9. The operating section 14 allows the ISO sensitivity to be set. A recording medium 11a is detachably attached to the recording section 11.

When the electronic viewfinder mode, video shooting, normal main shooting (still image shooting), etc. are instructed by operation of the operating section 14, the CPU 9 in the electronic camera 1 drives the image capturing control section 5 in accordance with the instruction. At this time, the lens control section 3 adjusts the focus and aperture as appropriate. The solid-state imaging device 4 is driven by a command from the imaging control section 5 and outputs a digital image signal. The digital image signal from the solid-state image sensor 4 is stored in the memory 7 after being processed by the digital signal processing section 6 . The CPU 9 causes the image signal to be displayed on the display unit 10 when in the electronic viewfinder mode, and records the image signal on the recording medium 11a when shooting a moving image. During normal actual shooting (still image shooting), the CPU 9 processes the digital image signal from the solid-state image sensor 4 in the digital signal processing section 6 and stores it in the memory 7, and then sends it to the operating section 14. Based on the command, desired processing is performed in the image processing section 13 and the image compression section 12 as necessary, and the processed signal is outputted to the recording section 11 and recorded on the recording medium 11a.

FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state image sensor 4 in FIG. 1. FIG. 3 is an enlarged circuit diagram showing the vicinity of four pixel blocks BL sequentially arranged in the column direction in FIG. FIG. 4 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL in FIG. FIG. 5 is a schematic plan view showing the vicinity of one pixel block BL in FIG. 4 in an enlarged manner. In this embodiment, the solid-state image sensor 4 is configured as a CMOS type solid-state image sensor, but is not limited to this, and may be configured as another XY address type solid-state image sensor, for example.

As shown in FIGS. 2 to 4, the solid-state image sensor 4 includes a pixel block BL arranged in a two-dimensional matrix in N rows and M columns and each having two pixels PX (PXA, PXB), and a first pixel block BL to be described later. A first transistor SWA serving as a first switch unit that electrically connects and disconnects the node Pa and the corresponding second node Pb and electrically connects the two second nodes Pb. and a second transistor SWB as a second switch section for disconnecting, a reset transistor RST as a third switch section that supplies the power supply voltage VDD as a predetermined potential to the second node Pb, and a vertical scanning circuit 21. , control lines 22 to 27 provided for each row of the pixel block BL and signals from the pixels PX (pixel block BL) of the corresponding column provided for each column of the pixel PX (for each column of the pixel block BL). A plurality of (M) vertical signal lines 28 to receive, a constant current source 29 provided for each vertical signal line 28, a column amplifier 30 provided corresponding to each vertical signal line 28, and a CDS circuit (correlation 2 It has a double sampling circuit) 31, an A/D converter 32, and a horizontal readout circuit 33.

Note that as the column amplifier 30, an analog amplifier or a so-called switched capacitor amplifier may be used. Further, the column amplifier 30 does not necessarily need to be provided.

For convenience of drawing notation, M=2 is shown in FIG. 2, but the number of columns M is actually set to a larger arbitrary number. Furthermore, the number of lines N is also not limited. When pixel blocks BL are distinguished by row, the j-th pixel block BL is indicated by the symbol BL(j). This point also applies to other elements and control signals described later. In FIGS. 2 and 3, pixel blocks BL(n-1) to BL(n+2) of the n-1th row to the n+2th row spanning four rows are shown.

In addition, in the drawings, the code of the lower pixel in FIGS. 2 and 3 in the pixel block BL is PXA, and the code of the upper pixel in FIGS. 2 and 3 is PXB to distinguish between the two, but the two are When the description is made without distinguishing between the two, the reference numeral PX may be attached to both. In addition, in the drawings, the photodiode of pixel PXA is denoted by PDA, and the photodiode of pixel PXB is denoted by PDB to distinguish between the two, but when explaining the two without distinguishing them, the symbol PD is attached to both. May be explained. Similarly, the code of the transfer transistor of pixel PXA is TXA, and the code of the transfer transistor of pixel PXB is TXB to distinguish between the two, but when explaining the two without distinguishing them, the code TX will be added to both. There are cases. Note that in this embodiment, the photodiodes PD of the pixel PX are arranged in a two-dimensional matrix of 2N rows and M columns.

In this embodiment, each pixel PX includes a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and a transfer switch that transfers charges from the photodiode PD to the first node Pa. transfer transistor TX.

In this embodiment, the plurality of pixels PX form a pixel block BL for each two pixels PX (PXA, PXB) in which photodiodes PD are sequentially lined up in the column direction. As shown in FIGS. 2 and 3, for each pixel block BL, two pixels PX (PXA, PXB) belonging to the pixel block BL are connected to a set of first nodes Pa, an amplification transistor AMP, and a selection transistor. We share SEL. A capacitor (charge-voltage conversion capacitor) is formed between the first node Pa and the reference potential, and the charge transferred to the first node Pa is converted into a voltage by the capacitor. The amplification transistor AMP constitutes an amplification section that outputs a signal according to the potential of the first node Pa. The selection transistor SEL constitutes a selection section for selecting the pixel block BL. The photodiode PD and the transfer transistor TX are provided for each pixel PX without being shared by the two pixels PX (PXA, PXB). In FIGS. 2 and 3, n indicates the row of the pixel block BL. For example, the first row pixel block BL is configured by the first row pixel PX (PXA) and the second row pixel PX (PXB), and the third row pixel PX (PXA) and the fourth row pixel PX (PXB) constitutes the second row pixel block BL.

For example, the transfer transistor TXA(n) of the pixel block BL(n) transfers charge from the photodiode PDA(n) to the first node Pa(n), and the transfer transistor TXB(n) transfers the charge from the photodiode PDA(n) to the first node Pa(n). ) to the first node Pa(n). A capacitor (charge-voltage conversion capacitor) is formed between the first node Pa(n) and the reference potential, and the charge transferred to the first node Pa(n) is converted into voltage by the capacitor. Ru. Amplification transistor AMP(n) outputs a signal according to the potential of first node Pa(n). These points also apply to the rows of other pixel blocks BL.

Note that, in the present invention, for example, the pixel block BL may be configured for each of three or more pixels PX in which photodiodes PD are sequentially lined up in the column direction.

Although not shown in the drawings, in this embodiment, on the light incident side of the photodiode PD of each pixel PX, a plurality of types of color filters each transmitting light of different color components are arranged in a predetermined color arrangement. (for example, Bayer array). The pixel PX outputs electrical signals corresponding to each color by color separation using a color filter.

The first transistor SWA(n) constitutes a first switch unit that electrically connects and disconnects the first node Pa(n) and the corresponding second node Pb(n). ing. Although such a first switch section can be configured by combining switches such as a plurality of transistors, in order to simplify the structure, a single first transistor SWA is used as in this embodiment. (n) is preferable. These points also apply to the other first transistors SWA.

Each second transistor SWB is connected to a second node Pb corresponding to the first node Pa of one pixel block BL and a second node Pb corresponding to the first node Pa of one pixel block BL for each two pixel blocks BL adjacent to each other in the column direction of each pixel block BL. A second switch section is provided to electrically connect and disconnect the first node Pa of the pixel block BL with the corresponding second node Pb. Accordingly, in this embodiment, the first nodes Pa of three or more pixel blocks BL are connected in a daisy-chain manner by the plurality of second switch sections. Although the second switch section described above can be configured by combining switches such as a plurality of transistors, in order to simplify the structure, it is possible to configure the second switch section by combining switches such as a plurality of transistors. It is preferable to use SWB.

For example, the second transistor SWB(n) connects the second node Pb(n) corresponding to the first node Pa(n) of the pixel block BL(n) of the nth row and the pixel of the n-1st row. It is provided to electrically connect and disconnect the first node Pa (n-1) of block BL (n-1) from the corresponding second node Pb (n-1). This point also applies to the other second transistor SWB.

The reset transistor RST(n) constitutes a third switch section that supplies the power supply voltage VDD as a predetermined potential to the second node Pb(n). Although such a third switch section can be configured by combining switches such as a plurality of transistors, in order to simplify the structure, a single reset transistor RST(n ) is preferable. These points also apply to other reset transistors RST.

In FIGS. 2 and 3, VDD is a power supply potential. Note that in this embodiment, transistors TXA, TXB, AMP, RST, SEL, SWA, and SWB are all nMOS transistors.

The gates of the transfer transistors TXA are commonly connected to a control line 26 for each row, and a control signal φTXA is supplied thereto from the vertical scanning circuit 21. The gates of the transfer transistors TXB are commonly connected to a control line 25 for each row, and a control signal φTXB is supplied thereto from the vertical scanning circuit 21. The gates of the reset transistors RST are commonly connected to a control line 24 for each row, and a control signal φRST is supplied thereto from the vertical scanning circuit 21. The gates of the selection transistors SEL are commonly connected to a control line 23 for each row, and a control signal φSEL is supplied thereto from the vertical scanning circuit 21. The gates of the first transistors SWA are commonly connected to the control line 22 for each row, and a control signal φSWA is supplied thereto from the vertical scanning circuit 21. The gates of the second transistors SWB are commonly connected to the control line 27 for each row, and a control signal φSWB is supplied thereto from the vertical scanning circuit 21. For example, the gate of the transfer transistor TXA(n) is supplied with the control signal φTXA(n), the gate of the transfer transistor TXB(n) is supplied with the control signal φTXB(n), and the gate of the reset transistor RST(n) is supplied with the control signal φTXA(n). A control signal φRST(n) is supplied to the gate of the selection transistor SEL(n), a control signal φSEL(n) is supplied to the gate of the first transistor SWA(n), and a control signal φSWA(n) is supplied to the gate of the first transistor SWA(n). is supplied, and a control signal φSWB(n) is supplied to the gate of the second transistor SWB(n).

Each transistor TXA, TXB, RST, SEL, SWA, SWB is turned on when the corresponding control signal φTXA, φTXB, φRST, φSEL, φSWA, φSWB is at high level (H), and is turned on when it is at low level (L). Turn off.

The vertical scanning circuit 21 outputs control signals φTXA, φTXB, φRST, φSEL, φSWA, and φSWB for each row of the pixel block BL under the control of the imaging control unit 5 in FIG. The first transistor SWA and the second transistor SWB are controlled to realize a still image readout operation, a moving image readout operation, and the like. In this control, a read operation in each operation mode, which will be described later, is performed depending on the set value of the ISO sensitivity, for example. Through this control, each vertical signal line 28 is supplied with the signal (analog signal) of the pixel PX in the corresponding column.

In this embodiment, the vertical scanning circuit 21 constitutes a control section that switches between various operation modes, which will be described later, in response to commands (control signals) from the imaging control section 5 in FIG. 1.

The signals read out to the vertical signal line 28 are amplified by a column amplifier 30 for each column, and further processed by a CDS circuit 31 into an optical signal (a signal containing optical information photoelectrically converted by the pixel PX) and a dark signal (an optical signal). After processing is performed to obtain the difference between the signal and the difference signal (including the noise component to be subtracted from the signal), the signal is converted into a digital signal by the A/D converter 32, and the digital signal is held in the A/D converter 32. be done. The digital image signal held in each A/D converter 32 is horizontally scanned by a horizontal readout circuit 33, converted into a predetermined signal format as necessary, and externally (digital signal processing unit 6 in FIG. ) is output to.

Note that the CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in FIG. The output signal is sampled as a dark signal, and an optical signal sampling signal φSIGC is received from the timing generation circuit under the control of the imaging control unit 5 in FIG. 1, and when φSIGC is H, the output signal of the column amplifier 30 is converted into an optical signal. Sample as. Then, the CDS circuit 31 outputs a signal corresponding to the difference between the sampled dark signal and the optical signal based on the clock and pulse from the timing generation circuit. As the configuration of such a CDS circuit 31, a known configuration can be adopted.

Here, the structure of the pixel block BL will be explained with reference to FIGS. 4 and 5. In reality, a color filter, a microlens, etc. are arranged above the photodiode PD, but these are omitted in FIGS. 4 and 5. Note that in FIGS. 4 and 5, the layout of the power supply line, ground line, control lines 22 to 27, etc. is omitted.

In this embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and each element in the pixel block BL, such as a photodiode PD, is arranged in the P-type well. There is. In FIG. 5, reference numerals 41 to 50 are N-type impurity diffusion regions that are part of each of the transistors described above. Reference numerals 61 to 67 are gate electrodes of each transistor made of polysilicon. Note that the diffusion regions 42 and 50 are regions to which a power supply voltage VDD is applied by a power supply line (not shown).

The photodiodes PDA(n) and PDB(n) consist of an N-type charge storage layer (not shown) provided in the P-type well and a P-type depletion prevention layer (not shown) disposed on the surface side of the N-type charge storage layer (not shown). (not shown). The photodiodes PDA(n) and PDB(n) photoelectrically convert incident light and accumulate the generated charges in their charge storage layers.

The transfer transistor TXA(n) is an nMOS transistor that uses the charge storage layer of the photodiode PDA(n) as a source, the diffusion region 41 as a drain, and the gate electrode 61 as a gate. The transfer transistor TXB(n) is an nMOS transistor that uses the charge storage layer of the photodiode PDB(n) as a source, the diffusion region 41 as a drain, and the gate electrode 62 as a gate. Diffusion region 41 is provided between photodiode PDA(n) and photodiode PDB(n). The diffusion region 41 serves both as a diffusion region that becomes the drain of the transfer transistor TXA(n) and as a diffusion region that becomes the drain of the transfer transistor TXB(n). The gate electrode 61 of the transfer transistor TXA(n) is arranged on the photodiode PDA(n) side of the diffusion region 41. The gate electrode 62 of the transfer transistor TXB(n) is arranged on the photodiode PDB(n) side of the diffusion region 41.

The amplification transistor AMP(n) is an nMOS transistor having the diffusion region 42 as a drain, the diffusion region 43 as a source, and the gate electrode 63 as a gate. The selection transistor SEL(n) is an nMOS transistor having the diffusion region 43 as a drain, the diffusion region 44 as a source, and the gate electrode 64 as a gate. Diffusion region 44 is connected to vertical signal line 28 .

The first transistor SWA(n) is an nMOS transistor having the diffusion region 45 as a source, the diffusion region 46 as a drain, and the gate electrode 65 as a gate. The second transistor SWB(n) is an nMOS transistor having the diffusion region 47 as a drain, the diffusion region 48 as a source, and the gate electrode 66 as a gate. The reset transistor RST(n) is an nMOS transistor having the diffusion region 49 as a source, the diffusion region 50 as a drain, and the gate electrode 67 as a gate.

The gate electrode 63 and the diffusion regions 41 and 45 of the pixel block BL(n) are electrically connected to each other by a wiring 71(n) and are electrically conductive. In this embodiment, the first node Pa(n) corresponds to the wiring 71(n) and the entire portion that is electrically connected to and conductive thereto.

Drain diffusion region 46 of first transistor SWA(n), drain diffusion region 47 of second transistor SWB(n), source diffusion region 49 of reset transistor RST(n), and source of second transistor SWB(n+1) The diffusion regions 48 are electrically connected to each other by the wiring 72(n) and are electrically conductive. The second node Pb(n) corresponds to the wiring 72(n) and the entire portion electrically connected to and conducting thereto. These points also apply to other first transistors SWA, other second transistors SWB, and other reset transistors RST.

The structures of the pixel blocks BL other than the n-th row are also similar to the structure of the n-th pixel block BL(n) described above. The structures of the first transistors SWA other than the first transistor SWA(n) are also similar to the structure of the first transistor SWA(n) described above. The structures of the coupling transistors SWB other than the second transistor SWB(n) are also similar to the structure of the coupling transistor SWB(n) described above. The structures of reset transistors RST other than reset transistor RST(n) are also similar to the structure of reset transistor RST(n) described above.

In FIGS. 2 to 5, CC(n) is the capacitance between the first node Pa(n) and the reference potential when the first transistor SWA(n) is off. Let the capacitance value of capacitor CC(n) be Cfd1. CD(n) is the reference wiring 72(n) when the first transistor SWA(n), the second transistor SWB(n), SWB(n+1), and the reset transistor RST(n) are off. It is the capacitance between the electric potential and the electric potential. Let the capacitance value of capacitance CD(n) be Cfd2. These points also apply to other first transistors SWA, other second transistors SWB, and other reset transistors RST.

The capacitance CC(n) is the capacitance of the drain diffusion region 41 of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region of the first transistor SWA(n), and the capacitance of the amplification transistor AMP(n). It is composed of the capacitance of the gate electrode 63 and the wiring capacitance of the wiring 71(n), and the sum of these capacitance values becomes the capacitance value Cfd1 of the capacitor CC(n). This point also applies to the rows of other pixel blocks BL. Note that the drain diffusion region 47 of the second transistor SWB(n) and the source diffusion region 49 of the reset transistor RST(n) do not constitute the capacitance CC(n), so the capacitance of the capacitance CC(n) increases accordingly. The value Cfd1 becomes smaller.

Here, the value of the channel capacitance when the first transistor SWA is on and the value of the channel capacitance when the second transistor SWB is on are both Csw. Usually, the capacitance value Csw is a smaller value than the capacitance values Cfd1 and Cfd2.

Now, focusing on the pixel block BL(n), the first transistor SWA(n) is turned off (that is, the on-state transistor of each first transistor SWA and each second transistor SWB is The capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential is the capacitance CC(n). becomes. Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is Cfd1. This state is a state other than when the first node Pa(n) is reset during period T2 in FIG. period).

Also, focusing on the pixel block BL(n), when the first transistor SWA(n) is turned on, among the first transistors SWA and the second transistors SWB, the transistors other than the first transistor SWA(n) Unless the transistors in the on state are electrically connected to the first node Pa(n) (here, specifically, the second transistors SWB(n), SWB(n+1) is off), the capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential is the capacitance CC(n), the capacitance CD(n) and the first transistor This is the addition of the channel capacity when SWA(n) is on. Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is Cfd1+Cfd2+Csw≈Cfd1+Cfd2. This state corresponds to the state in period T2 in FIG. 7, which shows a second operation mode, which will be described later.

Furthermore, focusing on the pixel block BL(n), when the first transistor SWA(n) and the second transistor SWB(n+1) are turned on, among each of the first transistors SWA and each of the second transistors SWB, Unless the on-state transistors other than the transistors SWA(n) and SWB(n+1) become electrically connected to the first node Pa(n) (here, specifically, the transistor SWB (n), SWA(n+1), and SWB(n+2) are off), the charge-voltage conversion capacitance of the first node Pa(n) is the capacitance CD(n), This is the addition of the capacitance CD(n+1) and the channel capacitance of the transistors SWA(n) and SWB(n+1) when they are on. Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is Cfd1+2×Cfd2+2×Csw≈Cfd1+2×Cfd2. This state corresponds to the state of period T2 in FIG. 8, which shows the third A operation mode, which will be described later.

Furthermore, focusing on the pixel block BL(n), when the first transistors SWA(n), SWA(n+1) and the second transistor SWB(n+1) are turned on, each first transistor SWA and each second transistor SWA(n+1) turn on. Among the transistors SWB, the transistors in the on state other than the transistors SWA(n), SWA(n+1), and SWB(n+1) must be electrically connected to the first node Pa(n). (Here, specifically, if transistors SWB(n) and SWB(n+2) are off), the charge-voltage conversion capacitance of the first node Pa(n) is relative to the capacitance CC(n). This is the addition of capacitance CD(n), capacitance CD(n+1), capacitance CC(n+1), and channel capacitances of transistors SWA(n), SWA(n+1), and SWB(n+1) when they are on. Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is 2×Cfd1+2×Cfd2+3×Csw≈2×Cfd1+2×Cfd2. This state corresponds to the state of period T2 in FIG. 9, which shows the third B operation mode, which will be described later.

Also, focusing on the pixel block BL(n), when the first transistor SWA(n) and the second transistors SWB(n+1) and SWB(n+2) are turned on, each first transistor SWA and each second transistor If the on-state transistors other than the transistors SWA(n), SWB(n+1), and SWB(n+2) among the transistors SWB are not electrically connected to the first node Pa(n), ( Specifically, if the transistors SWA(n+1), SWA(n+2), SWB(n), and SWB(n+3) are off), the charge-voltage conversion capacity of the first node Pa(n) is Add the on-state channel capacitances of capacitance CD(n), capacitance CD(n+1), capacitance CD(n+2), and transistors SWA(n), SWB(n+1), and SWB(n+2) to capacitance CC(n). It becomes what it is. Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is Cfd1+3×Cfd2+3×Csw≈Cfd1+3×Cfd2. This state corresponds to the state of period T2 in FIG. 10 showing the third C operation mode, which will be described later.

In this way, if there is no on-state transistor electrically connected to the first node Pa(n) among each first transistor SWA and each second transistor SWB, the first node Pa( The capacitance value of the charge-voltage conversion capacitor n) becomes the minimum capacitance value Cfd1, and the charge-voltage conversion coefficient due to the charge-voltage conversion capacitor becomes large, so that reading with the highest SN ratio becomes possible.

On the other hand, the number of on-state transistors electrically connected to the first node Pa(n) among each first transistor SWA and each second transistor SWB is increased to one or more desired number. By doing so, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) can be increased to a desired value, and a large amount of signal charge can be handled, so the number of saturated electrons can be expanded. can. Thereby, the dynamic range can be expanded.

The first node Pa(n) of the pixel block BL(n) has been described above, but the same applies to the first nodes Pa of the other pixel blocks BL.

FIG. 6 is a timing chart showing the first operation mode of the solid-state image sensor 4 shown in FIG. In this first operation mode, each pixel block BL is sequentially selected row by row, and the first node Pa of the pixel block BL selected from each first transistor SWA and each second transistor SWB is connected to the first node Pa of the selected pixel block BL. Transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected in a state in which there is no transistor in an on-state electrically connected to the pixel block BL (a state in which the charge-voltage conversion capacity of the first node Pa is the minimum). This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read out row by row. In the example shown in FIG. 6, signals of all pixels PXA and PXB are read out, but the present invention is not limited to this, and for example, thinning readout in which pixel rows are thinned out and read out may be performed. This point also applies to each example shown in FIGS. 7 to 10, which will be described later.

In FIG. 6, the pixel block BL(n-1) in the n-1st row is selected in the period T1, the pixel block BL(n) in the n-th row is selected in the period T2, and the pixel block BL(n) in the n+1th row is selected in the period T3. This shows a situation in which block BL(n+1) is being selected. Since the operation is the same when the pixel block BL in any row is selected, only the operation when the n-th pixel block BL(n) is selected will be described here.

Before the start of period T2, exposure of photodiodes PDA(n) and PDB(n) has already been completed in a predetermined exposure period. During normal shooting (still image shooting), this exposure is performed by a mechanical shutter (not shown) after a so-called global reset that resets all pixels at the same time, and during electronic viewfinder mode or video shooting, etc. This is performed by a so-called rolling electronic shutter operation. Immediately before the start of period T2, all transistors SEL, RST, TXA, TXB, SWA, and SWB are off.

In period T2, the n-th row φSEL(n) is set to H, the selection transistor SEL(n) of the n-th pixel block BL(n) is turned on, and the n-th pixel block BL(n) is turned on. selected. Further, in period T2, φRST(n) of the nth row is set to H, and the reset transistor RST(n) is turned on. However, the reset transistor RST(n) does not necessarily need to be turned on for the entire period T2, and φRST(n) is not necessarily turned on during the entire period T2, and φRST(n) is not necessarily turned on during the reset of the first node Pa(n) (i.e., φSWA( Only the H period (n) may be set to H.

Immediately after the start of period T2, φSWA(n) is set to H for a certain period of time (when the first node Pa(n) is reset), and the first transistor SWA(n) in the nth row is temporarily turned on. . At this time, because φRST(n) is set to H and the reset transistor RST(n) is on, the Then, the potential of the first node Pa(n) is temporarily reset to the power supply potential VDD.

Thereafter, when the first transistor SWA(n) is turned off, it is electrically connected to the first node Pa(n) of the pixel block BL(n) selected among the transistors SWA and SWB. There is no transistor in the on state. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is Cfd1, which is the minimum.

The dark signal sampling signal φDARKC is set to H for a certain period from the subsequent time point t1 during the period T2, and the potential appearing at the first node Pa(n) is amplified by the n-th amplification transistor AMP(n). A signal that is subsequently amplified by the column amplifier 30 via the selection transistor SEL(n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

φTXA(n) is set to H for a predetermined period from a subsequent time point t2 during period T2, and the n-th row transfer transistor TXA(n) is turned on. As a result, the signal charge accumulated in the photodiode PDA(n) of the n-th pixel block BL(n) is transferred to the charge-voltage conversion capacitor of the first node Pa(n). The potential of the first node Pa(n), excluding noise components, has a value proportional to the amount of signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n).

At a subsequent time point t3 during period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa(n) is amplified by the n-th amplification transistor AMP(n), and then the selection transistor A signal that is further amplified by the column amplifier 30 via SEL(n) and the vertical signal line 28 is sampled by the CDS circuit 31 as an optical signal.

After that, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled in a certain period from time t1 and the optical signal sampled in a certain period from time t3. . The A/D converter 32 converts a signal corresponding to this difference into a digital signal and holds the digital signal. The digital image signals held in each A/D converter 32 are horizontally scanned by a horizontal readout circuit 33 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital image signal.

Then, for a certain period of time (when the first node Pa(n) is reset) from time t4 during period T2, φSWA(n) is set to H, and the first transistor SWA(n) of the nth row is once turned on. be made into At this time, since φSEL(n) is set to H and the reset transistor RST(n) is on, the Then, the potential of the first node Pa(n) is temporarily reset to the power supply potential VDD.

Thereafter, when the first transistor SWA(n) is turned off, it is electrically connected to the first node Pa(n) of the pixel block BL(n) selected among the transistors SWA and SWB. There is no transistor in the on state. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is Cfd1, which is the minimum.

The dark signal sampling signal φDARKC is set to H for a certain period from the subsequent time point t5 during the period T2, and the potential appearing at the first node Pa(n) is amplified by the n-th amplification transistor AMP(n). A signal that is subsequently amplified by the column amplifier 30 via the selection transistor SEL(n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

φTXB(n) is set to H for a certain period of time starting from a subsequent time point t6 during period T2, and the n-th row transfer transistor TXB(n) is turned on. As a result, the signal charge accumulated in the photodiode PDB(n) of the n-th pixel block BL(n) is transferred to the charge-voltage conversion capacitor of the first node Pa(n). The potential of the first node Pa(n), excluding noise components, has a value proportional to the amount of signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n).

At a subsequent time point t7 during the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa(n) is amplified by the n-th amplification transistor AMP(n), and then the selection transistor A signal that is further amplified by the column amplifier 30 via SEL(n) and the vertical signal line 28 is sampled by the CDS circuit 31 as an optical signal.

After that, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled for a certain period from time t5 and the optical signal sampled for a certain period from time t7. . The A/D converter 32 converts a signal corresponding to this difference into a digital signal and holds the digital signal. The digital image signals held in each A/D converter 32 are horizontally scanned by a horizontal readout circuit 33 and output as a digital image signal to the outside (digital signal processing section 6 in FIG. 1).

In this way, in the first operation mode, there is no transistor in the on state that is electrically connected to the first node Pa of the selected pixel block BL among the transistors SWA and SWB. The capacitance value of the charge-voltage conversion capacitor of the first node Pa of the pixel block BL becomes the minimum, and the charge-voltage conversion coefficient due to the charge-voltage conversion capacitor becomes large, so that readout with the highest SN ratio is possible. For example, when the ISO sensitivity setting value is the highest, the imaging control unit 5 issues a command to perform the first operation mode.

FIG. 7 is a timing chart showing the second operation mode of the solid-state image sensor 4 shown in FIG. In this second operation mode, each pixel block BL is sequentially selected row by row, and one transistor SWA in an on state among each first transistor SWA and each second transistor SWB is selected. While being electrically connected to the first node Pa of the pixel block BL, the transfer transistors TXA and TXB of the selected pixel block BL are sequentially and selectively turned on, and each of the selected pixel blocks BL is This is an example of an operation in which signals of photodiodes PDA and PDB are sequentially read out row by row.

Similarly to FIG. 6, in FIG. 7, the n-1st pixel block BL(n-1) is selected in the period T1, the n-th pixel block BL(n) is selected in the period T2, and the pixel block BL(n) is selected in the period T3. This shows a situation in which the pixel block BL(n+1) on the n+1th row is selected. The second operation mode shown in FIG. 7 differs from the first operation mode shown in FIG. 6 in the following points.

In the second operation mode shown in FIG. 7, during period T2 when the n-th pixel block BL(n) is selected, φSWA(n) is set to H, and φSWB(n) and φSWB(n+1) are set to L. , the first transistor SWA(n) is turned on, and the second transistors SWB(n) and φSWB(n+1) are turned off. As a result, in the period T2, the first transistor SW (here, the first transistor SWA(n)) in the on state of one of the transistors SWA and SWB is activated in the selected pixel block BL(n). It becomes electrically connected to the first node Pa(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is Cfd1+Cfd2+Csw≈Cfd1+Cfd2, which is one step larger than in the first operation mode shown in FIG. 6.

In the second operation mode shown in FIG. 7, φSWA(n) is set to H and the first transistor SWA(n) is turned on, while the first node Pa(n) is reset. φRST(n) is set to H and the reset transistor RST(n) is turned on only at a certain time (a certain period immediately after the start of period T2 and a certain period from time t4 in period T2). Thereby, the potential of the first node Pa(n) is appropriately reset.

Although the period T2 in which the n-th pixel block BL(n) is selected has been described here, the same applies to the periods in which other pixel blocks BL are selected.

In this way, in the second operation mode, the first transistor SWA of the transistors SWA and SWB, which is in the on state, is electrically connected to the first node Pa of the selected pixel block BL. As a result, the capacitance value of the charge-voltage conversion capacitor of the first node Pa of the selected pixel block BL increases by one step, and the saturated number of electrons in the charge-voltage conversion capacitor of the first node Pa increases by one step. Can be expanded. This allows the dynamic range to be expanded by one step. For example, when the ISO sensitivity setting value is one step smaller than the highest value, the imaging control unit 5 issues a command to perform the second operation mode.

FIG. 8 is a timing chart showing the third A operation mode of the solid-state image sensor 4 shown in FIG. The third A operation mode is one of the third operation modes. In this third operation mode, each pixel block BL is sequentially selected row by row, and electrical connections are made between the first node Pa of the selected pixel block BL and the corresponding second node Pb. The first transistor SWA connected to and disconnected from the selected pixel block BL is turned on, and the second transistor SWB electrically connected to the second node Pb corresponding to the first node Pa of the selected pixel block BL is turned on. In addition, the reset transistor RST that supplies the power supply potential VDD to the second node Pb corresponding to the first node Pa of the selected pixel block BL resets the first node Pa of the selected pixel block BL. An operation of sequentially selectively turning on the transfer transistors TXA and TXB of the selected pixel block BL in a state where they are turned on only when This is an example. In the third A operation mode, one first transistor SWA in an on state and one second transistor SWA in an on state are connected to a first node Pa of a selected pixel block BL. This is an example of an operation in which transistor SWB of is electrically connected.

Similarly to FIG. 6, in FIG. 8, the n-1st pixel block BL(n-1) is selected in the period T1, the n-th pixel block BL(n) is selected in the period T2, and the pixel block BL(n) is selected in the period T3. This shows a situation in which the pixel block BL(n+1) on the n+1th row is selected. The third A operation mode shown in FIG. 8 differs from the first operation mode shown in FIG. 6 in the following points.

In the third A operation mode shown in FIG. 8, φSWA(n) and φSWB(n+1) are set to H during a period T2 during which the n-th pixel block BL(n) is selected, and φSWA(n+1), φSWB (n), φSWB(n+2) are set to L, the first transistor SWA(n) and the second transistor SWB(n+1) are turned on, and the first transistor SWA(n+1) and the second transistor SWB (n), SWB(n+2) is turned off. As a result, in the period T2, one of the transistors SWA and SWB is the first transistor SWA (here, the first transistor SWA(n)) in the on state and one second transistor SWB (in the on state) is in the on state. Here, the second transistor SWB(n+1)) is electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) becomes Cfd1+Cfd2+Csw≈Cfd1+Cfd2, which is two steps larger than in the first operation mode shown in FIG. 6.

In the third A operation mode shown in FIG. 8, φSWA(n) is set to H and the first transistor SWA(n) is turned on, while the first node Pa(n) is reset. φRST(n) is set to H and the reset transistor RST(n) is turned on only at a certain time (a certain period immediately after the start of period T2 and a certain period from time t4 during period T2). Thereby, the potential of the first node Pa(n) is appropriately reset. This point also applies to the 3B operation mode shown in FIG. 9 and the 3C operation mode shown in FIG. 10, which will be described later.

Although the period T2 in which the n-th pixel block BL(n) is selected has been described here, the same applies to the periods in which other pixel blocks BL are selected.

In this manner, in the third operation mode, one first transistor SWA in an on state and one second transistor SWB in an on state out of each transistor SWA, SWB are connected to each other in the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacitance value of the charge-voltage conversion capacitor of the first node Pa of the selected pixel block BL increases by two steps, so that the charge of the first node Pa increases. The number of saturated electrons in the voltage conversion capacitor can be increased by two steps. Thereby, the dynamic range can be expanded by two steps. For example, when the set value of the ISO sensitivity is two steps smaller than the highest value, the imaging control unit 5 issues a command to perform the third A operation mode.

FIG. 9 is a timing chart showing the third B operation mode of the solid-state image sensor 4 shown in FIG. In this third B operation mode, two first transistors SWA in an on state and one second transistor SWA in an on state are connected to the first node Pa of the selected pixel block BL in the third operation mode. This is an example of an operation in which transistor SWB of is electrically connected.

9, similarly to FIG. 4, the n-1st pixel block BL(n-1) is selected in the period T1, the n-th pixel block BL(n) is selected in the period T2, and the pixel block BL(n) in the nth row is selected in the period T3. This shows a situation in which the pixel block BL(n+1) on the n+1th row is selected. The third B operation mode shown in FIG. 9 differs from the first operation mode shown in FIG. 4 in the following points.

In the third B operation mode shown in FIG. 9, during period T2 when the n-th pixel block BL(n) is selected, φSWA(n), φSWA(n+1), and φSWB(n+1) are set to H, and φSWB (n), φSWB(n+2) are set to L, the first transistors SWA(n), SWA(n+1) and the second transistor SWB(n+1) are turned on, and the second transistors SWB(n), SWB(n+2) is turned off. As a result, in the period T2, two of the transistors SWA and SWB are in the on state, the first transistor SWA (here, the first transistor SWA(n), SWA(n+1)), and one of the transistors SWA and SWB is in the on state. The second transistor SWB (here, the second transistor SWB(n+1)) is electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is 2×Cfd1+2×Cfd2+3×Csw≒2×Cfd1+2×Cfd2, and the first operation mode shown in FIG. Compared to , it is three steps larger.

Although the period T2 in which the n-th pixel block BL(n) is selected has been described here, the same applies to the periods in which other pixel blocks BL are selected.

In this manner, in the third B operation mode, two of the transistors SWA and SWB, the first transistor SWA in the on state and one second transistor SWB in the on state, are connected to the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacitance value of the charge-voltage conversion capacitor of the first node Pa of the selected pixel block BL increases by three steps, so that the charge of the first node Pa increases. The number of saturated electrons in the voltage conversion capacitor can be increased by three stages. Thereby, the dynamic range can be expanded by three steps. For example, when the set value of the ISO sensitivity is three steps smaller than the highest value, the imaging control unit 5 issues a command to perform the third B operation mode.

FIG. 10 is a timing chart showing the third C operation mode of the solid-state image sensor 4 shown in FIG. In this third C operation mode, each pixel block BL is sequentially selected row by row, and one of the first transistors SWA and the second transistors SWB is in the ON state. Transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected in a state in which the two on-state second transistors SWB are electrically connected to the first node Pa of the selected pixel block BL. This is an example of an operation in which the signals of the photodiodes PDA and PDB of the selected pixel block BL are sequentially read out row by row.

Similarly to FIG. 6, in FIG. 10, the n-1st pixel block BL(n-1) is selected in the period T1, the n-th pixel block BL(n) is selected in the period T2, and the pixel block BL(n) in the nth row is selected in the period T3. This shows a situation in which the pixel block BL(n+1) on the n+1th row is selected. The third C operation mode shown in FIG. 10 differs from the first operation mode shown in FIG. 4 in the following points.

In the third C operation mode shown in FIG. 10, during period T2 when the n-th pixel block BL(n) is selected, φSWA(n), φSWB(n+1), and φSWB(n+2) are set to H, and φSWA (n+1), φSWA(n+2), φSWB(n), φSWB(n+3) are set to L, and the first transistor SWA(n) and the second transistor SWB(n+1), SWB(n+2) are turned on. At the same time, the first transistors SWA(n+1), SWA(n+2) and the second transistors SWB(n), SWB(n+3) are turned off. As a result, in the period T2, one of the transistors SWA and SWB is the first transistor SWA (in this case, the first transistor SWA(n)) in the on state and the two second transistors SWB (in the on state) are in the on state. Here, the second transistors SWB(n+1), SWB(n+2)) are electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is Cfd1+3×Cfd2+3×Csw≈Cfd1+3×Cfd2, which is different from that in the first operation mode shown in FIG. Increases in size by 3 levels.

Although the period T2 in which the n-th pixel block BL(n) is selected has been described here, the same applies to the periods in which other pixel blocks BL are selected.

In this way, in the third C operation mode, one of the transistors SWA and SWB, the first transistor SWA in the on state and the two second transistors SWB in the on state, are connected to the selected pixel block BL. Since it is electrically connected to the first node Pa, the capacitance value of the charge-voltage conversion capacitor of the first node Pa of the selected pixel block BL increases by three steps, so that the charge of the first node Pa increases. The number of saturated electrons in the voltage conversion capacitor can be increased by three stages. Thereby, the dynamic range can be expanded by three steps. For example, when the set value of the ISO sensitivity is three steps lower than the highest value, the imaging control unit 5 issues a command to perform the second operation mode.

Here, a solid-state image sensor according to a comparative example to be compared with the solid-state image sensor 4 in this embodiment will be described. FIG. 11 is a circuit diagram showing the vicinity of three pixel blocks BL of the solid-state image sensor according to this comparative example, and corresponds to FIG. 3. FIG. 12 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 11, and corresponds to FIGS. 4 and 5. In FIGS. 11 and 12, elements that are the same as or correspond to those in FIGS. 3, 4, and 5 are denoted by the same reference numerals, and redundant explanation thereof will be omitted. Note that although the diffusion regions and gate electrodes are not labeled in FIG. 12, these symbols are the same as in FIG. 5, so please refer to FIG. 5 as necessary.

This comparative example differs from the present embodiment in the following points. In this comparative example, the first and second transistors SWA, SWB and the wirings 71, 72 are removed, and instead, the first connection transistor SWa, the second connection transistor SWb, and the wirings 97, 98 are provided. There is. Further, in this comparative example, there is a node P corresponding to the first node Pa, but there is no node corresponding to the second node Pb. Furthermore, in the present embodiment, the source of the reset transistor RST is not connected to the first node Pa but is connected to the second node Pb, whereas in this comparative example, the source of the reset transistor RST is connected to the node Pb. Connected to P.

In this comparative example, for each two pixel blocks BL adjacent to each other in the column direction among each pixel block BL, a first A connection transistor SWa and a second connection transistor SWb are provided in series. For example, between the node P(n) of the pixel block BL(n) in the n-th row and the node P(n+1) in the pixel block BL in the n+1st row, Connection transistors SWb(n) are provided in series.

In this comparative example, the gate electrode of the amplification transistor AMP(n) of the pixel block BL(n), the drain diffusion region of the transfer transistors TXA(n) and TXB(n), and the source diffusion region of the first connection transistor SWa(n) The drain diffusion region of the second connection transistor SWb(n-1) and the source diffusion region of the reset transistor RST(n) are electrically connected to each other by a wiring 97(n) and are electrically conductive. The node P(n) corresponds to the wiring 97(n) and the entire portion that is electrically connected to and conductive to the wiring 97(n). This point also applies to other pixel blocks BL.

Further, in this comparative example, two connection transistors SWa and SWb provided in series between each two nodes P are connected by a wiring 98. For example, the drain diffusion region of the first coupling transistor SWa(n) and the source diffusion region of the second coupling transistor SWb(n) are electrically connected by a wiring 98(n).

In FIGS. 11 and 12, CA(n) is the capacitance between the node P(n) and the reference potential when the coupling transistors SWa(n) and SWb(n-1) are off. Let the capacitance value of capacitor CA(n) be Cfd1'. CB(n) indicates the capacitance between the wiring 72(n) and the reference potential when the coupling transistors SWa(n) and SWb(n) are off. These points also apply to the rows of other pixel blocks BL.

The capacitance CA(n) is the capacitance of the drain diffusion region of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region of the reset transistor RST(n), and the capacitance of the first coupling transistor SWa(n). Consists of the capacitance of the source diffusion region, the capacitance of the drain diffusion region of the second connection transistor SWb(n-1), the capacitance of the gate electrode of the amplification transistor AMP(n), and the wiring capacitance of the wiring 97(n). The sum of these capacitance values becomes the capacitance value Cfd1' of the capacitor CA(n). This point also applies to the rows of other pixel blocks BL.

On the other hand, the capacitance CC(n) in this embodiment is the capacitance of the drain diffusion region 41 of the transfer transistors TXA(n) and TXB(n) and the capacitance of the first transistor SWA(n), as described above. It consists of the capacitance of the source diffusion region, the capacitance of the gate electrode of the amplification transistor AMP(n), and the wiring capacitance of the wiring 71(n), and the sum of these capacitance values is the capacitance value Cfd1 of the capacitor CC(n). It has become.

Therefore, the capacitance value Cfd1 of the capacitance CC(n) in this embodiment is higher than the capacitance value Cfd1' of the capacitance CA(n) in this comparative example in the drain diffusion region of the second coupling transistor SWb(n-1). and the capacitance of the source diffusion region of the reset transistor RST(n) (that is, two transistor diffusion capacitances).

In this comparative example, focusing on pixel block BL(n), when both connection transistors SWa(n) and SWb(n-1) are turned off, the capacitance (charge) between node P(n) and the reference potential is The voltage conversion capacitor) becomes the capacitance CA(n), and the capacitance value of the charge-voltage conversion capacitor at the node P(n) becomes the minimum Cfd1', and the charge-voltage conversion coefficient due to the charge-voltage conversion capacitance increases, so the highest SN It becomes possible to read in ratio. Furthermore, in this comparative example, if the number of on-state coupling transistors that are electrically connected to the node P(n) among the coupling transistors SWa and SWb is increased to a desired number of one or more, Since the capacitance value of the charge-voltage conversion capacitor of node P(n) can be increased to a desired value and a large amount of signal charge can be handled, the number of saturated electrons can be increased. Thereby, the dynamic range can be expanded.

As described above, the minimum capacitance value Cfd1 of the charge-voltage conversion capacitance of the first node Pa(n) in this embodiment is the minimum capacitance value of the charge-voltage conversion capacitance of the node P(n) in this comparative example. It is smaller than Cfd1' by two transistor diffusion capacitances. Therefore, according to the present embodiment, the charge-voltage conversion coefficient becomes even larger than that of this comparative example, and reading with an even higher SN ratio becomes possible.

In this embodiment, the second transistor SWB is provided between all two second nodes Pb sequentially adjacent in the column direction, but the present invention is not necessarily limited to this. For example, between r second nodes Pb arranged in the column direction (r is an integer of 2 or more) and a second node Pb adjacent to the second node Pb on the lower side in the figure, The gap between them may be always open without providing the second transistor SWB. In this case, as the number r becomes smaller, the maximum number of the predetermined numbers in the second operation mode becomes smaller, and the degree of expansion of the dynamic range decreases. ratio can be improved. Also, for example, between every s second nodes Pb (s is an integer of 1 or more) arranged in the column direction and a second node Pb adjacent to the second node Pb on the lower side in the figure, may be electrically short-circuited without providing the second transistor SWB. Furthermore, for example, between u second nodes Pb (u is an integer of 1 or more) arranged in the column direction and a second node Pb adjacent to the second node Pb on the lower side in the figure, A second transistor SWB is provided only, while a second node Pb other than every second node Pb arranged in the column direction and a second node Pb adjacent to the second node Pb on the lower side in the figure is connected to the second node Pb arranged in the column direction. It may be electrically short-circuited.

In this embodiment, the capacitance value of the capacitor CD may be set to a value within ±20% of the capacitance value of the capacitor CC by providing an adjustment capacitor in the wiring 72, or The value may be within ±10% of the capacitance value. These points also apply to the second embodiment described below.

Note that each operation example shown in FIGS. 6 to 10 is an example of an operation in which the signal charge of the photodiode PD of each pixel PX is read out without mixing it with the signal charge of the photodiode PD of other pixels PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be mixed with the signal charge of the photodiode PD of another pixel PX of the same color and read out.

For example, by turning on the first transistors SWA(n-1), SWA(n), SWA(n+1) and the second transistors SWB(n), SWB(n+1), the first node Pa(n-1) , Pa(n), Pa(n+1) are connected to each other and TXA(n-1), TXA(n), TXA(n+1) are turned on at the same time. The signal charges of the photodiodes PDA(n-1), PDA(n), and PDA(n-1) of the pixels PXA(n-1), PXA(n), and PXA(n-1) are connected to each other in the first are averaged at nodes Pa(n-1), Pa(n), and Pa(n+1), and the function of mixed readout of three pixels of the same color can be realized. At this time, the second transistors SWB(n-2) and SWB(n+2) are turned off and are electrically connected to the first nodes Pa(n-1), Pa(n), and Pa(n+1). By minimizing the number of first or second transistors in the on-state, the charge-voltage conversion capacitance value at the connected first nodes Pa(n-1), Pa(n), Pa(n+1) is is minimized, and mixed readout of three pixels of the same color can be performed at the highest SN ratio. On the other hand, in addition to the first transistors SWA(n-1), SWA(n), SWA(n+1) and the second transistors SWB(n), SWB(n+1), each first transistor SWA and each second transistor If one or more of the transistors SWB in the on state are electrically connected to the first nodes Pa(n-1), Pa(n), Pa(n+1), the According to the number of pixels, the charge-voltage conversion capacitance value at the connected first nodes Pa(n-1), Pa(n), Pa(n+1) increases, thereby expanding the dynamic range of mixed readout of three pixels of the same color. I can do it.

[Second embodiment]
FIG. 13 is a circuit diagram showing a schematic configuration of a solid-state image sensor 84 of an electronic camera according to a second embodiment of the present invention, and corresponds to FIG. 2. In FIG. 13, elements that are the same as or correspond to those in FIG. 2 are denoted by the same reference numerals, and redundant explanation thereof will be omitted.

This embodiment differs from the first embodiment in that in the first embodiment, the photodiode PDB and the transfer transistor TXB are removed from each pixel block BL, and each The point is that the pixel block BL is the pixel PXA. However, in this embodiment, the density of the photodiodes PDAs in the column direction is twice the density of the photodiodes PDAs in the column direction in the first embodiment, and The density in the column direction of the entire PDA and PDB is the same. In this embodiment, n indicates the row of the pixel block BL as well as the row of the pixel PXA.

In other words, in the first embodiment, each pixel block BL is composed of two pixels PX (PXA, PXB), whereas in this embodiment, each pixel block BL is composed of one pixel PX (PXA, PXB). It is composed of pixels PX (PXA). In the first embodiment, the two pixels PX (PXA, PXB) belonging to the pixel block BL share a set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL. In contrast, in this embodiment, each pixel PX (in this embodiment, only PXA) has one set of first node Pa, amplification transistor AMP, reset transistor RST, and selection transistor SEL. are doing.

Basically, the description of the first embodiment is applicable to the present embodiment by replacing the pixel block BL with the pixel PXA. Therefore, detailed description of this embodiment will be omitted here.

This embodiment also provides the same advantages as the first embodiment.

Although the embodiments and modifications of the present invention have been described above, the present invention is not limited to these.

4 Solid-state image sensor BL Pixel block PX Pixel PD Photodiode TXA, TXB Transfer transistor Pa First node Pb Second node AMP Amplification transistor SWA First transistor SWB Second transistor RST Reset transistor (third transistor)

Claims (1)

An image sensor comprising a plurality of pixel blocks arranged along a column direction,
The pixel block is
a first photoelectric conversion section that converts light into charge;
a second photoelectric conversion section that is a photoelectric conversion section that converts light into charge and is arranged in line with the first photoelectric conversion section in the column direction;
One diffusion region to which charges converted by the first photoelectric conversion unit and charges converted by the second photoelectric conversion unit are transferred, and the first photoelectric conversion unit and the first photoelectric conversion unit are connected in the column direction. a diffusion section disposed between the two photoelectric conversion sections;
a first transistor electrically connected to the diffusion portion via a first wiring;
an amplification transistor having a gate portion electrically connected to the diffusion portion via the first wiring;
a reset switch that controls a connection between the first transistor and a supply section to which a predetermined voltage is supplied;
The first transistor of a first pixel block among the plurality of pixel blocks, and the first transistor of a second pixel block arranged next to the first pixel block among the plurality of pixel blocks. , an image sensor electrically connected via a connection portion having a second wiring.

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