JP2014107448A - Laminated semiconductor device manufacturing method and laminated semiconductor manufacturing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a laminated semiconductor device in a simple process.SOLUTION: A laminated semiconductor device manufacturing method of laminating a light-receiving substrate having a light-receiving circuit including a light-receiving element and a processing substrate having a processing circuit for processing a signal received from the light-receiving circuit comprises: a heterogeneous substrate lamination step of laminating the light-receiving substrate and the processing substrate by facing a surface on the light-receiving circuit side and a surface on the processing circuit side; and a light-receiving substrate thinning step of thinning the light-receiving substrate after the heterogeneous substrate lamination step. In the above-described manufacturing method, a processing substrate thinning step for thinning the processing substrate may be included prior to the light-receiving substrate thinning step.

Description

  The present invention relates to a method for manufacturing a stacked semiconductor device and a stacked semiconductor manufacturing device.

There is a stacked semiconductor device manufactured by stacking a substrate including a light receiving element and a substrate including a signal processing circuit.
[Prior art documents]
[Patent Literature]
[Patent Document 1] Japanese Patent Application Laid-Open No. 2006-49361

  The laminated semiconductor device is low in productivity because the number of man-hours is increased by, for example, a procedure of detaching a supporting dummy substrate in the substrate thinning stage.

  According to a first aspect of the present invention, there is provided a method of manufacturing a laminated semiconductor device by laminating a light receiving substrate having a light receiving circuit including a light receiving element and a processing substrate having a processing circuit for processing a signal received from the light receiving circuit. A heterogeneous substrate stacking step in which the light receiving substrate side and the processing circuit side surface face each other, and a light receiving substrate thinning step in which the light receiving substrate is thinned after the heterogeneous substrate stacking step. A method for manufacturing a stacked semiconductor device is provided.

  In a second aspect of the present invention, there is provided an apparatus for manufacturing a laminated semiconductor device by laminating a light receiving substrate having a light receiving circuit including a light receiving element and a processing substrate having a processing circuit for processing a signal received from the light receiving circuit. The light receiving substrate and the processing substrate face each other with the light receiving circuit side surface of the light receiving substrate having the light receiving circuit including the light receiving element and the processing circuit side surface of the processing substrate having a processing circuit for processing a signal received from the light receiving circuit. There is provided a laminated semiconductor manufacturing apparatus comprising: a heterogeneous substrate laminating unit for laminating a semiconductor substrate; and a light receiving substrate laminated on a processing substrate by the heterogeneous substrate laminating unit, and a light receiving substrate thinning unit for thinning the light receiving substrate.

  The above summary of the present invention does not enumerate all necessary features of the present invention. A sub-combination of these feature groups can also be an invention.

2 is a cross-sectional view of a light receiving substrate 100. FIG. It is sectional drawing of the process board | substrate 200. FIG. 3 is a cross-sectional view of a multilayer substrate 300. FIG. 3 is a cross-sectional view of a multilayer substrate 300. FIG. 3 is a cross-sectional view of a multilayer substrate 300. FIG. 3 is a cross-sectional view of a multilayer substrate 300. FIG. 3 is a cross-sectional view of a multilayer substrate 300. FIG. 3 is a cross-sectional view of a multilayer substrate 300. FIG. 3 is a cross-sectional view of a multilayer substrate 300. FIG. 3 is a cross-sectional view of a multilayer substrate 300. FIG. 3 is a cross-sectional view of a multilayer substrate 300. FIG. 3 is a cross-sectional view of a multilayer substrate 300. FIG. 4 is a cross-sectional view of a laminated semiconductor device 400. FIG. 2 is a cross-sectional view of a multilayer substrate 301. FIG. 2 is a cross-sectional view of a multilayer substrate 301. FIG. 3 is a cross-sectional view of a multilayer substrate 302. FIG. 3 is a cross-sectional view of a multilayer substrate 302. FIG. 3 is a cross-sectional view of a multilayer substrate 302. FIG. 2 is a cross-sectional view of a stacked semiconductor device 401. FIG. 3 is a cross-sectional view of a multilayer substrate 303. FIG.

  Hereinafter, the present invention will be described through embodiments of the invention. The following embodiments do not limit the invention according to the claims. Not all combinations of features described in the embodiments are essential for the solution of the invention.

  FIG. 1 is a cross-sectional view of a light receiving substrate 100 that can be used as a material of the laminated semiconductor device 400. The light receiving substrate 100 includes a support substrate 110, a semiconductor well 130, and a multilayer wiring layer 150.

  The support substrate 110 is formed of a silicon single crystal wafer or the like, and has a thickness that bears the mechanical strength of the light receiving substrate 100, for example, a thickness of about 775 μm if the silicon single crystal wafer has a diameter of 12 inches. A semiconductor well 130 is disposed on one surface of the support substrate 110 via an insulating layer 120. A plurality of photodiodes 132 are formed in a matrix in the semiconductor well 130 in the surface direction of the support substrate 110.

  A plurality of field effect transistors are also formed in the semiconductor well 130 by the gate electrode 140 and the like formed adjacent to each other. With such a structure, the stray capacitance of the support substrate 110 with respect to the light receiving circuit 111 formed by the photodiode 132 and the field effect transistor is suppressed, so that the switching speed of the light receiving circuit 111 is improved and the power consumption is reduced.

  The multilayer wiring layer 150 is formed by interlayer insulating materials 152 and wiring materials 154 that are alternately stacked on the surface of the semiconductor well 130. As the wiring material 154, a metal material such as titanium or tungsten can be used.

  The photodiode 132 and the field effect transistor are connected to each other by the multilayer wiring layer 150 to form a light receiving circuit 111 having a thickness of approximately 10 μm or less. One end of the wiring member 154 in the multilayer wiring layer 150 is electrically connected to the connection pad 160 exposed to the outside on one surface opposite to the support substrate 110.

  In the light receiving circuit 111, each of the photodiodes 132 corresponds to a pixel, and a field effect transistor performs reset, selection, and amplification for each pixel. The electric charge accumulated by the photodiode 132 upon receiving incident light is output to the outside from the connection pad 160 as a voltage signal through a source follower by a field effect transistor.

  FIG. 2 is a cross-sectional view of a processing substrate 200 that can be used as a material for the stacked semiconductor device 400. The processing substrate 200 includes a support substrate 210, a semiconductor well 230, and a multilayer wiring layer 250.

  The support substrate 210 is formed of a silicon single crystal wafer or the like, and has a thickness that bears the mechanical strength of the light receiving substrate 100, for example, a thickness of about 775 μm in the case of a silicon single crystal wafer having a diameter of 12 inches. A semiconductor well 230 is disposed on one surface of the support substrate 210. A plurality of field effect transistors are formed in the semiconductor well 230 by the gate electrode 240 formed adjacent to the semiconductor well 230.

  The multilayer wiring layer 150 is formed by interlayer insulating materials 252 and wiring materials 254 that are alternately stacked on the surface of the semiconductor well 230. The plurality of field effect transistors are connected to each other by the multilayer wiring layer 250 to form the processing circuit 211.

  In addition, one end of the wiring member 254 in the multilayer wiring layer 250 is electrically connected to the connection pad 260 exposed to the outside on one surface opposite to the support substrate 210. The connection pad 260 of the processing substrate 200 is connected to the connection pad 160 of the light receiving substrate 100. As a result, the processing circuit 211 of the processing substrate 200 processes the output signal of the light receiving circuit 111 of the light receiving substrate 100. Examples of processing in the processing circuit 211 include analog / digital conversion, noise suppression, file generation, and the like.

  The illustrated processing substrate 200 has a through electrode 256 fitted into the support substrate 210. The through electrode is formed of copper by a dual damascene method, for example. One end of the through electrode 256 is electrically connected to the wiring member 254 of the multilayer wiring layer 250. The other end of the through electrode 256 is buried in the support substrate 210 in the illustrated stage.

  By laminating the light receiving substrate 100 and the processing substrate 200 as described above, a laminated semiconductor device 400 that can be used as an image sensor can be manufactured. 3 to 13 are cross-sectional views showing the manufacturing process of such a stacked semiconductor device 400 step by step.

  Each of the light receiving substrate 100 and the processing substrate 200 has the structure shown in FIG. 1 or FIG. 2 repeatedly in each plane direction. Therefore, by stacking the light receiving substrate 100 and the processing substrate 200, the stacked substrate 300 including a large number of stacked semiconductor devices 400 can be manufactured collectively.

  First, as shown in FIG. 3, the light receiving substrate 100 and the processing substrate 200 are laminated to form a laminated substrate 300. In the illustrated example, the front and back of the light receiving substrate 100 are reversed with respect to the state shown in FIG. Thereby, the laminated substrate 300 having a thickness of 1550 μm or more is formed at this stage. In the multilayer substrate 300, the connection pads 160 of the light receiving substrate 100 and the connection pads 260 of the processing substrate 200 are in contact with each other and are electrically connected.

  The light receiving substrate 100 and the processing substrate 200 may be bonded together by pressing at least one of the connection pads 160 and 260 with solder bumps, copper bumps, or the like. In this case, since the light receiving substrate 100 and the processing substrate 200 have the support substrates 110 and 210, respectively, a sufficient pressure can be applied.

  Further, the end surfaces of the light receiving substrate 100 and the processing substrate 200 including the connection pads 160 and 260 may be mirror-polished and bonded at room temperature. Also in this case, since the light receiving substrate 100 and the processing substrate 200 have the supporting substrates 110 and 210, the light receiving substrate 100 and the processing substrate 200 can be polished while holding the supporting substrates 110 and 210.

  For the alignment of the light receiving substrate 100 and the processing substrate 200, the yield of the multilayer substrate 300 is determined by a global alignment method that calculates the position where the total positional deviation is minimized based on the positional deviation of several predetermined alignment indices. Can be improved. Furthermore, the alignment accuracy can be further improved by adding offset correction, rotation correction, orthogonality correction, scaling correction, and the like based on the position of the alignment index.

  As the alignment index, the connection pads 160 and 260 themselves may be used, or wirings and substrates formed on the light receiving substrate 100 and the processing substrate 200 may be used. Further, alignment marks provided on the light receiving substrate 100 and the processing substrate 200 may be used for the purpose of use in alignment. In addition, when observing the alignment index for measuring the positional deviation, in addition to the method of directly observing the bonding surface of the light receiving substrate 100 and the processing substrate 200, the alignment index may be observed in the infrared band transmitting the substrate. .

  Next, as shown in FIG. 4, in the laminated substrate 300, the support substrate 210 of the processing substrate 200 is thinned to about 500 μm, for example. The support substrate 210 can be thinned by chemical mechanical polishing, for example. As a result, the end portion of the through electrode 256 is exposed on the lower surface of the support substrate 210 in the drawing.

  Prior to thinning of the processing substrate 200, the laminated substrate 300 may be annealed in a temperature range of 200 ° C. to 300 ° C. for a processing time of 30 minutes to 60 minutes. As a result, the internal stress generated in the laminated substrate 300 due to the bonding of the light receiving substrate 100 and the processing substrate 200 is relieved, so that the light receiving substrate 100 and the processing substrate 200 are peeled off by the stress generated by polishing or the like for thinning. It is prevented.

  In addition, the laminated substrate 300 may be annealed under the same conditions as described above even after the processing substrate 200 is thinned. Since the support substrate 210 after the thinning process has high flatness, the multilayer substrate 300 can be uniformly heated as a whole. Therefore, the internal stress that is relaxed by the annealing process is also uniform throughout the multilayer substrate 300.

  Next, as shown in FIG. 5, bumps 220 are formed on the end portions of the through electrodes 256 exposed on the lower surface of the support substrate 210 in the drawing. As a result, the processing circuit 211 of the processing substrate 200 can be connected to the outside from the lower surface of the multilayer substrate 300 in the drawing. As the bump 220, for example, a solder bump joined by molten solder, a copper bump joined by mutual diffusion, or the like can be appropriately selected.

  Next, as shown in FIG. 6, the support substrate 110 of the light receiving substrate 100 is thinned. For example, the support substrate 110 can be thinned by holding the support substrate 210 remaining on the processing substrate 200 side and performing chemical mechanical polishing. Here, in the illustrated example, the chemical mechanical polishing is stopped immediately before the insulating layer 120 is exposed without removing all of the support substrate 110.

  In the steps so far, the surface of the light receiving substrate 100 is covered with the support substrate 210 of the light receiving substrate 100. Therefore, dust generated by polishing of the support substrate 210 on the processing substrate 200 side, formation of the bumps 220, etc. is removed together with the thinning process of the support substrate 110 even if it adheres to the support substrate 110 on the light receiving substrate 100 side. Is done.

  Even when the support substrate 110 on the light receiving substrate 100 side is thinned as described above, the laminated substrate 300 may be annealed before and after the thinning process. Thereby, the residual stress of the multilayer substrate 300 can be relieved. Further, the stress generated by the thinning process can be released. The annealing process is effective in a temperature range of 200 ° C. to 300 ° C. and a processing time of 30 minutes to 60 minutes.

  Subsequently, as shown in FIG. 7, the support substrate 110 remaining on the surface of the insulating layer 120 is removed by chemical etching. As the etchant, a material having a selectivity that etches the support substrate 110 but does not react with the insulating layer 120 is used. As a result, the light receiving circuit 111 having a thickness of about 10 μm remains on the multilayer substrate 300. Thereby, the surface of the light receiving substrate 100 formed after the support substrate 110 is removed has the flatness of the insulating layer 120 itself. In this manner, by leaving the support substrate 110 by chemical mechanical polishing and removing the support substrate 110 by etching, it is possible to prevent unevenness in the polishing amount that tends to occur due to chemical mechanical polishing.

  Thus, in the above method, the laminated substrate 300 can be manufactured by executing the thinning process without using a dummy substrate that is temporarily used only when chemical mechanical polishing is performed. Therefore, the number of work steps such as attaching and detaching the dummy substrate can be omitted, and the manufacturing process of the laminated substrate can be simplified.

  Next, as illustrated in FIG. 8, a light shielding layer 170 is formed on the surface of the laminated substrate 300 on the light receiving substrate 100 side. The light shielding layer 170 blocks incident light incident on the periphery of the photodiode 132 in the light receiving substrate 100. In other words, incident light is incident on the light receiving substrate 100 only in the region where the photodiode 132 is formed.

  The light shielding layer 170 can be formed, for example, by depositing a metal material such as aluminum or tungsten by vapor deposition. The material of the light shielding layer 170 may be the same material as the wiring material 154 in the multilayer wiring layer 150. However, the light shielding layer 170 has a thickness that can block transmitted light. As described above, the pattern accuracy of the light shielding layer 170 can be improved by arranging the photodiode 132 adjacently.

  As described above, when the multilayer substrate 300 is used, a back-illuminated image sensor that makes light incident on the photodiode 132 from the side where the support substrate 110 is present in the light receiving substrate 100 is manufactured. Therefore, the subsequent manufacturing process includes a step of forming a layer that transmits incident light on the trace where the support substrate 110 is removed.

  Next, as illustrated in FIG. 9, a planarization layer 172 is formed on the surfaces of the insulating layer 120 and the light shielding layer 170. The planarization layer 172 can be formed of a silicon oxide film deposited by physical vapor deposition such as plasma CVD.

  Next, as shown in FIG. 10, an organic planarization layer 174 is formed on the surface of the planarization layer 172. The organic planarization layer 174 can be formed, for example, by applying a polyimide resin or the like. Thereby, the flatness of the incident side end face of the light receiving substrate 100 is improved, and the adhesiveness of another resin layer described below is improved.

  Note that the heat resistance temperature of the organic planarization layer 174 is lower than that of the Si compound or the like forming other layers. Therefore, high-temperature annealing cannot be performed at a stage after the organic planarization layer 174 is formed.

  Next, as shown in FIG. 11, an on-chip color filter 180 is formed on the surface of the organic planarization layer 174. The on-chip color filter 180 is disposed corresponding to each of the photodiodes 132. The on-chip color filter 180 is formed of a photoresist material containing a pigment, and is colored, for example, red, blue and green (primary colors) or cyan, magenta and yellow (complementary colors). Furthermore, the on-chip color filter 180 may be combined with four or more color filters.

  Next, as shown in FIG. 12, an organic planarization layer 182 is further formed on the surface of the light receiving substrate 100 including the surfaces of the organic planarization layer 174 and the on-chip color filter 180. As a result, the on-chip color filter 180 is embedded in the organic planarization layers 174 and 182. Further, the outermost surface of the light receiving substrate 100 is flattened again.

  Next, as shown in FIG. 13, an on-chip lens 190 is formed on the surface of the organic planarization layer 182. The on-chip lens 190 is formed by processing a lens material layer formed of an organic resin into a lens shape by etching back, reflow, or the like. Each of the on-chip lenses 190 is a convex lens whose center is thicker than the edge, and condenses incident light incident on a wide area on the photodiode 132. The light shielding layer 170, the flattening layer 172, the organic flattening layers 174 and 182, the on-chip color filter 180, and the on-chip lens 190 are not all essential, and may be wholly or partially depending on the application. Create it.

  Thus, the laminated semiconductor device 400 having the cross-sectional structure shown in FIG. 13 is completed. The laminated semiconductor device 400 is a backside illuminated image sensor in which incident light enters from the side where the support substrate 110 is present in the light receiving substrate 100. The electric charge generated by the incident light on the photodiode 132 is transferred to the processing circuit 211 as a voltage signal, and further output from the bump 220 through processing such as digital conversion.

  The laminated substrate 300 on which the laminated semiconductor device 400 is formed is cut into a large number of dies by dicing. Each of the dies thus obtained has a high yield and a high integration density because the light-receiving substrate 100 and the processing substrate 200 are laminated.

  When elements having an optical function such as the light shielding layer 170, the on-chip color filter 180, and the on-chip lens 190 are formed on the surface of the light receiving substrate 100 after the state shown in FIG. Is aligned with respect to the light receiving substrate 100. In this case, the photodiode 132 visible through the insulating layer 120, the planarization layer 172, and the organic planarization layers 174 and 182 may be used as an alignment index. An alignment mark may be formed in advance on the insulating layer 120. Furthermore, the light receiving substrate 100 may be observed with infrared band illumination light, and the structure of the multilayer wiring layer 150 may be used as an alignment index.

  FIG. 14 is a cross-sectional view of another laminated substrate 301. The multilayer substrate 301 is formed by stacking a pair of processing substrates 201 and 202 having the same structure as the processing substrate 200 shown in FIG. 2 so that the connection pads 260 are joined to each other. The alignment index, alignment method, and bonding method related to the bonding of the processing substrates 201 and 202 are as described with reference to FIG. As a result, the processing circuit 212 of the processing substrate 201 and the processing circuit 213 of the processing substrate 202 are connected to each other to form an integrated circuit.

  Next, as shown in FIG. 15, the support substrate 210 of one processing substrate 202 in the multilayer substrate 301 is thinned, and bumps 220 are formed on the end surfaces of the through electrodes 256 exposed on the surface of the support substrate 210. The thinning method and the bump 220 forming method are as described with reference to FIGS.

  Next, as illustrated in FIG. 16, the multilayer substrate 301 in the state illustrated in FIG. 15 and the multilayer substrate 300 in the state illustrated in FIG. 5 are bonded to form the multilayer substrate 302. The bumps 220 of the multilayer substrate 301 and the bumps 220 of the multilayer substrate 302 can be joined by mutual diffusion of copper bumps, melting of solder bumps, or the like.

  Thus, the light receiving circuit 111 and the processing circuit 211 included in the multilayer substrate 300 and the processing circuits 212 and 213 in the multilayer substrate 301 are coupled to each other through the bump 220 and the through electrode 256. As a result, a large scale processing circuit that is three times as large as the multilayer substrate 300 is formed on the entire multilayer substrate 302.

  Next, as shown in FIG. 17, the support substrate 210 of the processing substrate 201 positioned at the lower end of the multilayer substrate 302 is thinned, and bumps 220 are formed on the end surfaces of the through electrodes 256 exposed on the surface of the support substrate 210. Form. The thinning process and the bump 220 are formed in the same manner as described with reference to FIGS. Thus, the large-scale processing circuit formed on the multilayer substrate 302 can be output to the outside through the bumps 220 of the lowermost processing substrate 201 in the drawing.

  Next, as shown in FIG. 18, the support substrate 110 of the light receiving substrate 100 in the laminated substrate 302 is removed by thinning and etching. The thinning and removal of the support substrate 110 are as described with reference to FIGS.

  Subsequently, as illustrated in FIG. 19, the light shielding layer 170, the planarization layer 172, the organic planarization layers 174 and 182, the on-chip color filter 180 and the on-chip lens 190 are formed on the insulating layer 120 exposed in the light receiving substrate 100. Are sequentially formed to complete the stacked semiconductor device 401. The formation process of these optical elements is as described with reference to FIGS.

  Since the stacked semiconductor device 401 manufactured in this way includes a large-scale processing circuit including processing circuits 211, 212, and 213, in addition to an analog / digital converter, a buffer circuit, a storage circuit, a processor, and the like are integrated. It can be an image sensor. Further, in the process of laminating the processing substrates 200, 201, and 202, the light receiving surface of the light receiving substrate 100 is covered with the support substrate 110, and thus occurs due to a thinning process of the support substrate 210 of the processing substrates 200, 201, and 202. This prevents dust from remaining on the surface of the light receiving substrate 100 from affecting the performance of the image sensor.

  Also in the manufacturing process of the laminated semiconductor device 401, annealing may be performed before and after each of the lamination stage of the processing substrates 201 and 202 and the lamination stage of the lamination substrates 300 and 301. However, at the stage of laminating the individual laminated substrates 300 and 301, bonding may be performed at a low temperature without annealing, and annealing may be performed collectively after all the substrates have been laminated. This prevents the substrate laminated in the initial stage from being exposed to the heat of the annealing process repeatedly.

  FIG. 20 is a cross-sectional view of still another laminated substrate 303. The multilayer substrate 303 is formed by sequentially laminating a plurality of processing substrates 201 one by one on the multilayer substrate 300 in the state shown in FIG. That is, by repeating the steps of bonding the processing substrate 201 before thinning the support substrate 210 to the laminated substrate 300 with the support substrate 110 left, thinning the support substrate 210, and forming the bumps 220. A multilayer laminated substrate 303 can be formed.

  As described above, since the processing substrates 201 are sequentially stacked one by one in the manufacturing process of the multilayer substrate 303, any number of processing substrates 201 can be stacked according to the required specifications. 14 to 16, a procedure for stacking a prefabricated multilayer substrate 301 on another substrate and a procedure for stacking the processing substrates 201 one by one as shown in FIG. 20 are mixed. Thus, a larger scale semiconductor device may be manufactured.

  In this stacking process, the stacking and thinning of the processing substrate 201 can be repeated while the light receiving surface of the light receiving substrate 100 is covered with the support substrate 110. Therefore, dust generated by the thinning process of the support substrate 210 in the processing substrate 201 is prevented from remaining on the surface of the light receiving substrate 100 and affecting the performance as an image sensor.

  Thereby, a multilayer laminated semiconductor device can be manufactured without using a dummy substrate temporarily used in a thinning process such as polishing. Therefore, it is possible to reduce the man-hour when manufacturing the laminated semiconductor device and to suppress the consumption of the discarded dummy substrate.

  Even when the laminated substrate 303 as described above is manufactured, the individual layers may be bonded at a low temperature without annealing, and may be annealed collectively after all the substrates are laminated. This prevents the substrate laminated in the initial stage from being exposed to the heat of the annealing process repeatedly.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

100 light receiving substrate, 110 supporting substrate, 111 light receiving circuit, 120 insulating layer, 130, 230 semiconductor well, 132 photodiode, 140, 240 gate electrode, 150, 250 multilayer wiring layer, 152, 252 interlayer insulating material, 154, 254 wiring Material, 160, 260 connection pad, 170 light shielding layer, 172 planarization layer, 174, 182 organic planarization layer, 180 on-chip color filter, 190 on-chip lens, 200, 201, 202 processing substrate, 210 support substrate, 211, 212, 213 processing circuit, 220 bump, 256 through electrode, 300, 301, 302, 303 laminated substrate, 400, 401 laminated semiconductor device

Claims (12)

A manufacturing method for manufacturing a laminated semiconductor device by laminating a light receiving substrate having a light receiving circuit including a light receiving element and a processing substrate having a processing circuit for processing a signal received from the light receiving circuit,
A heterogeneous substrate stacking step of stacking the light receiving substrate and the processing substrate with the light receiving circuit side surface facing the processing circuit side surface;
A method for manufacturing a laminated semiconductor device, comprising: a light receiving substrate thinning step of thinning the light receiving substrate after the dissimilar substrate stacking step.   The method for manufacturing a laminated semiconductor device according to claim 1, further comprising a process substrate thinning step of thinning the processing substrate before the light receiving substrate thinning step.   3. The method according to claim 2, further comprising a step of collectively annealing the stacked light receiving substrate and the processing substrate after the processing substrate thinning step and before the light receiving substrate thinning step. The laminated semiconductor device manufacturing method according to claim.   The process substrate laminating step of laminating another processing substrate having another processing circuit connected to the processing circuit on the processing substrate having the processing circuit before the heterogeneous substrate laminating step. The method for manufacturing a laminated semiconductor device according to any one of claims 1 to 3.   5. The method of manufacturing a laminated semiconductor device according to claim 4, further comprising a step of collectively annealing the processed substrates that are stacked after the processing substrate stacking step and before the dissimilar substrate stacking step. .   6. The laminated semiconductor device manufacturing according to claim 1, wherein the light receiving substrate thinning step includes a polishing step of chemically mechanically polishing a support layer that supports an insulating layer adjacent to the light receiving circuit. Method.   The method of manufacturing a laminated semiconductor device according to claim 6, wherein the thinning step of the light receiving substrate includes an etching step of etching the support layer until reaching the insulating layer after the polishing step.   8. The method according to claim 1, further comprising a step of collectively annealing the stacked light receiving substrate and the processing substrate after the stacking step and before the light receiving substrate thinning step. The method for manufacturing a laminated semiconductor device according to one item.   9. The stacked semiconductor according to claim 1, further comprising a step of collectively annealing the stacked light receiving substrate and the processing substrate after the light receiving substrate thinning step. 10. Device manufacturing method.   10. The light receiving substrate stacking step of further stacking another light receiving substrate having another light receiving circuit on the light receiving substrate before the different substrate stacking step. 10. A method for manufacturing a laminated semiconductor device.   The method of manufacturing a stacked semiconductor device according to claim 10, further comprising a step of thinning the other light receiving substrate after the light receiving substrate stacking step and before the heterogeneous substrate stacking step. A device for manufacturing a laminated semiconductor device by laminating a light receiving substrate having a light receiving circuit including a light receiving element and a processing substrate having a processing circuit for processing a signal received from the light receiving circuit,
A light receiving substrate having a light receiving circuit including a light receiving element, and a surface on the light receiving circuit side facing a surface on the processing circuit side of a processing substrate having a processing circuit for processing a signal received from the light receiving circuit; A heterogeneous substrate stacking unit for stacking the processing substrates;
A laminated semiconductor manufacturing apparatus, comprising: a light receiving substrate thinned portion for thinning the light receiving substrate in the light receiving substrate laminated on the processing substrate by a heterogeneous substrate laminated portion.

Images