JP2001339057A - Method of manufacturing three-dimensional image processor - Google Patents

Method of manufacturing three-dimensional image processor

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JP2001339057A
JP2001339057A JP2000160330A JP2000160330A JP2001339057A JP 2001339057 A JP2001339057 A JP 2001339057A JP 2000160330 A JP2000160330 A JP 2000160330A JP 2000160330 A JP2000160330 A JP 2000160330A JP 2001339057 A JP2001339057 A JP 2001339057A
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substrate
dimensional image
formed
processing apparatus
image processing
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JP3713418B2 (en
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Mitsumasa Koyanagi
Nobuaki Miyagawa
Taisuke Okano
宣明 宮川
光正 小柳
泰典 岡野
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Fuji Xerox Co Ltd
Mitsumasa Koyanagi
富士ゼロックス株式会社
光正 小柳
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0232Optical elements or arrangements associated with the device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14609Pixel-elements with integrated switching, control, storage or amplification elements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14625Optical elements or arrangements associated with the device
    • H01L27/14627Microlenses
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14634Assemblies, i.e. Hybrid structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a three-dimensional image processor which can sharply simplify the manufacture process due to needlessness of mounting and removal process of a supporting board, can manufacture a three-dimensional image processor by simple and easy process, and can form embedded wiring surrounded by a highly reliable insulating film. SOLUTION: A transparent substrate 10 made of quartz glass, where many microlenses 12 are made two-dimensionally, is bonded to a photoelectric transfer substrate 20 where a photodiode and a MOS transistor are made on an n-type silicon crystalline substrate 16 wherein an insulating layer 36 consisting of silicon diode is inserted, through an adhesive 14 consisting of high polymer material such as epoxy resin, polyimide resin, or the like, so that the main face of the photoelectric transfer substrate 20 and the rear of the transparent substrate 10 may oppose to each other.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、3次元画像処理装置の製造方法に関する。 The present invention relates to a method for producing a three-dimensional image processing apparatus.

【0002】 [0002]

【従来の技術】近年、半導体集積回路装置の高集積化・ In recent years, high integration of semiconductor integrated circuit device,
高密度化等の目的から、複数の回路機能ブロックを立体的に集積した3次元半導体集積回路装置の開発が進められている。 The purpose of such high density, development of three-dimensional semiconductor integrated circuit device which sterically integrating a plurality of circuit function blocks has been developed. 特に、イメージセンサとその信号を処理するための信号処理回路を一体化した3次元画像処理装置(インテリジェントイメージプロセッサ)は、光センサから得られる画像データを並列に高速処理し、高画質画像をリアルタイムで得ることが可能になることから、多くの期待が寄せられている。 In particular, the image sensor and three-dimensional image processing apparatus obtained by integrating a signal processing circuit for processing the signal (Intelligent image processor), the image data obtained from the optical sensor and high-speed processing in parallel, the real-time high-quality image since it becomes possible to obtain, the number of expected are asked.

【0003】これら3次元半導体集積回路装置は、当初はレ−ザ再結晶化等によるSOI(Silicon On Insulat [0003] These three-dimensional semiconductor integrated circuit device is initially Le - The re-crystallization, and the like SOI (Silicon On Insulat by
or)技術を利用してSOI基板形成とSOI基板への半導体装置の形成を繰り返すモノリシック法によりその製造が検討されてきたが、SOIを多層に積層するには、 or) by utilizing the technique repeated formation of the semiconductor device to an SOI substrate formed with the SOI substrate but the production has been examined by a monolithic process, the laminated SOI multilayer is
結晶性の確保が難しい、製造時間が長い等の問題があった。 Ensuring crystallinity is difficult, production time was long such problems.

【0004】このため、半導体装置または半導体集積回路装置が予め作製された単結晶半導体基板同士を貼り合わせる貼り合わせ技術による3次元半導体集積回路装置の製造方法が種々検討されている。 [0004] Therefore, a method of manufacturing a semiconductor device or a semiconductor integrated circuit device is prefabricated three-dimensional semiconductor integrated circuit device according bonding technique bonded to the single crystal semiconductor substrate with each other have been studied.

【0005】月刊セミコンダクターワールド(林善宏等、1990年9月号p58〜64)には、貼り合わせ技術の一種として、研磨により薄膜化した半導体基板を貼り合わせるCUBIC技術が提案されている。 [0005] Monthly Semiconductor World in the (Yoshihiro Hayashi et al., 1990 September p58~64), as a kind of bonding technique, CUBIC technology for bonding the semiconductor substrate with a thin film has been proposed by polishing. CUB CUB
IC技術では、まずシリコン基板上に半導体素子が形成された第1の半導体基板を支持基板に接着した後、余分なシリコン基板をポリッシングして薄膜化する。 In IC technology, after bonding the first first semiconductor substrate having a semiconductor element on a silicon substrate is formed on the supporting substrate, a thin film by polishing the excess silicon substrate. 次に、 next,
埋め込み配線、裏面配線、バンプ/プールからなるコンタクト部材等のデバイスの縦方向の接続に必要な配線を形成し、第1の半導体基板とシリコン基板上に半導体素子の形成された第2の半導体基板とを貼り合わせる。 Embedded wiring, backside interconnect, the second semiconductor substrate to form a wiring required for vertical connection devices of the contact member or the like made of bumps / pool, which is formed of a semiconductor device in the first semiconductor substrate and the silicon substrate attaching the door. そして最後に支持基板を取り外して多層構造の半導体装置が完成する。 Finally, remove the support substrate a semiconductor device with a multilayer structure is completed.

【0006】また、特開平6−260594号公報には、貼り合わせ技術による3次元半導体集積回路装置の製造方法が開示されている。 [0006] JP-A-6-260594, combined method of manufacturing a three-dimensional semiconductor integrated circuit device according to techniques are disclosed together. この方法は、シリコン基板上に半導体素子が形成された第1の半導体基板を支持基板に接着した後、余分なシリコン基板をポリッシングして薄膜化する点はCUBIC技術と共通しているが、第1の半導体基板に予め埋め込み配線を形成するための深溝が設けられている点、及び第1の半導体基板とシリコン基板上に半導体素子の形成された第2の半導体基板とを貼り合わせ、貼り合わせ後に支持基板を取り除き埋め込み配線を形成する点で、CUBIC技術とは異なっている。 This method, after bonding the first semiconductor substrate having a semiconductor element formed on a silicon substrate to a supporting substrate, a point thinning by polishing the excess silicon substrate in common with CUBIC technology, the that deep grooves in order to form a pre-buried wiring 1 of the semiconductor substrate is provided, and the second bonding a semiconductor substrate formed of a semiconductor device in the first semiconductor substrate and the silicon substrate, bonding in terms of forming a removing buried wiring support substrate after is different from the CUBIC technology.

【0007】 [0007]

【発明が解決しようとする課題】しかしながら、いずれの製造方法も、第1の半導体基板を支持基板に貼り合わせ、研磨した後に支持基板から第1の半導体基板を剥離する工程を含んでおり、製造工程が煩雑であるという問題があった。 [SUMMARY OF THE INVENTION However, any of the manufacturing methods, bonding a first semiconductor substrate to the supporting substrate includes a step of removing the first semiconductor substrate from the support substrate after polishing, prepared process there has been a problem that is complicated. 特に、3次元画像処理装置を製造する場合には、支持基板を取り除いた後にその表面にイメージセンサを構成するマイクロレンズを備えた透明基板を設ける必要があるため、なおさら製造工程が煩雑になる。 In particular, in the production of three-dimensional image processing apparatus, it is necessary to provide a transparent substrate having a micro-lens constituting the image sensor on its surface after removing the supporting substrate, even more manufacturing process becomes complicated.

【0008】また、CUBIC技術では、余分なシリコン基板をポリッシングして薄膜化した後に支持基板を取り除くため、支持基板を取り除く際に半導体基板上に形成された集積回路が破損するという問題があった。 [0008] In the CUBIC technology, for removing the support substrate after thinning by polishing the excess silicon substrate, an integrated circuit formed on a semiconductor substrate is disadvantageously damaged when removing the supporting substrate .

【0009】また、特開平6−260594号公報に記載された方法では、埋め込み配線を形成するための深溝が予め設けられた第1の半導体基板を支持基板に接着するため、深溝に入り込んだ接着剤の除去が困難であるという問題や、第1の半導体基板と第2の半導体基板とを接着した後に深溝の側壁を酸化して絶縁膜を形成するため、接着剤の耐熱温度以上に酸化温度を上げることができず、信頼性のある絶縁膜を形成することができないという問題があった。 Further, in the method described in JP-A-6-260594, for bonding the first semiconductor substrate which deep groove for forming the buried wiring is provided in advance on the supporting substrate, it has entered deep groove adhesive and a problem that removal of the agent is difficult, the first semiconductor substrate and the side wall of the deep groove is oxidized to form an insulating film after bonding the second semiconductor substrate, oxidation temperature than heat-resistant temperature of the adhesive It can not be increased, making it impossible to form a reliable insulating film.

【0010】本発明は上記従来技術の問題点に鑑みなされたものであり、本発明の目的は、支持基板の着脱工程が不要で製造工程を大幅に簡略化することができ、簡素かつ容易な工程により3次元画像処理装置を製造することができる3次元画像処理装置の製造方法を提供することにある。 [0010] The present invention has been made in view of the above-mentioned problems of the prior art, an object of the present invention, removable step of supporting the substrate can greatly simplify the manufacturing process is unnecessary, a simple and easy it is to provide a method for producing a three-dimensional image processing apparatus capable of producing a three-dimensional image processing apparatus by the process. また、本発明の他の目的は、信頼性の高い絶縁膜で囲まれた埋め込み配線を形成することができる3 Another object of the present invention, it is possible to form a buried wiring surrounded by a reliable insulating film 3
次元画像処理装置の製造方法を提供することにある。 It is to provide a method of manufacturing dimensional image processing apparatus.

【0011】 [0011]

【課題を解決するための手段】上記目的を達成するために、請求項1に記載の3次元画像処理装置の製造方法は、光を集光するレンズを備えた透明基板と、主面に光電変換素子が形成されると共に該光電変換素子に電気的に接続された埋め込み配線が形成された光電変換基板とを、透明基板の裏面と光電変換基板の主面とが対向するように接着して、3次元画像処理装置を製造することを特徴とする。 To achieve the above object, according to the Invention The method for producing a three-dimensional image processing apparatus according to claim 1, transparent and substrate having a lens for collecting light, photoelectrically main surface a photoelectric conversion element electrically connected to the buried wiring is formed photoelectric conversion substrate with conversion element is formed, and the back surface and the photoelectric conversion substrate main surface of the transparent substrate is bonded so as to face , characterized in that to produce a 3-dimensional image processing apparatus.

【0012】請求項1の発明では、支持基板等を用いることなく、光を集光するレンズを備えた透明基板と、主面に光電変換素子が形成されると共に該光電変換素子に電気的に接続された埋め込み配線が形成された光電変換基板とを、透明基板の裏面と光電変換基板の主面とが対向するように接着するため、透明基板をそのままイメージセンサの透明基板として使用することができ、支持基板への接着工程、支持基板からの除去工程、及び透明基板の形成工程が不要であり、3次元画像処理装置の製造工程を大幅に簡略化することができる。 [0012] In the present invention of claim 1, without using the supporting substrate or the like, a transparent and a substrate having a lens for collecting light, photoelectric conversion elements electrically in conjunction with the photoelectric conversion element on the main surface is formed a connected embedded wiring formed photoelectric conversion substrate, a rear face of the photoelectric conversion substrate main surface of the transparent substrate for adhering to face, is the use of transparent substrate as a transparent substrate as an image sensor can, bonding process to the supporting substrate, step of removing from the support substrate, and it is not necessary transparent substrate forming process, it is possible to greatly simplify the manufacturing process of the three-dimensional image processing apparatus. また、光電変換基板に埋め込み配線を形成した後に透明基板と貼り合わせるため、信頼性の高い絶縁膜で囲まれた埋め込み配線を形成することができる。 Furthermore, for bonding the transparent substrate after forming the buried wiring the photoelectric conversion substrate, it is possible to form a buried wiring surrounded by a reliable insulating film.

【0013】請求項2に記載の3次元画像処理装置の製造方法は、請求項1の発明において、前記光電変換基板の裏面側を研磨して前記埋め込み配線を露出させ、該光電変換基板の裏面に、主面に増幅器及びアナログ/デジタル変換器が形成されると共に該増幅器及びアナログ/ The method of manufacturing a three-dimensional image processing apparatus according to claim 2 is the invention of claim 1, to expose the buried wiring by polishing the rear surface side of the photoelectric conversion substrate, the back surface of the photoelectric conversion substrate to, the with the amplifier and an analog / digital converter on the main surface is formed amplifier and an analog /
デジタル変換器に電気的に接続された埋め込み配線が形成された増幅変換基板を、該増幅器及びアナログ/デジタル変換器が前記埋め込み配線の露出部に電気的に接続されるように接着して、3次元画像処理装置を製造することを特徴とする。 Amplification converter board electrically connected to the buried wiring is formed on the digital converter, and bonded so as the amplifier and an analog / digital converter is electrically connected to the exposed portions of the embedded wiring, 3 characterized in that to produce a dimensional image processing apparatus.

【0014】請求項2の発明によれば、透明基板及び光電変換基板からなるイメージセンサ部に、研磨及び接着という簡素かつ容易な工程により、増幅器及びアナログ/デジタル変換器に電気的に接続された埋め込み配線が形成された増幅変換基板を積層した3次元画像処理装置を製造することができる。 According to the invention of claim 2, the image sensor unit comprising a transparent substrate and the photoelectric conversion substrate, a simple and easy steps of polishing and the adhesive, which is electrically connected to an amplifier and an analog / digital converter it is possible to produce a three-dimensional image processing apparatus formed by stacking the amplified converter board buried wiring is formed.

【0015】請求項3に記載の3次元画像処理装置の製造方法は、請求項2の発明において、前記増幅変換基板の裏面側を研磨して前記埋め込み配線を露出させ、 該増幅変換基板の裏面に、主面にデータ記憶装置が形成されると共に該データ記憶装置に電気的に接続された埋め込み配線が形成されたデータ記憶基板を、該データ記憶装置が前記埋め込み配線の露出部に電気的に接続されるように接着して、3次元画像処理装置を製造することを特徴とする。 The method of manufacturing a three-dimensional image processing apparatus according to claim 3 is the invention of claim 2, wherein the back surface side of the amplifying conversion substrate polished to expose the buried wiring, the back surface of the amplification converter board in the data storage substrate electrically connected to the buried wiring on the data storage device is formed with the data storage device is formed on the main surface, electrically to the exposed portion of the embedded wiring the data storage device adhered to so as to be connected, characterized in that to produce a 3-dimensional image processing apparatus.

【0016】請求項3の発明によれば、透明基板及び光電変換基板からなるイメージセンサ部に研磨と接着とにより増幅変換基板が形成された積層体に、研磨及び接着という簡素かつ容易な工程により、主面に記憶装置が形成されると共にデータ記憶装置に電気的に接続された埋め込み配線が形成されたデータ記憶基板を積層した3次元画像処理装置を製造することができる。 According to the invention of claim 3, the laminate amplification conversion substrate is formed by grinding the bonding and the image sensor unit comprising a transparent substrate and the photoelectric conversion substrate, a simple and easy steps of polishing and bonding , it is possible to produce a three-dimensional image processing apparatus formed by stacking an electrically connected embedded data storage substrate on which wiring is formed on the data storage device with the storage device to the main surface is formed.

【0017】請求項4に記載の3次元画像処理装置の製造方法は、請求項2の発明において、前記データ記憶基板の裏面側を研磨して前記埋め込み配線を露出させ、該データ記憶基板の裏面に、主面にデータ処理装置が形成されると共に該データ処理装置に電気的に接続された埋め込み配線が形成されたデータ処理基板を、該データ処理装置が前記埋め込み配線の露出部に電気的に接続されるように接着して、3次元画像処理装置を製造することを特徴とする。 The method for producing a three-dimensional image processing apparatus according to claim 4 is the invention of claim 2, wherein by polishing the rear surface side of the data storage substrate to expose the buried wiring, the back surface of the data storage substrate in the data processing board electrically connected to the buried wiring to the data processing apparatus is formed with a data processing device is formed on the main surface, electrically to the exposed portion of the buried wiring the data processing device adhered to so as to be connected, characterized in that to produce a 3-dimensional image processing apparatus.

【0018】請求項4の発明によれば、透明基板及び光電変換基板からなるイメージセンサ部に研磨と接着とにより増幅変換基板及びデータ記憶基板が形成された積層体に、研磨及び接着という簡素かつ容易な工程により、 According to the invention of claim 4, the amplifying converter board and the data storage substrate by polishing and the adhesive and the image sensor unit comprising a transparent substrate and the photoelectric conversion substrate is formed laminate, simpler that abrasive and adhesive and by an easy process,
主面にデータ処理装置が形成されると共に該データ処理装置に電気的に接続された埋め込み配線が形成されたデータ処理基板を積層した3次元画像処理装置を製造することができる。 It is possible to produce a three-dimensional image processing apparatus formed by stacking the data processing board electrically connected to the buried wiring is formed on the data processing device with a data processing device is formed on the main surface.

【0019】請求項5に記載の3次元画像処理装置の製造方法は、請求項4の発明において、前記データ処理基板の裏面側を研磨して前記埋め込み配線を露出させ、該データ処理基板の裏面に、主面に出力回路が形成されると共に該出力回路に電気的に接続された埋め込み配線が形成された出力回路基板を、該出力回路が前記埋め込み配線の露出部に電気的に接続されるように接着して、3 The method for producing a three-dimensional image processing apparatus according to claim 5 is the invention of claim 4, wherein the data processing by polishing the rear surface side of the substrate to expose the buried wiring, the back surface of the data processing board in the output circuit board electrically connected to the buried wiring to the output circuit with the output circuit on the main surface is formed is formed, it is electrically connected to the exposed portions of the buried wiring output circuit adhered to, 3
次元画像処理装置を製造することを特徴とする。 Characterized in that to produce a dimensional image processing apparatus.

【0020】請求項5の発明によれば、透明基板及び光電変換基板からなるイメージセンサ部に研磨と接着とにより増幅変換基板、データ記憶基板、及びデータ処理装置が形成された積層体に、研磨及び接着という簡素かつ容易な工程により、主面に出力回路が形成されると共に該出力回路に電気的に接続された埋め込み配線が形成された出力回路基板を積層した3次元画像処理装置を製造することができる。 According to the invention of claim 5, amplified conversion substrate by a polishing image sensor unit comprising a transparent substrate and the photoelectric conversion substrate adhesion and data storage substrate, and the laminate data processing device is formed, abrasive and a simple and easy process of adhesion, to produce a three-dimensional image processing apparatus is electrically connected to buried wiring is laminated an output circuit board formed in the output circuit with the output circuit on the main surface is formed be able to.

【0021】 [0021]

【発明の実施の形態】以下、本発明の3次元画像処理装置の製造方法を、図面を参照しつつ具体的に説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a three-dimensional image processing apparatus of the present invention will be described with reference to the drawings.
図1〜図5は、本発明の3次元画像処理装置の製造方法の各工程を示す断面図である。 1 to 5 are cross-sectional views illustrating steps of a method for manufacturing a three-dimensional image processing apparatus of the present invention.

【0022】まず、図1に示すように、光電変換基板2 [0022] First, as shown in FIG. 1, the photoelectric conversion substrate 2
0に、多数のマイクロレンズ12が2次元状に形成された石英ガラス製の透明基板10を、光電変換基板20の主面と透明基板10の裏面とが対向するように、エポキシ樹脂やポリイミド樹脂等の高分子材料からなる接着剤14を介して接着する。 0, the number of micro lenses 12 are two-dimensionally to form quartz glass transparent substrate 10, so that the rear surface of the main surface and the transparent substrate 10 of the photoelectric conversion substrate 20 faces, epoxy resin or polyimide resin adhered through an adhesive 14 made of a polymer material such as.

【0023】上記で用いる光電変換基板20は、内部にニ酸化ケイ素からなる絶縁層36が挿入されたn型シリコン結晶基板16上に、フォトダイオードとMOSトランジスタとを形成したものである。 The photoelectric conversion substrate 20 used in the above are those insulating layer 36 made of silicon dioxide therein on the n-type silicon crystal substrate 16 inserted, to form a photodiode and a MOS transistor. フォトダイオードは、光電変換基板20のn型シリコン結晶基板16上にp型不純物層18を形成し、p型不純物層18表層のマイクロレンズ12の焦点位置に対応する領域にn型不純物層22を設けることにより形成されている。 Photodiode, a p-type impurity layer 18 is formed on the n-type silicon crystal substrate 16 of the photoelectric conversion substrate 20, the n-type impurity layer 22 in the region corresponding to the focal position of the p-type impurity layer 18 surface micro lenses 12 It is formed by providing. また、M In addition, M
OSトランジスタは、p型不純物層18表層の撮像領域以外の部分にソース及びドレインとなるn型不純物層2 OS transistor is a source and a drain on a portion other than the image pickup area of ​​the p-type impurity layer 18 surface n-type impurity layer 2
2を設け、このn型不純物層22間のp型不純物層18 2 is provided, p-type impurity layer 18 between the n-type impurity layer 22
上に絶縁膜24Aにより相互に絶縁されたポリシリコンからなるゲート電極26を設けることにより形成されている。 It is formed by providing a gate electrode 26 made of mutually insulated polysilicon by an insulating film 24A above. なお、隣接するMOSトランジスタはニ酸化ケイ素からなる素子分離膜30で分離されている。 Incidentally, adjacent MOS transistors are isolated by an element isolation film 30 made of silicon dioxide.

【0024】また、光電変換基板20には、素子分離膜30を貫通し光電変換基板20の裏面に達するトレンチ(深溝)が設けられている。 Further, the photoelectric conversion substrate 20, a trench reaching the back surface of the photoelectric conversion substrate 20 through the isolation layer 30 (deep groove) is provided. なお、このようなトレンチは誘導結合型プラズマエッチング等により形成することができる。 Such a trench may be formed by inductively coupled plasma etching or the like. このトレンチの内表面に絶縁膜32が形成され、トレンチ内に導電材料が充填されて埋め込み配線3 The insulating film 32 on the inner surface of the trench is formed, buried wiring 3 is conductive material filled in the trench
4が形成されている。 4 is formed. 埋め込み配線34を形成する導電材料としては、例えば不純物をドープした低抵抗多結晶シリコンやタングステン等の低抵抗の金属が使用される。 As the conductive material for forming the buried wiring 34, a low-resistance metal such as a low-resistance polycrystalline silicon or tungsten is used which is doped with an impurity.

【0025】MOSトランジスタのソースとなるn型不純物層22は、例えばアルミニウムからなるソース電極28に接続されおり、ドレインとなるn型不純物層22 [0025] n-type impurity layer 22 serving as the source of the MOS transistor, for example, is connected to the source electrode 28 made of aluminum, a drain n-type impurity layer 22
は、絶縁膜24Bによりソース電極28と絶縁された例えばアルミニウムからなるドレイン電極29に接続されている。 It is connected to the drain electrode 29 made of insulated such as aluminum and the source electrode 28 by the insulating film 24B. このドレイン電極29は埋め込み配線34に接続されており、ゲート電極26に所定電圧を印加することによりn型チャネル22及びp型不純物層18からなるフォトダイオードに蓄積された電荷はこの埋め込み配線34を介して後述する増幅器へと転送される。 The drain electrode 29 is connected to the embedded wiring 34, the embedded wiring 34 of the charge accumulated in the photodiode consisting of an n-type channel 22 and the p-type impurity layer 18 by applying a predetermined voltage to the gate electrode 26 It is transferred to an amplifier, which will be described later, via.

【0026】次に、図2に示すように、透明基板10に接着された光電変換基板20を、化学的機械研磨により裏面側から研磨して薄膜化する。 Next, as shown in FIG. 2, the photoelectric conversion substrate 20 bonded to the transparent substrate 10, a thin film is polished from the back side by the chemical mechanical polishing. n型シリコン結晶基板16に挿入された絶縁層36を構成するニ酸化ケイ素はシリコンよりも研磨耐性が大きいため、研磨は絶縁層3 Because silicon dioxide constituting the inserted insulating layer 36 to n-type silicon crystal substrate 16 has a large polishing resistant than silicon, polishing the insulating layer 3
6の手前で止まり、埋め込み配線34が絶縁層36から露出される。 It stops at 6 before the, embedded wiring 34 is exposed from the insulating layer 36. このとき透明基板10が支持基板の役割を果たすが、当初からマイクロレンズ12を一体化して形成した石英ガラス製の透明基板を用いているので後で取り外す必要はない。 Serve this time the transparent substrate 10 is a support substrate is not necessary to remove later because of the use of a transparent substrate made of quartz glass which is formed by integrating the microlens 12 from the beginning.

【0027】以上の工程により、光を集光するレンズを備えた透明基板10、及び光電変換基板20を備えたイメージセンサ部が完成する。 [0027] Through the above process, the image sensor unit having a transparent substrate 10 having a lens condensing light and a photoelectric conversion substrate 20, is completed.

【0028】次に、図3に示すように、光電変換基板2 Next, as shown in FIG. 3, the photoelectric conversion substrate 2
0の裏面に、光電変換基板20からの信号を増幅すると共に増幅されたアナログ信号をデジタル信号に変換する増幅変換基板40を接着する。 On the back of 0 to adhere the amplified conversion board 40 which converts the analog signal amplified amplifies the signal from the photoelectric conversion substrate 20 into a digital signal. この増幅変換基板40 The amplified conversion board 40
は、内部にニ酸化ケイ素からなる絶縁層36Aが挿入されたシリコン基板38A上に、絶縁膜42Aにより絶縁されたゲート44A、ソース46A、及びドレイン48 Is the two of silicon oxide insulating layer 36A is a silicon substrate 38A which is inserted therein, the gate 44A is insulated by the insulating film 42A, source 46A, and drain 48
Aからなる複数のMOSFET50A(本実施の形態では2つのMOSFETを図示する)を形成したものである。 (In this embodiment illustrates two MOSFET) a plurality of MOSFET50A consisting of A is obtained by forming a. これら隣接するMOSFET50Aは、ニ酸化ケイ素からなる素子分離膜52Aにより分離されている。 These adjacent MOSFET50A are separated by the isolation layer 52A made of silicon dioxide.

【0029】また、増幅変換基板40には、この素子分離膜52Aを貫通し増幅変換基板40の裏面側表面から回路面に達するトレンチが設けられている。 Further, the amplification conversion board 40, a trench reaching the circuit surface from the back side surface of the amplification conversion board 40 through the isolation layer 52A is provided. このトレンチの内表面に絶縁膜54Aが形成され、トレンチ内に導電材料が充填されて埋め込み配線56Aが形成されている。 The insulating film 54A on the inner surface of the trench is formed, the wiring 56A burying conductive material in the trench is filled is formed. 埋め込み配線56Aを形成する導電材料としては、 As the conductive material for forming a buried wiring 56A,
例えば不純物をドープした低抵抗多結晶シリコンやタングステン等の低抵抗の金属が使用される。 For example, a low-resistance metal such as a low-resistance polycrystalline silicon or tungsten is used which impurities are doped. この埋め込み配線56Aの回路面側の端部にはアルミニウム配線58 This is the end of the circuit surface side of the buried wiring 56A aluminum wiring 58
Aが直接接続されている。 A is directly connected. これにより増幅器(アンプ) This amplifier (amp)
及びアナログ/デジタル変換器(ADC)を含む集積回路が構成されている。 And an integrated circuit including an analog / digital converter (ADC) is configured. 形成された集積回路はニ酸化ケイ素からなる絶縁膜60Aにより被覆され、増幅変換基板40の集積回路側の表面が平坦化されている。 Formed integrated circuit is covered with an insulating film 60A made of silicon dioxide, the surface of the integrated circuit side of the amplifying conversion board 40 is flattened. また、この絶縁膜60Aに設けられた開口からアルミニウム配線58Aが引き出され、絶縁膜60Aの表面に露出されている。 Further, the aluminum wiring 58A is pulled out from an opening provided in the insulating film 60A, which is exposed on the surface of the insulating film 60A.

【0030】上記光電変換基板20の裏面側の表面に、 [0030] back surface side of the surface of the photoelectric conversion substrate 20,
絶縁層36の表面から露出した埋め込み配線34の端部に接触するようにマイクロバンプ62を形成する。 Forming a micro-bump 62 to contact the end of the buried wiring 34 exposed from the surface of the insulating layer 36. 一方、増幅変換基板40の集積回路側の表面にも、絶縁膜60Aの表面に露出したアルミニウム配線58Aの端部に接触するようにマイクロバンプ64を形成する。 On the other hand, the surface of the integrated circuit side of the amplifier converter board 40 also form a micro-bump 64 to contact the end of the aluminum wiring 58A exposed on the surface of the insulating film 60A. マイクロバンプは、レジストマスクを用いたリフトオフ等により形成することができ、マイクロバンプの材料としては例えば金とインジウムとの合金またはインジウムを用いることができる。 Micro-bump can be formed by lift-off using a resist mask, the material of the micro-bump or an alloy or indium, for example, gold and indium.

【0031】光電変換基板20の裏面側の表面に設けられたマイクロバンプ62と、増幅変換基板40の集積回路面側の表面に設けられたマイクロバンプ64とが電気的に接続されるように、増幅変換基板40上に光電変換基板20を重ね合わせて仮接着する。 [0031] As the micro bumps 62 provided on the back surface side of the surface of the photoelectric conversion substrate 20, and the micro bumps 64 provided on the surface of the integrated circuit surface side of the amplifying conversion board 40 are electrically connected, amplification conversion substrate 40 superposed photoelectric conversion substrate 20 is provisionally bonded. なお、光電変換基板20と増幅変換基板40との位置合わせは、例えばシリコンウエハを透過する赤外線を用いた位置合わせ装置により行うことができる。 Incidentally, alignment between the photoelectric conversion substrate 20 and the amplifier converting the substrate 40 can be performed, for example, by positioning device using an infrared ray transmitted through the silicon wafer.

【0032】仮接着した光電変換基板20と増幅変換基板40とを、液状のエポキシ樹脂を保持した容器と共に気圧調整が可能なチャンバーに入れてチャンバー内を真空にし、仮接着した光電変換基板20と増幅変換基板4 [0032] The photoelectric conversion substrate 20 temporarily bonded amplification conversion board 40, the vacuum chamber and placed in a pressure adjustment chamber capable with the container holding the liquid epoxy resin, a photoelectric converter substrate 20 which is temporarily adhered amplifying converter board 4
0とを液状のエポキシ樹脂にディップして常圧に戻し基板間の隙間にエポキシ樹脂66を注入する。 0 and injecting epoxy resin 66 into the gap between the substrates back into the dip to normal pressure liquid epoxy resin. その後基板を引き上げエポキシ樹脂66を硬化させて、増幅変換基板40と光電変換基板20との接着が完了する。 By subsequently curing the pulling epoxy resin 66 to the substrate, adhesion to the amplification conversion board 40 and the photoelectric conversion substrate 20 is completed.

【0033】次に、図4に示すように、増幅変換基板4 Next, as shown in FIG. 4, the amplifier converts the substrate 4
0を裏面側から化学的機械研磨により均一な厚さに研磨して薄膜化する。 0 thinned by polishing to a uniform thickness by chemical mechanical polishing from the back side. 絶縁層36Aを構成するニ酸化ケイ素はシリコンよりも研磨耐性が大きいため、研磨は絶縁層36Aの手前で止まり、絶縁層36Aよりも深い位置まで形成されている埋め込み配線56Aが絶縁層36Aから露出される。 Because silicon dioxide constituting the insulating layer 36A has a larger polishing resistant than silicon, polishing stops in front of the insulating layer 36A, exposed from the embedded wiring 56A is an insulating layer 36A formed deeper than the insulating layer 36A It is.

【0034】次に、図5に示すように、光電変換基板2 [0034] Next, as shown in FIG. 5, the photoelectric conversion substrate 2
0に接着された増幅変換基板40の裏面に、一時的にデータを記憶するデータ記憶装置(レジスタアレイ)を備えたデータ記憶基板70を接着する。 The back surface of the bonded amplified conversion board 40 to 0, to adhere the data storage substrate 70 provided with a data storage device (register array) for temporarily storing data. ここで用いるデータ記憶基板70は、増幅変換基板40と同様に、内部にニ酸化ケイ素からなる絶縁層36Bが挿入されたシリコン基板38B上に、絶縁膜42Bにより絶縁されたゲート44B、ソース46B、及びドレイン48Bからなる複数のMOSFET50B(本実施の形態では2つのM Data storage substrate 70 used here, like the amplifier converter board 40, on a silicon substrate 38B to the insulating layer 36B is inserted consisting of silicon dioxide inside, the gate 44B is insulated by an insulating film 42B, a source 46B, and consisting drain 48B MOSFET50B (two in the present embodiment M
OSFETを図示する)を形成したものであり、隣接するMOSFET50Bは、ニ酸化ケイ素からなる素子分離膜52Bにより分離されている。 Illustrate OSFET) is obtained by the formation, adjacent MOSFET50B are separated by the isolation layer 52B made of silicon dioxide.

【0035】また、データ記憶基板70には、この素子分離膜52Bを貫通しデータ記憶基板70の裏面側表面から回路面に達するトレンチが設けられている。 Further, in the data memory board 70, a trench reaching the circuit surface from the back side surface of the device through the separation membrane 52B data storage substrate 70 is provided. このトレンチの内表面に絶縁膜54Bが形成され、トレンチ内に導電材料が充填されて埋め込み配線56Bが形成されている。 The insulating film 54B on the inner surface of the trench is formed, the wiring 56B embedding conductive material in the trench is filled is formed. 埋め込み配線56Bを形成する導電材料としては、例えば不純物をドープした低抵抗多結晶シリコンやタングステン等の低抵抗の金属が使用される。 As the conductive material for forming a buried wiring 56B, the low-resistance metal such as a low-resistance polycrystalline silicon or tungsten is used which is doped with an impurity. 埋め込み配線56Bの回路面側の端部にはアルミニウム配線58 Embedding an end portion of the circuit surface side of the wiring 56B aluminum wiring 58
Bが直接接続されている。 B are directly connected. これによりデータ記憶装置を含む集積回路が構成されている。 Thereby an integrated circuit including a data storage device is configured. 形成された集積回路は、ニ酸化ケイ素からなる絶縁膜60Bにより被覆され、データ記憶基板70の集積回路側の表面が平坦化されている。 Formed integrated circuit is covered with an insulating film 60B made of silicon dioxide, the surface of the integrated circuit side of the data storage substrate 70 is flattened. この絶縁膜60Bに設けられた開口からアルミニウム配線58Bが引き出されて、絶縁膜60Bの表面に露出されている。 This and aluminum wire 58B is pulled out from an opening provided in the insulating film 60B, are exposed on the surface of the insulating film 60B.

【0036】上記増幅変換基板40の裏面側の表面に、 [0036] back surface side of the surface of the amplified conversion board 40,
絶縁層36Aの表面から露出した埋め込み配線56Aの端部に接触するようにマイクロバンプ71を形成する。 Forming a micro-bump 71 to contact the end of the buried wiring 56A exposed from the surface of the insulating layer 36A.
一方、データ記憶基板70の集積回路側の表面にも、絶縁膜60Bの表面に露出したアルミニウム配線58Bの端部に接触するようにマイクロバンプ72を形成する。 On the other hand, also on the surface of the integrated circuit side of the data storage substrate 70, to form a micro-bump 72 to contact the end of the aluminum wiring 58B exposed on the surface of the insulating film 60B.
そして増幅変換基板40の裏面側の表面に設けられたマイクロバンプ71と、データ記憶基板70の集積回路側の表面に設けられたマイクロバンプ72とが電気的に接続されるようにデータ記憶基板70上に増幅変換基板4 The micro bumps 71 provided on the back surface side of the surface of the amplified conversion board 40, the data storage substrate 70 so that the micro bumps 72 provided on the surface of the integrated circuit side of the data storage substrate 70 are electrically connected amplification converted to upper substrate 4
0を重ね合わせて仮接着し、光電変換基板20及び増幅変換基板40を接着する場合と同様にして、増幅変換基板40とデータ記憶基板70とをエポキシ樹脂74により接着する。 0 superimposed temporarily bonded, as in the case of bonding the photoelectric conversion substrate 20 and the amplifier converting the substrate 40, and an amplifier conversion board 40 and the data storage substrate 70 adhered by epoxy resin 74.

【0037】次に、図6に示すように、データ記憶基板70の裏面に、データ処理基板80、出力回路基板9 Next, as shown in FIG. 6, the back surface of the data storage substrate 70, a data processing board 80, an output circuit board 9
0、及び出力端子部100を順に形成する。 0, and forms the output terminal portion 100 in this order. 上記増幅変換基板40やデータ記憶基板70の形成工程と同様にして、増幅変換基板40に接着されたデータ記憶基板70 In the same manner as in the step of forming the amplification conversion board 40 and data storage substrate 70, it is bonded to amplify conversion board 40 data storage substrate 70
を裏面側から研磨し、データ記憶基板70の裏面に、データ処理装置(プロセッサアレイ)を備え埋め込み配線82の形成されたデータ処理基板80を、両基板に設けられた集積回路が埋め込み配線82により電気的に接続されるように接着する。 The polished from the back side, the back surface of the data storage substrate 70, a data processing device data processing substrate 80 formed of the embedded wiring 82 comprises a (processor arrays), the integrated circuit is embedded wiring 82 provided on the substrates adhered so as to be electrically connected. さらに、このデータ処理基板8 Furthermore, the data processing board 8
0を裏面側から研磨した後に、データ処理基板80の裏面に埋め込み配線92の形成された出力回路基板90 0 after polishing from the back side, the output circuit board 90 formed of the embedded wiring 92 on the back surface of the data processing board 80
を、両基板に設けられた集積回路が埋め込み配線92により電気的に接続されるように接着する。 And adhered to the integrated circuit provided on both substrates are electrically connected by the buried wiring 92. そして出力回路基板90を裏面側から研磨して、出力回路基板90裏面の絶縁膜から埋め込み配線92の端部を露出させ、露出した埋め込み配線92の端部に接触するようにマイクロバンプ93を形成する。 And by polishing the output circuit board 90 from the back side, forming a micro-bump 93 as to expose the end portion of the buried wiring 92 from the output circuit board 90 back surface of the insulating film, in contact with the end portion of the exposed buried wiring 92 to.

【0038】そして最後に出力回路基板90の裏面に出力端子部100を形成する。 [0038] and forming an output terminal portion 100 on the rear surface of the last output circuit board 90. 出力端子部100はシリコン基板102にこのシリコン基板102を貫通し基板両面側に露出した埋め込み配線104が形成されたものである。 The output terminal portion 100 are those embedded wiring 104 is exposed on both surfaces of the substrate side through the silicon substrate 102 on the silicon substrate 102 is formed. 埋め込み配線104を形成する導電材料としては、例えば銅、タングステン、金等の低抵抗の金属が使用される。 As the conductive material for forming a buried wiring 104, for example, copper, tungsten, low-resistance metal such as gold is used. この出力端子部100の入力側の表面に、出力端子部100の絶縁層の表面から露出した埋め込み配線104の一方の端部に接触するようにマイクロバンプ94を形成する。 On the surface of the input side of the output terminal portion 100, to form a micro-bump 94 to contact the one end of the buried wiring 104 exposed from the surface of the insulating layer of the output terminal portion 100. そして出力回路基板90の裏面側の表面に設けられたマイクロバンプ93と出力端子部100 The output circuit micro bumps 93 and the output terminal portion 100 provided on the back surface side of the surface of the substrate 90
の入力側の表面に設けられたマイクロバンプ94とが接触し、出力回路基板90に設けられた集積回路が出力端子部100の出力端子に電気的に接続されるように両基板を接着する。 Of the micro-bump 94 is in contact which is provided to the input side of the surface, the integrated circuit provided in the output circuit board 90 is adhered to both substrates so as to be electrically connected to the output terminal of the output terminal portion 100. そして上記出力端子部100の出力側の表面には、埋め込み配線104の他方の端部に接触するようにマイクロバンプ106を形成する。 And on the surface of the output side of the output terminal portion 100, to form the micro bumps 106 to contact the other end of the buried wiring 104. マイクロバンプ106は、例えば金やインジウムまたはそれらの合金から形成することができる。 Micro bumps 106 may be formed from, for example, gold or indium or alloys thereof. また、はんだバンプとしてもよい。 It is also possible as a solder bump.

【0039】以上の工程により、光を集光するレンズを備えた透明基板10及び光電変換基板20からなるイメージセンサ部と、そのイメージセンサ部からの信号を処理するための処理部(増幅変換基板40、データ記憶基板70、データ処理基板80及び出力回路基板90)とを一体化した図6に示す3次元画像処理装置を得ることができる。 [0039] Through the above process, the image sensor unit consisting of a transparent substrate 10 and the photoelectric conversion substrate 20 having a lens for condensing light, processing unit for processing signals from the image sensor unit (amplification conversion substrate 40, the data storage substrate 70, a data processing board 80 and the output circuit board 90) and it is possible to obtain three-dimensional image processing apparatus shown in FIG. 6 with integrated.

【0040】本実施の形態では、多数のマイクロレンズが2次元状に形成された石英ガラス製の透明基板に光電変換基板を直接接着するので、支持基板を別途用意する必要がなく支持基板の着脱工程が不要となる。 [0040] In this embodiment, since a large number of microlenses are directly bonded to the photoelectric conversion substrate on the transparent substrate made of quartz glass formed two-dimensionally, attachment and detachment of the support substrate is not necessary to prepare a supporting substrate separately process is not required. これにより製造工程を大幅に簡略化することができ、簡素かつ容易な工程により3次元画像処理装置を製造することができる。 Thus the manufacturing process can be greatly simplified, it is possible to produce a three-dimensional image processing apparatus by simple and easy process. また、各集積回路基板の埋め込み配線は貼り合わせ前に形成されるので、信頼性の高い絶縁膜で囲まれた埋め込み配線を形成することができる。 Moreover, since the buried wiring of the integrated circuit substrate is formed before bonding, it is possible to form a buried wiring surrounded by a reliable insulating film.

【0041】上記実施の形態では、集積回路を形成するための各半導体基板にニ酸化ケイ素からなる絶縁層が内部に形成されたシリコン基板を使用したが、ニ酸化ケイ素からなる絶縁層を含まないシリコン基板を使用してもよい。 [0041] In the above embodiment, the insulating layer made of silicon dioxide on the semiconductor substrate for forming an integrated circuit using a silicon substrate having formed therein does not include an insulating layer made of silicon dioxide the silicon substrate may be used.

【0042】上記実施の形態では、埋め込み配線の両端部にマイクロバンプを形成し、マイクロバンプ同士を接触させて隣接する基板を電気的に接続する例について説明したが、埋め込み配線の一方の端部にのみマイクロバンプを形成して隣接する基板を電気的に接続するようにしても良い。 [0042] In the above embodiment, the embedded micro-bump is formed on both end portions of the wiring, an example has been described for electrically connecting the substrate adjacent in contact with each other micro-bumps, one end of the buried wiring it may be electrically connected to the substrate adjacent to form a micro-bumps only.

【0043】上記実施の形態では、集光レンズを備えた透明基板及び光電変換基板からなるイメージセンサ部に、そのイメージセンサ部からの信号を処理するための増幅変換基板、データ記憶基板、データ処理基板、及び出力回路基板の各処理部を研磨及び貼合せを繰り返すことにより形成する例について説明したが、イメージセンサ部を構成する光電変換基板を裏面側から研磨して埋め込み配線を露出させた後、配線により光電変換基板を増幅変換基板と電気的に接続することもできる。 [0043] In the above embodiment, the image sensor unit comprising a transparent substrate and a photoelectric conversion substrate having a condenser lens, amplifying converter board for processing signals from the image sensor unit, a data storage substrate, the data processing substrate, and an example has been described is formed by repeating the grinding and laminating the respective processing units of the output circuit board, after exposing the polished to buried wiring photoelectric conversion substrate forming an image sensor unit from the back side , it is also possible to connect the photoelectric conversion substrate amplified conversion substrate and electrically through a wire.

【0044】また、上記実施の形態と同様にしてイメージセンサ部に研磨及び貼合せにより増幅変換基板を形成し、増幅変換基板を裏面側から研磨して埋め込み配線を露出させた後、配線により増幅変換基板をデータ記憶基板と電気的に接続することもできる。 [0044] Further, in the same manner as the above embodiment the amplification conversion substrate was formed by polishing and laminating the image sensor section, after exposing the polished to buried wiring amplification conversion substrate from the back side, amplified by a wire it is also possible to connect the converter board data storage substrate and electrically. また、上記実施の形態と同様にしてイメージセンサ部に研磨及び貼合せにより増幅変換基板及びデータ記憶基板を形成し、データ記憶基板を裏面側から研磨して埋め込み配線を露出させた後、配線によりデータ記憶基板をデータ処理基板と電気的に接続することもできる。 Further, in the same manner as the above embodiment polished and bonded amplification converter board and the data storage substrate is formed by mating the image sensor section, after exposing the polished to buried wiring data storage substrate from the back side, by a wire it is also possible to connect the data storage board data processing board electrically. また、上記実施の形態と同様にしてイメージセンサ部に研磨及び貼合せにより増幅変換基板、データ記憶基板、及びデータ処理基板を形成し、データ処理基板を裏面側から研磨して埋め込み配線を露出させた後、配線によりデータ処理基板を出力回路基板と電気的に接続することもできる。 Also, amplified conversion substrate by polishing and laminating the image sensor unit in the same manner as the above-described embodiment, data storage substrate, and a data processing substrate formed to expose the polished to buried wiring data processing substrate from the back side and then, it is also possible to connect the data processing board output circuit board electrically by wiring.

【0045】なお、上記実施の形態において使用するシリコン基板は、ウエハスケールでもチップスケールでもよい。 [0045] The silicon substrate used in the above embodiment may be a chip scale at the wafer scale.

【0046】 [0046]

【発明の効果】本発明の3次元画像処理装置の製造方法は、支持基板の着脱工程が不要で、製造工程を大幅に簡略化することができ、簡素かつ容易な工程により3次元画像処理装置を製造することができる、という効果を奏する。 Method for producing a three-dimensional image processing apparatus of the present invention exhibits, unnecessary detachment process of the supporting substrate, it is possible to greatly simplify the manufacturing process, three-dimensional image processing apparatus by simple and easy steps it can be produced an effect that. また、本発明の3次元画像処理装置の製造方法は、信頼性の高い絶縁膜で囲まれた埋め込み配線を形成することができる、という効果を奏する。 A method of manufacturing a three-dimensional image processing apparatus of the present invention, it is possible to form a buried wiring surrounded by a reliable insulating film, an effect that.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本実施の形態の3次元画像形成装置の製造工程を示す概略断面図である。 1 is a schematic cross-sectional views showing the manufacturing process of the three-dimensional image forming apparatus of this embodiment.

【図2】本実施の形態の3次元画像形成装置の製造工程を示す概略断面図である。 It is a schematic sectional view showing the manufacturing process of Figure 2 a three-dimensional image forming apparatus of this embodiment.

【図3】本実施の形態の3次元画像形成装置の製造工程を示す概略断面図である。 3 is a schematic cross-sectional views showing the manufacturing process of the three-dimensional image forming apparatus of this embodiment.

【図4】本実施の形態の3次元画像形成装置の製造工程を示す概略断面図である。 Is a schematic sectional view showing the manufacturing process of FIG. 4 3-dimensional image forming apparatus of this embodiment.

【図5】本実施の形態の3次元画像形成装置の製造工程を示す概略断面図である。 5 is a schematic cross-sectional views showing the manufacturing process of the three-dimensional image forming apparatus of this embodiment.

【図6】本実施の形態の3次元画像形成装置の構造を示す概略断面図である。 6 is a schematic sectional view showing a structure of a 3-dimensional image forming apparatus of this embodiment.

【符号の説明】 DESCRIPTION OF SYMBOLS

10 透明基板 12 マイクロレンズ 16 n型シリコン結晶基板 18 p型不純物層 20 光電変換基板 22 n型不純物層 26 ゲート電極 28 電極 34 埋め込み配線 40 増幅変換基板 70 データ記憶基板 80 データ処理基板 90 出力回路基板 100 出力端子部 10 transparent substrate 12 microlens 16 n-type silicon crystal substrate 18 p-type impurity layer 20 photoelectric conversion substrate 22 n-type impurity layer 26 gate electrode 28 electrode 34 embedded wiring 40 amplifies converter board 70 data storage substrate 80 data processing board 90 outputs the circuit board 100 the output terminal portion

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl. 7識別記号 FI テーマコート゛(参考) H01L 21/8238 H01L 21/90 A 5F110 27/092 27/08 321G 27/14 27/14 D 29/786 29/78 613Z H04N 5/335 (72)発明者 宮川 宣明 神奈川県海老名市本郷2274番地 富士ゼロ ックス株式会社海老名事業所内 Fターム(参考) 4M118 AA10 AB01 BA04 BA14 CA03 EA04 EA20 FA33 GD01 GD04 GD07 HA21 HA33 5B047 BB04 BC01 BC05 DB01 5C024 CY47 EX43 GX03 GY31 HX01 HX17 HX40 HX41 5F033 HH04 HH08 HH11 HH13 HH19 JJ01 JJ08 KK01 MM30 QQ08 QQ09 QQ12 QQ37 QQ49 RR04 SS25 UU05 VV00 VV07 XX10 5F048 AA09 AB03 AB10 AC03 AC10 BA09 BB05 BC12 BF01 BF02 BF03 BF07 BF15 BG12 BG14 CB02 CB03 CB04 5F110 AA16 BB10 BB11 CC02 DD03 DD05 DD21 DD30 EE09 HL03 NN62 NN71 QQ16 QQ30 ────────────────────────────────────────────────── ─── of the front page continued (51) Int.Cl. 7 identification mark FI theme Court Bu (reference) H01L 21/8238 H01L 21/90 a 5F110 27/092 27/08 321G 27/14 27/14 D 29/786 29/78 613Z H04N 5/335 (72) inventor Nobuaki Miyagawa Ebina, Kanagawa Prefecture Hongo 2274 address Fuji zero box Co., Ltd. Ebina house F-term (reference) 4M118 AA10 AB01 BA04 BA14 CA03 EA04 EA20 FA33 GD01 GD04 GD07 HA21 HA33 5B047 BB04 BC01 BC05 DB01 5C024 CY47 EX43 GX03 GY31 HX01 HX17 HX40 HX41 5F033 HH04 HH08 HH11 HH13 HH19 JJ01 JJ08 KK01 MM30 QQ08 QQ09 QQ12 QQ37 QQ49 RR04 SS25 UU05 VV00 VV07 XX10 5F048 AA09 AB03 AB10 AC03 AC10 BA09 BB05 BC12 BF01 BF02 BF03 BF07 BF15 BG12 BG14 CB02 CB03 CB04 5F110 AA16 BB10 BB11 CC02 DD03 DD05 DD21 DD30 EE09 HL03 NN62 NN71 QQ16 QQ30

Claims (5)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】光を集光するレンズを備えた透明基板と、 1. A transparent and the substrate having a lens for collecting light,
    主面に光電変換素子が形成されると共に該光電変換素子に電気的に接続された埋め込み配線が形成された光電変換基板とを、透明基板の裏面と光電変換基板の主面とが対向するように接着して、3次元画像処理装置を製造する3次元画像処理装置の製造方法。 A photoelectric conversion element electrically connected to the buried wiring is formed photoelectric conversion substrate with a photoelectric conversion element is formed on the main surface, so that the rear face of the photoelectric conversion substrate main surface of the transparent substrate are opposed method for producing a bonded, three-dimensional image processing apparatus for producing a three-dimensional image processing apparatus.
  2. 【請求項2】前記光電変換基板の裏面側を研磨して前記埋め込み配線を露出させ、 該光電変換基板の裏面に、主面に増幅器及びアナログ/ 2. A by polishing the back surface side of the photoelectric conversion substrate to expose the buried wiring, the back surface of the photoelectric conversion substrate, an amplifier on the main surface and the analog /
    デジタル変換器が形成されると共に該増幅器及びアナログ/デジタル変換器に電気的に接続された埋め込み配線が形成された増幅変換基板を、該増幅器及びアナログ/ Amplification converter board electrically connected to the buried wiring to the amplifier and analog / digital converter is formed with digital converter is formed, the amplifier and the analog /
    デジタル変換器が前記埋め込み配線の露出部に電気的に接続されるように接着して、3次元画像処理装置を製造する請求項1に記載の3次元画像処理装置の製造方法。 Adhered to as digital converter is electrically connected to the exposed portions of the buried wiring, in the manufacturing method of the three-dimensional image processing apparatus according to claim 1 for producing a three-dimensional image processing apparatus.
  3. 【請求項3】前記増幅変換基板の裏面側を研磨して前記埋め込み配線を露出させ、 該増幅変換基板の裏面に、主面にデータ記憶装置が形成されると共に該データ記憶装置に電気的に接続された埋め込み配線が形成されたデータ記憶基板を、該データ記憶装置が前記埋め込み配線の露出部に電気的に接続されるように接着して、3次元画像処理装置を製造する請求項2に記載の3次元画像処理装置の製造方法。 3. to expose the buried wiring by polishing the rear surface side of the amplifier converter board, on the back of the amplification converter board, electrically to said data storage device with the data storage device is formed on the main surface a connected embedded wiring formed data storage substrate, adhered to said data storage device is electrically connected to the exposed portions of the buried wiring, in claim 2 of producing a 3-dimensional image processing apparatus method for producing a three-dimensional image processing apparatus according.
  4. 【請求項4】前記データ記憶基板の裏面側を研磨して前記埋め込み配線を露出させ、 該データ記憶基板の裏面に、主面にデータ処理装置が形成されると共に該データ処理装置に電気的に接続された埋め込み配線が形成されたデータ処理基板を、該データ処理装置が前記埋め込み配線の露出部に電気的に接続されるように接着して、3次元画像処理装置を製造する請求項3に記載の3次元画像処理装置の製造方法。 Wherein exposing the buried wiring by polishing the rear surface side of the data storage substrate, said the back surface of the data storage substrate, electrically to the data processing device with a data processing apparatus is formed on the main surface a connected embedded data processing substrate on which wiring is formed, by adhering to the data processing device is electrically connected to the exposed portions of the buried wiring to claim 3 for producing a three-dimensional image processing apparatus method for producing a three-dimensional image processing apparatus according.
  5. 【請求項5】前記データ処理基板の裏面側を研磨して前記埋め込み配線を露出させ、 該データ処理基板の裏面に、主面に出力回路が形成されると共に該出力回路に電気的に接続された埋め込み配線が形成された出力回路基板を、該出力回路が前記埋め込み配線の露出部に電気的に接続されるように接着して、 5. to expose the buried wiring by polishing the rear surface side of the data processing substrate, the back surface of the data processing board, the output circuit with the output circuit on the main surface is formed are electrically connected was buried output circuit board on which wiring is formed, adhered to as output circuit is electrically connected to the exposed portions of the embedded wiring,
    3次元画像処理装置を製造する請求項4に記載の3次元画像処理装置の製造方法。 Method for producing a three-dimensional image processing apparatus according to claim 4 for producing a three-dimensional image processing apparatus.
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