JP3713418B2 - Manufacturing method of three-dimensional image processing apparatus - Google Patents

Manufacturing method of three-dimensional image processing apparatus Download PDF

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JP3713418B2
JP3713418B2 JP2000160330A JP2000160330A JP3713418B2 JP 3713418 B2 JP3713418 B2 JP 3713418B2 JP 2000160330 A JP2000160330 A JP 2000160330A JP 2000160330 A JP2000160330 A JP 2000160330A JP 3713418 B2 JP3713418 B2 JP 3713418B2
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substrate
dimensional image
processing apparatus
image processing
embedded wiring
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JP2001339057A (en
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光正 小柳
泰典 岡野
宣明 宮川
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Fujifilm Business Innovation Corp
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Fuji Xerox Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Description

【０００１】
【発明の属する技術分野】
本発明は、３次元画像処理装置の製造方法に関する。
【０００２】
【従来の技術】
近年、半導体集積回路装置の高集積化・高密度化等の目的から、複数の回路機能ブロックを立体的に集積した３次元半導体集積回路装置の開発が進められている。特に、イメージセンサとその信号を処理するための信号処理回路を一体化した３次元画像処理装置（インテリジェントイメージプロセッサ）は、光センサから得られる画像データを並列に高速処理し、高画質画像をリアルタイムで得ることが可能になることから、多くの期待が寄せられている。
【０００３】
これら３次元半導体集積回路装置は、当初はレ−ザ再結晶化等によるＳＯＩ（Silicon On Insulator）技術を利用してＳＯＩ基板形成とＳＯＩ基板への半導体装置の形成を繰り返すモノリシック法によりその製造が検討されてきたが、ＳＯＩを多層に積層するには、結晶性の確保が難しい、製造時間が長い等の問題があった。
【０００４】
このため、半導体装置または半導体集積回路装置が予め作製された単結晶半導体基板同士を貼り合わせる貼り合わせ技術による３次元半導体集積回路装置の製造方法が種々検討されている。
【０００５】
月刊セミコンダクターワールド（林善宏等、１９９０年９月号ｐ５８〜６４）には、貼り合わせ技術の一種として、研磨により薄膜化した半導体基板を貼り合わせるＣＵＢＩＣ技術が提案されている。ＣＵＢＩＣ技術では、まずシリコン基板上に半導体素子が形成された第１の半導体基板を支持基板に接着した後、余分なシリコン基板をポリッシングして薄膜化する。次に、埋め込み配線、裏面配線、バンプ／プールからなるコンタクト部材等のデバイスの縦方向の接続に必要な配線を形成し、第１の半導体基板とシリコン基板上に半導体素子の形成された第２の半導体基板とを貼り合わせる。そして最後に支持基板を取り外して多層構造の半導体装置が完成する。
【０００６】
また、特開平６−２６０５９４号公報には、貼り合わせ技術による３次元半導体集積回路装置の製造方法が開示されている。この方法は、シリコン基板上に半導体素子が形成された第１の半導体基板を支持基板に接着した後、余分なシリコン基板をポリッシングして薄膜化する点はＣＵＢＩＣ技術と共通しているが、第１の半導体基板に予め埋め込み配線を形成するための深溝が設けられている点、及び第１の半導体基板とシリコン基板上に半導体素子の形成された第２の半導体基板とを貼り合わせ、貼り合わせ後に支持基板を取り除き埋め込み配線を形成する点で、ＣＵＢＩＣ技術とは異なっている。
【０００７】
【発明が解決しようとする課題】
しかしながら、いずれの製造方法も、第１の半導体基板を支持基板に貼り合わせ、研磨した後に支持基板から第１の半導体基板を剥離する工程を含んでおり、製造工程が煩雑であるという問題があった。特に、３次元画像処理装置を製造する場合には、支持基板を取り除いた後にその表面にイメージセンサを構成するマイクロレンズを備えた透明基板を設ける必要があるため、なおさら製造工程が煩雑になる。
【０００８】
また、ＣＵＢＩＣ技術では、余分なシリコン基板をポリッシングして薄膜化した後に支持基板を取り除くため、支持基板を取り除く際に半導体基板上に形成された集積回路が破損するという問題があった。
【０００９】
また、特開平６−２６０５９４号公報に記載された方法では、埋め込み配線を形成するための深溝が予め設けられた第１の半導体基板を支持基板に接着するため、深溝に入り込んだ接着剤の除去が困難であるという問題や、第１の半導体基板と第２の半導体基板とを接着した後に深溝の側壁を酸化して絶縁膜を形成するため、接着剤の耐熱温度以上に酸化温度を上げることができず、信頼性のある絶縁膜を形成することができないという問題があった。
【００１０】
本発明は上記従来技術の問題点に鑑みなされたものであり、本発明の目的は、支持基板の着脱工程が不要で製造工程を大幅に簡略化することができ、簡素かつ容易な工程により３次元画像処理装置を製造することができる３次元画像処理装置の製造方法を提供することにある。また、本発明の他の目的は、信頼性の高い絶縁膜で囲まれた埋め込み配線を形成することができる３次元画像処理装置の製造方法を提供することにある。
【００１１】
【課題を解決するための手段】
上記目的を達成するために、請求項１に記載の３次元画像処理装置の製造方法は、光を集光するレンズを備えた透明基板と、主面に光電変換素子が形成されると共に該光電変換素子に電気的に接続された埋め込み配線が形成された光電変換基板とを、透明基板の裏面と光電変換基板の主面とが対向するように接着して、３次元画像処理装置を製造することを特徴とする。
【００１２】
請求項１の発明では、支持基板等を用いることなく、光を集光するレンズを備えた透明基板と、主面に光電変換素子が形成されると共に該光電変換素子に電気的に接続された埋め込み配線が形成された光電変換基板とを、透明基板の裏面と光電変換基板の主面とが対向するように接着するため、透明基板をそのままイメージセンサの透明基板として使用することができ、支持基板への接着工程、支持基板からの除去工程、及び透明基板の形成工程が不要であり、３次元画像処理装置の製造工程を大幅に簡略化することができる。また、光電変換基板に埋め込み配線を形成した後に透明基板と貼り合わせるため、信頼性の高い絶縁膜で囲まれた埋め込み配線を形成することができる。
【００１３】
請求項２に記載の３次元画像処理装置の製造方法は、請求項１の発明において、前記光電変換基板の裏面側を研磨して前記埋め込み配線を露出させ、該光電変換基板の裏面に、主面に増幅器及びアナログ／デジタル変換器が形成されると共に該増幅器及びアナログ／デジタル変換器に電気的に接続された埋め込み配線が形成された増幅変換基板を、該増幅器及びアナログ／デジタル変換器が前記埋め込み配線の露出部に電気的に接続されるように接着して、３次元画像処理装置を製造することを特徴とする。
【００１４】
請求項２の発明によれば、透明基板及び光電変換基板からなるイメージセンサ部に、研磨及び接着という簡素かつ容易な工程により、増幅器及びアナログ／デジタル変換器に電気的に接続された埋め込み配線が形成された増幅変換基板を積層した３次元画像処理装置を製造することができる。
【００１５】
請求項３に記載の３次元画像処理装置の製造方法は、請求項２の発明において、前記増幅変換基板の裏面側を研磨して前記埋め込み配線を露出させ、 該増幅変換基板の裏面に、主面にデータ記憶装置が形成されると共に該データ記憶装置に電気的に接続された埋め込み配線が形成されたデータ記憶基板を、該データ記憶装置が前記埋め込み配線の露出部に電気的に接続されるように接着して、３次元画像処理装置を製造することを特徴とする。
【００１６】
請求項３の発明によれば、透明基板及び光電変換基板からなるイメージセンサ部に研磨と接着とにより増幅変換基板が形成された積層体に、研磨及び接着という簡素かつ容易な工程により、主面に記憶装置が形成されると共にデータ記憶装置に電気的に接続された埋め込み配線が形成されたデータ記憶基板を積層した３次元画像処理装置を製造することができる。
【００１７】
請求項４に記載の３次元画像処理装置の製造方法は、請求項２の発明において、前記データ記憶基板の裏面側を研磨して前記埋め込み配線を露出させ、該データ記憶基板の裏面に、主面にデータ処理装置が形成されると共に該データ処理装置に電気的に接続された埋め込み配線が形成されたデータ処理基板を、該データ処理装置が前記埋め込み配線の露出部に電気的に接続されるように接着して、３次元画像処理装置を製造することを特徴とする。
【００１８】
請求項４の発明によれば、透明基板及び光電変換基板からなるイメージセンサ部に研磨と接着とにより増幅変換基板及びデータ記憶基板が形成された積層体に、研磨及び接着という簡素かつ容易な工程により、主面にデータ処理装置が形成されると共に該データ処理装置に電気的に接続された埋め込み配線が形成されたデータ処理基板を積層した３次元画像処理装置を製造することができる。
【００１９】
請求項５に記載の３次元画像処理装置の製造方法は、請求項４の発明において、前記データ処理基板の裏面側を研磨して前記埋め込み配線を露出させ、該データ処理基板の裏面に、主面に出力回路が形成されると共に該出力回路に電気的に接続された埋め込み配線が形成された出力回路基板を、該出力回路が前記埋め込み配線の露出部に電気的に接続されるように接着して、３次元画像処理装置を製造することを特徴とする。
【００２０】
請求項５の発明によれば、透明基板及び光電変換基板からなるイメージセンサ部に研磨と接着とにより増幅変換基板、データ記憶基板、及びデータ処理装置が形成された積層体に、研磨及び接着という簡素かつ容易な工程により、主面に出力回路が形成されると共に該出力回路に電気的に接続された埋め込み配線が形成された出力回路基板を積層した３次元画像処理装置を製造することができる。
【００２１】
【発明の実施の形態】
以下、本発明の３次元画像処理装置の製造方法を、図面を参照しつつ具体的に説明する。図１〜図５は、本発明の３次元画像処理装置の製造方法の各工程を示す断面図である。
【００２２】
まず、図１に示すように、光電変換基板２０に、多数のマイクロレンズ１２が２次元状に形成された石英ガラス製の透明基板１０を、光電変換基板２０の主面と透明基板１０の裏面とが対向するように、エポキシ樹脂やポリイミド樹脂等の高分子材料からなる接着剤１４を介して接着する。
【００２３】
上記で用いる光電変換基板２０は、内部にニ酸化ケイ素からなる絶縁層３６が挿入されたｎ型シリコン結晶基板１６上に、フォトダイオードとＭＯＳトランジスタとを形成したものである。フォトダイオードは、光電変換基板２０のｎ型シリコン結晶基板１６上にｐ型不純物層１８を形成し、ｐ型不純物層１８表層のマイクロレンズ１２の焦点位置に対応する領域にｎ型不純物層２２を設けることにより形成されている。また、ＭＯＳトランジスタは、ｐ型不純物層１８表層の撮像領域以外の部分にソース及びドレインとなるｎ型不純物層２２を設け、このｎ型不純物層２２間のｐ型不純物層１８上に絶縁膜２４Ａにより相互に絶縁されたポリシリコンからなるゲート電極２６を設けることにより形成されている。なお、隣接するＭＯＳトランジスタはニ酸化ケイ素からなる素子分離膜３０で分離されている。
【００２４】
また、光電変換基板２０には、素子分離膜３０を貫通し光電変換基板２０の裏面に達するトレンチ（深溝）が設けられている。なお、このようなトレンチは誘導結合型プラズマエッチング等により形成することができる。このトレンチの内表面に絶縁膜３２が形成され、トレンチ内に導電材料が充填されて埋め込み配線３４が形成されている。埋め込み配線３４を形成する導電材料としては、例えば不純物をドープした低抵抗多結晶シリコンやタングステン等の低抵抗の金属が使用される。
【００２５】
ＭＯＳトランジスタのソースとなるｎ型不純物層２２は、例えばアルミニウムからなるソース電極２８に接続されおり、ドレインとなるｎ型不純物層２２は、絶縁膜２４Ｂによりソース電極２８と絶縁された例えばアルミニウムからなるドレイン電極２９に接続されている。このドレイン電極２９は埋め込み配線３４に接続されており、ゲート電極２６に所定電圧を印加することによりｎ型チャネル２２及びｐ型不純物層１８からなるフォトダイオードに蓄積された電荷はこの埋め込み配線３４を介して後述する増幅器へと転送される。
【００２６】
次に、図２に示すように、透明基板１０に接着された光電変換基板２０を、化学的機械研磨により裏面側から研磨して薄膜化する。ｎ型シリコン結晶基板１６に挿入された絶縁層３６を構成するニ酸化ケイ素はシリコンよりも研磨耐性が大きいため、研磨は絶縁層３６の手前で止まり、埋め込み配線３４が絶縁層３６から露出される。このとき透明基板１０が支持基板の役割を果たすが、当初からマイクロレンズ１２を一体化して形成した石英ガラス製の透明基板を用いているので後で取り外す必要はない。
【００２７】
以上の工程により、光を集光するレンズを備えた透明基板１０、及び光電変換基板２０を備えたイメージセンサ部が完成する。
【００２８】
次に、図３に示すように、光電変換基板２０の裏面に、光電変換基板２０からの信号を増幅すると共に増幅されたアナログ信号をデジタル信号に変換する増幅変換基板４０を接着する。この増幅変換基板４０は、内部にニ酸化ケイ素からなる絶縁層３６Ａが挿入されたシリコン基板３８Ａ上に、絶縁膜４２Ａにより絶縁されたゲート４４Ａ、ソース４６Ａ、及びドレイン４８Ａからなる複数のＭＯＳＦＥＴ５０Ａ（本実施の形態では２つのＭＯＳＦＥＴを図示する）を形成したものである。これら隣接するＭＯＳＦＥＴ５０Ａは、ニ酸化ケイ素からなる素子分離膜５２Ａにより分離されている。
【００２９】
また、増幅変換基板４０には、この素子分離膜５２Ａを貫通し増幅変換基板４０の裏面側表面から回路面に達するトレンチが設けられている。このトレンチの内表面に絶縁膜５４Ａが形成され、トレンチ内に導電材料が充填されて埋め込み配線５６Ａが形成されている。埋め込み配線５６Ａを形成する導電材料としては、例えば不純物をドープした低抵抗多結晶シリコンやタングステン等の低抵抗の金属が使用される。この埋め込み配線５６Ａの回路面側の端部にはアルミニウム配線５８Ａが直接接続されている。これにより増幅器（アンプ）及びアナログ／デジタル変換器（ＡＤＣ）を含む集積回路が構成されている。形成された集積回路はニ酸化ケイ素からなる絶縁膜６０Ａにより被覆され、増幅変換基板４０の集積回路側の表面が平坦化されている。また、この絶縁膜６０Ａに設けられた開口からアルミニウム配線５８Ａが引き出され、絶縁膜６０Ａの表面に露出されている。
【００３０】
上記光電変換基板２０の裏面側の表面に、絶縁層３６の表面から露出した埋め込み配線３４の端部に接触するようにマイクロバンプ６２を形成する。一方、増幅変換基板４０の集積回路側の表面にも、絶縁膜６０Ａの表面に露出したアルミニウム配線５８Ａの端部に接触するようにマイクロバンプ６４を形成する。マイクロバンプは、レジストマスクを用いたリフトオフ等により形成することができ、マイクロバンプの材料としては例えば金とインジウムとの合金またはインジウムを用いることができる。
【００３１】
光電変換基板２０の裏面側の表面に設けられたマイクロバンプ６２と、増幅変換基板４０の集積回路面側の表面に設けられたマイクロバンプ６４とが電気的に接続されるように、増幅変換基板４０上に光電変換基板２０を重ね合わせて仮接着する。なお、光電変換基板２０と増幅変換基板４０との位置合わせは、例えばシリコンウエハを透過する赤外線を用いた位置合わせ装置により行うことができる。
【００３２】
仮接着した光電変換基板２０と増幅変換基板４０とを、液状のエポキシ樹脂を保持した容器と共に気圧調整が可能なチャンバーに入れてチャンバー内を真空にし、仮接着した光電変換基板２０と増幅変換基板４０とを液状のエポキシ樹脂にディップして常圧に戻し基板間の隙間にエポキシ樹脂６６を注入する。その後基板を引き上げエポキシ樹脂６６を硬化させて、増幅変換基板４０と光電変換基板２０との接着が完了する。
【００３３】
次に、図４に示すように、増幅変換基板４０を裏面側から化学的機械研磨により均一な厚さに研磨して薄膜化する。絶縁層３６Ａを構成するニ酸化ケイ素はシリコンよりも研磨耐性が大きいため、研磨は絶縁層３６Ａの手前で止まり、絶縁層３６Ａよりも深い位置まで形成されている埋め込み配線５６Ａが絶縁層３６Ａから露出される。
【００３４】
次に、図５に示すように、光電変換基板２０に接着された増幅変換基板４０の裏面に、一時的にデータを記憶するデータ記憶装置（レジスタアレイ）を備えたデータ記憶基板７０を接着する。ここで用いるデータ記憶基板７０は、増幅変換基板４０と同様に、内部にニ酸化ケイ素からなる絶縁層３６Ｂが挿入されたシリコン基板３８Ｂ上に、絶縁膜４２Ｂにより絶縁されたゲート４４Ｂ、ソース４６Ｂ、及びドレイン４８Ｂからなる複数のＭＯＳＦＥＴ５０Ｂ（本実施の形態では２つのＭＯＳＦＥＴを図示する）を形成したものであり、隣接するＭＯＳＦＥＴ５０Ｂは、ニ酸化ケイ素からなる素子分離膜５２Ｂにより分離されている。
【００３５】
また、データ記憶基板７０には、この素子分離膜５２Ｂを貫通しデータ記憶基板７０の裏面側表面から回路面に達するトレンチが設けられている。このトレンチの内表面に絶縁膜５４Ｂが形成され、トレンチ内に導電材料が充填されて埋め込み配線５６Ｂが形成されている。埋め込み配線５６Ｂを形成する導電材料としては、例えば不純物をドープした低抵抗多結晶シリコンやタングステン等の低抵抗の金属が使用される。埋め込み配線５６Ｂの回路面側の端部にはアルミニウム配線５８Ｂが直接接続されている。これによりデータ記憶装置を含む集積回路が構成されている。形成された集積回路は、ニ酸化ケイ素からなる絶縁膜６０Ｂにより被覆され、データ記憶基板７０の集積回路側の表面が平坦化されている。この絶縁膜６０Ｂに設けられた開口からアルミニウム配線５８Ｂが引き出されて、絶縁膜６０Ｂの表面に露出されている。
【００３６】
上記増幅変換基板４０の裏面側の表面に、絶縁層３６Ａの表面から露出した埋め込み配線５６Ａの端部に接触するようにマイクロバンプ７１を形成する。一方、データ記憶基板７０の集積回路側の表面にも、絶縁膜６０Ｂの表面に露出したアルミニウム配線５８Ｂの端部に接触するようにマイクロバンプ７２を形成する。そして増幅変換基板４０の裏面側の表面に設けられたマイクロバンプ７１と、データ記憶基板７０の集積回路側の表面に設けられたマイクロバンプ７２とが電気的に接続されるようにデータ記憶基板７０上に増幅変換基板４０を重ね合わせて仮接着し、光電変換基板２０及び増幅変換基板４０を接着する場合と同様にして、増幅変換基板４０とデータ記憶基板７０とをエポキシ樹脂７４により接着する。
【００３７】
次に、図６に示すように、データ記憶基板７０の裏面に、データ処理基板８０、出力回路基板９０、及び出力端子部１００を順に形成する。上記増幅変換基板４０やデータ記憶基板７０の形成工程と同様にして、増幅変換基板４０に接着されたデータ記憶基板７０を裏面側から研磨し、データ記憶基板７０の裏面に、データ処理装置（プロセッサアレイ）を備え埋め込み配線８２の形成されたデータ処理基板８０を、両基板に設けられた集積回路が埋め込み配線８２により電気的に接続されるように接着する。さらに、このデータ処理基板８０を裏面側から研磨した後に、データ処理基板８０の裏面に埋め込み配線９２の形成された出力回路基板９０を、両基板に設けられた集積回路が埋め込み配線９２により電気的に接続されるように接着する。そして出力回路基板９０を裏面側から研磨して、出力回路基板９０裏面の絶縁膜から埋め込み配線９２の端部を露出させ、露出した埋め込み配線９２の端部に接触するようにマイクロバンプ９３を形成する。
【００３８】
そして最後に出力回路基板９０の裏面に出力端子部１００を形成する。出力端子部１００はシリコン基板１０２にこのシリコン基板１０２を貫通し基板両面側に露出した埋め込み配線１０４が形成されたものである。埋め込み配線１０４を形成する導電材料としては、例えば銅、タングステン、金等の低抵抗の金属が使用される。この出力端子部１００の入力側の表面に、出力端子部１００の絶縁層の表面から露出した埋め込み配線１０４の一方の端部に接触するようにマイクロバンプ９４を形成する。そして出力回路基板９０の裏面側の表面に設けられたマイクロバンプ９３と出力端子部１００の入力側の表面に設けられたマイクロバンプ９４とが接触し、出力回路基板９０に設けられた集積回路が出力端子部１００の出力端子に電気的に接続されるように両基板を接着する。そして上記出力端子部１００の出力側の表面には、埋め込み配線１０４の他方の端部に接触するようにマイクロバンプ１０６を形成する。マイクロバンプ１０６は、例えば金やインジウムまたはそれらの合金から形成することができる。また、はんだバンプとしてもよい。
【００３９】
以上の工程により、光を集光するレンズを備えた透明基板１０及び光電変換基板２０からなるイメージセンサ部と、そのイメージセンサ部からの信号を処理するための処理部（増幅変換基板４０、データ記憶基板７０、データ処理基板８０及び出力回路基板９０）とを一体化した図６に示す３次元画像処理装置を得ることができる。
【００４０】
本実施の形態では、多数のマイクロレンズが２次元状に形成された石英ガラス製の透明基板に光電変換基板を直接接着するので、支持基板を別途用意する必要がなく支持基板の着脱工程が不要となる。これにより製造工程を大幅に簡略化することができ、簡素かつ容易な工程により３次元画像処理装置を製造することができる。また、各集積回路基板の埋め込み配線は貼り合わせ前に形成されるので、信頼性の高い絶縁膜で囲まれた埋め込み配線を形成することができる。
【００４１】
上記実施の形態では、集積回路を形成するための各半導体基板にニ酸化ケイ素からなる絶縁層が内部に形成されたシリコン基板を使用したが、ニ酸化ケイ素からなる絶縁層を含まないシリコン基板を使用してもよい。
【００４２】
上記実施の形態では、埋め込み配線の両端部にマイクロバンプを形成し、マイクロバンプ同士を接触させて隣接する基板を電気的に接続する例について説明したが、埋め込み配線の一方の端部にのみマイクロバンプを形成して隣接する基板を電気的に接続するようにしても良い。
【００４３】
上記実施の形態では、集光レンズを備えた透明基板及び光電変換基板からなるイメージセンサ部に、そのイメージセンサ部からの信号を処理するための増幅変換基板、データ記憶基板、データ処理基板、及び出力回路基板の各処理部を研磨及び貼合せを繰り返すことにより形成する例について説明したが、イメージセンサ部を構成する光電変換基板を裏面側から研磨して埋め込み配線を露出させた後、配線により光電変換基板を増幅変換基板と電気的に接続することもできる。
【００４４】
また、上記実施の形態と同様にしてイメージセンサ部に研磨及び貼合せにより増幅変換基板を形成し、増幅変換基板を裏面側から研磨して埋め込み配線を露出させた後、配線により増幅変換基板をデータ記憶基板と電気的に接続することもできる。また、上記実施の形態と同様にしてイメージセンサ部に研磨及び貼合せにより増幅変換基板及びデータ記憶基板を形成し、データ記憶基板を裏面側から研磨して埋め込み配線を露出させた後、配線によりデータ記憶基板をデータ処理基板と電気的に接続することもできる。また、上記実施の形態と同様にしてイメージセンサ部に研磨及び貼合せにより増幅変換基板、データ記憶基板、及びデータ処理基板を形成し、データ処理基板を裏面側から研磨して埋め込み配線を露出させた後、配線によりデータ処理基板を出力回路基板と電気的に接続することもできる。
【００４５】
なお、上記実施の形態において使用するシリコン基板は、ウエハスケールでもチップスケールでもよい。
【００４６】
【発明の効果】
本発明の３次元画像処理装置の製造方法は、支持基板の着脱工程が不要で、製造工程を大幅に簡略化することができ、簡素かつ容易な工程により３次元画像処理装置を製造することができる、という効果を奏する。また、本発明の３次元画像処理装置の製造方法は、信頼性の高い絶縁膜で囲まれた埋め込み配線を形成することができる、という効果を奏する。
【図面の簡単な説明】
【図１】本実施の形態の３次元画像形成装置の製造工程を示す概略断面図である。
【図２】本実施の形態の３次元画像形成装置の製造工程を示す概略断面図である。
【図３】本実施の形態の３次元画像形成装置の製造工程を示す概略断面図である。
【図４】本実施の形態の３次元画像形成装置の製造工程を示す概略断面図である。
【図５】本実施の形態の３次元画像形成装置の製造工程を示す概略断面図である。
【図６】本実施の形態の３次元画像形成装置の構造を示す概略断面図である。
【符号の説明】
１０ 透明基板
１２ マイクロレンズ
１６ ｎ型シリコン結晶基板
１８ ｐ型不純物層
２０ 光電変換基板
２２ ｎ型不純物層
２６ ゲート電極
２８ 電極
３４ 埋め込み配線
４０ 増幅変換基板
７０ データ記憶基板
８０ データ処理基板
９０ 出力回路基板
１００ 出力端子部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a three-dimensional image processing apparatus.
[0002]
[Prior art]
In recent years, development of a three-dimensional semiconductor integrated circuit device in which a plurality of circuit function blocks are three-dimensionally integrated has been promoted for the purpose of high integration and high density of the semiconductor integrated circuit device. In particular, a three-dimensional image processing device (intelligent image processor) that integrates an image sensor and a signal processing circuit for processing the signal processes image data obtained from the optical sensor in parallel at high speed to produce a high-quality image in real time. Many expectations are placed on it.
[0003]
These three-dimensional semiconductor integrated circuit devices are initially manufactured by a monolithic method that repeats the formation of an SOI substrate and the formation of a semiconductor device on the SOI substrate using SOI (Silicon On Insulator) technology such as laser recrystallization. As discussed above, in order to stack SOI in multiple layers, there are problems such as difficulty in securing crystallinity and long manufacturing time.
[0004]
For this reason, various methods for manufacturing a three-dimensional semiconductor integrated circuit device using a bonding technique for bonding single crystal semiconductor substrates on which a semiconductor device or a semiconductor integrated circuit device is manufactured in advance have been studied.
[0005]
Monthly Semiconductor World (Yoshihiro Hayashi et al., September 1990 issue p58-64) proposes a CUBIC technique for bonding a semiconductor substrate thinned by polishing as a kind of bonding technique. In the CUBIC technology, first, a first semiconductor substrate having a semiconductor element formed on a silicon substrate is bonded to a support substrate, and then the excess silicon substrate is polished to reduce the thickness. Next, wiring necessary for vertical connection of devices such as embedded wiring, back surface wiring, and bump / pool contact members is formed, and a second semiconductor device is formed on the first semiconductor substrate and the silicon substrate. The semiconductor substrate is bonded together. Finally, the support substrate is removed to complete the multilayer semiconductor device.
[0006]
Japanese Patent Application Laid-Open No. 6-260594 discloses a method for manufacturing a three-dimensional semiconductor integrated circuit device by a bonding technique. This method is common to the CUBIC technology in that after a first semiconductor substrate having a semiconductor element formed on a silicon substrate is bonded to a support substrate, the excess silicon substrate is polished and thinned. The first semiconductor substrate is provided with a deep groove for forming a buried wiring in advance, and the first semiconductor substrate is bonded to the second semiconductor substrate on which the semiconductor element is formed on the silicon substrate. It differs from the CUBIC technology in that the support substrate is removed later to form a buried wiring.
[0007]
[Problems to be solved by the invention]
However, each of the manufacturing methods includes a step of peeling the first semiconductor substrate from the support substrate after bonding and polishing the first semiconductor substrate to the support substrate, and there is a problem that the manufacturing process is complicated. It was. In particular, in the case of manufacturing a three-dimensional image processing apparatus, it is necessary to provide a transparent substrate having a microlens constituting an image sensor on the surface after removing the support substrate, so that the manufacturing process becomes even more complicated.
[0008]
In addition, in the CUBIC technology, since the support substrate is removed after polishing the excess silicon substrate to reduce the thickness, the integrated circuit formed on the semiconductor substrate is damaged when the support substrate is removed.
[0009]
Further, in the method described in Japanese Patent Laid-Open No. 6-260594, the first semiconductor substrate provided with the deep groove for forming the embedded wiring is bonded to the support substrate, so that the adhesive that has entered the deep groove is removed. In order to form an insulating film by oxidizing the sidewall of the deep groove after bonding the first semiconductor substrate and the second semiconductor substrate, the oxidation temperature must be raised above the heat resistance temperature of the adhesive. There was a problem that a reliable insulating film could not be formed.
[0010]
The present invention has been made in view of the above-described problems of the prior art, and the object of the present invention is to eliminate the support substrate attaching / detaching step and greatly simplify the manufacturing process. An object of the present invention is to provide a method for manufacturing a three-dimensional image processing apparatus capable of manufacturing a three-dimensional image processing apparatus. Another object of the present invention is to provide a method for manufacturing a three-dimensional image processing apparatus capable of forming a buried wiring surrounded by a highly reliable insulating film.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a three-dimensional image processing apparatus according to claim 1 includes a transparent substrate having a lens for condensing light, a photoelectric conversion element formed on a main surface, and the photoelectric conversion element. A photoelectric conversion substrate on which an embedded wiring electrically connected to the conversion element is formed is bonded so that the back surface of the transparent substrate and the main surface of the photoelectric conversion substrate face each other to manufacture a three-dimensional image processing apparatus. It is characterized by that.
[0012]
In the first aspect of the invention, a transparent substrate having a lens for condensing light without using a support substrate or the like, and a photoelectric conversion element formed on the main surface and electrically connected to the photoelectric conversion element Since the photoelectric conversion substrate on which the embedded wiring is formed is bonded so that the back surface of the transparent substrate and the main surface of the photoelectric conversion substrate face each other, the transparent substrate can be used as it is as the transparent substrate of the image sensor. The step of bonding to the substrate, the step of removing from the support substrate, and the step of forming the transparent substrate are unnecessary, and the manufacturing process of the three-dimensional image processing apparatus can be greatly simplified. Further, since the embedded wiring is formed on the photoelectric conversion substrate and then bonded to the transparent substrate, the embedded wiring surrounded by the highly reliable insulating film can be formed.
[0013]
The manufacturing method of the three-dimensional image processing apparatus according to claim 2 is the invention according to claim 1, wherein the back surface side of the photoelectric conversion substrate is polished to expose the embedded wiring, and the back surface of the photoelectric conversion substrate is The amplifier and the analog / digital converter have the amplifier and the analog / digital converter formed on the surface, and the embedded conversion board formed with the embedded wiring electrically connected to the amplifier and the analog / digital converter. The three-dimensional image processing apparatus is manufactured by being bonded so as to be electrically connected to the exposed portion of the embedded wiring.
[0014]
According to the second aspect of the present invention, the embedded wiring electrically connected to the amplifier and the analog / digital converter is formed on the image sensor unit including the transparent substrate and the photoelectric conversion substrate by a simple and easy process of polishing and adhesion. A three-dimensional image processing apparatus in which the formed amplification conversion substrates are stacked can be manufactured.
[0015]
According to a third aspect of the present invention, there is provided a method of manufacturing a three-dimensional image processing apparatus according to the second aspect of the invention, wherein the back surface side of the amplification conversion substrate is polished to expose the embedded wiring, and the back surface of the amplification conversion substrate is A data storage substrate on which a data storage device is formed and an embedded wiring electrically connected to the data storage device is formed, and the data storage device is electrically connected to an exposed portion of the embedded wiring The three-dimensional image processing apparatus is manufactured by bonding as described above.
[0016]
According to the invention of claim 3, the main surface is obtained by a simple and easy process of polishing and bonding on a laminate in which an amplification conversion substrate is formed by polishing and bonding on an image sensor unit comprising a transparent substrate and a photoelectric conversion substrate. In addition, a three-dimensional image processing apparatus can be manufactured in which a storage device is formed and a data storage substrate on which an embedded wiring electrically connected to the data storage device is formed is laminated.
[0017]
According to a fourth aspect of the present invention, there is provided a method of manufacturing a three-dimensional image processing apparatus according to the second aspect of the invention, wherein the back surface side of the data storage substrate is polished to expose the embedded wiring, and the back surface of the data storage substrate is A data processing substrate having a data processing device formed on the surface and an embedded wiring electrically connected to the data processing device is electrically connected to the exposed portion of the embedded wiring. The three-dimensional image processing apparatus is manufactured by bonding as described above.
[0018]
According to the invention of claim 4, a simple and easy process of polishing and bonding to a laminate in which an amplification conversion substrate and a data storage substrate are formed by polishing and bonding on an image sensor unit composed of a transparent substrate and a photoelectric conversion substrate. Thus, it is possible to manufacture a three-dimensional image processing apparatus in which a data processing substrate is formed on a main surface and a data processing substrate on which an embedded wiring electrically connected to the data processing apparatus is formed.
[0019]
According to a fifth aspect of the present invention, there is provided a method for manufacturing a three-dimensional image processing apparatus according to the fourth aspect of the invention, wherein the back surface side of the data processing board is polished to expose the embedded wiring, and the main surface is formed on the back surface of the data processing board. An output circuit board on which an output circuit is formed and an embedded wiring electrically connected to the output circuit is bonded so that the output circuit is electrically connected to an exposed portion of the embedded wiring Then, a three-dimensional image processing apparatus is manufactured.
[0020]
According to the invention of claim 5, polishing and adhesion are performed on a laminate in which an amplification conversion substrate, a data storage substrate, and a data processing device are formed by polishing and adhesion on an image sensor unit composed of a transparent substrate and a photoelectric conversion substrate. Through a simple and easy process, it is possible to manufacture a three-dimensional image processing apparatus in which an output circuit board is formed by forming an output circuit on the main surface and forming an embedded wiring electrically connected to the output circuit. .
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the manufacturing method of the three-dimensional image processing apparatus of the present invention will be specifically described with reference to the drawings. 1-5 is sectional drawing which shows each process of the manufacturing method of the three-dimensional image processing apparatus of this invention.
[0022]
First, as shown in FIG. 1, a quartz glass transparent substrate 10 in which a large number of microlenses 12 are two-dimensionally formed on a photoelectric conversion substrate 20, a main surface of the photoelectric conversion substrate 20, and a back surface of the transparent substrate 10. Are bonded via an adhesive 14 made of a polymer material such as an epoxy resin or a polyimide resin.
[0023]
The photoelectric conversion substrate 20 used above is obtained by forming a photodiode and a MOS transistor on an n-type silicon crystal substrate 16 in which an insulating layer 36 made of silicon dioxide is inserted. In the photodiode, the p-type impurity layer 18 is formed on the n-type silicon crystal substrate 16 of the photoelectric conversion substrate 20, and the n-type impurity layer 22 is formed in a region corresponding to the focal position of the microlens 12 on the surface layer of the p-type impurity layer 18. It is formed by providing. Further, in the MOS transistor, an n-type impurity layer 22 serving as a source and a drain is provided in a portion other than the imaging region of the surface layer of the p-type impurity layer 18, and an insulating film 24A is formed on the p-type impurity layer 18 between the n-type impurity layers 22. The gate electrode 26 is made of polysilicon which is insulated from each other. Adjacent MOS transistors are separated by an element isolation film 30 made of silicon dioxide.
[0024]
The photoelectric conversion substrate 20 is provided with a trench (deep groove) that penetrates the element isolation film 30 and reaches the back surface of the photoelectric conversion substrate 20. Such a trench can be formed by inductively coupled plasma etching or the like. An insulating film 32 is formed on the inner surface of the trench, and a buried wiring 34 is formed by filling the trench with a conductive material. As the conductive material for forming the buried wiring 34, for example, a low-resistance metal such as low-resistance polycrystalline silicon or tungsten doped with impurities is used.
[0025]
The n-type impurity layer 22 serving as the source of the MOS transistor is connected to the source electrode 28 made of, for example, aluminum, and the n-type impurity layer 22 serving as the drain is made of, for example, aluminum insulated from the source electrode 28 by the insulating film 24B. The drain electrode 29 is connected. The drain electrode 29 is connected to the buried wiring 34. When a predetermined voltage is applied to the gate electrode 26, the charge accumulated in the photodiode composed of the n-type channel 22 and the p-type impurity layer 18 passes through the buried wiring 34. Via the amplifier described later.
[0026]
Next, as shown in FIG. 2, the photoelectric conversion substrate 20 bonded to the transparent substrate 10 is polished from the back side by chemical mechanical polishing to form a thin film. Since silicon dioxide constituting the insulating layer 36 inserted into the n-type silicon crystal substrate 16 has higher polishing resistance than silicon, polishing stops before the insulating layer 36 and the embedded wiring 34 is exposed from the insulating layer 36. . At this time, the transparent substrate 10 serves as a support substrate, but since a transparent substrate made of quartz glass formed by integrating the microlens 12 from the beginning is used, it is not necessary to remove it later.
[0027]
Through the above steps, an image sensor unit including the transparent substrate 10 including the lens for condensing light and the photoelectric conversion substrate 20 is completed.
[0028]
Next, as illustrated in FIG. 3, an amplification conversion substrate 40 that amplifies the signal from the photoelectric conversion substrate 20 and converts the amplified analog signal into a digital signal is bonded to the back surface of the photoelectric conversion substrate 20. This amplification conversion substrate 40 has a plurality of MOSFETs 50A (this book) composed of a gate 44A, a source 46A, and a drain 48A insulated by an insulating film 42A on a silicon substrate 38A in which an insulating layer 36A made of silicon dioxide is inserted. In the embodiment, two MOSFETs are illustrated). These adjacent MOSFETs 50A are separated by an element isolation film 52A made of silicon dioxide.
[0029]
The amplification conversion substrate 40 is provided with a trench that penetrates the element isolation film 52 </ b> A and reaches the circuit surface from the back surface of the amplification conversion substrate 40. An insulating film 54A is formed on the inner surface of the trench, and the buried wiring 56A is formed by filling the trench with a conductive material. As a conductive material for forming the embedded wiring 56A, for example, a low-resistance metal such as low-resistance polycrystalline silicon or tungsten doped with impurities is used. An aluminum wiring 58A is directly connected to the end of the embedded wiring 56A on the circuit surface side. Thus, an integrated circuit including an amplifier and an analog / digital converter (ADC) is configured. The formed integrated circuit is covered with an insulating film 60A made of silicon dioxide, and the surface of the amplification conversion substrate 40 on the integrated circuit side is flattened. Further, the aluminum wiring 58A is drawn out from the opening provided in the insulating film 60A and exposed on the surface of the insulating film 60A.
[0030]
Micro bumps 62 are formed on the back surface of the photoelectric conversion substrate 20 so as to be in contact with the ends of the embedded wiring 34 exposed from the surface of the insulating layer 36. On the other hand, micro bumps 64 are also formed on the surface of the amplification conversion substrate 40 on the integrated circuit side so as to be in contact with the end of the aluminum wiring 58A exposed on the surface of the insulating film 60A. The micro bumps can be formed by lift-off using a resist mask, and the material of the micro bumps can be, for example, an alloy of gold and indium or indium.
[0031]
Amplification conversion substrate so that micro bumps 62 provided on the back surface of photoelectric conversion substrate 20 and micro bumps 64 provided on the surface of integrated circuit surface of amplification conversion substrate 40 are electrically connected. The photoelectric conversion substrate 20 is superposed on 40 and temporarily bonded. The alignment between the photoelectric conversion substrate 20 and the amplification conversion substrate 40 can be performed by, for example, an alignment apparatus using infrared rays that pass through a silicon wafer.
[0032]
The temporarily bonded photoelectric conversion substrate 20 and amplification conversion substrate 40 are placed in a chamber capable of adjusting the atmospheric pressure together with a container holding a liquid epoxy resin, and the chamber is evacuated to temporarily bond the photoelectric conversion substrate 20 and amplification conversion substrate. 40 is dipped in a liquid epoxy resin to return to normal pressure, and an epoxy resin 66 is injected into the gap between the substrates. Thereafter, the substrate is pulled up to cure the epoxy resin 66, and the adhesion between the amplification conversion substrate 40 and the photoelectric conversion substrate 20 is completed.
[0033]
Next, as shown in FIG. 4, the amplification conversion substrate 40 is polished to a uniform thickness by chemical mechanical polishing from the back side. Since silicon dioxide constituting the insulating layer 36A has higher polishing resistance than silicon, polishing stops before the insulating layer 36A, and the embedded wiring 56A formed to a position deeper than the insulating layer 36A is exposed from the insulating layer 36A. Is done.
[0034]
Next, as shown in FIG. 5, a data storage substrate 70 having a data storage device (register array) for temporarily storing data is bonded to the back surface of the amplification conversion substrate 40 bonded to the photoelectric conversion substrate 20. . As in the case of the amplification conversion substrate 40, the data storage substrate 70 used here has a gate 44B, a source 46B, an insulating film 42B, and a gate 44B insulated on an insulating layer 36B made of silicon dioxide. And a plurality of MOSFETs 50B (in the present embodiment, two MOSFETs are shown in the figure) are formed, and adjacent MOSFETs 50B are separated by an element isolation film 52B made of silicon dioxide.
[0035]
Further, the data storage substrate 70 is provided with a trench that penetrates the element isolation film 52 </ b> B and reaches the circuit surface from the back surface of the data storage substrate 70. An insulating film 54B is formed on the inner surface of the trench, and the buried wiring 56B is formed by filling the trench with a conductive material. As the conductive material for forming the buried wiring 56B, for example, a low-resistance metal such as low-resistance polycrystalline silicon or tungsten doped with impurities is used. An aluminum wiring 58B is directly connected to the end of the embedded wiring 56B on the circuit surface side. Thus, an integrated circuit including a data storage device is configured. The formed integrated circuit is covered with an insulating film 60B made of silicon dioxide, and the surface of the data storage substrate 70 on the integrated circuit side is flattened. The aluminum wiring 58B is drawn out from the opening provided in the insulating film 60B and exposed on the surface of the insulating film 60B.
[0036]
Micro bumps 71 are formed on the back surface of the amplification conversion substrate 40 so as to be in contact with the ends of the embedded wiring 56A exposed from the surface of the insulating layer 36A. On the other hand, micro bumps 72 are also formed on the surface of the data storage substrate 70 on the side of the integrated circuit so as to be in contact with the end of the aluminum wiring 58B exposed on the surface of the insulating film 60B. The data storage substrate 70 is electrically connected to the micro bumps 71 provided on the back surface of the amplification conversion substrate 40 and the micro bumps 72 provided on the surface of the data storage substrate 70 on the integrated circuit side. The amplification conversion substrate 40 is superposed and temporarily bonded, and the amplification conversion substrate 40 and the data storage substrate 70 are bonded by the epoxy resin 74 in the same manner as when the photoelectric conversion substrate 20 and the amplification conversion substrate 40 are bonded.
[0037]
Next, as shown in FIG. 6, the data processing board 80, the output circuit board 90, and the output terminal unit 100 are sequentially formed on the back surface of the data storage board 70. Similar to the formation process of the amplification conversion substrate 40 and the data storage substrate 70, the data storage substrate 70 bonded to the amplification conversion substrate 40 is polished from the back surface side, and a data processing device (processor) is mounted on the back surface of the data storage substrate 70. The data processing substrate 80 including the array and having the embedded wiring 82 formed thereon is bonded so that the integrated circuits provided on both substrates are electrically connected by the embedded wiring 82. Further, after polishing the data processing board 80 from the back side, the output circuit board 90 having the embedded wiring 92 formed on the back side of the data processing board 80 is electrically connected to the integrated circuit provided on both substrates by the embedded wiring 92. Glue to be connected to. Then, the output circuit board 90 is polished from the back surface side, the end of the embedded wiring 92 is exposed from the insulating film on the back surface of the output circuit board 90, and the micro bump 93 is formed so as to be in contact with the exposed end of the embedded wiring 92. To do.
[0038]
Finally, the output terminal portion 100 is formed on the back surface of the output circuit board 90. The output terminal unit 100 is formed by forming embedded wirings 104 penetrating through the silicon substrate 102 and exposed on both sides of the substrate. As a conductive material for forming the embedded wiring 104, a low resistance metal such as copper, tungsten, or gold is used. A micro bump 94 is formed on the input side surface of the output terminal portion 100 so as to be in contact with one end portion of the embedded wiring 104 exposed from the surface of the insulating layer of the output terminal portion 100. Then, the micro bumps 93 provided on the back surface of the output circuit board 90 and the micro bumps 94 provided on the input surface of the output terminal unit 100 come into contact with each other, and the integrated circuit provided on the output circuit board 90 is The two substrates are bonded so as to be electrically connected to the output terminal of the output terminal unit 100. A micro bump 106 is formed on the output side surface of the output terminal portion 100 so as to be in contact with the other end portion of the embedded wiring 104. The micro bump 106 can be formed from, for example, gold, indium, or an alloy thereof. Moreover, it is good also as a solder bump.
[0039]
Through the above steps, an image sensor unit comprising the transparent substrate 10 and the photoelectric conversion substrate 20 having a lens for condensing light, and a processing unit (amplification conversion substrate 40, data for processing a signal from the image sensor unit). A three-dimensional image processing apparatus shown in FIG. 6 in which the storage substrate 70, the data processing substrate 80, and the output circuit substrate 90) are integrated can be obtained.
[0040]
In this embodiment, the photoelectric conversion substrate is directly bonded to a quartz glass transparent substrate on which a large number of microlenses are two-dimensionally formed, so that it is not necessary to prepare a support substrate separately, and a support substrate attaching / detaching step is unnecessary. It becomes. As a result, the manufacturing process can be greatly simplified, and the three-dimensional image processing apparatus can be manufactured by a simple and easy process. Further, since the embedded wiring of each integrated circuit substrate is formed before bonding, the embedded wiring surrounded by a highly reliable insulating film can be formed.
[0041]
In the above embodiment, a silicon substrate in which an insulating layer made of silicon dioxide is formed in each semiconductor substrate for forming an integrated circuit is used. However, a silicon substrate that does not include an insulating layer made of silicon dioxide is used. May be used.
[0042]
In the above embodiment, an example in which micro bumps are formed at both ends of the embedded wiring and the adjacent substrates are electrically connected by bringing the micro bumps into contact with each other is described. However, the micro wiring is only applied to one end of the embedded wiring. Bumps may be formed to electrically connect adjacent substrates.
[0043]
In the above-described embodiment, the image sensor unit including the transparent substrate and the photoelectric conversion substrate provided with the condensing lens, the amplification conversion substrate for processing the signal from the image sensor unit, the data storage substrate, the data processing substrate, and Although the example which forms each processing part of an output circuit board by repeating grinding and pasting was explained, after polishing the photoelectric conversion board which constitutes an image sensor part from the back side, and exposing the embedded wiring, The photoelectric conversion substrate can be electrically connected to the amplification conversion substrate.
[0044]
Similarly to the above embodiment, the amplification conversion substrate is formed on the image sensor portion by polishing and bonding, and the amplification conversion substrate is polished from the back side to expose the embedded wiring, and then the amplification conversion substrate is formed by the wiring. It can also be electrically connected to the data storage substrate. Similarly to the above embodiment, the amplification conversion substrate and the data storage substrate are formed on the image sensor portion by polishing and bonding, and the data storage substrate is polished from the back side to expose the embedded wiring, and then the wiring is formed. The data storage board can also be electrically connected to the data processing board. Similarly to the above embodiment, an amplification conversion substrate, a data storage substrate, and a data processing substrate are formed on the image sensor portion by polishing and bonding, and the data processing substrate is polished from the back side to expose the embedded wiring. Thereafter, the data processing board can be electrically connected to the output circuit board by wiring.
[0045]
The silicon substrate used in the above embodiment may be a wafer scale or a chip scale.
[0046]
【The invention's effect】
The manufacturing method of the three-dimensional image processing apparatus of the present invention does not require the attaching / detaching process of the support substrate, can greatly simplify the manufacturing process, and can manufacture the three-dimensional image processing apparatus by a simple and easy process. There is an effect that it is possible. In addition, the method for manufacturing a three-dimensional image processing apparatus according to the present invention has an effect that a buried wiring surrounded by a highly reliable insulating film can be formed.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a three-dimensional image forming apparatus according to an embodiment.
FIG. 2 is a schematic cross-sectional view showing a manufacturing process of the three-dimensional image forming apparatus of the present embodiment.
FIG. 3 is a schematic cross-sectional view showing a manufacturing process of the three-dimensional image forming apparatus of the present embodiment.
FIG. 4 is a schematic cross-sectional view showing a manufacturing process of the three-dimensional image forming apparatus of the present embodiment.
FIG. 5 is a schematic cross-sectional view showing a manufacturing process of the three-dimensional image forming apparatus of the present embodiment.
FIG. 6 is a schematic cross-sectional view showing the structure of the three-dimensional image forming apparatus according to the present embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Transparent substrate 12 Micro lens 16 N-type silicon crystal substrate 18 P-type impurity layer 20 Photoelectric conversion substrate 22 N-type impurity layer 26 Gate electrode 28 Electrode 34 Embedded wiring 40 Amplification conversion substrate 70 Data storage substrate 80 Data processing substrate 90 Output circuit substrate 100 Output terminal

Claims (5)

光を集光するレンズを備えた透明基板と、主面に光電変換素子が形成されると共に該光電変換素子に電気的に接続された埋め込み配線が形成された光電変換基板とを、透明基板の裏面と光電変換基板の主面とが対向するように接着して、３次元画像処理装置を製造する
３次元画像処理装置の製造方法。A transparent substrate having a lens for condensing light, and a photoelectric conversion substrate in which a photoelectric conversion element is formed on a main surface and an embedded wiring electrically connected to the photoelectric conversion element is formed. A method for manufacturing a three-dimensional image processing apparatus, in which a back surface and a main surface of a photoelectric conversion substrate are bonded so as to face each other to manufacture a three-dimensional image processing apparatus. 前記光電変換基板の裏面側を研磨して前記埋め込み配線を露出させ、
該光電変換基板の裏面に、主面に増幅器及びアナログ／デジタル変換器が形成されると共に該増幅器及びアナログ／デジタル変換器に電気的に接続された埋め込み配線が形成された増幅変換基板を、該増幅器及びアナログ／デジタル変換器が前記埋め込み配線の露出部に電気的に接続されるように接着して、３次元画像処理装置を製造する
請求項１に記載の３次元画像処理装置の製造方法。Polishing the back side of the photoelectric conversion substrate to expose the embedded wiring,
An amplification conversion substrate having an amplifier and an analog / digital converter formed on the main surface and an embedded wiring electrically connected to the amplifier and the analog / digital converter formed on the back surface of the photoelectric conversion substrate; The method of manufacturing a three-dimensional image processing apparatus according to claim 1, wherein an amplifier and an analog / digital converter are bonded so as to be electrically connected to the exposed portion of the embedded wiring to manufacture the three-dimensional image processing apparatus. 前記増幅変換基板の裏面側を研磨して前記埋め込み配線を露出させ、
該増幅変換基板の裏面に、主面にデータ記憶装置が形成されると共に該データ記憶装置に電気的に接続された埋め込み配線が形成されたデータ記憶基板を、該データ記憶装置が前記埋め込み配線の露出部に電気的に接続されるように接着して、３次元画像処理装置を製造する
請求項２に記載の３次元画像処理装置の製造方法。Polishing the back side of the amplification conversion substrate to expose the embedded wiring;
A data storage substrate on which a data storage device is formed on the back surface of the amplification conversion substrate and an embedded wiring electrically connected to the data storage device is formed. The method for manufacturing a three-dimensional image processing apparatus according to claim 2, wherein the three-dimensional image processing apparatus is manufactured by being bonded so as to be electrically connected to the exposed portion. 前記データ記憶基板の裏面側を研磨して前記埋め込み配線を露出させ、
該データ記憶基板の裏面に、主面にデータ処理装置が形成されると共に該データ処理装置に電気的に接続された埋め込み配線が形成されたデータ処理基板を、該データ処理装置が前記埋め込み配線の露出部に電気的に接続されるように接着して、３次元画像処理装置を製造する
請求項３に記載の３次元画像処理装置の製造方法。Polishing the back side of the data storage substrate to expose the embedded wiring;
A data processing board on which a data processing device is formed on the back surface of the data storage substrate and an embedded wiring electrically connected to the data processing device is formed. The method for manufacturing a three-dimensional image processing apparatus according to claim 3, wherein the three-dimensional image processing apparatus is manufactured by being bonded so as to be electrically connected to the exposed portion. 前記データ処理基板の裏面側を研磨して前記埋め込み配線を露出させ、
該データ処理基板の裏面に、主面に出力回路が形成されると共に該出力回路に電気的に接続された埋め込み配線が形成された出力回路基板を、該出力回路が前記埋め込み配線の露出部に電気的に接続されるように接着して、３次元画像処理装置を製造する
請求項４に記載の３次元画像処理装置の製造方法。Polishing the back side of the data processing substrate to expose the embedded wiring;
An output circuit board on which an output circuit is formed on the back surface of the data processing board and an embedded wiring electrically connected to the output circuit is formed on the back surface of the data processing board. The method for manufacturing a three-dimensional image processing apparatus according to claim 4, wherein the three-dimensional image processing apparatus is manufactured by bonding so as to be electrically connected.
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