JP5054182B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device that enables low color mixing, high sensitivity, low afterimage, low dark current, low noise, and high pixel density.

  Currently, CCD and CMOS solid-state imaging devices are widely used in video cameras, stale cameras, and the like. And there is a constant demand for improved performance such as higher resolution and higher sensitivity of solid-state imaging devices. On the other hand, in order to realize a higher resolution of the solid-state imaging device, technological innovation has been performed by increasing the pixel density. In addition, in order to realize high sensitivity of the solid-state imaging device, technological innovation has been performed by improving light collection efficiency, reducing noise, reducing dark current, and reducing afterimages.

Hereinafter, the operation of the conventional solid-state imaging device will be described (for example, see Non-Patent Document 1). FIG. 18A shows a one-pixel configuration diagram of this CMOS solid-state imaging device, and FIG. 18B shows the potential distribution when the signal charge 50 is accumulated along the line AA ′ in FIG. Show. In FIG. 18B, the accumulated charge is indicated by hatching for distinction. This one pixel has a signal charge accumulating portion composed of a P-type semiconductor substrate 53, a silicon oxide film (SiO ₂ film) 54a and a photogate PG conductor layer for accumulating the signal charge 50 generated by the irradiation light 52, and The transfer gate TG connected, the floating diode FD connected to the channel 55 under the transfer gate TG, the amplification MOS transistor 56 having the gate AG connected to the floating diode FD, and the selection gate (SG) connected to the amplification MOS transistor 56 ) The MOS transistor 57 and the reset MOS transistor 58 having a reset gate RG and a reset drain RD diode provided on the SiO ₂ film 54b connected to the floating diode FD. The reset drain RD of the reset MOS transistor 58 and the drain of the amplification MOS transistor 56 are connected to the power supply line of the voltage Vdd. The source of the select gate (SG) MOS transistor 57 is connected to the signal line 59.

  The irradiated light (irradiated light) 52 passes through the photogate PG and enters the P-type semiconductor substrate 53. The signal charges 50 (electrons in this case) generated thereby are accumulated in the potential well 51 formed on the surface of the P-type semiconductor substrate 53 by applying a predetermined voltage to the photogate PG. The accumulated signal charge 50 is transferred to the floating diode FD when an on-voltage is applied to the transfer gate TG electrode. As a result, the potential of the floating diode FD changes according to the amount of the signal charge 50. At the same time, the gate voltage of the amplification MOS transistor 56 connected to the floating diode FD changes according to the amount of the signal charge 50. When an ON voltage is applied to the selection gate SG of the selection gate (SG) MOS transistor 57, a signal current corresponding to the gate AG voltage of the amplification MOS transistor 56 flows through the signal line 59 and is read out as an output.

As another solid-state imaging device, unlike the signal charge storage structure using the photogate PG shown in FIGS. 18A and 18B, a photodiode structure in which signal charges are stored by the photodiode PD. (For example, refer to Patent Document 1 and Non-Patent Document 2). As such a photodiode structure, for example, a P ⁺ layer provided on the surface of the photodiode PD, and further connected to the P ⁺ layer and fixed (pinned) to the ground potential in order to electrically isolate the pixels. There is a structure (pinned photodiode) comprising a channel shopper P ⁺ layer.

As another solid-state imaging device, there is one in which one pixel is formed in one island-shaped semiconductor 60 as shown in FIG. 19 (see, for example, Patent Document 2). In this pixel, a signal line N ⁺ layer 61 is formed on the substrate. In addition, a MOS transistor including a P-type semiconductor layer 62, insulating films 63a and 63b, and gate conductor layers 64a and 64b is formed on the outer periphery of the island-shaped semiconductor 60 connected to the signal line N ⁺ layer 61. Further, a photodiode that is connected to the MOS transistor and accumulates charges generated by light irradiation is formed on the outer periphery of the island-shaped semiconductor 60. This photodiode is composed of a P-type semiconductor layer 62 and N-type semiconductor layers 65a and 65b. Further, the P type semiconductor 62 surrounded by the photodiode is used as a channel, the photodiode is used as a gate, and a P ⁺ layer 66 and a signal line N ⁺ layer 61 formed on the photodiode and connected to the pixel selection lines 67a and 67b. An amplifying junction transistor is formed using the neighboring P-type semiconductor layer 62 as a source and a drain.
The basic operation of this solid-state imaging device includes a signal charge accumulation operation in which signal charges (electrons in this case) generated by light irradiation are accumulated in the photodiode, and the P-type semiconductor layer 62 and P ^{+ in the} vicinity of the signal line N ⁺ layer 61. A signal read operation for modulating a source / drain current flowing between the layer 66 by a gate voltage based on a photodiode voltage corresponding to the above-described accumulated signal charge, and reading the modulated current as a signal current, and this signal read operation Thereafter, the signal charge accumulated in the photodiode is applied to the gate conductor layers 64a and 64b of the MOS transistor by applying an ON voltage to the signal line N ⁺ layer 61 to perform a reset operation.

JP 2000-244818 A International Publication No. 2009/034623

Sunetra K. Mendis, Sabrina E. Kemeny and Eric R. Fossum: “A 128 × 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems”, IEDM93, Digest Papers, 22.6.1.pp.583-586 (1993) RMGuidash, THLee, PPKLee, DHSackett, CIDrowley, MSSwenson, L.Arbaugh, R.Hollstein, F.Shapiro, and S.Domer: ”A 0.6um CMOS Pinned Photodiode Color Imager Technology”, IEDM Digest Papers , pp.927-929 (1997)

  In the conventional CMOS solid-state imaging device shown in FIG. 18A, light 52 enters from above the photogate PG conductor layer. For the photogate PG conductor layer, for example, impurity-doped thin polycrystalline silicon (polycrystalline Si) is used. However, in such a structure, it is inevitable that a part of the blue wavelength light in the incident light 52 is absorbed by the polycrystalline Si layer. In addition, since the photogate PG is formed so as to cover the signal charge storage portion on the surface of the P-type semiconductor substrate 53, the potential of the signal charge storage portion cannot be directly connected to the gate AG of the amplification MOS transistor 56. Therefore, the transfer gate TG electrode and the floating diode FD are provided, and the signal charge 50 accumulated in the potential well 51 of the signal accumulation unit is temporarily transferred to the floating diode FD, and the potential of the floating diode FD is increased in the amplification MOS transistor 56. Giving to gate AG. For this reason, the transfer gate TG electrode and the floating diode FD are required in the pixel region. The addition of such a region is a cause of impairing the pixel density increase of the conventional CMOS solid-state imaging device.

In the solid-state imaging device having the pinned photodiode structure described in Patent Document 1 and Non-Patent Document 2, there is no problem of lowering the blue wavelength light sensitivity as in the above-described photogate PG structure. In addition, by fixing the surface of the photodiode PD to the ground potential, it is possible to prevent the occurrence of afterimage and kTC noise generated by incomplete signal charge transfer when the signal charge is transferred to the floating diode FD. . Furthermore, holes are accumulated in the P ⁺ layer on the surface of the photodiode PD. These holes recombine with electrons that are thermally excited from the SiO ₂ —Si interface state, and the electrons are mixed into the signal charge 50. Is preventing. Thereby, dark current can be reduced. However, like the above-described photogate PG structure, since the surface of the photodiode PD that accumulates signal charges is covered with the P ⁺ layer, the photodiode potential in which the signal charges are accumulated is directly amplified by the MOS transistor for amplification. Cannot connect to the gate. For this reason, similarly to the signal charge storage structure using the photogate PG, the transfer gate TG electrode and the floating diode FD region are required, which is a cause of hindering the increase in pixel density of the CMOS solid-state imaging device.

As shown in FIG. 19, in the pixel structure of a solid-state imaging device including pixels composed of island-shaped semiconductors 60, the pixels are electrically separated from each other as in the above-described pinned photodiode structure solid-state imaging device. There is no channel stopper P ⁺ layer. Instead, the pixels are separated by insulating layers (or air layers) 68a and 68b between the island-shaped semiconductors 60. Therefore, it does not have a P ⁺ layer for fixing (pinning) the surfaces of the N-type semiconductor layers (photodiode N layers) 65a and 65b to 0 V as in the pinned photodiode structure. For this reason, in this solid-state imaging device, as described above, there are problems that afterimages are generated and that kTC noise and dark current are high. In contrast, for example, ^{the P +} layer and N-type semiconductor layer 65a, between 65b and the ground ^{P +} layer led to external wiring 0V provided, further N-type semiconductor layer 65a, and the ground ^{P +} layer on the 65b When a connected P ⁺ layer is provided, it is necessary to newly form a channel stopper P ⁺ layer, a contact hole connected to the P ⁺ layer, a metal wiring, and the like. This complicates the pixel structure and increases the number of manufacturing processes, thereby impairing the increase in pixel density of the solid-state imaging device.

In the solid-state imaging device described above, the pixels 60 shown in FIG. 19 are two-dimensionally arranged. In this case, light enters from the P ⁺ layer 66 side. Among this light, there is light (incident light) 69 a incident on the P ⁺ layer 66 from an oblique direction. Part of the incident light 69a passes through the incident pixel and enters the adjacent pixel. Signal charges are generated in the adjacent pixels by the light (leakage light) 69b incident on the adjacent pixels. As a result, in the monochrome solid-state imaging device, the resolution is reduced. In a color solid-state imaging device, for example, part of red light incident on a red signal pixel is incident on an adjacent green signal pixel to generate a signal charge. As a result, image quality degradation called color mixing occurs.

  The present invention has been made in view of the above circumstances, and an object thereof is to realize a solid-state imaging device having low color mixing, high sensitivity, low afterimage, low dark current, low noise, and high pixel density.

  In order to achieve the above object, a solid-state imaging device of the present invention is a solid-state imaging device having one or a plurality of pixels, each of the pixels being a first semiconductor layer formed on a substrate; A second semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on an upper side surface region of the second semiconductor layer and spaced apart from an upper surface of the second semiconductor layer; A third semiconductor layer formed between the inner surface of the fourth semiconductor layer and the second semiconductor layer and spaced apart from the upper surface of the second semiconductor layer; and at least the second semiconductor layer A first insulating film formed on a side surface of the second semiconductor layer and an outer side surface of the fourth semiconductor layer, and a lower side surface of the side surface of the second semiconductor layer where the third semiconductor layer is not formed. A gate conductor layer formed through one insulating film, and the fourth conductive layer through the first insulating film. A conductor electrode formed on the outer surface of the conductor layer, and a fifth semiconductor layer formed on the upper surface of the second semiconductor layer so as not to contact the third semiconductor layer and the fourth semiconductor layer; At least the third semiconductor layer, an upper region of the second semiconductor layer where the third semiconductor layer is formed, the fourth semiconductor layer, and the fifth semiconductor layer. Is formed in an island shape, and the third semiconductor layer and the second semiconductor layer in the vicinity of the third semiconductor layer form a diode, and the second semiconductor layer in the vicinity of the first semiconductor layer. A junction transistor having either one of the semiconductor layer and the fifth semiconductor layer as a drain, the other as a source, and the diode as a gate is formed; the first semiconductor layer as a drain; and the third semiconductor Layer as a source and the gate conductor layer as A field effect transistor serving as a gate is formed, and changes depending on a means for accumulating in the diode signal charges generated in the pixel by irradiation of electromagnetic energy waves, and the amount of signal charges accumulated in the diode; Measuring a current flowing through the junction transistor to measure the amount of the signal charge; applying a turn-on voltage to the gate conductor layer of the field effect transistor; and Reset means for removing signal charges accumulated in the diode to the first semiconductor layer by forming a channel in a region including the second semiconductor layer between the third semiconductor layer and the third semiconductor layer; And applying a voltage to the conductor electrode so that a charge having a polarity opposite to that of the signal charge accumulated in the diode is accumulated in the fourth semiconductor layer. It is characterized by that.

  According to the present invention, it is possible to provide a solid-state imaging device having low color mixing, high sensitivity, low afterimage, low dark current, low noise, and high pixel density.

1 is a pixel structure diagram of a solid-state imaging device according to a first embodiment of the present invention. It is a pixel structure figure of the solid imaging device concerning the modification of the 1st embodiment of the present invention. It is an example of the circuit block diagram of the solid-state imaging device which concerns on 1st Embodiment. FIG. 2 is a pixel structure diagram and a potential distribution diagram for explaining the solid-state imaging device according to the first embodiment. It is a pixel structure figure for demonstrating the solid-state imaging device which concerns on the 2nd Embodiment of this invention. It is a pixel structure figure for demonstrating the solid-state imaging device which concerns on the 3rd Embodiment of this invention. It is a one part enlarged view of the pixel structure for demonstrating the solid-state imaging device which concerns on the 4th Embodiment of this invention. It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 4th Embodiment. It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 4th Embodiment. It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 4th Embodiment. It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 4th Embodiment. It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 4th Embodiment. It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 4th Embodiment. It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 4th Embodiment. It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 4th Embodiment. It is a figure for demonstrating the manufacturing method of the solid-state imaging device which concerns on 4th Embodiment. It is a one part enlarged view of the pixel structure of the solid-state imaging device concerning the 5th Embodiment of this invention. It is a pixel structure figure for demonstrating the solid-state imaging device concerning the 6th Embodiment of this invention. It is a pixel structure diagram and potential distribution diagram for explaining a first conventional solid-state imaging device. It is a pixel structure figure for demonstrating the 2nd conventional solid-state imaging device.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1A to 17.

(First embodiment of the present invention)
1A and 1B show the structure of the pixel 10 of the solid-state imaging device 100 according to the first embodiment of the present invention.

In FIG. 1A, each pixel 10 is formed with a first semiconductor layer N ⁺ layer 1 connected to a wiring XL connected in the first scanning direction on the substrate. On the first semiconductor layer N ⁺ layer 1, a second semiconductor layer P layer 2 having a conductivity type opposite to that of the first semiconductor layer N ⁺ layer 1 is formed. In the upper side surface region of the second semiconductor layer P layer 2, the third semiconductor layer N layer 5 a having the same conductivity type as the first semiconductor layer N ⁺ layer 1 is formed so as to surround the second semiconductor layer P layer 2. , 5b are formed. The third semiconductor layer N layers 5 a and 5 b are provided so as not to contact the upper surface of the second semiconductor layer P layer 2. The third semiconductor layer N layers 5a and 5b and the region of the second semiconductor layer P layer 2 in the vicinity of the third semiconductor layer N layers 5a and 5b are made of electromagnetic energy waves such as light, X-rays, and electron beams. A photodiode 112 that accumulates signal charges generated by irradiation is configured.
Further, on the surface of the photodiode 112, fourth semiconductor layers P ⁺ layers 6 a and 6 b having a conductivity type opposite to that of the first semiconductor layer N ⁺ layer 1 are formed so as to surround the outer periphery of the photodiode 112. Yes. The fourth semiconductor layer P ⁺ layers 6 a and 6 b are also provided so as not to contact the upper surface of the second semiconductor layer P layer 2.
Insulating films (SiO ₂ films) 3a and 3b are formed so as to cover the side surfaces of the second semiconductor layer P layer 2 and the outer surfaces of the fourth semiconductor layers P ⁺ layers 6a and 6b. Conductor electrodes 7a and 7b are formed on the side surfaces of the fourth semiconductor layer P ⁺ layers 6a and 6b via the insulating films 3a and 3b.
Gate conductor layers 4a and 4b are formed on the lower side surface of the second semiconductor layer P layer 2 via insulating films 3a and 3b. The gate conductor layers 4a and 4b are made of a light-shielding material such as a metal film or a sufficiently thick high-concentration impurity polycrystalline Si. The insulating films 3a and 3b and the gate conductor layers 4a and 4b constitute a MOS transistor 111 having the lower region of the second semiconductor layer P layer 2 as a channel.
On the upper surface of the second semiconductor layer P layer 2, a fifth semiconductor layer P ⁺ layer 8 having the same conductivity type as that of the second semiconductor layer P layer 2 is formed. The fifth semiconductor layer P ⁺ layer 8 is provided separately from the third semiconductor layer N layers 5a and 5b and the fourth semiconductor layer P ⁺ layers 6a and 6b. The fifth semiconductor layer P ⁺ layer 8 is connected to a wiring YL that is connected in a direction orthogonal to the first scanning direction.

A junction transistor is formed in which the second semiconductor layer P layer 2 and the fifth semiconductor layer P ⁺ layer 8 in the vicinity of the first semiconductor layer N ⁺ layer 1 are the drain and source, and the photodiode 112 is the gate. . Furthermore, the upper region of the second semiconductor layer P layer 2 where the photodiode 112 is formed, the third semiconductor layers N layers 5a and 5b, the fourth semiconductor layers P ⁺ layers 6a and 6b, The semiconductor layer P ⁺ layer 8 is formed in an island shape. In this embodiment, the wiring XL is a signal line and the wiring YL is a pixel selection line, but the wiring XL may be a pixel selection line and the wiring YL may be a signal line.

In such a structure of the pixel 10, since the conductor electrodes 7 a and 7 b on the photodiode 112 are formed on the side surfaces of the island-shaped semiconductor, the incident light 12 a is directly emitted from the fifth semiconductor layer P ⁺ layer 8. Irradiate the diode area. Thereby, in the solid-state imaging device 100 according to the present embodiment, the blue wavelength photosensitivity that occurs in the conventional solid-state imaging device as shown in FIG. 18A does not occur. Furthermore, the conductor electrodes 7a and 7b are formed of a light-shielding material such as a metal film or a sufficiently thick high-concentration impurity polycrystalline Si. Thereby, the incident light 12a incident on the photodiode region from the fifth semiconductor layer P ⁺ layer 8 is absorbed or reflected by the conductor electrodes 7a and 7b. Further, since the conductor electrodes 7a and 7b are formed so as to surround the outer periphery of the photodiode 112, the incident light 12a and the reflected light 12c reflected by the conductor electrodes 7a and 7b are prevented from leaking to adjacent pixels. Both the incident light 12a and the reflected light 12c can effectively contribute as signal charges. Thereby, in this solid-state imaging device 100, it is possible to suppress color mixing and a decrease in resolution.

In the solid-state imaging device shown in FIG. 1A, the second semiconductor layer is a P layer 2 made of a P-type conductive semiconductor. Instead of the P layer 2 made of this P-type conductive semiconductor, the second semiconductor layer may be an i layer 2i made of a substantially genuine semiconductor, as shown in FIG. 1B. An authentic semiconductor is manufactured so that impurities are not mixed therein, but in reality, it contains unavoidable trace amounts of impurities. The substantial genuine semiconductor layer constituting the i layer 2i may contain a small amount of acceptor or donor impurities as long as the function as the solid-state imaging device 100 is not hindered. According to such a configuration, the third semiconductor layer N layers 5a and 5b and the second semiconductor layer i layer 2i can form a diode. When a sufficient voltage is applied between the fifth semiconductor layer P ⁺ layer 8 and the signal line N ⁺ layer 1, holes in the fifth semiconductor layer P ⁺ layer 8 are 2 flows toward the signal line N ⁺ layer 1 due to the potential gradient generated in the semiconductor layer i layer 2i. In this way, the second semiconductor layer i layer 2i also functions as a channel of the junction transistor.

  FIG. 2 shows a circuit configuration example of the solid-state imaging device 100 according to the present embodiment. The solid-state imaging device 100 includes a plurality of pixels 10a to 10d arranged in a two-dimensional matrix, a vertical scanning circuit 201, a horizontal scanning circuit 202, a reset circuit 203, pixel selection lines YL1 and YL2, and signal lines. XL1 and XL2, a reset line RSL, signal line MOS transistors Tr1 and Tr2, and a correlated double sampling (CDS) output circuit 204 are mainly provided. In the present embodiment, the case where the pixels 10a to 10d are arranged in two rows and two columns will be described. However, the solid-state imaging device according to the present invention is not limited to this.

As shown in FIG. 2, a vertical scanning circuit 201 that inputs a pixel selection signal to each of the pixels 10a to 10d is connected to each of the pixels 10a to 10d via the pixel selection lines YL1 and YL2. The pixels 10a to 10d are also connected to the CDS output circuit 204 via signal lines XL1 and XL2 for each column. The gate electrodes of the signal line MOS transistors Tr1 and Tr2 disposed on the signal lines XL1 and XL2 are connected to a horizontal scanning circuit 202 that inputs a signal line selection signal to the gate electrodes. The signal lines XL1 and XL2 are also connected to the changeover switch sections SW1 and SW2. The gate conductor layers 4a and 4b of the MOS transistor for reset operation are connected to a reset circuit 203 that inputs a reset signal to the gate conductor layers 4a and 4b via a reset line RSL. Furthermore, the conductor electrodes 7a and 7b on the photodiodes 112 of the pixels 10a to 10d are connected to the external voltage _Vpg . By the operation of this circuit configuration, the signal current of each of the pixels 10a to 10d is sequentially read from the CDS output circuit 204.

Next, the basic operation of the solid-state imaging device 100 according to the present embodiment will be described with reference to FIGS. 1A to 3. In the potential distribution diagram of FIG. 3A, the accumulated signal charge is indicated by hatching for distinction.
The basic operation of this apparatus is composed of a signal charge accumulation operation, a signal read operation, and a reset operation.

In the signal charge accumulation operation, signal charges generated by irradiation with electromagnetic energy waves such as light, X-rays, or electron beams are accumulated in the photodiode 112.
In the signal read operation, the photodiode 112 is measured by measuring the current flowing between the fifth semiconductor layer P ⁺ layer 8 and the second semiconductor layer P layer 2 in the vicinity of the first semiconductor layer N ⁺ layer 1. Measure the signal charge accumulated in the. When the photodiode 112 is the gate of the amplifying junction transistor, the current flowing between the second semiconductor layer P layer 2 and the fifth semiconductor layer P ⁺ layer 8 in the vicinity of the first semiconductor layer N ⁺ layer 1 is It changes in accordance with the signal charge accumulated in the photodiode 112. Therefore, by measuring this current, the accumulated signal charge amount can be read out.
In the reset operation, an on-voltage is applied to the gate conductor layers 4a and 4b of the MOS transistor 111, and the signal charge accumulated in the photodiode 112 is caused to flow through the first semiconductor layer N ⁺ layer 1 to be removed.

FIG. 3A shows a potential distribution diagram along the line AA ′ in FIG. 1A during the signal charge accumulation operation period. [Phi _PR, the third semiconductor layer N layer 5a when the signal charges are not accumulated, which is the deepest potential in 5b.
In the signal charge accumulation operation period, the voltage V _pg of the conductor electrodes 7a and 7b is set so that the potential of the fourth semiconductor layer P ⁺ layers 6a and 6b becomes the ground potential or a potential close to the ground potential. For example, V _pg = 0V, voltage V _XLR = 0V of the signal line XL, and voltage V _YLR = 0V of the pixel selection line YL can be set. As a result, a potential distribution as shown in FIG. 3A is obtained, and signal charges are accumulated in the regions of the third semiconductor layer N layers 5a and 5b as shown by hatching.
Further, by setting the potential of the fourth semiconductor layer P ⁺ layers 6a and 6b to the ground potential or a potential close to the ground potential, many holes 30 are accumulated in the fourth semiconductor layer P ⁺ layers 6a and 6b. Is done. The holes 30 are supplied from the second semiconductor layer P layer 2 between the fourth semiconductor layer P ⁺ layers 6 a and 6 b and the fifth semiconductor layer P ⁺ layer 8. The electrons that are thermally generated from the trap order at the interface between the insulating films 3a and 3b and the fourth semiconductor layer P ⁺ layers 6a and 6b and cause dark current are generated by the fourth semiconductor layer P ⁺ layers 6a and 6b. Recombination with the holes 30 accumulated in the layer disappears. Thereby, generation of dark current can be prevented.

In order to suppress the dark current, for example, the fifth semiconductor layer ^{P +} layer 8 fourth semiconductor layer ^{P +} layer 6a, and connects the 6b, the fourth semiconductor layer ^{P +} layer 6a, 6b of the potential Can also be set to ground potential. However, in this case, since the fourth semiconductor layer P ⁺ layers 6a and 6b are not always fixed to the ground potential, they are affected by the potential of the fifth semiconductor layer P ⁺ layer 8 that varies in the imaging operation. It becomes easy. On the other hand, in the solid-state imaging device 100 according to the present embodiment, since the potentials of the fourth semiconductor layers P ⁺ layers 6a and 6b are set by the conductor electrodes 7a and 7b, the fifth semiconductor layers P ⁺ layers 8 ⁺ It is possible to prevent deterioration of image characteristics due to noise or the like that may be caused by potential fluctuation.

FIG. 3B is a pixel structure diagram when no signal charge is accumulated in the photodiode 112 in the signal readout operation period. In this case, the depletion layer 9 (9a, 9b) of the photodiode 112 is indicated by a broken line. Show. In this embodiment, when no signal charge is accumulated in the photodiode 112, the depletion layers 9a and 9b of the photodiode 112 are one of the upper regions of the second semiconductor layer P layer 2 where the photodiode 112 is formed. It is formed in the part. When signal charges are accumulated in the photodiode 112, the widths of the depletion layers 9a and 9b are reduced as shown in FIG. 3C, and the amplification junction transistor formed in the second semiconductor layer P layer 2 is reduced. The channel width increases. In the signal read operation period, a current corresponding to the channel width of the amplifying junction transistor, that is, the amount of accumulated signal charge flows through this channel.
Also in the signal read operation, the voltage of the conductor electrodes 7a and 7b can be set so that the potential of the fourth semiconductor layer P ⁺ layers 6a and 6b becomes almost the ground potential. Therefore, the fourth semiconductor layer P ⁺ Holes 30 can be accumulated on the surfaces of the layers 6a and 6b. Thereby, the influence on the photodiode potential due to the voltage fluctuation of the gate conductor layers 4a and 4b of the MOS transistor 111 is reduced, and the solid-state imaging device 100 according to the present embodiment can operate stably.

FIG. 3D shows a potential distribution diagram along the line BB ′ in FIG. 1A during the reset operation period. In the reset operation period, the potential V _{YLR of} the fifth semiconductor layer P ⁺ layer 8, the deepest potential Φ _pm in the third semiconductor layer N layers 5a and 5b when no signal charge is accumulated, the gate of the MOS transistor The channel potential Φ _rg of the MOS transistor 111 in the second semiconductor layer P layer 2 and the potential V _XLR of the first semiconductor layer N ⁺ layer 1 when the ON voltage is applied to the conductor layers 4a and 4b increase in this order. As described above, the voltage V _XLR of the signal line XL, the voltage V _YLR of the pixel selection line YL, and the voltage V _pg of the conductor electrodes 7a and 7b are set. Due to such a potential relationship, the signal charge accumulated in the photodiode 112 is removed in the first semiconductor layer N ⁺ layer 1 without remaining in the photodiode 112. As a result, afterimages are prevented from being generated, and furthermore, since no current flows through the channel of the reset MOS transistor 111 after the signal charge is transferred to the signal line XL, the occurrence of kTC noise is prevented. Further, the potential Φ _pm of the third semiconductor layer N layers 5a, 5b can be controlled by the voltage V _pg of the conductor electrodes 7a, 7b. Therefore, the potential Φ _pm of the third semiconductor layer N layers 5a and 5b can be set so that the potential V _XLR of the deepest first semiconductor layer N ⁺ layer 1 becomes shallow during the reset operation period. Thereby, the drive voltage of the solid-state imaging device 100 can be lowered.

(Second Embodiment)
FIG. 4 shows a cross-sectional view of two adjacent pixels 10e and 10f for explaining a solid-state imaging device 100a according to the second embodiment of the present invention. In addition, the same number is attached | subjected to the same part as the solid-state imaging device 100 which concerns on 1st Embodiment. For distinction, aa and ab are attached to the part included in the pixel 10e, and ba and bb are attached to the part included in the pixel 10f. The difference from the first embodiment is that the conductor electrodes 7aa, 7ab, 7ba, 7bb of the pixels 10e, 10f are connected in the vicinity of the gate conductor layers 4aa, 4ab, 4ba, 4bb. In the present embodiment, a pixel selection line is composed of the conductor electrodes 7aa, 7ab, 7ba, and 7bb and the wiring conductor layers 13a to 13c that connect the conductor electrodes 7aa, 7ab, 7ba, and 7bb of adjacent pixels. . In the present embodiment, the conductor electrodes 7aa, 7ab, 7ba, 7bb and the wiring conductor layers 13a to 13c are integrally formed.

Conductor electrodes 7aa, 7ab, 7ba, 7bb and wiring conductor layers 13a-13c are formed of a light-shielding material such as a metal film or sufficiently thick high-concentration impurity polycrystalline Si. Therefore, for example, light (incident light) 12a incident on the fifth semiconductor layer P ⁺ layer 8a of the pixel 10a is reflected by the conductor electrodes 7ab and 7ba and the wiring conductor layer 13b. The reflected light (reflected light) 12c generates an effective signal charge in the pixel 10e. Then, the leaked light 12b to the adjacent pixel 10f as indicated by the dotted arrow in FIG. 4 does not occur. Furthermore, the conductor electrodes 7aa, 7ab, 7ba, 7bb are connected in the vicinity of the gate conductor layers 4aa, 4ab, 4ba, 4bb, so that light incident on the pixel gaps 11a, 11b, 11c (light leaked to the pixel gaps). As shown in FIG. 4, 14 is reflected or absorbed by the wiring conductor layers 13a to 13c. Therefore, while the light 14 reaches the bottoms of the pixels 10e and 10f, the first of the pixels 10e and 10f from the optical path such as the gap between the gate electrodes 4aa, 4ab, 4ba and 4bb and the conductor electrodes 7aa, 7ab, 7ba and 7bb. It is possible to prevent the two semiconductor layers P layers 2a and 2b from entering. Thereby, it is possible to prevent the occurrence of color mixing and the reduction in resolution.

FIG. 4 shows a case where the conductor electrodes 7aa, 7ab, 7ba, 7bb connect the pixels 10e, 10f arranged in the direction shown in the drawing (the direction horizontal to the drawing). Alternatively, pixels arranged in the vertical direction may be connected. In this case as well, it is possible to prevent the occurrence of color mixing and the reduction in resolution.
Further, as shown in FIG. 2, the conductor electrodes 7a and 7b of all the pixels 10a to 10d in the photosensitive region of the solid-state imaging device 100a according to the present embodiment can be connected and connected to one external voltage _Vpg. it can. In this case, the conductor electrodes 7aa, 7ab, 7ba and 7bb and the wiring conductor layers 13a to 13c are formed so as to cover the entire pixel gaps 11a to 11c in the photosensitive region, so that the light incident on the pixel gaps 11a to 11c is second. It is possible to almost completely prevent the semiconductor layer P layers 2a and 2b from entering.

(Third embodiment)
FIG. 5 shows a cross-sectional view of two pixels 10e and 10f for explaining a solid-state imaging device 100b according to the third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same part as the solid-state imaging device 100a which concerns on 2nd Embodiment. In the solid-state imaging device 100a according to the second embodiment, the conductor electrodes 7aa, 7ab, 7ba, 7bb are connected in the vicinity of the gate conductor layers 4aa, 4ab, 4ba, 4bb. On the other hand, in the solid-state imaging device 100b according to the present embodiment, among the pixel gaps 11a to 11c of the pixels 10e and 10f, between the conductor electrodes 7aa, 7ab, 7ba, and 7bb and the gate conductor layers 4aa, 4ab, and 4ba. , 4bb, embedded conductor layers 15a to 15c and 16a to 16c are embedded in either one of them. FIG. 5 shows a case where the buried conductor layers 15a to 15c and 16a to 16c are buried in both. In this case, the wiring directions of the conductor electrodes 7aa, 7ab, 7ba, 7bb and the gate conductor layers 4aa, 4ab, 4ba, 4bb are the same. In the case where both the wirings are taken out in a direction orthogonal to each other, in FIG. 5, the buried conductor is only embedded in any one of the conductor electrodes 7aa, 7ab, 7ba, 7bb and the conductor gate layers 4aa, 4ab, 4ba, 4bb. Layers 15a-15c, 16a-16c are shown.

The buried conductor layers 15a to 15c and 16a to 16c are formed of a light-shielding material such as a metal film or a sufficiently thick high-concentration impurity polycrystalline Si. Therefore, for example, the light 12a incident on the fifth semiconductor layer P ⁺ layer 8a of the pixel 10e is reflected by the gate conductor layers 4ab and 4ba and the conductor electrodes 7ab and 7ba. The reflected light (reflected light) 12c generates an effective signal charge in the pixel 10e. Even if the incident light 12a and the reflected light 12c leak from the gaps between the gate conductor layers 4aa, 4ab, 4ba, 4bb and the conductor electrodes 7aa, 7ab, 7ba, 7bb, the leaked light remains in the embedded conductor layers 15a to 15b. Reflected or absorbed by 15c, 16a-16c. Therefore, it is possible to more effectively prevent the incident light 12a and the reflected light 12c from entering the second semiconductor layer P layers 2a and 2b of the adjacent pixels 10e and 10f. As a result, it is possible to more effectively prevent a reduction in resolution or color mixing.

(Fourth embodiment)
FIG. 6 shows a pixel structure for explaining a solid-state imaging device 100c according to the fourth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same part as the solid-state imaging device 100a which concerns on 2nd Embodiment. This figure shows the second semiconductor layer P layers 2a and 2b, the gate conductor layers 4ab and 4ba, the third semiconductor layer N layers 5ab and 5ba, the fourth semiconductor layer P ⁺ layers 6ab and 6ba, and the conductor electrodes 7ab and 7ba. FIG. 5 is a pixel cross-sectional view in which a region including the fifth semiconductor layer P ⁺ layers 8a and 8b is enlarged. Here, the conductive electrodes 7ab and 7ba are connected to each other through the wiring conductor layer 13b. The difference from the solid-state imaging device 100a according to the second embodiment is that the conductor electrodes 7ab and 7ba are at least the gate conductor layer 4ab via the insulating films 17ab and 17ba provided to cover the gate conductor layers 4ab and 4ba. , 4ba is overlapped with a part.

  In the solid-state imaging device 100c, since there is no gap between the gate conductor layers 4ab and 4ba and the conductor electrodes 7ab and 7ba, light does not leak from the gap. Therefore, it is possible to more effectively prevent light leakage to adjacent pixels.

  In the present embodiment, the case where the conductor electrodes 7ab and 7ba are connected to each other has been described. However, the conductor electrodes 7a and 7b are not connected to each other as in the solid-state imaging device 100 according to the first embodiment. In addition, by forming the conductor electrodes 7a and 7b so as to overlap the gate conductor layers 4a and 4b, light leakage to the adjacent pixels can be more effectively prevented in the same manner as described above.

  Next, a method for manufacturing the solid-state imaging device 100c according to the fourth embodiment will be described with reference to FIGS.

First, as shown in FIG. 7, a P-type silicon layer 301, a silicon nitride film 302, and a silicon oxide film 303 are deposited on a silicon (SiO ₂ ) substrate. Thereafter, as shown in FIG. 8, island-shaped semiconductor layers 304a and 304b are formed by etching or the like. Next, for example, the silicon oxide film 305 is formed by heating the substrate in an oxygen atmosphere and oxidizing the silicon surface. Next, polysilicon is deposited and etched back to form a sidewall-like polysilicon film 306 as shown in FIG.

Next, the first semiconductor layer N ⁺ layers 1a and 1b are formed by implanting phosphorus or the like into the P-type silicon layer 301 by an ion implantation method or the like. Thereafter, the polysilicon film 306 and the silicon oxide film 305 are peeled off. Next, a silicon oxide film layer 307 is formed, a gate oxide film 308 is formed by gate oxidation, and a polysilicon film 309 is deposited by a CVD method based on thermal decomposition of monosilane (SiH ₄ ) as shown in FIG. Next, a silicon oxide film (SiO ₂ film) 310 is formed on the region defining the gate conductor layers 4aa, 4ab, 4ba, 4bb on the polysilicon film 309. Next, the polysilicon film 309 other than the gate conductor layers 4aa, 4ab, 4ba, 4bb is removed by etching using the SiO ₂ film 310 or the resist film as a mask, and the gate conductor layers 4aa, 4ab are removed as shown in FIG. , 4ba, 4bb are formed. Thereafter, the SiO ₂ film 310 is removed, and the polysilicon of the gate conductor layers 4aa, 4ab, 4ba, 4bb is oxidized to form insulating films 17aa, 17ab, 17ba, 17bb.

Next, phosphorus or the like is implanted into the P-type silicon layer 301 by an ion implantation method or the like to form third semiconductor layer N layers 5aa, 5ab, 5ba, 5bb. Further, boron or the like is implanted into the third semiconductor layer N layers 5aa, 5ab, 5ba, 5bb by ion implantation or the like, and as shown in FIG. 12, the fourth semiconductor layers P ⁺ layers 6aa, 6ab, 6ba, 6bb are formed. Form. Thereafter, the silicon nitride film 302 is peeled off. Next, silicon oxide or silicon nitride is deposited, and planarized and etched back to form a silicon oxide film 311a. The exposed semiconductor layer is oxidized to form a silicon oxide film 312, and boron or the like is implanted to form fifth semiconductor layers P ⁺ layers 8a and 8b as shown in FIG. Thereafter, the silicon oxide film 312 is peeled off, and the silicon oxide film 311a is removed by etching to a depth where the conductor electrodes 7ab and 7ba and the gate conductor layers 4ab and 4ba overlap as shown in FIG. 311b is formed. Next, the polysilicon of the gate conductor layers 4aa, 4ab, 4ba, 4bb is oxidized. Thereafter, a metal film is formed on the entire surface of the substrate by vacuum vapor deposition, sputtering, or the like, and is patterned to provide conductor electrodes 7aa, 7ab, 7ba, 7bb and conductor electrodes 7aa, 7ab, 7ba, Wiring conductor layers 13a to 13c that connect 7bb to each other can be formed.
By such a process, the pixel structure of the solid-state imaging device 100c according to the fourth embodiment is obtained.

(Fifth embodiment)
A solid-state imaging device 100d according to a fifth embodiment of the present invention will be described with reference to FIG. This figure is an enlarged view of a part of the pixel 10 shown in FIG.
In the direction from the fifth semiconductor layer ^{P +} layer 8 in the first semiconductor layer ^{N +} layer 1, conductive electrodes 7a, 7b of the electrode upper end 20a, 20b, the fourth semiconductor layer ^{P +} layer 6a, 6b of the ^{P +} The layer upper ends 19a and 19b and the third semiconductor layer N layers 5a and 5b are formed away from the fifth semiconductor layer P ⁺ layer 8 in the order of the N layer upper ends 18a and 18b.

Surface regions 21a, 21b of the second semiconductor layer P layer 2 between the electrode upper ends 20a, 20b of the conductor electrodes 7a, 7b and the P ⁺ layer upper ends 19a, 19b of the fourth semiconductor layer P ⁺ layers 6a, 6b. Is controlled by the voltage applied to the conductor electrodes 7a and 7b. As a result, the potentials of the fourth semiconductor layer P ⁺ layers 6a and 6b are not easily affected by the voltage of the fifth semiconductor layer P ⁺ layer 8 that changes in voltage during the imaging operation period. Therefore, the potential of the fourth semiconductor layer P ⁺ layers 6a and 6b can be set stably by the voltage applied to the conductor electrodes 7a and 7b.

Further, the N semiconductor layer N layers 5a and 5b have N layer upper ends 18a and 18b that are higher than the P ⁺ layer upper ends 19a and 19b of the fourth semiconductor layer P ⁺ layers 6a and 6b. Therefore, the area where the fourth semiconductor layer P ⁺ layers 6a and 6b are in contact with the second semiconductor layer P layer 2 is increased. Therefore, the holes 30 are stably supplied from the second semiconductor layer P layer 2 to the fourth semiconductor layers P ⁺ layers 6a and 6b. In this embodiment, since the signal charge accumulated in the photodiode is an electron, a hole having the opposite polarity is supplied. Thereby, generation | occurrence | production of dark current can be prevented stably.

Further, as shown in FIG. 16B, the P ⁺ layer upper ends 19a and 19b of the fourth semiconductor layers P ⁺ layers 6a and 6b, and the N layer upper ends 18a and 18b of the third semiconductor layers N layers 5a and 5b, The positions of may match. Even in such a configuration, since holes are supplied from the second semiconductor layer P layer 2 to the fourth semiconductor layers P ⁺ layers 6a and 6b, generation of dark current can be prevented.

(Sixth embodiment)
FIGS. 17A to 17C show the structure of the pixel 10 for explaining a solid-state imaging device 100e according to the sixth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same part as the solid-state imaging device 100 which concerns on 1st Embodiment.

As shown in FIG. 17A, the depletion layer 9c of the photodiode 112 is the photodiode of the second semiconductor layer P layer 2 when no signal charge is accumulated in the photodiode 112 during the signal read operation period. Occupies the upper region where 112 is formed. The state of the depletion layer 9c of the photodiode 112 is adjusted by appropriately adjusting the layer thickness, impurity concentration, etc. of the third semiconductor layer N layers 5a and 5b and the second semiconductor layer P layer 2, and further on the photodiode 112. It can be formed by appropriately setting the voltage applied to the conductor electrodes 7a and 7b.
When the depletion layer 9c occupies the upper region of the second semiconductor layer P layer 2, the vicinity of the fifth semiconductor layer P ⁺ layer 8 and the first semiconductor layer N ⁺ layer 1 of the amplifying junction transistor A channel for passing a current is not formed between the second semiconductor layer P layer 2 and the second semiconductor layer P.

  When the signal charge is accumulated in the photodiode 112, the width of the depletion layers 9a and 9b of the photodiode 112 decreases as shown in FIG. 17B during the signal read operation period, and the second semiconductor layer P layer 2 The channel of the amplifying junction transistor is formed, and a current corresponding to the accumulated signal charge flows through this channel.

FIG. 17C is a pixel structure diagram in which the depletion layer 9c is written when no signal charge is accumulated in the photodiode 112 during the signal charge accumulation operation period. In the signal charge accumulation operation period, normally, for example, the voltage V _{XLR of the} first semiconductor layer N ⁺ layer 1 = 0 V, the voltage V _{YLR of} the fifth semiconductor layer P ⁺ layer 8 = 0 V, and the external voltage V _pg = 0 V Set.

As shown in FIG. 17C, in the signal charge accumulation operation period, when no signal charge is accumulated, the depletion layer 9c is formed so as to occupy the upper region of the second semiconductor layer P layer 2. If the depletion layer 9c does not occupy the second semiconductor layer P layer 2, the signal charge generated in the second semiconductor layer P layer 2 without the depletion layer 9c diffuses to form a fifth semiconductor layer P ⁺ layer. 8 or the first semiconductor layer N ⁺ layer 1 is reached. As a result, the signal charge generated in the second semiconductor layer P layer 2 becomes invalid as a signal. On the other hand, since the depletion layer 9 c occupies the upper region of the second semiconductor layer P layer 2, signal charges are effectively accumulated in the photodiode 112. In particular, in a state where the amount of irradiation light is small, the generated signal charge can be effectively captured and accumulated in the photodiode 112.

Further, when the signal charge is not accumulated during the signal charge accumulation operation period, the channel of the amplifying junction transistor is pinched off. For example, due to noise jumping into the pixel selection line, the fifth semiconductor layer P ⁺ Even if holes are to be injected from the layer 8 into the second semiconductor layer P layer 2, the depletion layer 9c prevents such hole injection.

  Thus, in the signal read operation period and the signal charge accumulation operation period, the depletion layer 9c of the photodiode 112 occupies the upper region of the second semiconductor layer P layer 2 when no signal charge is accumulated in the photodiode 112. By being formed as described above, it is possible to provide a solid-state imaging device having good low illuminance characteristics.

In the first to sixth embodiments, the case where the first semiconductor layer is an N ⁺ layer has been described. However, the first semiconductor layer is a P ⁺ layer, and the second semiconductor layer is similarly formed. The same applies to a solid-state imaging device in which the polarity of the semiconductor layer is reversed, with the N layer being the N layer, the third semiconductor layer being the P layer, the fourth semiconductor layer on the photodiode surface being the N ⁺ layer, the fifth semiconductor layer being the N ⁺ layer The effect of this can be obtained. In that case, since holes are accumulated in the photodiode as signal charges, the voltage V _{pg of the} conductor electrode is set so as to accumulate electrons on the surface of the fourth semiconductor layer.

In the first, second, and fourth to sixth embodiments, the wiring direction connected to the first semiconductor layer N ⁺ layer 1 and the wiring direction connected to the fifth semiconductor layer P ⁺ layer 8 are arranged. However, when the first semiconductor layer N ⁺ layer 1 is used exclusively for the signal charge removal drain in the reset operation, it is not necessary to be orthogonal.

  In the first to sixth embodiments, the description has been given using one pixel or two pixels. However, a plurality of pixels may be arranged one-dimensionally or two-dimensionally.

  In addition, the pixel arrangement in the first to sixth embodiments may be linear, zigzag or the like in the one-dimensional pixel arrangement, but may be a linear lattice or honeycomb in the two-dimensional pixel arrangement, but is not limited thereto. It is not a thing.

In the solid-state imaging device according to the present invention, at least the diode, the fourth semiconductor layer P ⁺ layers 6a and 6b, and the fifth semiconductor layer P ⁺ layer 8 are formed in an island shape. The island-shaped semiconductor may be cylindrical, hexagonal, or other shapes.

  In the second to fourth embodiments, the conductor electrodes 7aa, 7ab, 7ba, 7bb, the conductor layers 13a to 13c, and the buried conductor layers 15a to 15c and 16 to 16c are distinguished as materials. Needless to say, the same effect can be obtained.

  In the first to sixth embodiments, the solid-state imaging device that generates signal charges in the pixels by light irradiation has been described. However, electromagnetic waves such as visible light, ultraviolet light, infrared light, X-rays, radiation, and electron beams are used. Needless to say, the present invention is also applied to a pixel in which signal charges are generated by irradiation of energy waves.

  In the first to sixth embodiments, the MOS transistor uses the second semiconductor layer P layer 2 as a channel. For example, an impurity is introduced into the region of the second semiconductor layer P layer 2 by ion implantation or the like. The channel may be formed by implanting.

  Further, the first semiconductor layer 1 may be formed continuously between the pixels on the substrate, or may be formed for each pixel. When the first semiconductor layer 1 is formed for each pixel, the first semiconductor layers 1 can be connected to each other by another metal wiring. Further, the first semiconductor layer 1 and the second semiconductor layer 2 do not need to be in contact (bonded) over the entire surface, and may be in contact with each other. Further, a part of the first semiconductor layer 1 may be replaced with another semiconductor layer.

  In the first to sixth embodiments, the case where the gate conductor layers 4a and 4b and the conductor electrodes 7a and 7b of the MOS transistor are made of a single material has been described. It may be composed of a plurality of layers such as a crystalline silicon layer.

In the solid-state imaging devices according to the first to sixth embodiments, the voltage V _pg applied to the conductor electrodes 7a and 7b is substantially over the entire period of the signal charge accumulation operation period, the signal read operation period, and the reset operation period. The voltage V _pg may be varied as long as holes can be supplied from the second semiconductor layer P layer 2 and stored in the fourth semiconductor layer P ⁺ layers 6a and 6b.

In the first to sixth embodiments, the P of the fourth semiconductor layer P ⁺ layers 6 a and 6 b extends from the fifth semiconductor layer P ⁺ layer 8 toward the first semiconductor layer N layer 1. ^{When the +} layer upper ends 19a and 19b are aligned with the electrode upper ends 20a and 20b of the conductor electrodes 7a and 7b, and the P ⁺ layer upper ends 19a and 19b are farther from the fifth semiconductor layer 8 than the electrode upper ends 20a and 20b. Explained the case. However, if the fourth semiconductor layer P ⁺ layers 6 a and 6 b and the fifth semiconductor layer P ⁺ layer 8 are separated from each other by the second semiconductor layer P layer 2, the second semiconductor layer P layer 2 is separated from the second semiconductor layer P layer 2. Since holes are supplied to the fourth semiconductor layer P ⁺ layers 6a and 6b, the electrode upper ends 20a and 20b may be further away from the fifth semiconductor layer P ⁺ layer 8 than the P ⁺ layer upper ends 19a and 19b.

1, 1a, 1b 1st semiconductor layer N ⁺ layer 2, 2a, 2b 2nd semiconductor layer P layer 3a, 3b, 3aa, 3ab, 3ba, 3bb, 63a, 63b Insulating film (SiO ₂ film)
4a, 4b, 4aa, 4ab, 4ba, 4bb, 64a, 64b Gate conductor layers 5a, 5b, 5aa, 5ab, 5ba, 5bb Third semiconductor layer N layers 6a, 6b, 6aa, 6ab, 6ba, 6bb Semiconductor layer P ⁺ layer 7a, 7b, 7aa, 7ab, 7ba, 7bb Conductor electrode 8, 8a, 8b Fifth semiconductor layer P ⁺ layer 9, 9a-9c Depletion layer 10, 10a-10f Pixel 11a-11c Pixel gap 12a 69a Incident light (light)
12b, 69b Leaked light (light)
12c Reflected light 13a to 13c Wiring conductor layer 14 Light leaked to pixel gaps 15a to 15c, 16a to 16c Embedded conductor layers 17aa, 17ab, 17ba, 17bb Insulating films 18a, 18b N layer upper end 19a, 19b P ⁺ layer upper end 20a, 20b Electrode upper end 21a, 21b Surface region 30 of second semiconductor layer P layer 2 Hole 50 Signal charge 51 Potential well 52 of signal charge storage part Irradiation light (light)
53 P-type semiconductor substrates 54a and 54b Silicon oxide film (SiO ₂ film)
55 Transfer gate electrode lower channel 56 Amplification MOS transistor 57 Select gate MOS transistor 58 Reset MOS transistor 59 Signal line 60 Island-like semiconductor (pixel)
61 Signal line N ⁺ layer 62 P type semiconductor layers 65a and 65b N type semiconductor layer 66 P ⁺ layers 67a and 67b Pixel selection lines 68a and 68b Insulating layers 100 and 100a to 100e Solid-state imaging device 111 MOS transistor 112 Photo diode 201 Vertical scanning Circuit 202 Horizontal scanning circuit 203 Reset circuit 204 Correlated double sampling (CDS) output circuit 301 P-type silicon layer 302 Silicon nitride film 303, 310, 311a, 311b, 312 Silicon oxide film (SiO ₂ film)
304a, 304b Insular semiconductor layer 305 Silicon oxide film 306, 309 Polysilicon film 307 Silicon oxide film layer 308 Gate oxide film XL1, XL2 Signal line YL1, YL2 Pixel selection line RSL Reset line Tr1, Tr2 Signal line MOS transistors SW1, SW2 Changeover switch

Claims (9)

A solid-state imaging device having one or a plurality of pixels,
Each of the pixels
A first semiconductor layer formed on a substrate;
A second semiconductor layer formed on the first semiconductor layer;
A fourth semiconductor layer formed on the upper side surface region of the second semiconductor layer and away from the upper surface of the second semiconductor layer;
A third semiconductor layer formed between the inner side surface of the fourth semiconductor layer and the second semiconductor layer, away from the upper surface of the second semiconductor layer;
A first insulating film formed on at least a side surface of the second semiconductor layer and an outer surface of the fourth semiconductor layer;
A gate conductor layer formed through the first insulating film on a lower side surface of the side surface of the second semiconductor layer where the third semiconductor layer is not formed;
A conductor electrode formed on the outer surface of the fourth semiconductor layer via the first insulating film;
A fifth semiconductor layer formed on an upper surface of the second semiconductor layer so as not to contact the third semiconductor layer and the fourth semiconductor layer;
Have
At least the third semiconductor layer, an upper region of the second semiconductor layer where the third semiconductor layer is formed, the fourth semiconductor layer, and the fifth semiconductor layer are island-shaped Formed in shape,
The third semiconductor layer and the second semiconductor layer in the vicinity of the third semiconductor layer form a diode,
A junction transistor is formed in which one of the second semiconductor layer and the fifth semiconductor layer in the vicinity of the first semiconductor layer is a drain, the other is a source, and the diode is a gate.
A field effect transistor having the first semiconductor layer as a drain, the third semiconductor layer as a source, and the gate conductor layer as a gate is formed;
Means for storing in the diode signal charges generated in the pixels by irradiation of electromagnetic energy waves;
Signal readout means for measuring the amount of signal charge by measuring the current flowing through the junction transistor, which varies according to the amount of signal charge accumulated in the diode;
By applying a turn-on voltage to the gate conductor layer of the field effect transistor to form a channel in a region including the second semiconductor layer between the first semiconductor layer and the third semiconductor layer; Reset means for removing signal charges accumulated in the diode in the first semiconductor layer;
With
Applying a voltage to the conductor electrode so as to cause the fourth semiconductor layer to accumulate a charge having a polarity opposite to that of the signal charge accumulated in the diode;
A solid-state imaging device. The second semiconductor layer is of a conductivity type opposite to or substantially true of the first semiconductor layer;
The third semiconductor layer has the same conductivity type as the first semiconductor layer;
The fourth semiconductor layer has a conductivity type opposite to that of the first semiconductor layer;
The fifth semiconductor layer has a conductivity type opposite to that of the first semiconductor layer;
The solid-state imaging device according to claim 1.   The wiring conductor layer which connects the said conductor electrodes of the said adjacent pixel in the vicinity of the said gate conductor layer, and is comprised from the light-shielding electrically-conductive material, It is further characterized by the above-mentioned. The solid-state imaging device described.   The solid-state imaging device according to claim 3, wherein the wiring conductor layer connects all the conductor electrodes of the plurality of pixels. A second insulating film formed to cover the gate conductor layer;
5. The device according to claim 1, wherein the conductor electrode is formed so as to overlap at least a part of the gate conductor layer with the second insulating film interposed therebetween. Solid-state imaging device.   Light-shielding conductivity embedded between the conductor electrodes of adjacent pixels, between the gate conductor layers of adjacent pixels, or between the conductor electrodes of adjacent pixels and between the gate conductor layers of the adjacent pixels The solid-state imaging device according to claim 1, further comprising an embedded conductor layer made of a material. The third semiconductor layer, the fourth semiconductor layer, and the conductor electrode are arranged such that, in the direction from the fifth semiconductor layer toward the first semiconductor layer, the upper end of the third semiconductor layer and the fourth semiconductor layer The upper end of the semiconductor layer and the upper end of the conductor electrode are substantially aligned with each other, or the third semiconductor layer, the fourth semiconductor layer, and the conductor electrode are the fifth semiconductor layer. In the direction from the first semiconductor layer to the first semiconductor layer, the upper end of the third semiconductor layer is farther from the fifth semiconductor layer than the upper end of the conductor electrode, and the upper end of the fourth semiconductor layer is the third semiconductor layer. It is formed so as to be located between the upper end of the semiconductor layer and the upper end of the conductor electrode,
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided.   The reset means applies a voltage to the conductor electrode, and the potential of the fifth semiconductor layer, the deepest potential in the third semiconductor layer when no signal charge is accumulated in the diode, the field effect The potential relationship is set so that the channel potential of the second semiconductor layer and the potential of the first semiconductor layer become deeper in the order of when a turn-on voltage is applied to the gate conductor layer of the transistor. The solid-state imaging device according to any one of claims 1 to 7.   The signal readout means applies a voltage to the conductor electrode so that the depletion layer of the diode occupies the entire upper region of the second semiconductor layer when no signal charge is accumulated in the diode; The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided.

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