JP2013162077A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent characteristic deterioration of a photodiode.SOLUTION: In a solid-state imaging device, a photodiode 1 includes a first semiconductor layer 10 of a first conductivity type buried in a groove RX in a semiconductor substrate 150, and a first impurity region 151 of the first conductivity type provided in the semiconductor substrate 150 along the first semiconductor layer 10.

Description

  Embodiments described herein relate generally to a solid-state imaging device.

  Solid-state imaging devices such as CCD image sensors and CMOS image sensors are used in various applications such as digital still cameras, video cameras, and surveillance cameras.

  In order to improve the resolution of an image to be formed and reduce the chip cost, miniaturization of elements forming an image sensor has been promoted.

JP 2000-294757 A

  A technology for miniaturization of elements included in an image sensor is proposed.

  The solid-state imaging device of the embodiment includes a semiconductor substrate including a pixel array, a first semiconductor layer of a first conductivity type provided in the pixel array and embedded in a groove in the semiconductor substrate, and the first A plurality of photodiodes each including a first impurity region of the first conductivity type provided in the semiconductor substrate along one semiconductor layer.

The top view which shows an example of the layout of the chip | tip of a solid-state imaging device. Sectional drawing which shows the structural example of a solid-state imaging device. The equivalent circuit diagram which shows an example of the circuit structure of the pixel array of a solid-state imaging device. The top view which shows an example of the layout of the pixel array of a solid-state imaging device. FIG. 3 is a cross-sectional view illustrating a structure example of a photoelectric conversion element included in the solid-state imaging device according to the first embodiment. Sectional process drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 1st Embodiment. The figure for demonstrating 1 process of the manufacturing method of the solid-state imaging device of 1st Embodiment. The figure for demonstrating 1 process of the manufacturing method of the solid-state imaging device of 1st Embodiment. 1 is a cross-sectional view illustrating a configuration example of a solid-state imaging device according to a first embodiment. Sectional drawing which shows an example of the structure of the solid-state imaging device of 2nd Embodiment. Sectional drawing which shows an example of the structure of the solid-state imaging device of 3rd Embodiment. The figure for demonstrating 1 process of the manufacturing method of the solid-state imaging device of 3rd Embodiment. The figure for demonstrating one process of the manufacturing process of the solid-state imaging device of 3rd Embodiment. The figure for demonstrating the modification of the solid-state imaging device of embodiment. The figure for demonstrating the modification of the solid-state imaging device of embodiment. The figure for demonstrating the modification of the solid-state imaging device of embodiment.

[Embodiment]
Hereinafter, this embodiment will be described in detail with reference to the drawings. In the following description, elements having the same function and configuration are denoted by substantially the same reference numerals, and overlapping description will be given as necessary.

(1) First embodiment
With reference to FIG. 1 thru | or FIG. 9, the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment, and a solid-state imaging device is demonstrated.

(A) Overall configuration
The solid-state imaging device according to the first embodiment will be described with reference to FIGS. 1 to 5.

  The overall configuration of the solid-state imaging device will be described with reference to FIGS.

  FIG. 1 is a schematic diagram illustrating a chip layout example of a solid-state imaging device (hereinafter referred to as an image sensor). FIG. 2 is a cross-sectional view schematically showing the structure of the image sensor 100.

  As shown in FIG. 1, in the image sensor of this embodiment, a region (referred to as a peripheral circuit region) 121 in which a pixel array 120 and a circuit for controlling the pixel array 120 are formed includes one semiconductor substrate (chip) 110. Is provided inside.

  The pixel array 120 includes a plurality of unit cells UC. Each unit cell UC includes a photoelectric conversion element (hereinafter also referred to as a pixel) for converting incident light from the outside into an electric signal. One unit cell UC includes at least one pixel.

  The unit cell adjacent to each other and the formation region of the pixel included therein are surrounded by the element isolation region 9.

  As shown in FIGS. 1 and 2, in the image sensor 100 of the present embodiment, the pixel array 120 and the peripheral circuit region 121 are provided in one semiconductor substrate 150. The semiconductor substrate 150 is an element formation substrate on which elements are formed. The semiconductor substrate 150 is, for example, a p-type silicon single crystal substrate. The semiconductor substrate 150 is not limited to a silicon single crystal substrate, and may be, for example, a silicon layer (epitaxial layer) formed on an insulator of an SOI (Silicon-On-Insulator) substrate.

  As shown in FIGS. 1 and 2, in the pixel array 120, unit cell UC formation regions (hereinafter also referred to as unit cell formation regions) UA including at least one photoelectric conversion element 1 are two-dimensionally arranged. Has been. The unit cell formation area UA is a semiconductor area provided in the semiconductor substrate 150. The unit cell formation area UA includes at least one photodiode formation area (hereinafter referred to as a photodiode formation area). The formation region of the photodiode 1 is provided in the unit cell formation region UA. The structure of the unit cell formation area UA and the unit cell will be described later.

  In the present embodiment, the photodiode 1 as one photoelectric conversion element corresponds to one pixel. The photodiode 1 photoelectrically converts incident light (light from a subject) corresponding to an image into an electric signal (charge, voltage) corresponding to the amount of incident light. The photodiode 1 can accumulate charges generated in the photodiode 1 by photoelectric conversion. For example, a CMOS sensor or a CCD sensor is formed using the photodiode 1.

  As shown in FIG. 2, the photodiode 1 is formed from at least one impurity semiconductor layer formed in the semiconductor substrate 150. The structure of the photodiode 1 included in the image sensor of this embodiment will be described later.

  An impurity semiconductor layer as a floating diffusion (floating diffusion layer, signal detection unit) 6 is provided in the semiconductor substrate 150.

  A field effect transistor as the transfer gate 2 is provided on the semiconductor substrate 150 between the photodiode 1 and the floating diffusion 6. The gate electrode 21 of the transfer gate 2 is provided on the semiconductor substrate 150 via the gate insulating film 22.

  The element isolation region 9 is provided in the semiconductor substrate 150 so as to surround the adjacent unit cell formation region UA and the adjacent photodiode formation region. The element isolation region 9 electrically isolates the unit cell UC and the photodiode 1 adjacent to each other. An element isolation layer 90 is provided in the element isolation region 9 in the pixel array 120. In the pixel array 120, the element isolation layer 90 is formed by, for example, an impurity semiconductor layer (referred to as an element isolation impurity layer) or an insulating film having an STI structure (referred to as an element isolation insulating film).

  The peripheral circuit region 121 is provided in the semiconductor substrate 150 so as to be adjacent to the pixel array 120. In the peripheral circuit area 121, peripheral circuits such as an analog circuit and a logic circuit are provided. More specifically, a circuit for controlling the operation of the pixel array 120 and a circuit for processing a signal from the pixel array 120 such as an AD (Analog-digital) conversion circuit are provided in the peripheral circuit region 121. .

  The peripheral circuit region 121 is electrically isolated from the pixel array 120 by, for example, an element isolation region. In the element isolation region for partitioning the peripheral circuit region 121, for example, an element isolation insulating film 91 having an STI structure is embedded.

  The circuit in the peripheral circuit region 121 is formed by a plurality of elements such as the field effect transistor 7, a resistance element, and a capacitance element. In FIG. 2, only the field effect transistor 7 is shown for simplification of illustration. Although only one field effect transistor is illustrated in FIG. 2, a plurality of transistors are provided on the semiconductor substrate 150.

  For example, in the peripheral circuit region 121, the field effect transistor (for example, MOS transistor) 7 is provided in the well region 159 in the semiconductor substrate 150. Two diffusion layers (impurity semiconductor regions) 73 are provided in the well region 159. These two diffusion layers 73 function as the source / drain of the transistor 7. A gate electrode 71 is provided on the surface of the well region (channel region) between the two diffusion layers 73 via the gate insulating film 72. As a result, the field effect transistor 7 is formed on the well region 159.

  Whether the field effect transistor 7 is a p-channel type or an n-channel type depends on the conductivity type of the well region 15 in which the transistor 7 is provided and the conductivity type of the diffusion layer 73 serving as the source / drain. The field effect transistor 7 may be an enhancement type or a depletion type depending on the circuit including the field effect transistor 7.

  A plurality of interlayer insulating films 92 are stacked on the semiconductor substrate 150 so as to cover the gate electrodes 21 and 71 of the transistors 2 and 7 and the upper surface of the photodiode 3. For example, silicon oxide is used for the interlayer insulating film 92.

  The image sensor of this embodiment uses a multilayer wiring technique. That is, a plurality of wirings 80 are provided in the laminated interlayer insulating film 92 according to each wiring level (height with respect to the substrate surface). Each wiring 80 is electrically connected to another wiring located at the wiring level immediately above by plugs 81, CP 1, CP 2 embedded in the interlayer insulating film 92. Note that a dummy layer that is not connected to a light shielding film, an element, or a circuit is provided in the interlayer insulating film 92. The light shielding film and the dummy layer are formed substantially simultaneously with the wiring 80.

  The gate electrodes 21 and 71 of the transistors 2 and 7, the source / drain 73, and the terminal of the element formed on the semiconductor substrate 150 are the first (lowermost layer) counted from the semiconductor substrate 150 side through the contact plug CP1. It is connected to the wiring 80 located at the wiring level. The plurality of wirings 80 connect a plurality of elements provided on the semiconductor substrate 150. Thereby, a plurality of circuits are formed.

  Here, in this embodiment, the surface on which the element is formed, more specifically, the surface (first surface) of the semiconductor substrate 150 on which the gate electrodes 21 and 71 of the transistors 2 and 7 are provided is the semiconductor substrate. It is called 150 surface. On the surface of the semiconductor substrate 150, an interlayer insulating film 92 formed by a multilayer wiring technique is provided. A surface (second surface) facing the front surface of the semiconductor substrate 150 is referred to as a back surface.

  In the present embodiment, as shown in FIG. 2, a color filter layer CF is provided on the back surface side of the semiconductor substrate 150 via, for example, a protective layer (not shown) or an adhesive layer (not shown). The color filter layer CF is provided above the pixel array 120 on the back side of the semiconductor substrate 150.

  For example, in the present embodiment, a single plate type image sensor 100 is formed. The single-plate pixel array 120 acquires a plurality of pieces of color information with the single pixel array 120. A color filter of at least one of red, blue and green is attached so as to correspond to each pixel.

  In this case, the color filter layer CF includes, for example, a filter that transmits light having a wavelength corresponding to red (R), a filter that transmits light having a wavelength corresponding to green (G), and a wavelength corresponding to blue (B). Filters that transmit light are included, and these filters are arranged in a predetermined pattern. The color filter layer CF is formed so that one color filter corresponds to one photodiode. Note that the color filter layer CF may include a white (W) filter that transmits yellow and all wavelengths of visible light in addition to red, green, and blue. The color filter 70 has, for example, an array pattern such as a Bayer array or a WRGB array.

  The microlens array ML is attached on the color filter layer CF via a protective layer (not shown) and an adhesive layer (not shown).

  The microlens array ML is provided at a position overlapping the pixel array 120 via the color filter layer CF. The microlens array ML is formed by two-dimensionally arranging microlenses corresponding to one pixel (photodiode 3). The microlens array ML collects incident light (light from the subject). The adhesive layer / protective layer for attaching the microlens array ML and the color filter layer CF is transmissive to incident light.

As shown in FIG. 2, the surface on which the microlens array ML is attached is the back surface of the semiconductor substrate 150. Thus, in the image sensor of the present embodiment, the microlens array ML and the color filter layer CF are opposite to the surface (front surface) on which the gate electrode 71 and the interlayer insulating film 92 of the transistor are provided (back surface). ). The semiconductor substrate 150 on which the element is formed is sandwiched between the interlayer insulating film 92 and the microlens array ML. Incident light corresponding to the image (light from the subject) is applied to the pixel array 120 from the back side of the semiconductor substrate 150 via the microlens array ML and the color filter CF.
As in the image sensor of this embodiment, an image sensor having a structure in which light from a subject is irradiated onto pixels from the back surface facing the surface of the substrate 150 on which elements are formed is called a back-illuminated image sensor.

  For example, through holes (openings) are formed in the semiconductor substrate 150 so as to penetrate the semiconductor substrate 150 from the front surface side to the back surface side of the semiconductor substrate 150 by TSV (Through Silicon Via) technology. A via (through via) 88 is embedded in the through hole. An insulating layer 98 is provided on the side surface of the through hole, and the through via 88 is electrically separated from the semiconductor substrate 150 by the insulating layer 98. The through via 88 is connected to the wiring 80 in the interlayer insulating film 92 via the contact plug CP2. The through via 88 is connected to a pad (electrode) 89 provided on the back surface of the semiconductor substrate 150. The pad 89 is provided on the through via 88 and the insulating layer 99. The pad 89 is electrically isolated from the semiconductor substrate 150 by the insulating layer 99. As described above, in the backside illumination type image sensor, the pad 89 may be provided on the backside of the semiconductor substrate 150.

  A support substrate 119 is provided on the interlayer insulating film 92 on the surface side of the semiconductor substrate 150. The support substrate 119 is laminated on the insulating layer 92 via, for example, a protective layer (not shown) and an adhesive layer (not shown). For example, a silicon substrate or an insulating substrate is used as the support substrate 119. A wiring (hereinafter referred to as a rewiring) 82 formed by a rewiring technique may be provided between the support substrate 119 and the uppermost interlayer insulating film 92. The rewiring 82 is covered with an insulating layer (for example, a resin layer) 96. The rewiring 82 is connected to the wiring 80 in the interlayer insulating film 92 through an electrode (via plug) 83. For example, the rewiring 82 is connected to pads (illustrated) on the support substrate 119 on the front surface side of the semiconductor substrate 150. In addition, a pad may be formed by the rewiring 82.

  A signal is input / output between the image sensor 100 and an external device or a voltage is supplied to the image sensor 100 by the rewiring (pad) 82 on the front surface side of the semiconductor substrate 150 and the pad 89 on the back surface side of the semiconductor substrate 150. Or

FIG. 3 is a diagram illustrating a circuit configuration example of the pixel array 120 and circuits in the vicinity thereof.
The plurality of unit cells UC are arranged in the pixel array 120. Each unit cell UC is provided at the intersection of the read signal lines RD1, RD2 and the vertical signal line VSL.

  The unit cell UC shown in FIG. 3 has a two-pixel one-cell structure in which one unit cell UC includes two pixels 1A and 1B. In the unit cell UC having a two-pixel one-cell structure, part of the elements in the unit cell UC and a signal detection unit (floating diffusion) are shared by the two pixels (photodiodes) 1A and 1B.

  The unit cell UC having a two-pixel / one-cell structure includes, for example, five field effect transistors 2A and 2B as control elements (hereinafter also referred to as cell control elements) for controlling the operations of the unit cell UC and the two pixels 1A and 1B. , 3, 4 and 5 are included. Each field effect transistor 2A, 2B, 3, 4, and 5 is, for example, an n-channel MOS transistor. The five field effect transistors included in the unit cell UC are referred to as transfer gates 2A and 2B, an amplifier transistor 5, an address transistor 4 and a reset transistor 3, respectively.

  A unit cell UC having a two-pixel one-cell structure includes two photodiodes 1A and 1B as two pixels. The unit cell UC having a two-pixel one-cell structure includes a transfer gate 2A corresponding to the photodiode 1A and a transfer gate 2B corresponding to the photodiode 1B.

  The anodes of the photodiodes 1A and 1B are grounded (connected to the ground terminal). The cathodes of the photodiodes 1A and 1B are connected to the floating diffusion as the signal detection unit 6 via the current paths of the corresponding transfer gates 2A and 2B. As described above, the photodiodes 1A and 1B convert the light that has passed through the microlens and the color filter into an electric signal (signal charge), and accumulate the charge. Due to the charges in the photodiodes 1A and 1B, a potential difference is generated between the terminals of the photodiodes 1A and 1B. Hereinafter, when the photodiodes 1A and 1B are not distinguished from each other, they are referred to as photodiodes 1.

  The transfer gates 2A and 2B control the accumulation and emission of signal charges of the photodiodes 1A and 1B, respectively. The gates of the transfer gates 2A and 2B are connected to the read signal lines RD1 and RD2, respectively. One ends of the current paths of the transfer gates 2A and 2B are connected to the cathodes of the photodiodes 1A and 1B, respectively. The other ends of the current paths of the transfer gates 2A and 2B are connected to the floating diffusion FD. Hereinafter, when the transfer gates 2A and 2B are not distinguished, they are referred to as transfer gates 2. The transfer gate 2 is also called a read transistor.

  In the unit cell UC having the two-pixel one-cell structure, the reset transistor 3, the address transistor 4 and the amplifier transistor 5 are shared by the two pixels 1A and 1B.

  The reset transistor 3 resets the potential of the floating diffusion FD (the gate potential of the amplifier transistor 5). The gate of the reset transistor 3 is connected to the reset signal line RST. One end of the current path of the reset transistor 3 is connected to the floating diffusion FD, and the other end of the current path of the reset transistor 3 is connected to the ground terminal. The other end of the current path of the reset transistor 3 is connected to a power supply terminal on the high voltage (power supply VDD) side or a unit cell (reference potential cell) in an optical block region (light shielding region) in the pixel array 120. May be.

  The address transistor 4 functions as a selection element for selecting (activating) the unit cell UC. The gate of the address transistor 4 is connected to the address signal line ADR. One end of the current path of the address transistor 4 is connected to the other end of the current path of the amplifier transistor 5, and the other end of the current path of the address transistor 134 is connected to a power supply terminal (for example, a ground terminal).

  The amplifier transistor 5 amplifies the signal from the photodiode 1 held by the floating diffusion FD. The gate of the amplifier transistor 5 is connected to the floating diffusion FD. One end of the current path of the amplifier transistor 5 is connected to the vertical signal line VSL, and the other end of the current path of the amplifier transistor 5 is connected to one end of the current path of the address transistor 4. The signal amplified by the amplifier transistor 5 is output to the vertical signal line VSL as a unit cell (or pixel) signal. The amplifier transistor 5 functions as a source follower in the unit cell UC.

  The unit cell UC may not include the address transistor 4. In this case, the address signal line ADR is not provided, and the other end of the current path of the amplifier transistor 5 is connected to a power supply terminal (for example, a ground terminal).

  In the image sensor 100 of the present embodiment, the unit cell UC is not limited to a two-pixel one-cell structure. For example, one unit cell UC includes three or more pixels (photodiodes) as in a four-pixel one-cell structure or an eight-pixel one-cell structure, and three or more pixels are included in one unit cell UC. A structure in which one floating diffusion (signal detection unit) 6, one reset transistor 3, one address transistor 4, and one amplifier transistor 5 are shared may be employed. Further, the image sensor 100 according to the present embodiment may have a one-pixel one-cell structure in which one unit cell UC includes one pixel (photodiode).

  As peripheral circuits for controlling the operation of the pixel array 120, a timing generation circuit 130, a vertical shift register 131, an AD conversion circuit 132, and a load transistor 136 are provided in the same chip 110 as the pixel array 120. Other circuits are also provided in the same chip 110 as the pixel array 120 as peripheral circuits.

  The vertical shift register 131 is connected to the read signal lines RD1 and RD2, the address signal line ADR, and the reset signal line RST. The vertical shift register 131 controls the potentials of the read control lines RD1, RD2, the address control line ADR, and the reset control line RST based on a predetermined operation timing, and controls the plurality of unit cells UC in the pixel array 120 in units of rows. Control and select. The vertical shift register 131 supplies a control signal (voltage pulse) for controlling on and off of the transistors 2A, 2B, 3, 4, and 5 in each unit cell to the control lines RD1 and RD2 at a predetermined operation timing. , RST, ADR. The vertical shift register 131 turns on or off a plurality of transistors connected to the common control lines RD1, RD2, RST, and ADR all at once.

  The AD conversion circuit 132 is connected to the vertical signal line VSL. For example, the AD conversion circuit 132 performs analog-digital conversion processing and CDS (Correlated Double Sampling) processing on the signal from the pixel array 120 output to the vertical signal line VSL. The output signal (digital data) from the AD conversion circuit 132 is subjected to correction processing and feature amount calculation processing by a subsequent image processing circuit. Thereby, for example, an image corresponding to one frame of the pixel array 120 is formed.

  The timing generation circuit 130 controls the operation timing of the pixel array 120. The timing generation circuit 130 controls the timing at which the vertical shift register 131 and the AD conversion circuit 132 output signals.

  One end of the current path of the load transistor 136 is connected to the vertical signal line VSL. The load transistor 136 is diode-connected. The other end of the current path of the load transistor 136 is connected to the gate of the load transistor 136. The other end of the current path of the load transistor 136 is connected to a power supply terminal (for example, a ground terminal). The load transistor 136 is used as a constant current source for the vertical signal line VSL.

  Here, an example of the operation of the image sensor will be described.

  Based on the operation timing instructed from the timing generation circuit 130, the reset control line RST corresponding to the row of the selected pixel array 120 is set to the “H” level by the vertical shift register 131, and the reset transistor 3 is turned on. Is done. As a result, the potential of the floating diffusion 6 is reset.

  Further, based on the operation timing instructed by the timing generation circuit 130, the address control line ADR corresponding to the row of the selected pixel array 120 is set to the “H” level by the vertical shift register 131. As a result, the address transistor 4 is turned on. The other end of the current path of the amplifier transistor 5 is connected to a power supply terminal (for example, a ground terminal) via the address transistor 4 in the on state.

  The potential of the floating diffusion 6 in the reset state is applied to the gate of the amplifier transistor 5. The amplifier transistor 5 is driven according to the magnitude of the potential of the floating diffusion 6. The potential of the vertical signal line VSL varies depending on the driving force of the amplifier transistor 5 to which the reset state potential is applied.

  Thus, the output from the amplifier transistor 5 driven by the potential of the floating diffusion 6 in the reset state is output to the vertical signal line VSL as the output of the unit cell UC. In the present embodiment, the output signal from the unit cell UC when the floating diffusion 6 is in the reset state is referred to as a reset signal or a reset voltage.

  The AD conversion circuit 132 acquires the reset signal output to the vertical signal line VSL based on the operation timing instructed by the timing generation circuit 131.

  After the reset signal is acquired by the AD conversion circuit 132, the reset control line RST is set to the “L” level, and the reset transistor 3 is turned off.

  The photodiodes 1A and 1B in the unit cell UC acquire light from the subject at a predetermined operation timing and convert the optical signal into an electric signal (signal charge). The photodiodes 1A and 1B accumulate signal charges. While the photodiodes 1A and 1B accumulate signal charges, the signal levels of the read control lines RD1 and RD2 are set to the “L” level. The transfer gates 2A and 2B corresponding to the two photodiodes 1A and 1B in the unit cell UC are turned off.

  Based on the operation timing instructed from the timing generation circuit 131, the vertical shift register 131 outputs an “H” level read signal. An “H” level read signal is applied to the gates of the transistors as the transfer gates 2A and 2B via the read signal lines RD1 and RD2, and the transfer gates 2A and 2B are turned on.

  In the two-pixel one-cell structure, for example, one read signal line (for example, the signal line RD1) selected from the two read signal lines RD1 and RD2 is set to “H” by the operation timing controlled by the timing generation circuit 131. Is set to "level" and one of the two transfer gates 2A and 2B (for example, transfer gate 2A) is turned on.

  The signal charge accumulated in the photodiode 1 in the unit cell UC is read out to the floating diffusion 6 via the current path (channel) of the transfer gate 2 in the on state.

  A potential of the floating diffusion 6 corresponding to the amount of signal charge from the photodiode 1 is applied to the gate of the amplifier transistor 5. The amplifier transistor 5 is driven with a driving force corresponding to the magnitude of the potential of the floating diffusion 6 (the amount of signal charge from the photodiode 1). The potential of the vertical signal line VSL varies according to the driving force of the amplifier transistor 5 to which a potential corresponding to the signal charge amount is applied.

  Thus, the output from the amplifier transistor 5 driven by the potential of the floating diffusion 6 in the signal charge holding state is output to the vertical signal line VSL as the output of the unit cell UC. The output signal from the unit cell when the floating diffusion 6 holds the signal charge from the photodiode is called a pixel signal or a pixel voltage.

  The AD conversion circuit 132 acquires the pixel signal output to the vertical signal line VSL based on the operation timing instructed by the timing generation circuit 131.

  For example, the reset signal and the pixel signal from the photodiode 1A of the unit cell UC are subjected to digital conversion processing and CDS processing by the AD conversion circuit 132, and digital pixel data Dsig is formed.

  By the same operation, digital pixel data Dsig for the pixel signal (and reset signal) of the photodiode 1B of the unit cell UC belonging to the same row is obtained. Pixel data Dsig is output to a circuit subsequent to the AD conversion circuit 132.

  For example, the selected read signal line RD1 is changed from “H” level to “L” level, and the corresponding transfer gate 2A is turned off. Similar to the above-described operation, the potential of the floating diffusion is reset and a reset signal is output to the vertical signal line VSL. After the reset signal is output, the other read signal line RD2) of the two read signal lines RD1 and RD2 is set to the “H” level, and the other transfer gate 2B of the two transfer gates 2A and 2B is set. Is turned on. A pixel signal corresponding to the other photodiode 1B is output to the vertical signal line VSL. Then, similarly to the above-described operation, the reset signal and the pixel signal are subjected to AD conversion processing and CDS processing, and pixel data Dsig is output.

  After the operation for the selected row is completed, the operation target row is switched by the vertical shift register 131.

  This operation is sequentially repeated, and an image for one frame of the pixel array 120 is formed by a subsequent circuit (for example, an image processing device) based on the formed pixel data.

  Here, an example is shown in which two photodiodes 1A and 1B in one unit cell UC are conducted to the floating diffusion 6 at different operation timings. However, the potentials of the two read control lines RD1 and RD2 are controlled so that the photodiodes 1A and 1B are simultaneously connected to the floating diffusion 6 according to the characteristics (for example, photosensitivity) of the photodiodes 1A and 1B. May be. In this case, the two transfer gates 2A and 2B in the unit cell UC are activated (turned on) simultaneously. Note that the operation of the image sensor described in the present embodiment is an example, and the operation of the image sensor is appropriately changed according to the circuit configuration of the unit cell UC and the configuration of the pixel array 120 and peripheral circuits.

  FIG. 4 is a diagram illustrating a planar structure of the pixel array 120.

  In FIG. 4, the layout of the unit cell UC having a two-pixel one-cell structure in the pixel array 120 is shown.

  As shown in FIG. 4, in the formation region (unit cell formation region) UA of the unit cell UC having the two-pixel one-cell structure, the region (photodiode formation region) PA in which the photodiodes 1A and 1B are formed and the control element An area AA in which 3, 4 and 5 are formed is provided. The area AA in which the control element of the unit cell is formed is called a control element formation area AA.

  The unit cell formation area UA is partitioned by element isolation areas 90 and 95 for each unit cell UC in the pixel array 120. The unit cell formation area UA is surrounded by element isolation areas 90 and 95.

  The photodiode formation area PA and the control element formation area AA are semiconductor areas provided in the semiconductor substrate (chip) 110. In one unit cell formation area UA, two photodiode formation areas PA and one control element formation area AA are continuous in the semiconductor substrate 150. In one unit cell formation region UA, adjacent corners of two photodiode formation regions PA are connected to one end of the control element formation region AA, respectively.

  The photodiode formation area PA has a rectangular (quadrangle) planar shape. The control element formation area AA has a rectangular (line) planar shape.

  Two photodiode formation regions PA in one unit cell formation region UA are adjacent to each other in the y direction with an element isolation region (element isolation layer) 90 interposed therebetween. For example, two photodiode formation regions PA in one unit cell formation region UA may be partitioned by an impurity semiconductor layer as the element isolation layer 90, or may be partitioned by an element isolation layer made of an insulator. Sometimes it is. The photodiode formation areas PA of the unit cell formation areas UA different from each other are electrically isolated by an impurity semiconductor layer or an insulator as an element isolation layer.

  The two photodiode formation regions PA in the unit cell formation region UA have a layout sandwiched between the control element formation regions AA of the two unit cell formation regions UA that are different from each other in the y direction. A plurality of photodiode formation regions PA of different unit cell formation regions UA are arranged along the x direction so as to be shifted alternately (zigzag) in the y direction. Between the two photodiode formation areas PA of the two unit cell formation areas UA adjacent in the x direction, the photodiode formation area PA of the unit cell formation area UA adjacent in the oblique direction with respect to the xy plane is laid out. ing.

  The control element formation area AA is partitioned by an insulator as the element isolation layer 95.

  In the plurality of unit cell formation areas UA arranged along the x direction, the plurality of control element formation areas AA are laid out in the pixel array 120 so as to be arranged on the same straight line along the x direction.

  The plurality of control element formation areas AA are laid out in the pixel array 120 so as to be sandwiched between two photodiode formation areas PA belonging to different unit cell formation areas UA in the y direction.

  The other end in the longitudinal direction of the control element formation area AA is arranged between two photodiode formation areas PA of another unit cell formation area UA adjacent in the x direction.

  As shown in FIG. 4, the gate electrode 21 of the transfer gate 2 is provided on the connection portion (semiconductor region) between the photodiode formation region PA and the control element formation region AA via the gate insulating film. .

  The gate electrode 21 of the transfer gate 2 is inclined in an oblique direction with respect to the extending direction of the control element formation region AA. The channel length direction of the transfer gate 2 is oblique with respect to the extending direction of the control element formation region AA.

  By turning on / off the transfer gates 2A and 2B respectively corresponding to the two photodiodes 1A and 1B, the photodiode formation region PA and the control element formation region AA made of continuous semiconductor regions are electrically connected, or , Electrically separated.

  The photodiode formation region PA includes an impurity semiconductor layer for forming the photodiode 1.

  For example, an impurity semiconductor layer included in the photodiode 1 in the photodiode formation region PA is used as one end (source / drain region) of the current path of the transfer gate 2.

  The impurity semiconductor layer 60 as the floating diffusion 6 is provided in the control element formation region AA. The floating diffusion 6 is laid out in the control element formation region AA so as to be surrounded by the gate electrodes 21 of the two transfer gates 2A and 2B and the gate electrode 30 of the reset transistor 3.

  The floating diffusion 6 is used as the other end (source / drain region) of the current path of the transfer gate 2.

  The gate electrode 30 of the reset transistor 3 is provided on the control element formation region AA via a gate insulating film. The channel length direction of the reset transistor 3 is set in the extending direction (longitudinal direction) of the control element formation region AA. One end and the other end of the gate electrode 30 of the reset transistor 3 in the channel width direction of the transistor are arranged on the element isolation region.

  The floating diffusion 6 substantially becomes one end (source / drain region) of the current path of the reset transistor 3. The other end of the current path of the reset transistor 3 is an impurity semiconductor layer (impurity semiconductor region) provided in the control element formation region AA.

  The address transistor 4 is disposed at the end opposite to the side (one end) where the floating diffusion is provided in the longitudinal direction of the control element formation area AA.

  The gate electrode 40 of the address transistor 4 is provided on the control element formation region AA via a gate insulating film. One end and the other end (source / drain region) of the current path of the address transistor 4 are formed from an impurity semiconductor layer provided in the control element formation region AA. The impurity semiconductor layer as the other end of the current path of the address transistor 4 is provided at the end of the control element formation region AA in the extending direction (the side opposite to the side where the floating diffusion 6 is provided). The impurity semiconductor layer as the other end of the current path of the address transistor 4 is not shared with other transistors. For example, a contact plug (not shown) is provided on the impurity semiconductor layer that is not shared with other transistors of the address transistor 4.

  The amplifier transistor 5 is laid out between the reset transistor 3 and the address transistor 4 in the control element formation area AA.

  Between the gate electrode 30 of the reset transistor 3 and the gate electrode 40 of the address transistor 4, the gate electrode 50 of the amplifier transistor 5 is provided on the control element formation region AA via a gate insulating film.

  The impurity semiconductor layer as one end of the current path of the amplifier transistor 5 is shared with the impurity semiconductor layer as the other end of the current path of the reset transistor 3. The impurity semiconductor layer as the other end of the current path of the amplifier transistor 5 is shared with the impurity semiconductor layer as one end of the current path of the address transistor 4.

  The gate electrode 50 of the amplifier transistor 5 is connected to the floating diffusion 6 via a wiring (not shown) and a plug (not shown).

  As described above, the transistors 2, 3, 4, and 5 as the control elements share the impurity semiconductor layer as the source / drain (one end and the other end of the current path) between adjacent transistors. As a result, the area occupied by the unit cell formation region UC is reduced, and the unit cell UC is miniaturized.

  Similar to the reset transistor 3, the channel length direction of the address transistor 4 and the amplifier transistor 5 corresponds to the extending direction (longitudinal direction) of the control element formation region AA. The channel width direction of the reset transistor 3, the address transistor 4 and the amplifier transistor 5 corresponds to the width direction of the control element formation region AA. In the channel width direction of the transistor, one end and the other end of the gate electrodes 40 and 50 of the address transistor 4 and the amplifier transistor 5 are arranged on the element isolation region.

(B) Photodiode structure
The structure of the photodiode 1 included in the image sensor of this embodiment will be described in detail with reference to FIG.
FIG. 5 is a cross-sectional view showing the structure of the photodiode 1 included in the image sensor of this embodiment. FIG. 5 shows a cross section taken along line VV in FIG. In FIG. 5, only the photodiode 1, the transfer gate 2, and the floating diffusion (FD) 6 are shown as components of the unit cell 20 for clarity of illustration. Further, in FIG. 5, the illustration of the interlayer insulating film is omitted.

  As shown in FIG. 5, the photodiode 1, the transfer gate 2, and the floating diffusion 6 are provided in an element formation region (active region) surrounded by the element isolation region 9.

  One photodiode 1 includes at least one impurity semiconductor layer 10 or 11. At least one of the impurity semiconductor layers 10 and 11 functions as a charge storage unit.

  The floating diffusion 6 is provided in the semiconductor substrate 150 so as to face the photodiode 1 with the transfer gate 2 interposed therebetween. The photodiode 1 and the floating diffusion 6 are arranged in the channel length direction of the transfer gate 2. The floating diffusion 6 is an n-type impurity semiconductor layer (impurity semiconductor region) formed in the semiconductor substrate 150.

The transfer gate 2 is disposed on the semiconductor substrate 150 so as to be adjacent to the photodiode 1 and the floating diffusion 6.
The gate electrode 21 of the transfer gate 2 is provided on the semiconductor substrate 150 via the gate insulating film 22. A semiconductor region between the impurity semiconductor layers 10 and 11 of the photodiode 1 and the n-type impurity semiconductor layer 60 of the floating diffusion 60 becomes a channel region between the source region and the drain region of the transfer gate 2.

  In the present embodiment, the photodiode 1 has a structure embedded in a trench RX formed in the semiconductor substrate 150. A photodiode having a structure embedded in a groove in the semiconductor substrate 150 as in the present embodiment is hereinafter referred to as an embedded photodiode.

  In the present embodiment, the embedded photodiode 1 is provided in the trench RX in the photodiode formation region PA of the semiconductor substrate (for example, a p-type Si substrate) 150. The semiconductor substrate 150 on which the photodiode 1 is formed may be a semiconductor layer (for example, a p-type silicon layer) of an SOI (Silicon On Insulator) substrate.

  The first semiconductor layer 10 is embedded in the trench RX in the photodiode formation region PA. The first semiconductor layer 10 is, for example, a silicon layer (hereinafter referred to as a Si layer). In the trench RX, the second semiconductor layer 11 is provided on the top of the Si layer 10. Similar to the first semiconductor layer 10, the second semiconductor layer 11 is, for example, a Si layer. Hereinafter, for clarity of explanation, the Si layer 10 on the bottom side of the groove (the back side of the semiconductor substrate 150) is referred to as a lower Si layer 10 and is a groove laminated on the upper surface of the lower Si layer 10. The Si layer 11 on the RX opening side (the surface side of the semiconductor substrate 150) is referred to as the upper Si layer 11.

  The lower Si layer 10 and the upper Si layer 11 are, for example, a polycrystalline Si layer or an epitaxial Si layer. The lower Si layer 10 and the upper Si layer 11 may be one Si layer that is continuous (the interface is unclear) or two Si layers that are discontinuous (the interface is clear).

The lower Si layer 10 embedded in the trench RX is, for example, an n-type Si layer 10. The lower Si layer 10 includes, for example, phosphorus (P) or arsenic (As) as an n-type dopant. For example, the impurity concentration of the n-type dopant of the n-type lower Si layer 10 in the photodiode 1 is lower than the impurity concentration of the n-type impurity semiconductor layer 60 as the floating diffusion 6. For example, the lower Si layer 10 includes an n-type dopant having an impurity concentration in the range of about 1 × 10 ¹⁶ cm ⁻³ to 5 × 10 ¹⁶ cm ⁻³ .

  In the direction perpendicular to the surface of the Si substrate 150, the position ZX of the bottom (bottom of the groove) of the lower Si layer 10 is on the back side of the Si substrate 150 relative to the position of the bottom of the impurity semiconductor layer 60 as the floating diffusion 6. Is set to In the direction perpendicular to the surface of the Si substrate 150, the position ZX of the bottom (bottom of the groove) of the lower Si layer 10 is set closer to the surface of the Si substrate 150 than the position of the bottom of the element isolation layer 90. .

  In the photodiode formation region PA, the trench RX in which the lower Si layer 10 containing the dopant is embedded is formed so as to reach a deep region of the Si substrate 150. Along with this, the Si layer 10 is provided in a deep region of the Si substrate 150. For example, the trench RX is formed to have a depth of about 2 μm to 4 μm (dimension in the direction perpendicular to the surface of the Si substrate 150).

  In FIG. 5, in order to improve the characteristics (for example, sensitivity) of the photodiode 131 in the lower Si layer 10 of the photodiode 1, a plurality of n-types having different impurity concentrations in the depth direction of the Si substrate 150 and A p-type impurity region may be provided.

  The upper surface of the upper Si layer 11 is exposed from the opening of the trench RX. For example, the position of the upper surface of the upper Si layer 11 matches the position of the surface of the semiconductor substrate 150. The upper Si layer 11 is formed as an undoped Si layer (intrinsic Si layer) containing almost no n-type or p-type dopant at the time of deposition. An n-type or p-type dopant is added into an intrinsic Si layer (hereinafter also referred to as an i-type Si layer) 11 in accordance with characteristics required for the photodiode 1. As a result, the upper Si layer 11 includes at least one impurity semiconductor region.

  For example, an impurity semiconductor region (hereinafter, referred to as a p-type Si region) 111 containing a p-type dopant is provided in the upper Si layer 11 on the surface side of the Si substrate 150. The p-type Si region 111 functions as, for example, a surface shield layer that suppresses diffusion (for example, carbon) from an interlayer insulating film on the surface of the Si substrate 150 into the n-type Si layer 10 of the photodiode 1. To do. Alternatively, the p-type Si region 111 forms, for example, a pn junction for photoelectric conversion between the region 111 and the lower n-type impurity semiconductor layer 10.

  An impurity semiconductor region 151 is provided in the Si substrate 150 in the vicinity of the interface between the lower Si layer 10 and the Si substrate 150. The impurity semiconductor region 151 surrounds the lower Si layer 10 along the shape of the trench RX (the side walls and the bottom of the trench RX). The impurity semiconductor region 12 provided in the Si substrate 150 is, for example, n-type conductivity type. An impurity semiconductor region 113 is provided in the upper Si layer 11 in the vicinity of the interface between the lower Si layer 10 and the upper Si layer 11. For example, the impurity semiconductor region 113 in the upper Si layer 11 provided on the lower Si layer 10 side has an n-type conductivity type. For example, the entire surface of the lower Si layer 10 is surrounded by n-type impurity semiconductor regions (hereinafter also referred to as n-type Si regions) 151 and 113 in the Si substrate 150 and the upper Si layer 11.

  When the trench RX is formed, crystal defects (damage) may occur in the exposed surface of the Si substrate 150 in the exposed surface of the Si substrate 150 in the trench RX. The n-type impurity semiconductor region 151 is formed in the Si substrate 150 along the shape of the trench RX, and thus is generated at the interface between the n-type Si layer 10 and the Si substrate 150 due to crystal defects in the Si substrate 150. Leakage (for example, junction leak) can be reduced.

  The n-type impurity semiconductor regions 151 and 113 are formed by diffusing impurities (for example, phosphorus) included in the lower Si layer 10 into the Si substrate 150 and the upper Si layer 11.

  The impurity concentration of the n-type dopant in the impurity semiconductor regions 151 and 113 is lower than the impurity concentration of the n-type dopant in the lower Si layer 10.

In the following, for the sake of clarification, the lower Si layer is referred to as an n-type Si layer 10 based on the impurity concentration of the n-type dopant in the n-type lower Si layer 10 and is more n than the n-type Si layer 10. The n-type impurity semiconductor regions 113 and 151 in which the impurity concentration of the n-type dopant is low are referred to as n ⁻ -type Si regions 113 and 151, and the n-type impurity semiconductor in which the n-type dopant has a higher impurity concentration than the n-type Si layer 10. The region may be referred to as an n ⁺ type Si region.

  For example, the dimension D2 of the groove RX on the back surface side of the Si substrate 150 in the horizontal direction with respect to the surface of the Si substrate 150 is the dimension of the groove RX (dimension of the opening of the groove RX) D1 on the surface side of the Si substrate 150. They have substantially the same size. The dimension of the embedded photodiode 1 depends on the dimension of the trench RX, and the dimension D1 of the lower portion (bottom side of the trench RX) of the photodiode 1 in the horizontal direction with respect to the surface of the Si substrate 150 is on the surface of the Si substrate 150. On the other hand, it is substantially the same as the dimension D2 of the upper part (opening side of the groove RX) of the photodiode 1 in the horizontal direction.

  Thus, in the image sensor of this embodiment, the photodiode 1 has a structure in which the semiconductor layers (Si layers) 10 and 12 containing impurities are embedded in the trench RX in the semiconductor substrate 150.

  In an image sensor, the aspect ratio of the photodiode tends to increase as the photodiode becomes finer as the pixel in the unit cell (area reduction). As a result of the miniaturization of the photodiode, the impurity semiconductor region included in the photodiode is formed in a relatively deeper region (region on the back side of the semiconductor substrate) in the semiconductor substrate (Si substrate).

  In the case where an impurity semiconductor region is formed using ion implantation in a deep region of a semiconductor substrate, ions serving as a dopant are implanted into the semiconductor substrate using a large ion acceleration. The implanted ions (atoms) collide with constituent atoms of the semiconductor substrate 150, and the implanted ions are scattered in the semiconductor substrate 150 due to the collision between the atoms. As ion acceleration used for ion implantation increases, ion (dopant) scattering increases.

  Therefore, impurities formed on the back surface (deep region) side of the semiconductor substrate using ion implantation in the horizontal direction with respect to the surface of the semiconductor substrate due to ion scattering in the horizontal direction with respect to the surface of the semiconductor substrate. The size of the semiconductor region tends to be larger than the size of the impurity semiconductor region formed on the surface side of the semiconductor substrate.

  When the dimension of the impurity semiconductor region in the horizontal direction with respect to the semiconductor substrate surface is increased on the back surface side of the semiconductor substrate, leakage or contact between adjacent photodiodes may occur. Further, when the scattered dopant is mixed in the impurity semiconductor layer as the element isolation layer, there is a possibility that an element isolation defect occurs. As a result, there is a risk of malfunction of the elements (pixels and unit cells) or color mixture of the formed image.

  In order to prevent leakage or contact between adjacent photodiodes, the area of the unit cell including the photodiodes increases when the interval between the photodiodes (area of the element isolation region) is increased.

  In order to suppress deterioration of device characteristics and increase in device area due to ion (dopant) scattering, when an impurity semiconductor region as a constituent element of a photodiode is not formed in a deep region of the semiconductor substrate 150, The loss of light energy increases in the optical path until the light is photoelectrically converted, and the charge (voltage or current) obtained by photoelectric conversion of the photodiode is reduced. As a result, the signal output from the pixel and the unit cell becomes small, and the reproducibility of an image (color, brightness, etc.) formed based on the light from the subject is deteriorated. Therefore, when the impurity semiconductor layer is not formed in a deep region of the semiconductor substrate, the image quality of the formed image may be deteriorated.

  In the photodiode 1 having a structure in which the impurity semiconductor layer 10 is embedded in the trench RX of the semiconductor substrate 150 as in the image sensor of the present embodiment, for example, the semiconductor substrate 150 in the trench RX as in the manufacturing method described later. A dopant (for example, phosphorus) included in the impurity semiconductor layer 10 provided on the back side of the semiconductor layer 10 is added to the semiconductor layer 10 during the deposition of the impurity semiconductor layer 10. That is, in the image sensor according to the present embodiment, the semiconductor layer 10 containing the dopant in the deep region of the semiconductor substrate 150 is embedded in the trench RX of the semiconductor substrate 150 and is formed in the semiconductor substrate 150 without using ion implantation. The

  Therefore, the photodiode included in the image sensor 100 of the present embodiment does not cause deterioration in characteristics of the photodiode and malfunction of the image sensor due to ion (dopant) scattering caused by ion implantation. Therefore, the photodiode included in the image sensor according to the present embodiment can suppress degradation of element characteristics and element defects.

  In the present embodiment, the size of the photodiode 1 depends on the size of the trench RX formed in the semiconductor substrate 150. Therefore, unlike the case where the impurity semiconductor layer is formed by ion implantation, the image sensor 100 according to the present embodiment does not need to increase the interval between the photodiodes in consideration of ion scattering. Therefore, the photodiode 1 used in the image sensor of this embodiment can reduce the size (occupied area) of the photodiode and the size of the unit cell.

  As described above, the semiconductor layer 10 containing the impurity of the photodiode 1 is embedded in the trench RX formed in the semiconductor substrate 150 to form a photodiode using ion implantation as in the present embodiment. A photodiode can be formed without causing deterioration (defects) in device characteristics or an increase in unit cell area.

  Therefore, according to the solid-state imaging device of the first embodiment, the size of the photodiode can be reduced, and deterioration or failure of the element characteristics of the photodiode can be suppressed.

(C) Manufacturing method
A manufacturing method of the solid-state imaging device (for example, an image sensor) of the first embodiment will be described with reference to FIGS.

  6 to 8 are cross-sectional views illustrating one process of the method of manufacturing the image sensor according to the present embodiment. 6 to 8 show each step in a cross section taken along the line V-V in FIG. 4. Here, the manufacturing method of the image sensor of this embodiment will be described with reference to FIGS. 2, 4 and 5 as appropriate.

  As shown in FIG. 6, the element isolation layer 90 is formed in the element isolation region of the semiconductor substrate 150. The element isolation layer 90 may be an impurity semiconductor layer (element isolation impurity layer) formed by ion implantation, or may be an insulator (element isolation insulating layer) embedded in an STI trench in the semiconductor substrate 150.

  A mask material (for example, a resist) is formed on the surface of a semiconductor substrate (for example, a p-type Si single crystal substrate or a p-type Si layer of an SOI substrate). The mask material is patterned by a photolithography technique. By this patterning, an opening is formed in the mask material so that the surface of the Si substrate 150 is exposed in a region (photodiode formation region) PA where the photodiode is formed. As a result, a mask layer 200 having a predetermined pattern is formed on the Si substrate 150.

  Using the mask layer 200 having the opening as a mask, the Si substrate 150 is etched by, for example, RIE (Reactive Ion Etching). As a result, a trench RX reaching a deep region of the Si substrate 150 is formed in the photodiode formation region 110 of the Si substrate 150. For example, the trench RX is formed to have a depth of about 2 μm to 4 μm (dimension in the direction perpendicular to the surface of the Si substrate 150).

  The trench RX may be formed in the same process as the STI trench (not shown) for embedding the element isolation insulating layer.

  As shown in FIG. 7, after the mask layer is removed, a semiconductor layer (here, Si layer) 19 is deposited on the Si substrate 150. The Si layer 19 is formed by, for example, a CVD (Chemical Vapor Deposition) method at a deposition temperature of about 600 ° C. to 700 ° C. The formed Si layer 19 may be a polycrystalline Si layer or an epitaxial Si layer.

  The deposited Si layer 19 is filled in the trench RX. The lower Si layer 10 on the bottom side of the trench RX in the Si layer 19 is formed, for example, in a gas atmosphere containing phosphorus as an n-type dopant, and is embedded in the trench RX in the Si substrate 150. That is, during the deposition of the Si layer 10, n-type dopants for silicon are doped into the Si layer 10 in-situ.

  In this way, by adding the dopant into the Si layer 10 while filling the Si layer 10 in the trench RX of the Si substrate 150, the n-type Si layer 10 can be formed deep in the Si substrate 150 without using ion implantation. It can be formed in the region. In this case, since the scattering of the dopant due to the collision between the ion (dopant) and the Si atom, such as ion implantation, does not occur, the size of the Si layer 10 due to the scattering of the dopant does not increase unintentionally. The size of the lower Si layer 10 of the mold depends on the size of the groove formed in the Si substrate 150.

For example, the impurity concentration of the n-type dopant doped in the lower Si layer 10 is adjusted from 1 × 10 ¹⁶ cm ⁻³ to 5 × 10 10 by adjusting the supply amount of the n-type dopant during the deposition of the Si layer 10. The range is set to about ¹⁶ cm ⁻³ .

  On the upper surface of the lower Si layer 10, an undoped upper Si layer (i-type Si layer) 11A as a part of the Si layer 19 is formed. For example, the undoped Si layer 11A is continuously formed on the n-type Si layer 10 by stopping the supply of phosphorus and continuing the deposition of the Si layer. If the upper Si layer 11A is laminated on the upper surface of the lower Si layer 10 in the trench RX, the formation of the lower Si layer 10 including the dopant and the formation of the upper Si layer 11A not including the dopant are continuous. Not necessary.

  As shown in FIG. 8, the upper Si layer 11 is processed by, for example, etch back or CMP (Chemical Mechanical Polishing) so that the position (height) of the upper surface of the upper Si layer 11 matches the surface of the Si substrate. Is done. The Si substrate 150 is subjected to heat treatment, and the n-type dopant nd in the lower Si layer 10 is thermally diffused. The temperature of the heat treatment for diffusing the dopant nd included in the Si layer 10 from the Si layer 10 into the Si substrate 150 is set to 600 ° C. to 700 ° C., for example.

  By this heat treatment, the n-type dopant (for example, phosphorus) nd in the lower Si layer 10 becomes a boundary (interface) between the lower Si layer 10 and the Si substrate 150 and between the lower Si layer 10 and the upper Si layer 11. It diffuses in the Si substrate 150 and the upper Si layer 11 across the boundary. As a result, an n-type impurity semiconductor region (n-type Si region) 151 is formed in the Si substrate 150 along the shape of the trench RX and the lower Si layer 10. An n-type impurity semiconductor region (n-type Si region) 113 is formed in the upper Si layer 11 along the boundary between the lower Si layer 10 and the upper Si layer.

  The impurity concentration of the n-type dopant included in the n-type Si regions 113 and 151 formed by thermal diffusion is lower than the impurity concentration of the n-type dopant in the lower Si layer 10.

The low concentration n ⁻ type Si regions 113 and 151 are formed in the Si substrate 150 and the upper Si layer 11 so as to surround the periphery of the n type lower Si layer 10.

  For example, the exposed surface of the Si substrate 150 along the inner surface of the groove RX may be damaged by etching for forming the groove RX, and crystal defects may be generated on the exposed surface of the Si substrate 150 in the groove RX. Due to crystal defects in the Si substrate 150 generated by the formation of the trench RX, a junction leak occurs between the Si substrate 150 and the lower Si layer 10 embedded in the trench RX, and the operating characteristics of the photodiode deteriorate. there's a possibility that.

As in this embodiment, a low concentration n ⁻ type Si region 151 is formed along the interface between the lower Si layer 10 and the Si substrate 150 by thermal diffusion of the n type dopant nd included in the lower Si layer 10. As a result, the adverse effects of crystal defects at the interface between the Si layer 10 and the Si substrate 150 are alleviated, and junction leakage between the lower Si layer 10 and the Si substrate 150 is suppressed. In addition, regarding the boundary between the lower Si layer 10 and the upper Si layer 11, the adverse effect of discontinuity between the lower Si layer 10 and the upper Si layer 11 is mitigated by the n ⁻ -type Si region 113.

Note that the diffusion amount (diffusion distance) of the dopant by heating is controlled by the temperature and time of the heat treatment.
Since the diffusion coefficient of phosphorus (P) as an n-type dopant is larger than the diffusion coefficient of arsenic (As) as an n-type dopant, the n-type Si regions 113 and 115 are formed by thermal diffusion as shown in FIG. If formed, phosphorus is preferably used. However, when the size of the unit cell and the pitch between the unit cells are reduced or the size of the formed photodiode is reduced, arsenic may be used to accurately control the diffusion range of the dopant due to heat. Good. The n-type Si layer 10 may be doped with both phosphorus and arsenic.

  For example, the crystallinity of the Si layers 10 and 11 in the trench RX is improved by the heat treatment on the Si substrate 150.

  As shown in FIG. 5, for example, the gate insulating film 22 of the transistor is formed on the upper surface of the Si substrate 150 and the upper surface of the upper Si layer 11. For example, a polysilicon layer is deposited on the gate insulating film 22 by a CVD method. The polysilicon layer is processed into a predetermined shape by photolithography and RIE (Reactive Ion Etching), and the gate electrode 21 of the transistor 2 is formed. Simultaneously with the step of forming the gate electrode 22 of the transfer gate 2, the gate electrodes of the field effect transistors such as the reset transistor 3, the address transistor 4 and the amplifier transistor 5 in FIG. 4 and the transistor 7 in the peripheral circuit region in FIG. It is formed.

  An impurity semiconductor region 60 as a floating diffusion 60 is formed in the Si substrate 150 by ion implantation. Further, a p-type dopant (for example, boron) or an n-type dopant is added into the undoped upper Si layer 11 by ion implantation, for example. Thereby, an impurity semiconductor region 111 is formed in the upper Si layer 11.

  Since the Si region 111 containing the dopant formed in the floating diffusion 6 and the upper Si layer 11 is ion-implanted into a shallow region of the Si substrate 150, it can be formed by ion implantation with low ion acceleration. Therefore, the expansion of the dimensions of the floating diffusion 6 and the Si region 111 due to the scattering of the dopant hardly occurs.

The order of ion implantation for forming the floating diffusion and ion implantation for the Si layer is not limited to the above example. Doping using ion implantation for the upper Si layer 11 may be performed before the transistor 2 is formed. The impurity semiconductor region 111 may not be formed in the undoped upper Si layer 11.
The element isolation layer 90 may be formed after the photodiode 1 is formed. In addition, before forming the trench RX for embedding the Si layer 19, the gate insulating film 22 of the transistor 2 may be formed, and the gate electrode 21 of the transistor may be formed using the Si layer 19 embedded in the trench RX. .

  As described above, the embedded photodiode 1 is formed in the trench RX of the photodiode formation region PA, and a unit cell including the embedded photodiode 1 is formed.

  Thereafter, as shown in FIG. 2, an interlayer insulating film 92, a contact plug 81, and a metal film 80 inside thereof are sequentially formed on the surface of the Si substrate 150 by a known technique. For example, the wiring 82 is formed on the upper surface of the uppermost interlayer insulating film 92 by a rewiring technique. A support substrate 119 is attached to the upper surface of the insulating layer 96 that covers the wiring 82.

  After the thickness of the Si substrate 150 is reduced by etching or grinding on the back surface of the Si substrate 150, the color filter layer CF and the back surface side of the Si substrate 150 are interposed via an insulating film and an adhesive layer (not shown). A microlens array ML is attached.

  Further, before or after the color filter layer CF and the microlens array ML are attached, an opening (through hole) penetrating from the front surface side to the back surface side of the Si substrate 150 is formed, and on the inner surface of the through hole. Then, an insulating film 98 is formed. A through electrode 88 is embedded in the through hole of the Si substrate 150 so as to be connected to the metal film (wiring) 80 in the interlayer insulating film 92. A pad 89 is formed on the insulating film 99 on the back surface of the Si substrate 150 so as to be connected to the through electrode 88. The through electrode 88 may be formed before the photodiode 1 is formed.

  Through the above manufacturing process, an image sensor including the embedded photodiode 1 according to this embodiment is manufactured.

  When an impurity semiconductor region is formed in a deep region of a semiconductor substrate by using ion implantation, ions are implanted at a large acceleration. Therefore, due to collision between implanted ions (dopant) and constituent atoms of the semiconductor substrate. The effect of dopant scattering is increased. Due to the scattering of the dopant, in the impurity semiconductor region of the photodiode formed in the deep region of the semiconductor substrate 150, it is difficult to scale the impurity semiconductor region in the horizontal direction with respect to the surface of the semiconductor substrate.

  In this case, for example, the impurity semiconductor region formed in the deep region of the semiconductor substrate by ion implantation becomes larger in the horizontal direction with respect to the surface of the semiconductor substrate, and leakage or contact between adjacent photodiodes may occur. There is sex. In order to prevent leakage or contact between adjacent photodiodes due to dopant scattering, if the interval between photodiodes (area of the element isolation region) is increased, the area of the unit cell including the photodiodes is increased.

  The influence of the scattering of the dopant and the difficulty in scaling the photodiode become conspicuous as the photodiode is miniaturized and the aspect ratio is increased.

  Photoelectric conversion of a photodiode when an impurity semiconductor layer as a photodiode component is not formed in a deep region of a semiconductor substrate in order to suppress deterioration of device characteristics and an increase in area due to ion (dopant) scattering. There is a possibility that the efficiency is lowered and the image quality of the formed image is deteriorated.

  In the image sensor manufacturing method of the present embodiment, the trench RX is formed in the semiconductor substrate 150 so as to reach a deep region of the semiconductor substrate 150, and the impurity semiconductor layer 10 containing the dopant is formed in the formed trench RX. Embedded. A dopant (for example, phosphorus) in the impurity semiconductor layer 10 is added to the semiconductor layer 10 during the deposition of the impurity semiconductor layer 10.

  Thus, in the image sensor manufacturing method of the present embodiment, the semiconductor layer 10 containing the dopant is formed so as to reach a deep region of the semiconductor substrate 150 without using ion implantation. Therefore, according to the method of manufacturing the image sensor of this embodiment, the photodiode 1 having the impurity semiconductor layer 10 formed in a deep region of the semiconductor substrate 150 without adversely affecting the scattering of ions (dopant) due to ion implantation. Can be formed in the semiconductor substrate 150.

  Therefore, the manufacturing method of the image sensor according to the present embodiment can form a photodiode capable of suppressing deterioration of element characteristics and element defects. Moreover, the manufacturing method of the image sensor of this embodiment can form a photodiode with a small size (occupied area).

  The size of the photodiode depends on the size of the trench RX formed in the semiconductor substrate 150. Therefore, unlike the case where the impurity semiconductor layer is formed by ion implantation, in the method for manufacturing the photodiode according to the present embodiment, in consideration of ion scattering, the distance between the photodiodes is not increased. Good. Therefore, according to the method of manufacturing the image sensor of the present embodiment, the size of the unit cell and the element isolation region can be reduced by forming the photodiode in the trench RX in the semiconductor substrate 150.

  As described above, according to the method for manufacturing a solid-state imaging device of the present embodiment, it is possible to provide a solid-state imaging device that can suppress deterioration or failure of the element characteristics of the photodiode. Moreover, according to the manufacturing method of the solid-state imaging device of this embodiment, a solid-state imaging device including a small-sized photodiode and unit cell can be provided.

(D) Configuration example
A configuration example of the image sensor of this embodiment will be described with reference to FIG.

  When the image sensor is a single-plate image sensor that acquires a plurality of pieces of color information with one pixel array 2, the color filter layer CF provided above the pixel array 120 shown in FIG. Corresponding filter (dye film) is included.

  An example of the arrangement of each color of the color filter layer CF is a Bayer arrangement. The Bayer array is formed of filters corresponding to wavelength ranges (wavelength band, wavelength range, or single wavelength) of red (R), green (R), and blue (B). In the light applied to the color filter layer CF, light having a wavelength component corresponding to the color of each filter is transmitted through the filter. At least one color filter of red, blue, and green corresponds to one pixel (photodiode) or one unit cell, respectively.

  When considering the light absorption characteristics and photoelectric conversion efficiency of the impurity semiconductor layer forming the photodiode, the photons are transmitted in accordance with the light components (colors and wavelength ranges) that pass through the filters of each color and enter the photodiode. In order to adjust the thickness of the impurity semiconductor layer of the diode 1, it is preferable to vary the depth of the trench RX in which the impurity semiconductor layer of the photodiode 1 is embedded.

  For example, when the embedded photodiode included in the image sensor of the present embodiment is formed of a silicon (Si) layer, the absorption coefficient of Si for blue light is large, and the absorption coefficient of Si for red light is blue. It is smaller than the absorption coefficient for light. Blue light having a short wavelength is relatively easily absorbed by the Si layer, and red light having a long wavelength is less easily absorbed by the Si layer than blue light. The wavelength of green light is located approximately halfway between the wavelength of blue light and the wavelength of red light, and green light is less likely to be absorbed than blue light and more easily absorbed than red light. Therefore, blue light is absorbed near the surface of the Si layer. On the other hand, absorption of red light requires a deeper region of the Si layer than blue light.

  In consideration of the light absorption characteristics of a material (here, silicon) for forming the embedded photodiode 1 of the present embodiment, the photodiode 1 is formed according to the correspondence between the filter and the pixel. In order to ensure the thickness (film thickness) of the semiconductor layer, the depth of the groove is preferably set to be different so as to correspond to each color of the color filter layer CF.

For example, as shown in FIG. 9, in the photodiode 1 ₁ corresponding to the blue filter F1, blue light L1 as described above, the semiconductor layer (silicon layer) 10 _1, 11 is easily absorbed in _1, photoelectric because easily converted, Si layer ₁₀ 1 are embedded in the photodiode _{1 1} in the groove RX _1, 11 ₁ of the film thickness may be relatively thin. For example, the film thickness of the Si layers 10 ₁ and 11 ₁ is preferably about 0.3 μm or more and 1 μm or less.

In the embedded photodiode 1 ₁ for photoelectrically converting blue light (wavelength range of blue light), in a direction perpendicular to the Si substrate 150 surface, the bottom of the groove RX ₁ photodiode 1 ₁ is embedded (Si layer 10 _1, 11 ₁ of the bottom) position Z1-Z1 'of, for example, surface Z0-Z0 of Si substrate 150' on the basis of the position of the, is set at a position in the range of 0.3μm to 1 [mu] m.

On the other hand, with respect to the photodiode 1 ₃ corresponding to the red color filter F3, red light L3 is less likely to be absorbed than the blue and green light L1, L2, photoelectric conversion of the photodiode is less likely to occur. Therefore, the film thickness of the Si layer ₁₀ 3, 11 ₃ for forming the photodiode _{1 3} corresponding to red, thick than the photodiode _{1 1} Si layer ₁₀ 1, 11 ₁ of a thickness corresponding to blue It will be lost. For example, the Si layers 10 ₃ and 11 ₃ are preferably formed with a film thickness of about 3 μm to 4 μm.

Respect buried photodiode 1 ₃ red light (wavelength range of red light) photoelectrically converting, in a direction perpendicular to the Si substrate 150 surface, the bottom of the groove RX ₃ photodiode 1 ₃ is embedded (Si layer 10 _3, 11 ', for example, surface Z0-Z0 of Si substrate 150' position Z3-Z3 of ₃ bottom of) so as to be positioned at a position from 3μm from above 4μm depth of grooves RX ₃ is formed.

In the photodiode 1 ₂ corresponding to the green color filter F2, green light L2 is less likely to be absorbed than blue light L1, easily absorbed than red light L2. Therefore, Si layer ₁₀ 2 for forming the photodiode _{1 2} corresponding to the green color filter F2, 11 ₂ of the film thickness, for example, Si layer of the photodiode _{1 1} corresponding to the blue color filter F1 10 _It may be thicker than the film thicknesses ₁ and 11 ₁ . For example, Si layer ₁₀ 2, 11 ₂ of the film thickness is set to about 2 [mu] m.

Respect buried photodiode 1 ₂ green light (wavelength region of green light) photoelectrically converting, in a direction perpendicular to the Si substrate 150 surface, the bottom of the groove RX ₂ photodiode 1 ₂ is embedded (Si layer 10 _2, 11 position Z2-Z2 'includes a photodiode _{1 1} position of the bottom Z1-Z1 of the groove RX1 corresponding to blue' _two bottom) of the photodiode _{1 3} grooves RX ₃ corresponding to the red and the bottom of the It is located between positions Z3-Z3 ′. For example, in the buried photodiode _{1 2} corresponding to the green, so as to be positioned from 2μm from the position of the bottom of the groove RX ₂ surface Z0-Z0 of the Si substrate 150 'to a depth of about 3 [mu] m, the groove RX ₂ is formed Is done.

  The formation positions (layouts) of the grooves RX1, RX2, and RX3 having different depths in the pixel array 120 are set based on a preset filter arrangement pattern in the color filter layer CF.

Thus, in the image sensor of this embodiment, the wavelength (color) of light incident on the photodiodes 1 ₁ , 1 ₂ , and 13 corresponding to each pixel through the filters F 1, F 2, and F ₃ of each color. In consideration of the above, Si layers 10 ₁ , 10 ₂ , 10 ₃ , 11 ₁ for generating signal charges by varying the depths of the grooves RX ₁ , RX ₂ , RX _{3 in} the direction perpendicular to the surface of the Si substrate 150. , 11 ₂ , 11 ₃ are secured.

  Thereby, the photoelectric conversion characteristics of the photodiode corresponding to each color are ensured, and the image quality of the formed image can be improved.

  However, in the single-plate image sensor using the embedded photodiode according to the present embodiment, the depth of the plurality of grooves (without changing the depth of the groove RX according to the wavelength of light absorbed by the photodiode) The film thickness of the Si layer may be the same in the pixel array 120.

(2) Second embodiment
With reference to FIG. 10, the solid-state imaging device (for example, image sensor) of 2nd Embodiment is demonstrated. In the present embodiment, the same components / functions as those of the image sensor of the first embodiment will be described as necessary.

  FIG. 10 is a cross-sectional view showing the structure of the photodiode 1X included in the image sensor of this embodiment along the line VV in FIG.

  As shown in FIG. 10, in the present embodiment, the embedded photodiode 1 </ b> X is formed using a silicon germanium layer (hereinafter referred to as a SiGe layer) 13.

  The SiGe layer 13 is provided in the trench RX. The SiGe layer 13 is an n-type SiGe layer and contains, for example, phosphorus or arsenic as an n-type dopant.

For example, the upper Si layer 11 is provided on the upper surface of the SiGe layer 13. However, a SiGe layer may be used instead of the upper Si layer 11. For example, the n ⁻ type impurity regions 113 and 151 adjacent to the SiGe layer 13 may contain Ge diffused from the SiGe layer 13.

  When an embedded photodiode is formed using the SiGe layer 13, the depth of the trench RX in which the SiGe layer 13 is embedded is set to about 2 μm, for example.

  In the present embodiment, the manufacturing process of the embedded photodiode is substantially the same except that the material used for the embedded photodiode is changed from Si to SiGe. Therefore, description of the manufacturing process of the image sensor of this embodiment is omitted.

  In the embedded photodiode 1X of the present embodiment, the SiGe layer 13 is embedded in the trench RX in the Si substrate 150.

The absorption coefficient of SiGe for red light is larger than the absorption coefficient of Si for red light. As shown in FIG. 9, Si is the absorption coefficient for the red light is low, buried photodiode 1 ₃ for photoelectrically converting red light, the photodiode 1 to detect the green or blue light Compared to ₁ , the thickness of the Si layer that absorbs red light is increased, and the depth of the groove is increased. As a result, the photodiode corresponding to the red light has a larger aspect ratio of the groove than the photodiode corresponding to the blue or green light. It may be difficult to completely fill the groove.

  As in this embodiment, SiGe, which absorbs red light more easily than Si, is used for the impurity semiconductor layer 13 included in the embedded photodiode, whereby the photoelectric conversion efficiency of the photodiode 1X for red light can be improved.

  Also, the embedded photodiode 1X using SiGe of this embodiment has a semiconductor layer that is larger than the embedded photodiode using Si in order to increase the film thickness of the impurity semiconductor layer that absorbs red light. It is not necessary to increase the depth of the trench to be embedded, and the depth of the trench RX in which the impurity semiconductor layer 13 of the photodiode 1X is embedded can be reduced.

  Since the position ZZ at the bottom of the trench RX can be brought closer to the surface side of the Si substrate 150, the formation of the trench RX for embedding the impurity semiconductor layer and the embedding property of the impurity semiconductor layer of the photodiode 1X in the trench RX are improved. The processing difficulty of the embedded photodiode 1X included therein is reduced. This improves the manufacturing yield of the image sensor.

  As described above, according to the solid-state imaging device of the second embodiment, the same effects as those of the first embodiment can be obtained, and the manufacturing cost of the image sensor can be reduced.

(3) Third embodiment
A solid-state imaging device (for example, an image sensor) and a manufacturing method thereof according to the third embodiment will be described with reference to FIGS. In the present embodiment, the same components / functions as those of the image sensors of the first and second embodiments will be described as necessary.

(A) Structure
The structure of the image sensor according to the third embodiment will be described with reference to FIG.

  FIG. 11 is a cross-sectional view showing the structure of the photodiode included in the image sensor of the present embodiment along the line VV in FIG.

  In the embedded photodiode, when the SiGe layer is directly formed on the exposed surface of the Si substrate in the groove, a crystal of the exposed surface of the Si substrate in the groove (the inner surface of the groove) generated when the groove RX is formed. The SiGe layer with good crystallinity may not be formed due to damage to the surface, difference in thermal expansion coefficient between the SiGe layer and the Si substrate, or lattice mismatch between the SiGe layer and the crystal surface of the Si substrate in the groove. . As a result, the characteristics (for example, photoelectric conversion characteristics) of the embedded photodiode formed using the SiGe layer may be deteriorated.

As shown in FIG. 11, the embedded photodiode 1Z of the present embodiment includes a SiGe layer 13 provided in the trench RX.
In the present embodiment, the Si layer 16 is provided between the SiGe layer 13 and the Si substrate 150. The Si layer 16 includes, for example, an n-type dopant. Note that the Si layer 16 may contain Ge having a lower concentration than the SiGe layer 13. The Si layer 16 is, for example, a polycrystalline silicon layer, an epitaxial silicon layer, or an amorphous silicon layer.

For example, an n-type Si layer 14 is provided on the upper surface of the SiGe layer 13 and the upper end of the Si layer 16. The impurity concentration of the n-type dopant in the Si layer 14 may be higher than the impurity concentration of the n-type dopant in the n-type SiGe layer 13 or may be lower than the impurity concentration of the n-type dopant in the n-type SiGe layer 13.
The upper Si layer 11 including the impurity regions 111 and 113 is provided on the Si layer 14.

  In addition, without providing the Si layers 11 and 15 in the groove RX, the inside of the groove RX may be filled with the SiGe layer 13 and the Si layer 16 as a buffer layer.

  The side and bottom surfaces of the SiGe layer 13 are in contact with the Si layer 16 deposited in the trench. In the trench RX, the SiGe layer 13 is covered with the Si layer 16 without contacting the Si substrate 150. The Si layer 16 functions as a buffer layer (buffer layer) between the SiGe layer 13 and the Si substrate 150.

  Since the SiGe layer 13 is not directly deposited on the Si substrate 150 as in the present embodiment, damage to the crystal of the Si substrate 150 that occurs during the formation of the trench RX is caused by the crystallinity of the SiGe layer 13 provided in the trench RX. Can be adversely affected. Further, since the Si layer 16 is interposed between the SiGe layer 13 and the Si substrate 150, the Si layer 16 becomes a buffer layer, and the SiGe layer 13 caused by the difference in thermal expansion coefficient or lattice constant between SiGe and Si. Deterioration of crystallinity can be suppressed. As a result, the crystallinity of the SiGe layer 13 used for the embedded photodiode 1Z can be improved.

  Note that the Si layer 16 as a buffer layer may be provided in the trench RX with respect to the Si layer embedded in the trench RX as in the first embodiment.

  As described above, according to the solid-state imaging device of the third embodiment, the same effects as those of the first and second embodiments can be obtained, and the characteristics of the photodiode can be improved.

(B) Manufacturing Method A method of manufacturing the image sensor according to the third embodiment will be described with reference to FIGS. In addition, the description regarding the process substantially the same as the manufacturing method described in 1st Embodiment is given as needed.

  As shown in FIG. 12, a trench RX having a predetermined depth is formed in the p-type Si substrate 150. Then, the Si layer 16A is deposited on the Si substrate 150 by, for example, a CVD method so that the formed trench RX is not filled. The Si layer 16A is formed in the groove RX along the shape of the groove RX, and covers the exposed surface of the Si substrate 150 in the groove RX. The Si layer 16A immediately after formation may be an undoped Si layer, or an impurity (for example, phosphorus) may be added to the Si layer 16A during the deposition of the Si layer 16A.

  The Si layer 16A is formed in the groove RX so that the Si layers 16A on the inner side surface of the groove RX facing the Si substrate surface in the horizontal direction do not contact each other. Further, the Si layer 16A is formed so that the opening of the trench RX is not blocked by the Si layer 16A. For example, the film thickness of the Si layer 16A on the inner surface of the groove RX in the horizontal direction with respect to the surface of the Si substrate 150 is such that the dimension (opening width) of the opening of the groove RX in the horizontal direction with respect to the surface of the Si substrate 150. The Si layer 16A is deposited so as to be smaller than half of the above.

  Then, the SiGe layer 13A containing the n-type dopant is deposited on the Si layer 16A in the trench RX by, for example, a CVD method at a deposition temperature of about 600 ° C. to 700 ° C. The SiGe layer 13A is embedded in the trench RX via the Si layer 16A. An n-type dopant such as phosphorus or arsenic is added into the SiGe layer 13A during the deposition of the SiGe layer 13A.

  As shown in FIG. 13, the SiGe layer and the Si layer are etched so that the top surfaces of the SiGe layer and the Si layer are set back from the surface of the Si substrate 150 toward the back side of the Si substrate 150. Accordingly, the upper ends of the SiGe layer 13 and the Si layer 16 are located on the back side of the Si substrate 150 with respect to the opening of the trench RX.

  An n-type Si layer 10 is deposited on the SiGe layer 13 and the Si layer 16 in the trench RX. On the n-type Si layer 10, an undoped Si layer 11A is deposited.

  If the Si layer 16 as the buffer layer is formed between the SiGe layer 13 and the Si substrate 150, the upper end of the SiGe layer 13 and the n-type Si layer 14 and the undoped Si layer 11A are not formed. The SiGe layer 13 and the Si layer 16 may be formed inside the trench RX so that the upper end of the Si layer 16 as the buffer layer coincides with the surface of the Si substrate.

  In the present embodiment, after the upper surface of the SiGe layer 13 in the groove RX is retreated from the surface of the Si substrate 151 toward the bottom of the Si substrate 150, the n-type Si layer 14 and the undoped Si layer 11A are formed in the groove RX. An example of deposition on the upper surface of the SiGe layer 13 is shown. However, the n-type Si layer and the undoped Si layer may be continuously formed on the SiGe layer 13 deposited so as not to fill the trench RX.

  Thereafter, as shown in FIG. 11, similarly to the manufacturing process described in the first embodiment, after the upper surface of the undoped Si layer 11 </ b> A matches the upper surface of the Si substrate 150, Heat treatment is performed, and the n-type dopant included in the Si layers 14 and 16 is thermally diffused into the Si substrate 150 and the undoped upper Si layer 11. Thereby, impurity semiconductor regions 113 and 151 are formed in the upper Si layer 11 and the Si substrate 150.

  Further, an impurity semiconductor layer 60 as a transfer gate (field effect transistor) 2 and a floating diffusion 6 is formed. After the interlayer insulating film and the metal film are sequentially formed, the color filter layer CF and the microlens array ML are formed at a position overlapping the pixel array 120 in the vertical direction.

  Through the above manufacturing process, an image sensor including the embedded photodiode 1 according to this embodiment is manufactured.

In the image sensor manufacturing method of the present embodiment, when the SiGe layer 13A is formed in the trench RX, the SiGe layer 13A is deposited on the Si layer 16A covering the exposed surface of the Si substrate 150 in the trench RX. . As a result, it is possible to reduce the damage caused to the exposed surface of the Si substrate 150 due to the formation of the trench RX from adversely affecting the SiGe layer 16A. Further, by forming the Si layer between the SiGe layer 13 and the Si substrate 150, the difference in thermal expansion coefficient and the lattice mismatch between the SiGe layer 13 and the Si substrate 150 can be alleviated.
As a result, the crystallinity of the SiGe layer 13 in the trench RX included in the embedded photodiode can be improved.

  Therefore, according to the method for manufacturing the solid-state imaging device of the third embodiment, it is possible to provide a solid-state imaging device including a photodiode having the same effects as those of the first and second embodiments and improved characteristics. .

(4) Modification
A modification of the photodiode included in the image sensors of the first to third embodiments will be described with reference to FIGS. In the present modification, the same components / functions as those of the image sensors of the first to third embodiments will be described as necessary.

FIG. 14 is a cross-sectional view showing one modification of the photodiode included in the image sensor of the embodiment.
As illustrated in FIG. 14, when the aspect ratio of the trench RX in which the impurity semiconductor layers 10 and 11 of the photodiode 1 are embedded increases, the cross-sectional shape of the trench RX may be tapered. In this case, the dimension D3 of the bottom of the groove RX in the horizontal direction with respect to the surface of the Si substrate 150 is smaller than the dimension D1 of the opening of the groove RX in the horizontal direction with respect to the surface of the Si substrate 150.

  Depending on the shape of the trench RX, in the impurity semiconductor layer 10 embedded in the trench RX, the dimension D3 of the impurity semiconductor layer 10 on the bottom side of the trench RX in the horizontal direction with respect to the surface of the semiconductor substrate is And smaller than the dimension D3 of the upper semiconductor layer 11 on the opening side of the groove RX in the horizontal direction.

FIG. 15 is a cross-sectional view showing one modification of the photodiode included in the image sensor of the embodiment.
For example, in the upper Si layer 11 of the photodiode 1Y, an n ⁻ type impurity caused by diffusion of a dopant included in a p type impurity semiconductor region (p type Si region) 111 and an n type Si layer (or n type SiGe layer). A semiconductor region 115 different from the p-type or n ⁻ -type impurity semiconductor regions 111, 113 may be provided between the semiconductor region 113. The semiconductor region 115 between the two semiconductor regions 111 and 113 of the upper Si layer 11 may be an intrinsic semiconductor region (for example, an i-type Si region) resulting from the formation of an undoped Si layer, or an n-type Si layer (or An n ⁺ -type impurity semiconductor region (for example, an n ⁺ -type Si region) including an impurity concentration of an n-type dopant higher than that of the (n-type SiGe layer) may be used. The semiconductor region 115 in the upper Si layer 11 may be a p-type Si region containing a higher or lower p-type dopant impurity concentration than the p-type Si region 111 as the surface shield layer.

FIG. 16 is a cross-sectional view showing one modification of the photodiode included in the image sensor of the embodiment.
As shown in FIG. 16, the embedded photodiode 1X using the SiGe layer 13 described in the second or third embodiment is replaced with the embedded photodiode 1 using the Si layer described in the first embodiment. And may be provided in the same Si substrate 150.

  In this case, the photodiode 1X using the SiGe layer 13 is provided at a predetermined position of the pixel array so as to correspond to the red filter of the color filter layer, and the photodiode 1 using the Si layer 10 is a color filter. It is provided at a predetermined position of the pixel array so as to correspond to the blue filter of the layer. In the photodiode corresponding to the green filter of the color filter layer, the photodiode 1X using the SiGe layer 13 may be used, or the photodiode 1 using the Si layer 10 may be used.

  For example, in the photodiode 1X using the SiGe layer 13 and the photodiode 1 using the Si layer 10, the characteristics of the photodiode (for example, photoelectric conversion characteristics) and the processing difficulty are taken into consideration with respect to the surface of the Si substrate 150. The position of the bottom of the SiGe layer 13 (the bottom of the groove) in the vertical direction is set to substantially the same depth as the position of the bottom of the Si layer 10 (the bottom of the groove) in the vertical direction with respect to the surface of the Si substrate 150. They may be set at different positions.

  The SiGe layer may be formed by adding Ge into the Si layer by ion implantation.

  In each of the above-described embodiments, a structural example of a buried photodiode having a structure in which an n-type semiconductor layer is buried in a groove in a p-type semiconductor substrate (or a p-type semiconductor layer) is shown. However, the embedded photodiode of this embodiment may have a structure in which a p-type semiconductor layer is embedded in a groove in an n-type semiconductor substrate (or n-type well region).

  In each of the above-described embodiments, an example in which the photodiode with the embedded structure according to the present embodiment is used in a back-illuminated image sensor is shown. However, the photodiode with an embedded structure according to the present embodiment has a front-illuminated image. It may be used for a sensor. In the surface irradiation type image sensor, the surface side of a semiconductor substrate on which an interlayer insulating film and elements are formed serves as an irradiation surface of light from a subject, and a color filter and a macro lens array are stacked on the interlayer insulating film.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  120: pixel array, UC: unit cell, 9: element isolation region, 1: photodiode, 2: transistor (transfer gate), 6: floating diffusion, 150: semiconductor substrate, 10, 11: impurity semiconductor layer, 113, 151 : Impurity semiconductor region, RX: Groove.

Claims (6)

A semiconductor substrate including a pixel array;
A plurality of photodiodes provided in the pixel array;
A first filter corresponding to a color of a first wavelength band and a second filter corresponding to a color of a second wavelength band including a wavelength longer than the wavelength of the first wavelength band; A color filter layer provided at a position overlapping with the pixel array in a direction perpendicular to one surface;
Comprising
Each of the photodiodes includes a first semiconductor layer of a first conductivity type embedded in a groove in the semiconductor substrate, a second semiconductor layer provided on an upper surface of the first semiconductor layer, A first impurity region of the first conductivity type provided in the semiconductor substrate along the first semiconductor layer and the first semiconductor layer provided on the first semiconductor layer side in the second semiconductor layer. A second impurity region of a conductivity type of
The photodiode corresponds to any one of the first and second filters,
The depth of the trench in which the first semiconductor layer of the photodiode corresponding to the second filter is embedded is such that the first semiconductor layer of the photodiode corresponding to the first filter is embedded in the groove. Greater than the depth of the groove,
A solid-state imaging device. A semiconductor substrate including a pixel array;
A first semiconductor layer of a first conductivity type provided in the pixel array and embedded in a groove in the semiconductor substrate; and the first semiconductor layer provided in the semiconductor substrate along the first semiconductor layer. A plurality of photodiodes each including a first impurity region of one conductivity type;
A solid-state imaging device comprising: Each photodiode is
A second semiconductor layer provided on an upper surface of the first semiconductor layer;
The solid-state imaging device according to claim 2, further comprising: a second impurity region of the first conductivity type provided on the first semiconductor layer side in the second semiconductor layer.   4. The solid-state imaging device according to claim 1, wherein the first semiconductor layer is a SiGe layer. 5.   5. The solid state according to claim 1, wherein each of the photodiodes further includes a third semiconductor layer provided between the first semiconductor layer and the semiconductor substrate. Imaging device. A first filter corresponding to a color of a first wavelength band and a second filter corresponding to a color of a second wavelength band including a wavelength longer than the wavelength of the first wavelength band; A color filter layer provided at a position overlapping with the pixel array in a direction perpendicular to one surface;
Further comprising
The depth of the trench in which the first semiconductor layer of the photodiode corresponding to the second filter is embedded is such that the first semiconductor layer of the photodiode corresponding to the first filter is embedded in the groove. Greater than the depth of the groove,
The solid-state imaging device according to claim 2, wherein the solid-state imaging device is provided.

Images