JP2014053431A - Manufacturing method of solid-state imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce manufacturing cost.SOLUTION: The manufacturing method of the solid-state imaging apparatus comprises the steps of: forming an interlayer insulation film 92 including an image sensor element and wiring on a first surface of a first epitaxial layer 53A which is the top layer, among the first to a third epitaxial layers laminated on a bulk substrate 50; removing the bulk substrate 50 using the third epitaxial layer 51A between the second epitaxial layer 52Z and the bulk substrate 50 as a stopper, after attaching a support substrate 119 on the interlayer insulation film 92; and removing the third epitaxial layer 51A so that the second epitaxial layer 52Z may remain on the second surface of the first epitaxial layer 53A, and forming a shield layer 19 which consists of the remained second epitaxial layer 52Z on the second surface of the first epitaxial layer 53A.

Description

  Embodiments described herein relate generally to a method for manufacturing a solid-state imaging device.

  Solid-state imaging devices such as CCD image sensors and CMOS image sensors are used in various applications such as digital still cameras, video cameras, and surveillance cameras. Single-plate image sensors that acquire a plurality of pieces of color information with a single pixel array have become mainstream.

  In recent years, development of a backside illuminated image sensor that takes in light from a subject from the backside of a semiconductor substrate has been promoted.

JP 2010-92988 A

  A technique for reducing the manufacturing cost of a solid-state imaging device is proposed.

  The manufacturing method of the solid-state imaging device according to the present embodiment includes the first, second, and third epitaxial layers stacked on the bulk substrate on the first surface of the uppermost first epitaxial layer. After forming an image sensor element, forming an interlayer insulating film including wiring on the first surface of the first epitaxial layer, and pasting a support substrate on the interlayer insulating film Removing the bulk substrate using the third epitaxial layer between the second epitaxial layer and the bulk substrate as a stopper, and between the first and third epitaxial layers. The third epitaxial layer is removed so that the second epitaxial layer remains on the second surface opposite to the first surface of the first epitaxial layer, and the remaining second No A step of the shielding layer is formed on the second surface of the first epitaxial layer made of Takisharu layer, the shield layer in the second surface, and forming a color filter, a.

The top view which shows an example of the layout of the chip | tip of a solid-state imaging device. Sectional drawing which shows an example of the structure of a solid-state imaging device. The equivalent circuit diagram which shows the circuit structure of a pixel array and the pixel array vicinity. FIG. 3 is a schematic diagram for explaining a method for manufacturing the solid-state imaging device according to the first embodiment. Sectional process drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 1st Embodiment. Sectional process drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 1st Embodiment. Sectional process drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 1st Embodiment. Sectional process drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 1st Embodiment. Sectional process drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 1st Embodiment. FIG. 6 is a schematic diagram for explaining a method for manufacturing a solid-state imaging device according to a second embodiment. The figure for demonstrating the manufacturing method of the solid-state imaging device of 2nd Embodiment. Sectional process drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 2nd Embodiment. Sectional process drawing which shows 1 process of the manufacturing method of the solid-state imaging device of 2nd Embodiment. The figure for demonstrating the modification of the manufacturing method of the solid-state imaging device of embodiment. The figure for demonstrating the example of application of the solid-state imaging device of embodiment.

[Embodiment]
Hereinafter, this embodiment will be described in detail with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given as necessary.

(1) First embodiment
A solid-state imaging device and a method for manufacturing the same according to the first embodiment will be described with reference to FIGS.

(A) Structure
The structure of the solid-state imaging device according to the first embodiment will be described with reference to FIGS. 1 to 5.

  FIG. 1 is a schematic diagram illustrating a chip layout example of a solid-state imaging device (hereinafter referred to as an image sensor) of the present embodiment. FIG. 2 is a cross-sectional view schematically showing the structure of the image sensor of the present embodiment.

  As shown in FIGS. 1 and 2, in the image sensor 100 of the present embodiment, a peripheral circuit region 121 where a pixel array 120 and an analog circuit or a logic circuit for controlling the pixel array 120 are formed is formed on one semiconductor substrate ( Chips) 52Z and 53A.

  The pixel array 120 includes a plurality of unit cells UC. Unit cells (and unit cell regions) UC are arranged in a matrix in the pixel array 120.

  Each unit cell UC includes a photoelectric conversion element for converting light from the subject (light from the outside) into an electrical signal. One unit cell UC includes at least one photoelectric conversion element. A pixel is formed using a photoelectric conversion element.

  The unit cells UC adjacent to each other and the photoelectric conversion elements adjacent to each other are separated by an element isolation region (element isolation layer) 9. The formation region of each unit cell UC and each photoelectric conversion element is surrounded by the element isolation region 9.

  The photoelectric conversion element 1 is formed using, for example, a photodiode. As shown in FIG. 2, the photodiode 1 is formed using at least one impurity layer 10 in the semiconductor substrates 52Z and 53A. The photodiode 1 photoelectrically converts light from the subject into an electrical signal (charge, voltage) corresponding to the amount of light. The photodiode 1 can accumulate charges generated in the impurity layer 10 in accordance with the amount of light.

  An impurity layer 60 as a floating diffusion (floating diffusion layer, detection unit) 6 is provided in the semiconductor substrates 52Z and 53A. The impurity layer 60 as the floating diffusion 6 holds the charge output from the photodiode 1 via the field effect transistor 2 described later.

  Between the photodiode 1 and the floating diffusion 6, the field effect transistor 2 is provided on the semiconductor substrates 52Z and 53A. The gate electrode 21 of the field effect transistor 2 is provided on the channel regions in the semiconductor substrates 52Z and 53A with the gate insulating film 22 interposed therebetween.

  A CMOS sensor or a CCD sensor is configured using the unit cell UC. The unit cell UC may include other components in addition to the photodiode 1, the floating diffusion 6, and the transfer gate 2, depending on the circuit configuration of the image sensor. For example, the unit cell UC includes a field effect transistor called an amplifier transistor or a reset transistor as a constituent element.

  FIG. 3 is a diagram illustrating a circuit configuration example of the pixel array 120 and circuits in the vicinity thereof.

  The unit cells UC arranged in a matrix in the pixel array 120 are provided at intersections between the read control lines TRF and the vertical signal lines VSL.

  The plurality of unit cells UC arranged along the row direction of the pixel array 120 are connected to a common read control line TRF. A plurality of unit cells UC arranged along the column direction of the pixel array 120 are connected to a common vertical signal line VSL.

  For example, each unit cell UC includes four field effect transistors 2, 3, 4 and 5 in order to control the operation of the unit cell UC and the photodiode 1. In the example shown in FIG. 3, the four field effect transistors 2, 3, 4, and 5 included in the unit cell UC are a transfer gate (read transistor) 2, an amplifier transistor 3, a reset transistor 4, and an address transistor 5. Each field effect transistor 2, 3, 4, 5 is, for example, an N-channel MOS transistor.

  The elements 1, 2, 3, 4, and 5 in the unit cell UC are connected as follows.

  The anode of the photodiode 1 is grounded, for example. The cathode of the photodiode 1 is connected to the floating diffusion 6 through the current path of the transfer gate 2.

  The transfer gate 2 controls the accumulation and transfer of signal charges photoelectrically converted by the photodiode 1. The gate of the transfer gate 2 is connected to the read control line TRF. One end of the current path of the transfer gate 2 is connected to the cathode of the photodiode 1, and the other end of the current path of the transfer gate 2 is connected to the floating diffusion 6.

  The amplifier transistor 3 detects and amplifies the signal (potential) of the floating diffusion 6. The gate of the amplifier transistor 3 is connected to the floating diffusion 6. One end of the current path of the amplifier transistor 3 is connected to the vertical signal line VSL, and the other end of the current path of the amplifier transistor 3 is connected to one end of the current path of the address transistor 5. The signal amplified by the amplifier transistor 3 is output to the vertical signal line VSL. The amplifier transistor 3 functions as a source follower.

  The reset transistor 4 resets the potential of the floating diffusion 6 (signal charge holding state). The gate of the reset transistor 4 is connected to the reset control line RST. One end of the current path of the reset transistor 4 is connected to the floating diffusion 6, and the other end of the current path of the reset transistor 4 is connected to the power supply terminal 135.

  The address transistor 5 controls the activation of the unit cell UC. The gate of the address transistor 5 is connected to the address control line ADR. One end of the current path of the address transistor 5 is connected to the other end of the current path of the amplifier transistor 3, and the other end of the current path of the address transistor 5 is connected to the power supply terminal 135.

  The power supply terminal 135 is connected to a drain power supply, a ground power supply, or a unit cell (reference potential cell) in the optical black region.

  In the present embodiment, a configuration in which one unit cell UC includes one photodiode 1 as a pixel is referred to as a one-pixel one-cell structure.

  The vertical shift register 133 is connected to the read control line TRF, the address control line ADR, and the reset control line RST. The vertical shift register 133 controls the potentials of the read control line TRF, the address control line ADR, and the reset control line RST, and controls and selects a plurality of unit cells UC in the pixel array 120 in units of rows. The vertical shift register 133 outputs a control signal (voltage pulse) for controlling on and off of the transistors 2, 4, and 5 to the control lines TRF, ADR, and RST.

  The AD conversion circuit 131 is connected to the vertical signal line VSL. The AD conversion circuit 131 includes a processing unit 132 that converts an analog signal from the unit cell UC into a digital signal and performs a CDS (Corrected Double Sampling) process on the signal from the unit cell UC. .

  The load transistor 134 is used as a current source for the vertical signal line VSL. The gate of the load transistor 134 is connected to the selection line SF. One end of the current path of the load transistor 134 is connected to one end of the current path of the amplifier transistor 3 via the vertical signal line VSL. The other end of the current path of the load transistor 134 is connected to the control line DC.

  The read operation of the signal (charge) from the unit cell UC of the pixel array 120 is executed as follows, for example.

A predetermined row of the pixel array 120 is selected by the vertical shift register 133.
The address transistor 5 belonging to the selected row is turned on under the control of the address control line ADR by the vertical shift register 133. The reset transistor 4 is turned on by the control of the reset control line RST by the vertical shift register 133. The floating diffusion 6 is connected to the power supply terminal 135 via the reset transistor 4 in the on state. As a result, the floating diffusion 6 is reset.

  The potential of the vertical signal line VSL is changed to a voltage (reset voltage) corresponding to the potential of the floating diffusion 6 in the reset state by the amplifier transistor 3 forming the source follower. The reset voltage is input to the AD conversion circuit 131. After the reset voltage is sampled by the AD conversion circuit 131, the reset transistor 4 is turned off.

  The transfer gate 2 is turned on under the control of the read control line TRF by the vertical shift register 133, and the charge (signal charge) accumulated in the photodiode 1 is transferred to the floating diffusion 6. The potential of the floating diffusion 6 is modulated according to the number of signal charges transferred from the photodiode 1.

  By the amplifier transistor 3 forming the source follower, the potential of the vertical signal line VSL is changed to a magnitude corresponding to the potential (signal voltage) of the modulated floating diffusion. A signal voltage corresponding to light from the subject is sampled by the AD conversion circuit 131.

  The reset voltage and signal voltage from each unit cell UC belonging to a common row are sequentially converted from an analog value to a digital value by each processing unit 132 of the AD conversion circuit 131, or CDS processing is performed on the reset voltage and the signal voltage. To do. A difference value between the reset voltage and the signal voltage from each unit cell UC is output as pixel data Dsig to a subsequent circuit (for example, an image processing circuit).

  Thus, the signal reading operation from the plurality of unit cells (pixels) belonging to the predetermined row is completed. Such a row-by-row readout operation for the pixel array 120 is sequentially repeated to form a predetermined image.

  Each unit cell UC may not include the address transistor 5. In this case, in the unit cell UC, the other end of the current path of the reset transistor 4 is connected to the other end of the current path of the amplifier transistor 3. When the unit cell UC does not include the address transistor 5, the address signal line ADR is not provided.

  The unit cell UC may have a circuit configuration in which one unit cell includes two or more pixels (photodiodes) such as a 2-pixel 1-cell structure, a 4-pixel 1-cell structure, or an 8-pixel 1-cell structure. In a unit cell including a plurality of pixels, two or more photodiodes share one floating diffusion 6, reset transistor 4, amplifier transistor 3, and address transistor 5. In a unit cell including a plurality of pixels, one transfer gate is provided for each photodiode.

  As shown in FIGS. 1 and 2, the peripheral circuit region 121 is provided in the semiconductor substrates 52Z and 53A so as to be adjacent to the pixel array 120 with the element isolation region interposed therebetween.

  In the peripheral circuit area 121, a circuit for controlling the operation of the pixel array 120 such as the vertical shift register 133 described above and a circuit for processing a signal from the pixel array 120 such as the AD conversion circuit 131 are provided. .

  The peripheral circuit region 121 is electrically isolated from the pixel array 120 by the element isolation region. In an element isolation region for partitioning the peripheral circuit region 121, for example, an element isolation insulating film 91 having an STI structure is embedded.

  The circuit in the peripheral circuit region 121 is formed using a plurality of elements such as the field effect transistor 7, a resistance element, and a capacitor element. In FIG. 2, only the field effect transistor 7 is shown for simplicity of illustration. In FIG. 2, only one field effect transistor is shown, but a plurality of transistors for forming peripheral circuits are provided on the semiconductor substrates 52Z and 53A.

  For example, in the peripheral circuit region 121, the field effect transistor (for example, MOS transistor) 7 is provided in the well region 159 in the semiconductor substrates 52Z and 53A. Two diffusion layers (impurity layers) 73 are provided in the well region 159. These two diffusion layers 73 function as the source / drain of the transistor 7. A gate electrode 71 is provided on the surface of the well region (channel region) between the two diffusion layers 73 via the gate insulating film 72. As a result, the field effect transistor 7 is formed in the well region 159.

  Whether the field effect transistor 7 is a P-channel type or an N-channel type depends on the conductivity type of the well region 159 in which the transistor 7 is provided and the conductivity type of the diffusion layer 73 serving as the source / drain.

  A plurality of interlayer insulating films 92 are stacked on the semiconductor substrates 52Z and 53A so as to cover the gate electrodes 21 and 71 of the transistors 2 and 7 and the upper surface of the photodiode 1. For example, silicon oxide is used for the interlayer insulating film 92.

  A multilayer wiring technique is used for the image sensor 100 of the present embodiment. That is, a plurality of wirings 80 are provided in the laminated interlayer insulating film 92 according to each wiring level (height with respect to the substrate surface). Each wiring 80 is electrically connected to another wiring located at a different wiring level by plugs 81, CP 1, CP 2 embedded in the interlayer insulating film 92. Note that the wiring 80 includes a dummy layer (for example, a light shielding film) that is not connected to the element and the circuit.

  The terminals of the elements formed on the gate electrodes 21 and 71, the source / drain 73, and the semiconductor substrates 52Z and 53A of the transistors 2 and 7 are connected to the wiring 80 in the interlayer insulating film 92 through the contact plugs CP1 and CP2. Is done. The lower wiring 80 and the upper wiring 80 are connected to a plurality of elements provided on the semiconductor substrates 52Z and 53A via via plugs 81 embedded in the interlayer insulating film 92. Thus, a plurality of circuits are formed by the multilayer wiring technique.

  In the present embodiment, the surface on which the element is formed, more specifically, the surface of the semiconductor substrates 52Z and 53A on which the gate electrodes 21 and 71 of the transistors 2 and 7 are provided is the surface of the semiconductor substrates 52Z and 53A ( The first side). On the surfaces of the semiconductor substrates 52Z and 53A, an interlayer insulating film 92 and wirings 80 formed by a multilayer wiring technique are provided. A surface (surface opposite to the surface) facing the surfaces of the semiconductor substrates 52Z and 53A in a direction perpendicular to the surfaces of the semiconductor substrates 52Z and 53A is referred to as a back surface (second surface). When the front and back surfaces of the semiconductor substrates 52Z and 53A are not distinguished, the front / back surfaces of the semiconductor substrates 52Z and 53A are called main surfaces of the semiconductor substrates 52Z and 53A.

  For example, vias (through vias or through electrodes) 88A pass through the semiconductor substrates 52Z, 53A from the front side to the back side of the semiconductor substrates 52Z, 53A by TSV (Through Substrate Via) technology. 53A is formed. The through via 88A is embedded in a through hole (opening) formed in the semiconductor substrates 52Z and 53A. An insulating layer 98A is provided on the inner surface of the through hole, and the through via 88A is electrically separated from the semiconductor substrates 52Z and 53A by the insulating layer 98A.

  The through via 88A is connected to the wiring 80 in the interlayer insulating film 92 via the contact plug CP2. The through via 88A is connected to a pad (electrode) 89 provided on the back side of the semiconductor substrates 52Z and 53A. The pad 89 is provided on an insulating layer (planarization layer or protective film) 97 on the back surfaces of the semiconductor substrates 52Z and 53A. The pad 89 is electrically isolated from the semiconductor substrates 52Z and 53A by the insulating layer 97.

  In the present embodiment, as shown in FIG. 2, a color filter 117 is provided on the back side of the semiconductor substrates 52Z and 53A via, for example, a protective layer (not shown) or an adhesive layer (not shown). . The color filter 117 is provided at a position corresponding to the pixel array 120 on the back side of the semiconductor substrates 52Z and 53A. For example, the image sensor 100 of the present embodiment is a single-plate image sensor 100. The single-plate image sensor acquires a plurality of pieces of color information with a single pixel array 120. The color filter 117 has a plurality of dye films corresponding to a plurality of color information.

  The microlens array 118 is attached on the color filter 117 via a protective layer (not shown) and an adhesive layer (not shown). The microlens array 117 is provided at a position overlapping the pixel array 120 in the direction perpendicular to the main surfaces of the semiconductor substrates 52Z and 53A via the color filter 117. The microlens array 117 is formed by two-dimensionally arranging microlenses corresponding to one pixel (photodiode 1). Each microlens collects light from the subject onto the photodiode 1.

  In the image sensor 100 of the present embodiment, the microlens array 118 and the color filter 117 are opposite to the surface (surface) on which the gate electrodes 21 and 71 of the transistors 2 and 7 and the interlayer insulating film 92 are provided (surface). On the back). The semiconductor substrates 52Z and 53A on which the elements are formed are sandwiched between the interlayer insulating film 92 and the microlens array 118.

  Light from the subject is irradiated to the pixel array 120 from the back side of the semiconductor substrates 52Z and 53A via the microlens array 118 and the color filter 117, and taken into the photodiode 1.

  The support substrate 119 is provided on the interlayer insulating film 92. The support substrate 119 is stacked on the interlayer insulating film 92 via, for example, a protective layer (not shown) and an adhesive layer (not shown). For example, a silicon substrate or an insulating substrate is used as the support substrate 119.

In the present embodiment, the light receiving surface (irradiation surface) of light from the subject is the back surface of the semiconductor substrates 52Z and 53A to which the microlens array 118 is attached.
An image sensor having a structure in which light from the back surface side of the semiconductor substrates 52Z and 53A is irradiated onto the pixels 1 as in the image sensor 100 of the present embodiment is called a back-illuminated image sensor.

  The color filter 117 is provided on the back surfaces of the semiconductor substrates 52Z and 53A via the insulating film 95.

  In the single-plate image sensor, the color filter 117 includes a plurality of dye films. The color filter 117 includes, for example, red, blue, and green pigment films. In each dye film, one color dye film is provided in the color filter 117 so as to correspond to one photodiode 1 (pixel). The color film of each color is arranged in the color filter 117 so as to have a Bayer pattern layout, for example. The color filter 117 may include a yellow or white filter in addition to red, green, and blue.

  In the microlens array 118, each microlens is provided on each dye film so that one microlens corresponds to one unit cell UC and the photodiode 1.

  The image sensor of this embodiment is formed using a semiconductor substrate including three epitaxial layers.

  FIG. 4 is a diagram showing a configuration of a semiconductor substrate used for forming the image sensor of the present embodiment.

  As shown in FIG. 4, in the semiconductor substrate 5A before the image sensor is formed, three epitaxial layers 51A, 52, and 53A are provided on a silicon bulk substrate (silicon single crystal substrate) 50. . Each epitaxial layer 51A, 52, 53A is made of a silicon layer.

  The silicon bulk substrate 50 is, for example, a P-type silicon substrate. In the present embodiment, each of the epitaxial layers 51A, 52, 53A is a P-type silicon layer.

  In the following, for clarity of explanation, of the three epitaxial layers stacked on the bulk substrate 50, the epitaxial layer in contact with the bulk substrate 50 (here, the layer 51A) is referred to as the lowermost epitaxial layer. The epitaxial layer (here, the layer 53A) provided on the side opposite to the bulk substrate 50 side is referred to as the uppermost epitaxial layer. An epitaxial layer sandwiched between the uppermost layer and the lowermost epitaxial layer (here, the layer 52) is referred to as an intermediate epitaxial layer.

  In each epitaxial layer 51A, 52, 53, the surface on the bulk substrate 50 side is referred to as the back surface of the epitaxial layer, and the surface opposite to the surface on the bulk substrate 50 side (opposite side) is the surface of the epitaxial layer. Call it.

In the semiconductor substrate 5A before the image sensor is formed, each epitaxial layer 51A, 52, 53A has the following film thickness.
The film thickness of the lowermost epitaxial layer 51A in contact with the bulk substrate 50 is set to about 0.9 μm to 1.3 μm, for example.

  The film thickness of the intermediate epitaxial layer 52 in contact with the lowermost epitaxial layer 51A is set to about 0.30 μm to 0.40 μm, for example.

  The film thickness of the uppermost epitaxial layer 53A in which the element is formed is set to, for example, about 3.0 μm to 4.0 μm.

  In the semiconductor substrate 5A before the image sensor is formed, each epitaxial layer 51A, 52, 53A has the following impurity concentration.

The concentration of the P-type dopant in the lowermost epitaxial layer 51A is set to, for example, about 1 × 10 ¹⁴ cm ^{−3 to} about 1 × 10 ¹⁶ cm ⁻³ .
The concentration of the P-type dopant in the intermediate epitaxial layer 52 is set to, for example, about 1 × 10 ¹⁸ cm ^{−3 to} about 1 × 10 ²⁰ cm ⁻³ .
The concentration of the P-type dopant in the uppermost epitaxial layer 53A is set, for example, from about 1 × 10 ¹⁵ cm ^{−3 to} about 1 × 10 ¹⁷ cm ⁻³ .

  The impurity concentration of the intermediate epitaxial layer 52 is lower than the impurity concentration of the lowermost layer and the uppermost epitaxial layers 51A and 53A.

  Thus, the three epitaxial layers 51A, 52, 53A on the bulk substrate 50 have different impurity concentrations. Further, the bulk substrate 50 and the epitaxial layer 51A in contact with the bulk substrate 50 have different impurity concentrations.

  The etching rate (etching rate) between the epitaxial layers 51A, 52, and 53A is adjusted by the difference in impurity concentration between the epitaxial layers 51A, 52, and 53A. As a result, the etching selectivity between the epitaxial layers 51A, 52, 53A can be ensured.

  Further, the etching rate between the bulk substrate 50 and the epitaxial layer 51A is adjusted by the difference in impurity concentration between the bulk substrate 50 and the epitaxial layer 51A. As a result, the epitaxial layer 51A can function as an etching stopper under the etching conditions (for example, wet etching conditions) for the bulk substrate 50.

  Note that a large etching selectivity is ensured between the bulk substrate 50 and the epitaxial layer 51A so that the lowermost epitaxial layer 51A in contact with the bulk substrate 50 functions as a stopper layer with respect to the etching conditions of the bulk substrate 50. If so, the impurity concentration of the P-type dopant in the epitaxial layer 51 </ b> A may be higher than the impurity concentration of the P-type dopant in the bulk substrate 50. However, the impurity concentration of the lowermost epitaxial layer 51A is preferably different from the impurity concentration of the intermediate epitaxial layer 52.

As shown in FIGS. 2 and 4, the elements forming the image sensor such as the photodiode 1 and the transistors 2 and 7 are formed of the three epitaxial layers 51 </ b> A, 52 and 53 </ b> A stacked on the bulk substrate 50. In the uppermost epitaxial layer 53A and on the epitaxial layer 53A. On the surface of the epitaxial layer 53A, an interlayer insulating film 92 including the wiring 80 by the multilayer wiring technique is formed.
Hereinafter, of the three epitaxial layers 51A, 52, and 53A stacked on the bulk substrate 50, the uppermost epitaxial layer 53A on which the component (element) of the image sensor is formed is clarified. Therefore, it may be called an element formation layer.

As in the image sensor manufacturing method of the present embodiment described later, an image sensor element is formed on the uppermost epitaxial layer (P ^- type epitaxial layer) 53A, and the surface of the epitaxial layer 53A (the surface of the semiconductor substrate). ) After the formation of the interlayer insulating film 92 and the attachment of the support substrate 119 to the interlayer insulating film 92, a part of the bulk substrate 50 and the lowermost epitaxial layer (P ⁻ type epitaxial layer) 51A is, for example, wet etched Is removed.

Further, the remaining portion of the lowermost epitaxial layer 51A and a portion of the intermediate epitaxial layer 52 are removed using, for example, CMP (Chemical Mechanical Polishing). As a result, the film thickness of the intermediate epitaxial layer (P ⁺ -type epitaxial layer) 52 is reduced.

The intermediate epitaxial layer 52 remaining on the back surface of the epitaxial layer 53A as the element forming layer is used as the back shield layer 19 made of a P ⁺ -type impurity layer.

  As in the present embodiment, the image sensor is formed by using the epitaxial layers 51A, 52, 53A having a three-layer structure stacked on the bulk substrate 50, whereby the manufacturing cost of the image sensor can be reduced.

(B) Manufacturing method
A manufacturing method of the solid-state imaging device (for example, an image sensor) according to the first embodiment will be described with reference to FIGS.
5 to 9 are sectional process diagrams of the pixel array 120 and the peripheral circuit region 121 in each process of the image sensor manufacturing method of the present embodiment. Here, in addition to FIGS. 5 to 9, FIGS. 2 and 4 are also used as appropriate to describe each step of the method of manufacturing the image sensor of the present embodiment.
In the image sensor manufacturing method of the present embodiment, the order of forming each component described later may be changed as appropriate as long as process consistency is ensured.

  As shown in FIG. 5, a semiconductor substrate 5A including a bulk substrate 50 and three epitaxial layers 51A, 52, 53A stacked on the bulk substrate 50 is prepared.

The bulk substrate 50 is a P-type silicon single crystal substrate. The impurity concentration of the P-type dopant (for example, boron) in the P-type silicon single crystal substrate is about 10 ¹⁸ cm ⁻³ (resistance value: 10 to ²⁰ mOhm).

  Three P-type silicon layers 51A, 52, and 53A are sequentially formed on the P-type silicon single crystal substrate 50 by epitaxial growth.

The lowermost epitaxial layer 51A has, for example, a thickness of 1.1 μm and includes a P-type dopant of about 1 × 10 ¹⁴ cm ^{−3 to} about 1 × 10 ¹⁶ cm ⁻³ so as to include the bulk substrate 50. Formed on top.

The second epitaxial layer 52 has, for example, a thickness of 0.35 μm and includes a P-type dopant of about 1 × 10 ¹⁸ cm ^{−3 to} about 1 × 10 ²⁰ cm ^−3. It is formed on the lower epitaxial layer 51A.

The uppermost epitaxial layer 53A has, for example, two layers so as to have a thickness of 3.5 μm and include a P-type dopant of about 1 × 10 ¹⁵ cm ^{−3 to} about 1 × 10 ¹⁷ cm ^−3. It is formed on the first (intermediate) epitaxial layer 52.

  A P-type dopant (for example, boron) for each epitaxial layer 51A, 52, 53A may be added by doping during epitaxial growth of each layer 51A, 52, 53 (in-situ doping), or by ion implantation after epitaxial growth. It may be added.

  The P-type dopant added to the epitaxial layers 51A, 52, 53A is formed at the time of forming the semiconductor substrate 5A including the epitaxial layers 51A, 52, 53A, in other words, before forming the image sensor elements and wirings on the semiconductor substrate 5A. Activated.

  The bulk substrate 50 may be N-type or P-type, but it is preferable to use a P-type silicon single crystal substrate as the bulk substrate 50 in view of impurity gettering.

As shown in FIG. 5, using a mask (not shown) formed by photolithography and RIE (Reactive Ion Etching), element isolation layers 90 and 91 are formed as epitaxial layers 51A, 52, and 53A on a semiconductor substrate 5A. Formed in a predetermined region.
An element isolation trench having an STI (Shallow Trench Isolation) structure is formed in the semiconductor substrate 5A based on the mask, and an insulator is embedded in the element isolation trench by a CVD (Chemical Vapor Deposition) method or a coating method. Thereby, the element isolation insulating film 91 having the STI structure is formed at a predetermined position in the semiconductor substrate 5A.
For example, the element isolation layer 90 made of an impurity semiconductor layer is formed at a predetermined position (for example, in the pixel array 120) in the epitaxial layer 51A by ion implantation based on the formed mask.

  As a result, the pixel array 120, the unit cell region UC in the pixel array 120, and the peripheral circuit region 121 are partitioned in the epitaxial layers 51, 52, 53 A on the bulk substrate 50.

  An N-type or P-type well region is formed in a predetermined region in the semiconductor substrate 5A using a mask different from the mask for forming the element isolation layer.

  Elements included in the image sensor are formed in the unit cell region of the pixel array 120 and the well region 159 of the peripheral circuit region 121.

The gate insulating films 22 and 72 of the transistors 2 and 7 are formed on the exposed surface (surface) of the uppermost epitaxial layer (element formation layer) 53A by, for example, thermal oxidation treatment on the semiconductor substrate 5A.
A polysilicon layer is deposited on the formed gate insulating films 22 and 72 by a CVD method. Then, the polysilicon layer is processed by photolithography and RIE, and the gate electrodes 21 and 71 having a predetermined gate length and a predetermined gate width are formed on the P ⁻ type epitaxial layer with the gate insulating films 22 and 72 interposed therebetween. It is formed on the surface of 53A.

As shown in FIG. 5, the gate electrode 22 and the resist film (not shown) formed in the pixel array 120 of the P ⁻ type epitaxial layer 53A are used as a mask, and the N type impurity layer of the photodiode 1 is used. 10 are formed in the photodiode formation region in the unit cell region by ion implantation.

In the floating diffusion formation region of the unit cell region, an impurity layer 60 as the floating diffusion 6 is formed in the P ⁻ type epitaxial layer 53A of the semiconductor substrate 5A by ion implantation.

  Impurity layers (not shown) such as amplifier transistors are formed as the source / drain of each transistor in the pixel array 120.

  In the surface layer (exposed surface) of the N-type impurity layer 10 of the photodiode 1, a P-type impurity layer 18 as a surface shield layer 18 is formed in the N-type impurity layer 10 by ion implantation.

  For example, the peripheral circuit region 121 is covered with a resist film (not shown) during a period in which ion implantation for forming the photodiode 1 and the floating diffusion 6 is performed in the pixel array 120.

The element isolation layer 90 formed of a P-type impurity layer formed in the pixel array 120 is used as the N-type impurity layer 10 of the photodiode 1, the well region for forming the transfer gate, and the N-type impurity layer 60 of the floating diffusion. As a result of the formation in the epitaxial layer 53A, the P ⁻ type epitaxial layer 53A may be used to form a self-alignment with respect to the formation region of the component of the unit cell.

  In a region (N-type or P-type well region) 159 in the peripheral circuit region 121 where the transistor 7 is formed, P-type or N-type as the source / drain of the transistor 7 by ion implantation using the gate electrode 72 as a mask. The impurity layer 73 is formed in the epitaxial layer 53A. Note that the process for forming the transistor 7 in the peripheral circuit region 121 may be shared with the process for forming the transistor in the pixel array 120.

  As shown in FIG. 6, a multilayer wiring including a plurality of interlayer insulating films 92 and a plurality of wirings 80 on the surface of the epitaxial layer 53A on which the gate electrodes 21 and 71 of the transistors 2 and 7 are formed by a multilayer wiring technique. A structure is formed. The interlayer insulating film 92 covers the surface side of the semiconductor substrate 5 </ b> A, for example, covers the gate electrode 21 of the transistor 2.

In the formation process at each wiring level of the multilayer wiring structure, the interlayer insulating film 92 and the wiring 80 are sequentially formed as follows.
For example, a silicon oxide interlayer insulating film 92 is deposited using a CVD method. At each wiring level, the deposited interlayer insulating film 92 is flattened by the CMP method, and then contact plug CP1 is formed in the contact hole formed in the interlayer insulating film 92 by photolithography and RIE. Alternatively, the via plug 81 is embedded.

  For example, a conductive layer containing aluminum, copper, or the like as a main component is deposited on the interlayer insulating film 92 and the plugs CP1, 81 by sputtering. The deposited conductive layer is processed into a predetermined shape so as to be connected to the plugs CP1 and 81 by photolithography and RIE. Thereby, a conductive layer 80 as a wiring is formed. Simultaneously with the formation of the conductive layer 80 as a wiring, a light shielding film and a dummy layer made of the same material are formed on the interlayer insulating film 90. The wiring 80 may be formed using a damascene method.

  As a result, the plurality of elements 1, 2, and 7 on the semiconductor substrate 5A are connected by the wiring of the multilayer wiring technique, and each circuit of the image sensor is formed.

  After the planarization process is performed on the interlayer insulating film 92 (and the conductive layer) on the uppermost layer (the layer opposite to the epitaxial layer side) on the surface side of the semiconductor substrate 5A, the uppermost interlayer insulating film 92 An adhesive layer (not shown) is formed on the planarized surface. Then, the support substrate 119 is attached on the adhesive layer. As a result, the support substrate 119 is bonded to the interlayer insulating film 92 covering the surface of the semiconductor substrate.

  For example, before the support substrate 119 is attached to the interlayer insulating film 92, the wiring formed by the rewiring technique is connected to the wiring in the interlayer insulating film 92 on the uppermost interlayer insulating film 92. It may be formed.

  As shown in FIG. 7, after the support substrate 119 is attached to the interlayer insulating film 92, the semiconductor substrate 5A is thinned.

  In the present embodiment, in the semiconductor substrate 5A including the three epitaxial layers 51Z, 52, 53A on the bulk substrate 50, the P-type silicon bulk substrate 50 is selectively removed by, for example, wet etching.

  For example, a part of the lowermost epitaxial layer on the bulk substrate 50 side is removed by wet etching on the bulk substrate 50. The lowermost epitaxial layer 51 </ b> Z that has not been etched remains on the back surface of the intermediate epitaxial layer 52.

For example, the portion of the lowermost P ⁻ -type epitaxial layer that is removed by wet etching with respect to the bulk substrate 50 is doped with impurities from the bulk substrate 50 to the P ⁻ -type epitaxial layer 51 (for example, the impurity concentration of the bulk substrate 50 (for example, 1 × 10 ¹⁸ cm ⁻³ ). Of the lowermost P ⁻ -type epitaxial layer, the portion 51Z having an impurity concentration sufficiently lower than the impurity concentration of the bulk substrate 50 is wet-etched with respect to the bulk substrate 50 due to the difference in etching rate (etching rate) caused by the difference in impurity concentration. It remains almost unetched by (etching solution).

The remaining low concentration (P ⁻ -type) epitaxial layer 51Z functions as a wet etching stopper for the bulk substrate 50. As a result, the back surface of the P ⁺ -type intermediate epitaxial layer 52 is not exposed to wet etching conditions for the bulk substrate 50.

  In this way, in consideration of the difference in impurity concentration between the bulk substrate 50 and the epitaxial layers 51A, 52, 53A, an etching solution for wet etching is selected, and the substrate 50 and the epitaxial layers 51A, 51A, The etching selectivity between 52 and 53A is adjusted. Thereby, the bulk substrate 50 is selectively removed by etching.

  By removing the bulk substrate by wet etching, it is possible to reduce variation in flatness on the back surface side of the semiconductor substrate (epitaxial layer) as compared with the case of removing the bulk substrate by CMP.

As shown in FIG. 8, after the bulk substrate 50 is removed, the remaining lowermost layer (bulk substrate side) epitaxial layer is ground and removed by CMP.
At this time, a part of the P ⁺ -type intermediate epitaxial layer 52Z is also ground by CMP, and the thickness of the epitaxial layer 52Z is reduced.

The CMP performed on the intermediate epitaxial layer 52Z is performed such that the portion of the P ⁺ type epitaxial layer 52Z that is in contact with the epitaxial layer 53A on the uppermost layer (interlayer insulating film side) remains in the uppermost epitaxial layer 53A. Is done.
For example, the intermediate epitaxial layer 52Z is cut by about 0.1 μm by CMP, and the film thickness of the intermediate epitaxial layer 52Z is made about 0.25 μm.

By CMP, the back surface of the second P ⁺ -type epitaxial layer 52Z is flattened, for example, mirror-shaped. By flattening the back surface of the epitaxial layer 52Z that is a light receiving surface for light from the subject, nonuniformity in element characteristics due to variations in flatness of the back surface of the epitaxial layer 52Z can be reduced.

The remaining P ⁺ -type epitaxial layer 52Z is used as the back shield layer 19 of the image sensor.
In the P ⁺ -type epitaxial layer 52Z, a high concentration dopant is added and the dopant is activated when the epitaxial layer is formed. As a result, in this embodiment, addition of a dopant for forming the back shield layer (for example, ion implantation) and activation of the dopant are performed after the formation of the image sensor elements 1, 2, 7 and the wiring 80. It is not necessary.

  As shown in FIG. 9, after the back shield layer 19 is formed, the insulating layer 97 is formed on the epitaxial layer 52Z as the back shield layer by, for example, a CVD method.

  In the through via formation region, an interlayer insulating film 92 or a through hole reaching the wiring in the interlayer insulating film 92 is formed in the epitaxial layers 52Z and 53. As a result, the plug CP2 (or the wiring 80) in the interlayer insulating film 92 is exposed through the through hole.

  An insulating layer (side wall insulating film) 98A is formed on the side surfaces of the epitaxial layers 52Z and 53 exposed by the formation of the through holes.

  As shown in FIG. 2, the through via 88 </ b> A is embedded in a through hole formed in the epitaxial layers 52 </ b> Z and 53. Then, a metal film is deposited on the insulating layer 97 and the through via 88A by a sputtering method. The deposited metal film is processed into a predetermined shape by lithography and RIE. As a result, pads 89 or wirings 89 connected to the through vias 88A are formed on the back surfaces of the semiconductor substrates (epitaxial layers) 52Z and 53A.

  A color filter 117 having an arrangement pattern of a predetermined dye film at a position overlapping the pixel array 120 in a direction perpendicular to the main surfaces of the semiconductor substrates (epitaxial layers) 52Z and 53A is an insulating film 97 on the back side of the epitaxial layer 52Z. Formed on top.

  A microlens array 118 is formed on the color filter 117 at a position overlapping the pixel array 120 with the color filter 117 interposed therebetween.

  After the color filter 117 and the microlens array 118 are formed, the through via 88A and the wiring, pad, or metal light shielding layer on the back side of the semiconductor substrate 5A (epitaxial layers 52Z, 53A) may be formed.

  Through the above steps, the backside illuminated image sensor of this embodiment is formed.

When an image sensor is formed using an SOI substrate, the manufacturing cost of the image sensor tends to increase because the cost of the SOI substrate is high.
As in the present embodiment, an image sensor is formed by using the semiconductor substrate 5A including the bulk substrate 50 and the three epitaxial layers 51A, 52, and 53A on the bulk substrate 50 as shown in FIG. The manufacturing cost of the sensor can be reduced.

  In a back-illuminated image sensor, when a P-type back shield layer is formed by ion implantation into a bulk substrate or an epitaxial layer after the formation of the image sensor elements and wiring, laser annealing is used to reduce the temperature and temperature for a short time. The P-type dopant is activated by the heat treatment for the local region on the back side of the substrate. Activation of the P-type dopant in the back shield layer using laser annealing may cause an increase in manufacturing cost of the image sensor.

  When the dopant is activated by high-temperature heat treatment, deterioration of the flatness of the back surface of the semiconductor substrate and stress due to annealing may occur. In addition, when heat treatment is performed for a long time, a metal wiring such as Al may be deteriorated.

In the present embodiment, the back shield layer 19 in the back-illuminated image sensor is formed using P ⁺ type epitaxial layers (intermediate epitaxial layers) 52 and 52Z included in the semiconductor substrate.
That is, the P ⁺ -type impurity layers 52 and 52Z as the back shield layers are formed on the bulk substrate 50 by forming the epitaxial layer 52 containing the P-type dopant before the elements and wirings of the image sensor are formed. Pre-formed. The dopant in the epitaxial layer 52 is activated from when the epitaxial layer is formed to before the image sensor elements and wiring are formed.

  Thereby, during the process of forming the element and wiring of the image sensor of the present embodiment, the dopant in the back shield layer 19 is subjected to high-cost annealing or annealing that may deteriorate the constituent members of the image sensor. It does not have to be activated.

  When the image sensor is formed using one or two epitaxial layers on the bulk substrate, the flatness of the back surface of the epitaxial layer 50 on the side where the bulk substrate is peeled may be deteriorated. For this reason, when a back-illuminated image sensor in which the back side of the semiconductor substrate is a light-receiving surface for light from a subject is formed using a semiconductor substrate in which one or two epitaxial layers are stacked, characteristics and reliability of the image sensor. May deteriorate.

  On the other hand, in the image sensor manufacturing method of the present embodiment, etching and CMP are performed by forming an image sensor using a semiconductor substrate including three epitaxial layers with different impurity concentrations stacked on a bulk substrate. In combination, the back surface of the semiconductor substrate can be processed with relatively high accuracy. Accordingly, the flatness of the back surface of the epitaxial layer on the light receiving surface side can be improved by a relatively simple process, and a flat surface can be formed on the back surface side of the epitaxial layer.

  Therefore, according to this embodiment, the manufacturing cost of the image sensor can be reduced. Moreover, according to this embodiment, the characteristic deterioration of an image sensor can be suppressed and the reliability of an image sensor can be improved.

  As described above, according to the solid-state imaging device and the manufacturing method thereof according to the first embodiment, the image quality can be improved.

(2) Second embodiment
A solid-state imaging device (for example, an image sensor) of the second embodiment will be described with reference to FIGS. In the present embodiment, the description about the substantially same configuration as the configuration described in the first embodiment will be given as necessary. 10, the illustration of the interlayer insulating film, the wiring, and the support substrate on the surface side of the semiconductor substrate is simplified as in FIG.

  In the first embodiment, the case where all of the epitaxial layers stacked on the bulk substrate have the P-type conductivity has been described.

  However, at least one of the stacked epitaxial layers may be an N-type epitaxial layer according to the configuration of the image sensor to be formed.

  FIG. 10 is a schematic diagram showing a configuration of a semiconductor substrate 5B including P-type and N-type epitaxial layers 51B, 52, and 53B.

For example, among the three epitaxial layers 51B, 52, and 53B stacked on the bulk substrate (for example, P-type silicon substrate) 50, the uppermost epitaxial layer 53B is the N-type silicon epitaxial layer 51B.
Components of the image sensor such as a photodiode and a transistor are formed on the N-type epitaxial layer 53B and in the N-type epitaxial layer 53B.

The N type epitaxial layer 53B has a film thickness of about 3 μm to 4 μm, for example. The impurity concentration of the N-type dopant (for example, phosphorus) in the N-type epitaxial layer 53B is set to, for example, about 1.0 × 10 ¹⁶ cm ⁻³ to 1.4 × 10 ¹⁶ cm ⁻³ .

  N-type epitaxial layer 53B is formed on intermediate epitaxial layer 52 used as the back shield layer.

The intermediate epitaxial layer 52 is made of a P-type silicon epitaxial layer. The P-type epitaxial layer 52 as an intermediate epitaxial layer is set to an impurity concentration of a P-type dopant of about 0.8 × 10 ¹⁹ cm ^{−3 to} 1.2 × 10 ¹⁹ cm ⁻³ . The film thickness of the P-type epitaxial layer 52 is set to about 0.25 μm to 0.45 μm.

  The epitaxial layer 51B between the bulk substrate 50 and the intermediate epitaxial layer 52 may be an N-type silicon epitaxial layer or a P-type silicon epitaxial layer.

When the epitaxial layer 51B in contact with the bulk substrate 50 is N-type, the impurity concentration of the N-type dopant in the epitaxial layer 51B is, for example, about 0.8 × 10 ¹⁵ cm ⁻³ to 1.2 × 10 ¹⁵ cm ⁻³ . Is set. When the epitaxial layer 51B in contact with the bulk substrate 50 is P-type, the impurity concentration of the P-type dopant in the epitaxial layer 51B is set to, for example, about 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ . .

  The N-type or P-type lowermost epitaxial layer 51B has a film thickness of, for example, about 0.9 μm to 1.3 μm.

  As shown in FIG. 10, when the image sensor is formed, the bulk substrate 50 and the lowermost epitaxial layer 51B are removed.

  When the P-type and N-type epitaxial layers 51B, 52, and 53B are stacked on the bulk substrate 50 as in the present embodiment, the epitaxial layers having different conductivity types according to the impurity concentrations of the bulk substrate and the epitaxial layer. Impurity diffusion may occur between 51B, 52, and 53B.

  FIG. 11 is a diagram schematically showing impurity diffusion between epitaxial layers in a semiconductor substrate including epitaxial layers having different conductivity types.

  In the example of FIG. 11, a structure in which an N-type epitaxial layer 51B, a P-type epitaxial layer 52, and an N-type epitaxial layer 53B are stacked in order from the bulk substrate 50 side is shown.

In the example of FIG. 11, the N-type epitaxial layer 51B on the P-type bulk substrate 50 has a film thickness of about 1.1 μm and an impurity concentration of the N-type dopant of about 1.0 × 10 ¹⁵ cm ^−3. . The P-type epitaxial layer 52 has a film thickness of about 0.35 μm and an impurity concentration of P-type dopant of about 1.0 × 10 ¹⁹ cm ⁻³ . The N-type epitaxial layer 53B has a film thickness of about 3.5 μm and an N-type dopant impurity concentration of about 1.2 × 10 ¹⁶ cm ⁻³ . The P-type bulk substrate 50 has a P-type dopant impurity concentration of about 1.0 × 10 ¹⁸ cm ⁻³ .

The N type epitaxial layer 51 </ b> B on the bulk substrate 50 is sandwiched between the P type bulk substrate 50 and the P type epitaxial layer 52.
In the boundary region between the N-type epitaxial layer 51B and the P-type bulk substrate 50, the P-type dopant resulting from the P-type bulk substrate 50 may diffuse into the N-type epitaxial layer 51B. Further, in the boundary region between the N-type epitaxial layer 51B and the P-type epitaxial layer 52, there is a possibility that the P-type dopant resulting from the P-type epitaxial layer 52 will diffuse into the N-type epitaxial layer 51B.

  As shown in FIG. 11, the impurity concentration of the P-type dopant due to the bulk substrate 50 in the N-type epitaxial layer 51B is the highest near the interface between the N-type epitaxial layer 51B and the bulk substrate 50, and the semiconductor substrate 5B. It decreases toward the inner side of the N-type epitaxial layer 51B in the direction perpendicular to the main surface of the semiconductor layer. In the direction perpendicular to the main surface of the semiconductor substrate 5B, the P-type dopant from the bulk substrate 50 is in the region 510 of the N-type epitaxial layer 51B from the interface between the N-type epitaxial layer 51B and the bulk substrate 50 to the depth d1. Diffuses.

  For example, the region 510 on the bulk substrate 50 side of the N-type epitaxial layer 51 </ b> B can be removed by wet etching conditions common to the P-type bulk substrate 50.

  A region (N-type region) 511 containing almost no P-type dopant in the N-type epitaxial layer 51 </ b> B functions as a wet etching stopper layer for the P-type bulk substrate 50.

  As shown in FIG. 11, the impurity concentration of the P-type dopant due to the P-type epitaxial layer in the N-type epitaxial layer 51B is highest near the interface between the N-type epitaxial layer 51B and the P-type epitaxial layer 52, It decreases toward the inner side of the N-type epitaxial layer 51B in the direction perpendicular to the main surface of the semiconductor substrate.

  From the P-type epitaxial layer 52 in the region 512 of the N-type epitaxial layer 51B from the interface between the N-type epitaxial layer 51B and the P-type epitaxial layer 52 to the depth d2 in the direction perpendicular to the main surface of the semiconductor substrate. P-type dopant is diffused.

  For example, the depths d1 and d2 of the P-type region in the N-type epitaxial layer 51B are about 0.5 μm.

  The P-type dopant resulting from the P-type intermediate epitaxial layer 52 as the back shield layer diffuses into the N-type epitaxial layer 53B as the element formation layer. Since P type epitaxial layer 52 remains on the back surface of N type epitaxial layer 53B as a back shield layer, P type region 530 in N type epitaxial layer 53B is not removed.

  The impurity layer of the photodiode may be formed in the epitaxial layer 53B so that photoelectric conversion occurs in the N-type region 531 that hardly contains the P-type dopant (the P-type dopant is not diffused).

  For example, in a backside illuminated image sensor, blue light is photoelectrically converted at a depth of about 0.3 μm to 1.0 μm from the light irradiation side (epitaxial layer 52 side).

  Therefore, even if the P-type region 530 exists in the N-type epitaxial layer 53B as the element formation layer, the P-type region 530 is used for photoelectric conversion of the photodiode formed in the N-type epitaxial layer 53B. There is almost no adverse effect.

  The regions up to the depth d3 (eg, 0.1 μm) of the N-type epitaxial layer 51B and the P-type epitaxial layer 52 are removed by CMP.

  An epitaxial layer having a conductivity type different from that of the bulk substrate can be used as a stopper in the selective etching of the bulk substrate.

In the image sensor of the second embodiment, the components of the image sensor are formed on the N-type epitaxial layer 53B and in the N-type epitaxial layer 53B, and the image sensor includes only the difference from the first embodiment. The structure of the components is substantially the same.
Therefore, description of the structure of the image sensor of the second embodiment is omitted here.

  Even when at least one of the three epitaxial layers of the semiconductor substrate 5B is an N-type epitaxial layer as in the image sensor of the second embodiment, the same effect as that of the first embodiment is obtained. It is done.

(B) Manufacturing method
A method of manufacturing the image sensor according to the second embodiment will be described with reference to FIGS. In addition, the description regarding the manufacturing process substantially the same as the manufacturing method of the image sensor of 1st Embodiment is demonstrated as needed.

  As shown in FIG. 12, semiconductor substrate 5B including epitaxial layers 51B, 52, and 53B having a three-layer structure including N-type epitaxial layer 53B as an element formation layer is formed.

The N type epitaxial layer 53B as the element formation layer is epitaxially grown on the P ⁺ type epitaxial layer 52. The N-type dopant in the epitaxial layer 53B is added into the epitaxial layer in-situ during the growth of the epitaxial layer 53B, similarly to the addition of the P-type dopant. Note that, after the formation of the epitaxial layer 53B not containing the dopant, an N-type dopant may be added into the epitaxial layer 53B by ion implantation to activate the dopant before forming the image sensor element and wiring.

  The lowermost epitaxial layer 51B in contact with the bulk substrate 50 may be an N-type layer or a P-type layer.

  As a device formation layer in a predetermined region of the semiconductor substrate 5B including the epitaxial layers 51B, 52, and 53B having a three-layer structure, by a process substantially similar to the manufacturing process described with reference to FIGS. The photodiode 1 and the transistors 2 and 7 are formed in the N-type epitaxial layer 53B and on the layer 53B.

  After the photodiode 1 and the transistors 2 and 7 are formed, an interlayer insulating film 92 including a wiring 80 is formed on the N-type epitaxial layer 53B by a multilayer wiring technique. A support substrate 119 is affixed on the uppermost interlayer insulating film 92.

  After the support substrate 119 is attached, the bulk substrate 50 is removed by wet etching through a process substantially similar to the manufacturing process described with reference to FIG. At this time, a part of the N-type or P-type epitaxial layer 51B is etched by wet etching for removing the bulk substrate 50. As described above, the region containing almost no P-type dopant or the region having a low impurity concentration of the P-type dopant in the lowermost epitaxial layer 51 </ b> B functions as a stopper for wet etching of the P-type bulk substrate 50.

  Thereby, the bulk substrate 50 is selectively removed, and a relatively flat surface is formed on the back surface of the epitaxial layer 51Z.

As shown in FIG. 13, a part of the P ⁺ type epitaxial layer 52 </ b> Z is formed on the back surface of the N type epitaxial layer 53 </ b> B as an element forming layer by a process substantially similar to the manufacturing process described with reference to FIG. 8. CMP is performed on the lowermost layer and the intermediate epitaxial layers 51B and 52Z so as to remain.

The P ⁺ -type epitaxial layer 52Z remaining on the back surface of the N-type epitaxial layer 53B is used as the back shield layer 19.

  Thereafter, through vias, color filters, and microlenses are sequentially formed by a process substantially similar to the manufacturing process described with reference to FIGS. 9 and 4 to form the image sensor of the second embodiment.

  In the image sensor manufacturing method according to the second embodiment, as in the first embodiment, the three epitaxial layers stacked on the bulk substrate 50 are used without using a high-cost SOI substrate. An image sensor with relatively little deterioration / variation in element characteristics can be formed.

  Further, in the image sensor manufacturing method of the present embodiment, in order to form the back shield layer, after the formation of the elements and wirings, it is not necessary to perform an annealing process that may degrade the cost and members.

  Therefore, according to the image sensor and the manufacturing method thereof of the second embodiment, the manufacturing cost of the image sensor can be reduced as in the first embodiment.

(3) Modification
A modification of the image sensor manufacturing method of the embodiment will be described with reference to FIG. In addition, the description regarding the component / process substantially the same as the component and manufacturing process of the image sensor described in the first and second embodiments will be given as necessary.

  In the above-described embodiment, the example in which the entire bulk substrate and a part of the lowermost epitaxial layer are removed using wet etching has been described.

  In consideration of the manufacturing cost of the image sensor, the manufacturing efficiency, the yield of the formed image sensor, or the reliability of the operation of the image sensor, a part of the bulk substrate 50 as in the modification shown in FIG. Bulk substrate 50 may be removed (ground) by CMP such that 501 remains on the back surface of lowermost epitaxial layer 51B. The remaining bulk substrate portion 501 and the lowermost epitaxial layer 51B are removed by wet etching as described above.

  If the back surface of the P-type epitaxial layer 52 for forming the back shield layer 19 is flat (for example, mirror-like), the epitaxial layers 51B and 52 may be removed and thinned by etching, or CMP. May be removed and thinned.

  In FIG. 14, a semiconductor substrate including N-type and P-type epitaxial layers is illustrated as in the second embodiment and the like, but a semiconductor substrate in which all three epitaxial layers are P-type ( This modification may be applied to the first embodiment).

  In the manufacturing process in which the remaining portion 501 and the epitaxial layer 51B of the bulk substrate 50 are removed by etching after the bulk substrate 50 is ground and thinned by the CMP method as in the present modification, the first and second steps are also performed. The same effect as in the embodiment can be obtained.

(4) Application examples
An application example of the solid-state imaging device of each embodiment will be described with reference to FIG.

  The solid-state imaging device (image sensor) of the embodiment is modularized and applied to a digital camera or a camera-equipped mobile phone.

  FIG. 15 is a block diagram illustrating an application example of the image sensor of the present embodiment.

  In addition to the image sensor 100, the camera (or mobile phone with camera) 900 including the image sensor 100 of the present embodiment includes, for example, an optical lens unit (lens unit) 101 and a signal processing unit (for example, DSP: Digital Signal Processor). 102, a storage unit (memory) 103, a display unit (display) 104, and a control unit (controller) 105.

  The image sensor 100 converts light from a subject into an electrical signal.

  The lens unit 101 collects light from the subject on the image sensor 100 and forms an image corresponding to the light from the subject on the image sensor 100. The lens unit 101 includes a plurality of lenses, and can control optical characteristics (for example, focal length) mechanically or electrically.

  The DSP 102 processes the signal output from the image sensor 100. The DSP 102 forms an image (image data) corresponding to the subject based on a signal from the image sensor 100.

  The memory 103 stores image data from the DSP 102. The memory 103 can also store signals and data given from the outside. The memory 103 may be a memory chip such as a DRAM or a flash memory mounted in the camera 900, or may be a memory card or USB memory that can be detached from the camera 900 body.

  The display 104 displays image data from the DSP 102 or the memory 103. The data output from the DSP 102 or the memory 103 to the display 104 is displayed on the display as a still image or a moving image.

  The controller 105 controls the operation of each component 100 to 104 in the camera based on a request / command from the outside (for example, a user).

As described above, the image sensor 100 according to the embodiment can be applied to the camera or the mobile phone 900 with a camera.
The camera 900 including the image sensor 100 of the present embodiment can improve the image quality of the formed image.

  In the first and second embodiments, the case where the three epitaxial layers included in the semiconductor substrate are all P-type and the case where they are N-type and P-type epitaxial layers is shown. However, all of the three epitaxial layers included in the semiconductor substrate may be N-type epitaxial layers.

  In the above description, the CMOS image sensor is exemplified to describe the manufacturing method of the solid-state imaging device of the present embodiment. However, in the CCD image sensor and the manufacturing method thereof, a bulk substrate including the three epitaxial layers described in each embodiment. (See, eg, FIGS. 4 and 10) may be used.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  5: Semiconductor substrate, 50: Bulk substrate, 51, 52, 53: Epitaxial layer, 120: Pixel array, UC: Unit cell, 9: Element isolation region, 1: Photo diode, 2: Transistor (transfer gate), 6: Floating diffusion.

Claims (5)

Among the first, second and third epitaxial layers stacked on the bulk substrate, an image sensor element is formed on the first surface of the first epitaxial layer having the first impurity concentration of the uppermost layer. Forming, and
Forming an interlayer insulating film including wiring on the first surface of the first epitaxial layer;
A third impurity which is provided between the second epitaxial layer having a second impurity concentration and the bulk substrate and is lower than the second impurity concentration after a support substrate is attached on the interlayer insulating film; Removing the bulk substrate by wet etching using the third epitaxial layer having a concentration as a stopper;
The second epitaxial layer between the first and third epitaxial layers remains on the second surface opposite to the first surface of the first epitaxial layer. Removing the third epitaxial layer by grinding, and forming a remaining shield layer made of the second epitaxial layer on the second surface of the first epitaxial layer;
Forming a color filter on the shield layer on the second surface side;
A method of manufacturing a solid-state imaging device. Forming an element of an image sensor on the first surface of the first epitaxial layer of the top layer among the first, second and third epitaxial layers stacked on the bulk substrate;
Forming an interlayer insulating film including wiring on the first surface of the first epitaxial layer;
After pasting a support substrate on the interlayer insulating film, removing the bulk substrate using the third epitaxial layer between the second epitaxial layer and the bulk substrate as a stopper;
The second epitaxial layer between the first and third epitaxial layers remains on the second surface opposite to the first surface of the first epitaxial layer. Removing the third epitaxial layer, and forming a remaining shield layer made of the second epitaxial layer on the second surface of the first epitaxial layer;
Forming a color filter on the shield layer on the second surface side;
A method of manufacturing a solid-state imaging device. The bulk substrate is removed using wet etching,
The third epitaxial layer is removed by CMP;
The method for manufacturing a solid-state imaging device according to claim 2. The bulk substrate and the first to third epitaxial layers have a P-type conductivity type,
The impurity concentration of the P-type dopant in the third epitaxial layer is lower than the impurity concentration in the bulk substrate,
The impurity concentration of the P-type dopant in the second epitaxial layer is higher than the impurity concentration in the third epitaxial layer,
The impurity concentration of the P-type dopant in the first epitaxial layer is lower than the impurity concentration in the second epitaxial layer,
The method for manufacturing a solid-state imaging device according to claim 2, wherein: The bulk substrate has a P-type conductivity, the first epitaxial layer has an N-type conductivity, the second epitaxial layer has a P-type conductivity, and the third epitaxial layer The layer has a P-type or N-type conductivity type,
The impurity concentration of the N-type dopant in the first epitaxial layer is 1.0 × 10 ¹⁶ cm ⁻³ or more and 1.3 × 10 ¹⁶ cm ⁻³ or less,
The impurity concentration of the P-type dopant in the second epitaxial layer is 0.9 × 10 ¹⁹ cm ⁻³ or more and 1.1 × 10 ¹⁹ cm ⁻³ or less,
The method for manufacturing a solid-state imaging device according to claim 2, wherein:

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