JP2017188615A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance such as sensitivity and dynamic range of a solid-state imaging device without reducing the degree of integration of pixels.SOLUTION: A solid-state imaging device includes: a photoelectric conversion part for generating an electric charge by photoelectric conversion; a first transistor for transferring the electric charge generated in the photoelectric conversion part to a charge holding part; a second transistor constituting an in-pixel readout circuit for outputting a pixel signal based on the amount of electric charge held by the charge holding part; a first contact electrode connected to a gate electrode of the first transistor; and a second contact electrode connected to the second transistor. The size of the first contact electrode is smaller than that of the second contact electrode.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a solid-state imaging device.

  Patent Document 1 describes a solid-state imaging device that can realize both imaging and focus detection by providing two photoelectric conversion units in one pixel. During focus detection, signals are read independently from each of the two photoelectric conversion units, thereby generating two images of light beams that have passed through different positions of the lens pupil. On the other hand, at the time of imaging, a subject image is generated by adding signals read from the two photoelectric conversion units.

  By the way, as one of the major factors that determine performance such as sensitivity and dynamic range of the solid-state imaging device, there is an effective area of the photoelectric conversion unit. By expanding the effective area of the photoelectric conversion unit per pixel, it is possible to improve the sensitivity and dynamic range of the solid-state imaging device.

JP 2014-216536 A

  In the solid-state imaging device described in Patent Document 1, in order to read signals independently from two photoelectric conversion units of one pixel, two transfer transistors corresponding to the respective photoelectric conversion units are provided, and the two transfers It is necessary to connect separate control signal lines to the transistors. However, in such a configuration, the arrangement area of the wiring occupying the unit pixel is wider than that in the case of the solid-state imaging device in which one photoelectric conversion unit is provided in one pixel, and accordingly, the photoelectric conversion unit The effective area will be pressed. In order to improve the performance of the solid-state imaging device, such as sensitivity and dynamic range, it is important how to increase the effective area of the photoelectric conversion unit per pixel without reducing the degree of integration. The request for increasing the effective area of the photoelectric conversion unit is not only a solid-state imaging device having a plurality of photoelectric conversion units in one pixel as described in Patent Document 1, but also one photoelectric conversion unit provided in one pixel. The same applies to the solid-state imaging device.

  An object of the present invention is to provide a solid-state imaging device capable of improving performances such as sensitivity and dynamic range without reducing the integration degree of pixels.

  According to an aspect of the present invention, a first photoelectric conversion unit that generates charges by photoelectric conversion, a first transistor that transfers charges generated in the first photoelectric conversion unit to a charge holding unit, and the charge A second transistor constituting an in-pixel readout circuit that outputs a pixel signal based on the amount of charge held in the holding unit; a first contact electrode connected to a gate electrode of the first transistor; A second contact electrode connected to a source or a drain of the second transistor, and a size of a first contact portion in which the first contact electrode is connected to the gate electrode of the first transistor A solid-state imaging device in which the second contact electrode is smaller than the size of the second contact portion connected to the source or the drain of the second transistor is provided. It is.

  According to the present invention, it is possible to increase the effective area of the photoelectric conversion unit without reducing the integration degree of pixels, and to improve the performance of the solid-state imaging device such as sensitivity and dynamic range.

1 is a block diagram illustrating a solid-state imaging device according to a first embodiment of the present invention. It is a figure which shows the pixel circuit of the solid-state imaging device by 1st Embodiment of this invention. It is a top view of a unit pixel of a solid imaging device by a 1st embodiment of the present invention. 1 is a schematic cross-sectional view of a solid-state imaging device according to a first embodiment of the present invention. It is a top view of the unit pixel of the solid-state imaging device by the comparative example of 1st Embodiment. It is process sectional drawing (the 1) which shows the manufacturing method of the solid-state imaging device by 1st Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the solid-state imaging device by 1st Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the solid-state imaging device by 1st Embodiment of this invention. It is process sectional drawing (the 4) which shows the manufacturing method of the solid-state imaging device by 1st Embodiment of this invention. It is process sectional drawing (the 5) which shows the manufacturing method of the solid-state imaging device by 1st Embodiment of this invention. It is a top view of a unit pixel of a solid imaging device by a 2nd embodiment of the present invention. It is a top view of a unit pixel of a solid imaging device by a comparative example of a 2nd embodiment. It is the schematic which shows the imaging system by 3rd Embodiment of this invention.

[First Embodiment]
A solid-state imaging device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS.

  First, the structure of the solid-state imaging device according to the present embodiment will be described with reference to FIGS. FIG. 1 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the present embodiment. FIG. 2 is a diagram illustrating an example of a pixel circuit of the solid-state imaging device according to the present embodiment. FIG. 3 is a plan view of a unit pixel of the solid-state imaging device according to the present embodiment. FIG. 4 is a schematic cross-sectional view of the solid-state imaging device according to the present embodiment. FIG. 5 is a plan view of a unit pixel of the solid-state imaging device according to the comparative example of the present embodiment.

  As shown in FIG. 1, the solid-state imaging device 100 according to the present embodiment includes a pixel region 10, a vertical scanning circuit 20, a column readout circuit 30, a horizontal scanning circuit 40, a control circuit 50, and an output circuit 60. Have.

  The pixel region 10 is provided with a plurality of pixels 12 arranged in a matrix over a plurality of rows and columns. Each row of the pixel array in the pixel region 10 is provided with a control signal line 14 extending in the row direction (lateral direction in FIG. 1). The control signal line 14 is connected to each pixel 12 arranged in the row direction, and forms a common signal line for these pixels 12. Each column of the pixel array in the pixel area 10 is provided with a vertical output line 16 extending in the column direction (vertical direction in FIG. 1). The vertical output lines 16 are respectively connected to the pixels 12 arranged in the column direction, and form a signal line common to these pixels 12.

  The control signal line 14 in each row is connected to the vertical scanning circuit 20. The vertical scanning circuit 20 is a circuit unit that supplies a control signal for driving a reading circuit in the pixel 12 to the pixel 12 via the control signal line 14 when reading a pixel signal from the pixel 12. One end of the vertical output line 16 of each column is connected to the column readout circuit 30. The pixel signal read from the pixel 12 is input to the column readout circuit 30 via the vertical output line 16. The column readout circuit 30 is a circuit unit that performs predetermined signal processing such as amplification processing and AD conversion processing on the pixel signal read from the pixel 12. The column readout circuit 30 may include a differential amplifier circuit, a sample / hold circuit, an AD conversion circuit, and the like.

  The horizontal scanning circuit 40 is a circuit unit that supplies the column readout circuit 30 with a control signal for sequentially transferring the pixel signals processed in the column readout circuit 30 to the output circuit 60 for each column. The control circuit 50 is a circuit unit for supplying control signals for controlling operations and timings to the vertical scanning circuit 20, the column readout circuit 30, and the horizontal scanning circuit 40. The output circuit 60 includes a buffer amplifier, a differential amplifier, and the like, and is a circuit unit for outputting the pixel signal read from the column readout circuit 30 to a signal processing unit outside the solid-state imaging device.

  As shown in FIG. 2, each pixel 12 includes photoelectric conversion units PD1 and PD2, transfer transistors M1 and M2, a reset transistor M3, an amplification transistor M4, and a selection transistor M5. The photoelectric conversion units PD1 and PD2 are, for example, photodiodes. The photoelectric conversion unit PD1 has an anode connected to the ground voltage line and a cathode connected to the drain of the transfer transistor M1. The photoelectric conversion unit PD2 has an anode connected to the ground voltage line and a cathode connected to the drain of the transfer transistor M2. The sources of the transfer transistors M1 and M2 are connected to the source of the reset transistor M3 and the gate of the amplification transistor M4. A connection node between the sources of the transfer transistors M1 and M2, the source of the reset transistor M3, and the gate of the amplification transistor M4 forms a so-called floating diffusion (FD) region. The drain of the reset transistor M3 and the drain of the amplification transistor M4 are connected to the power supply voltage line (Vdd). The source of the amplification transistor M4 is connected to the drain of the selection transistor M5. The source of the selection transistor M5 is connected to the vertical output line 16. Connected to the other end of the vertical output line 16 is a current source 18 for supplying a bias current to the amplification transistor M4 to form a source follower circuit.

  The photoelectric conversion units PD1 and PD2 generate charges corresponding to the amount of incident light by photoelectric conversion. The transfer transistor M1 transfers charges generated in the photoelectric conversion unit PD1 to the FD region. The transfer transistor M2 transfers charges generated in the photoelectric conversion unit PD2 to the FD region. The FD region functions as a charge holding unit that holds charges transferred from the photoelectric conversion units PD1 and PD2 by the capacitance parasitic on the node, and converts the held charge amount into a voltage applied to the gate of the amplification transistor M4. Also functions as a charge-voltage converter. The reset transistor M3 has a function of resetting the potentials of the FD region and the photoelectric conversion units PD1 and PD2. The amplification transistor M4 outputs a pixel signal corresponding to the gate voltage to the vertical output line 16 via the selection transistor M5. The reset transistor M3, the amplification transistor M4, and the selection transistor M5 are transistors that constitute an in-pixel readout circuit that outputs a pixel signal based on the amount of charge held in the FD region that is a charge holding unit.

  In the case of the circuit configuration shown in FIG. 2, the control signal line 14 includes transfer gate signal lines TX1 and TX2, a reset signal line RES, and a selection signal line SEL. The transfer gate signal line TX1 is connected to the gate of the transfer transistor M1. The transfer gate signal line TX2 is connected to the gate of the transfer transistor M2. The reset signal line RES is connected to the gate of the reset transistor M3. The selection signal line SEL is connected to the gate of the selection transistor M5.

  FIG. 3 shows an example of a planar layout of the pixel 12. 4 is a schematic cross-sectional view taken along the line AA ′ and the line BB ′ in FIG. 3.

  A p-type semiconductor region 202 constituting a P-well is provided on the surface portion of the n-type semiconductor substrate 200. On the surface portion of the p-type semiconductor region 202, an element isolation region 208 that defines active regions 204 and 206 is provided.

  In the active region 204, among the components of the pixel 12, photoelectric conversion units PD1 and PD2 and transfer transistors M1 and M2 are arranged. On the surface portion of the p-type semiconductor region 202 in the active region 204, n-type semiconductor regions 210A, 210B, 212A, and 212B are provided so as to be separated from each other. The n-type semiconductor region 210A forms a PN junction with the p-type semiconductor region 202, and constitutes a photodiode as the photoelectric conversion unit PD1. Similarly, the n-type semiconductor region 210B forms a PN junction with the p-type semiconductor region 202, and constitutes a photodiode as the photoelectric conversion unit PD2. The photoelectric conversion portions PD1 and PD2 may be embedded photodiodes in which p-type semiconductor regions are further provided on the surface portions of the n-type semiconductor regions 210A and 210B. The n-type semiconductor region 210A and the n-type semiconductor region 210B may be provided in the same active region, or may be electrically isolated by the element isolation region 208.

  A gate electrode 216A is provided on the p-type semiconductor region 202 between the n-type semiconductor region 210A and the n-type semiconductor region 212A with a gate insulating film 214 interposed therebetween. As a result, a transfer transistor M1 having the n-type semiconductor region 210A as a drain, the n-type semiconductor region 212A as a source, and the gate electrode 216A as a gate is configured. The n-type semiconductor region 212A is also an FD region.

  A gate electrode 216B is provided on the p-type semiconductor region 202 between the n-type semiconductor region 210B and the n-type semiconductor region 212B with a gate insulating film 214 interposed therebetween. As a result, a transfer transistor M2 having the n-type semiconductor region 210B as a drain, the n-type semiconductor region 212B as a source, and the gate electrode 216B as a gate is configured. The n-type semiconductor region 212B is also an FD region.

  Among the components of the pixel 12, the active region 206 includes a reset transistor M3, an amplification transistor M4, and a selection transistor M5. Some or all of these transistors may be arranged in separate active regions. On the surface portion of the p-type semiconductor region 202 of the active region 206, n-type semiconductor regions 218, 220, 222, and 224 are provided so as to be separated from each other.

  A gate electrode 226 is provided on the p-type semiconductor region 202 between the n-type semiconductor region 218 and the n-type semiconductor region 220 with a gate insulating film 214 interposed therebetween. As a result, a reset transistor M3 having the n-type semiconductor region 218 as a source, the n-type semiconductor region 220 as a drain, and the gate electrode 226 as a gate is configured.

  A gate electrode 228 is provided on the p-type semiconductor region 202 between the n-type semiconductor region 220 and the n-type semiconductor region 222 with a gate insulating film 214 interposed therebetween. Thus, an amplifying transistor M4 having the n-type semiconductor region 222 as a source, the n-type semiconductor region 220 as a drain, and the gate electrode 228 as a gate is configured.

  A gate electrode 230 is provided on the p-type semiconductor region 202 between the n-type semiconductor region 222 and the n-type semiconductor region 224 with a gate insulating film 214 interposed therebetween. As a result, a selection transistor M5 is formed which has the n-type semiconductor region 224 as a source, the n-type semiconductor region 222 as a drain, and the gate electrode 230 as a gate.

  An interlayer insulating film 232 is provided on the semiconductor substrate 200 on which the photoelectric conversion units PD1 and PD2, transfer transistors M1 and M2, reset transistor M3, amplification transistor M4, and selection transistor M5 are provided. In the interlayer insulating film 232, a contact plug 234A connected to the gate electrode 216A and a contact plug 234B connected to the gate electrode 216B are provided. In the interlayer insulating film 232, a contact plug 236A connected to the n-type semiconductor region 212A and a contact plug 236B connected to the n-type semiconductor region 212B are provided. In the interlayer insulating film 232, contact plugs 238, 240, 242, 244, 246, 248 connected to the n-type semiconductor regions 218, 220, 224 and the gate electrodes 226, 228, 230, respectively, are provided. .

  An interlayer insulating film 250 is provided on the interlayer insulating film 232. In the interlayer insulating film 250, wirings 252 connected to the contact plugs 234A, 234B, 236A, 236B, 238, 240, 242, 244, 246, 248 are provided. The wiring 252 includes a wiring 252A connected to the gate electrode 216A via the contact plug 234A and a wiring 252B connected to the gate electrode 216B via the contact plug 234B. The wirings 252A and 252B are, for example, transfer gate signal lines TX1 and TX2. The wiring 252 includes a wiring 252C connected to the n-type semiconductor region 212A via the contact plug 236A and connected to the n-type semiconductor region 212B via the contact plug 236B.

  An interlayer insulating film 254 is provided on the interlayer insulating film 250. A wiring 256 connected to the wiring 252 is provided in the interlayer insulating film 254. An interlayer insulating film 258 is provided over the interlayer insulating film 254. A contact plug 260 connected to the wiring 256 is provided in the interlayer insulating film 258. A wiring 262 connected to the contact plug 260 is provided on the interlayer insulating film 258. An interlayer insulating film 264 and a passivation film 266 are provided over the interlayer insulating film 258 provided with the wiring 262.

  In FIG. 3, for simplification of the drawing, a part of the gate wiring layer and the first metal wiring layer (wiring 252), a wiring member above the second metal wiring layer (wiring 256), and the like are illustrated. Omitted. In the pixel 12, the pixel circuit shown in FIG. 2, the control signal line 14, the vertical output line 16, the ground voltage line, the power supply voltage line, the light shielding film, and the like are provided by wirings 252, 256, and 262 and contact plugs connecting them Is configured. Further, a color filter, a microlens, and the like (not shown) are provided in a layer further above the passivation film 266.

  Here, in the solid-state imaging device according to the present embodiment, the size of the contact electrode connected to the gate electrodes 216A and 216B of the transfer transistors M1 and M2 is smaller than the size of the contact electrode connected to the other transistors of the pixel 12. It has become. That is, the size of the contact portion of the contact plugs 234A, 234B is smaller than the size of the contact portion of the contact plugs 238, 240, 242, 244, 246, 248. In one example, the diameter or width of the contact plugs 234A, 234B can be 0.10 μm, and the diameter or width of the contact plugs 238, 240, 242, 244, 246, 248 can be 0.14 μm.

  In the pixel 12 having two sets of photoelectric conversion units and transfer transistors, for example, as shown in FIG. 3, two wirings 252A connected to the gate electrodes 216A and 216B of the transfer transistors M1 and M2 are provided above the gate electrodes 216A and 216B. 252B are arranged in parallel at intervals. Therefore, by reducing the size of the contact plugs 234A and 234B, the width of the gate electrodes 216A and 216B in the gate length direction (Y direction in FIG. 3) can be reduced. The area can be enlarged.

  By narrowing the width of the gate electrodes 216A and 216B, it is assumed that the wirings 252A and 252B overlap the photoelectric conversion units PD1 and PD2 depending on the layout of the upper wirings 252A and 252B connected to the gate electrodes 216A and 216B. The In such a case, for example, as shown in FIG. 3, it is desirable to reduce the line widths of the wirings 252A and 252B so as not to overlap the photoelectric conversion units PD1 and PD2. In one example, the line width of the wiring 252 connected to the contact plugs 238, 240, 242, 244, 246, and 248 can be 0.14 μm, and the line width of the wirings 252A and 252B can be 0.12 μm.

  Further, the size of the contact electrode connected to the sources (n-type semiconductor regions 212A and 212B) of the transfer transistors M1 and M2 is also made smaller than the size of the contact portion of the contact electrode connected to the other transistors of the pixel 12. Also good. That is, the contact portions of the contact plugs 236A and 236B may be made smaller than the contact portions of the contact plugs 238, 240, 242, 244, 246, and 248. In one example, the diameter or width of the contact plugs 236A, 236B can be 0.10 μm, and the diameter or width of the contact plugs 238, 240, 242, 244, 246, 248 can be 0.14 μm.

  By reducing the size of the contact plugs 236A and 236B, the area (width in the Y direction in FIG. 3) of the n-type semiconductor regions 212A and 212B to which the contact plugs 236A and 236B are connected can be reduced. Thereby, the area of photoelectric conversion part PD1, PD2 can further be expanded. At this time, for the wiring 252C connected to the n-type semiconductor regions 212A and 212B via the contact plugs 236A and 236B, the line width may be reduced as shown in FIG. 3, for example. For example, the line width of the wiring 252 connected to the contact plugs 238, 240, 242, 244, 246, and 248 can be 0.14 μm, and the line width of the wiring 252C can be 0.12 μm.

  In the present specification, the size of the contact electrode or the contact plug is a diameter or a width of the contact electrode or the contact plug in a plan view. Alternatively, the size of the contact electrode or contact plug can also be referred to as the diameter or width of the contact portion to which the contact electrode or contact plug is connected. The shape of the contact electrode or contact plug in plan view is almost the same as the shape of these contact portions.

  In FIG. 5, the contact electrodes connected to the gate electrodes 216A and 216B and the sources (n-type semiconductor regions 212A and 212B) of the transfer transistors M1 and M2 have the same size as the contact electrodes connected to other transistors. FIG. As is clear from a comparison between FIG. 3 and FIG. 5, according to the layout of the present embodiment shown in FIG. 3, the areas of the photoelectric conversion units PD1 and PD2 can be greatly enlarged.

  In the solid-state imaging device according to the present embodiment, among the contact electrodes connected to the transistors of the pixel 12, the sizes of the contact electrodes connected to the gates and sources (FD regions) of the transfer transistors M1 and M2 are selectively reduced. Yes. This is to increase the effective area of the photoelectric conversion unit per pixel and improve the sensitivity and dynamic range without degrading the performance of the solid-state imaging device.

  Even if the contact electrodes connected to the gate electrodes 216A and 216B of the transfer transistors M1 and M2 and the contact electrodes connected to the FD region have a relatively large contact resistance of about several kΩ or more, the circuit operation of the solid-state imaging device The impact on is small. On the other hand, the contact electrode of the connection part that supplies the power supply voltage to the transistor of the pixel 12 and the contact electrode of the connection part that outputs the pixel signal to the vertical output line 16 are saturated by suppressing a voltage drop due to an increase in contact resistance. It is desirable to improve the signal output. In the example of FIGS. 3 and 4, the contact plug 240 corresponds to the contact electrode of the connection portion that supplies the power supply voltage Vdd to the transistor, and the contact plug 242 serves as the contact electrode of the connection portion that outputs the pixel signal to the vertical output line 16. Correspond.

  Therefore, the contact plug 240 connected to the drains of the reset transistor M3 and the amplifying transistor M4 and the contact plug 242 connected to the source of the selection transistor M5 have a large size that can sufficiently reduce the contact resistance. On the other hand, the contact plugs 234A, 234B, 236A, and 236B connected to the gates and sources of the transfer transistors M1 and M2 are smaller than the contact plugs 240 and 242, respectively. Thereby, the effective area of a photoelectric conversion part can be expanded without reducing the integration degree of the pixel 12, and the sensitivity and dynamic range of a solid-state imaging device can be improved.

  Note that the selection transistor M5 of the pixel 12 is not necessarily required depending on the control method of the pixel circuit, the circuit configuration of the column readout circuit 30, and the like. In this case, the contact electrode of the connection portion that outputs the pixel signal to the vertical output line 16 becomes a contact electrode connected to the source of the amplification transistor M4.

  3 and 4, the contact plugs 238, 244, 246, and 248 are the same size as the contact plugs 240 and 242, but may be different from the contact plugs 240 and 242. This is because these contact electrodes have a small influence on the circuit operation of the solid-state imaging device, similarly to the contact electrodes connected to the gate of the transfer transistor and the FD region.

  Next, the method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS. 6 to 10 are process cross-sectional views illustrating the method of manufacturing the solid-state imaging device according to the present embodiment, and correspond to the cross-sectional views along the lines AA ′ and BB ′ of FIG.

  First, an element isolation region 208 that defines active regions 204 and 206 is formed on the surface portion of a semiconductor substrate 200, for example, an n-type silicon substrate, by, for example, the STI method or the LOCOS method. For example, in the STI method, a trench is formed in the semiconductor substrate 200 using photolithography and anisotropic dry etching, and then an isolation film 208 is formed by embedding an insulating film such as a silicon oxide film in the trench. be able to.

  Next, after ion-implanting p-type impurities into the pixel region 10, the impurities implanted by the heat treatment are electrically activated to form a p-type semiconductor region 202 serving as a well in the surface portion of the semiconductor substrate 200 (FIG. 6 ( a)).

Next, a gate insulating film 214 made of, for example, a silicon oxide film or the like is formed on the surface portions of the active regions 204 and 206 by, eg, thermal oxidation.
Next, after depositing a conductive film such as a polycrystalline silicon film by CVD or the like, the conductive film is patterned using photolithography and anisotropic dry etching to form gate electrodes 216A, 216B, 226, 228, and 230. .
Next, using photolithography and ion implantation, n-type semiconductor regions 210A and 210B constituting the photoelectric conversion portions PD1 and PD2 and n-type semiconductor regions 212A and 212B constituting the FD region are formed on the surface portion of the active region 204. Form. These n-type semiconductor regions 210A, 210B, 212A, 212B are also the source / drain of the transfer transistors M1, M2. Similarly, n-type semiconductor regions 218, 220, 222, and 224 constituting the source / drain of the reset transistor M3, the amplification transistor M4, and the selection transistor M5 are formed on the surface portion of the active region 206.
In this way, the photoelectric conversion parts PD1 and PD2 and the transfer transistors M1 and M2 are formed in the active region 204, and the reset transistor M3, the amplification transistor M4, and the selection transistor M5 are formed in the active region 206 (FIG. 6B). )).

Next, for example, a silicon oxide film is deposited on the semiconductor substrate 200 on which the photoelectric conversion parts PD1 and PD2 and the transistors M1, M2, M3, M4, and M5 are formed by the CVD method or the like, and then the surface is planarized by the CMP method. An insulating film 232 is formed.
Next, the interlayer insulating film 232 is patterned using photolithography and anisotropic dry etching, and contact holes 268A to 268J reaching the terminals of the transistors M1, M2, M3, M4, and M5 are opened in the interlayer insulating film 232. . At this time, the opening diameters of the contact holes 268A, 268B, 268C, and 268D reaching the gate and source of the transfer transistor are made smaller than the opening diameters of the contact holes 268G and 268J (FIG. 7A). Note that the contact hole 268D (not shown) is a contact hole opened on the n-type semiconductor region 212B.

  Next, after depositing a conductive film containing a barrier metal such as titanium nitride (TiN) / titanium (Ti) and a wiring material such as tungsten (W) by CVD or the like, the conductive film on the interlayer insulating film 232 is etched back or Polish back. As a result, contact plugs 234A, 234B, 236A, 236B, 238, 244, 260, 246, 248, and 242 embedded in the contact holes 268A to 268J are formed. In this manner, contact plugs 240 and 242 and contact plugs 234A, 234B, 236A, and 236B having smaller sizes than these are formed (FIG. 7B).

  In the above example, the contact holes 268A to 268D having a small opening diameter and the contact holes 268E to 268J having a large opening diameter are formed in the same process, but they may be formed in different processes. For example, after forming the contact holes 268E to 268J, the contact holes 268A to 268D can be formed while protecting the contact holes 268E to 268J with a photoresist.

  Next, for example, a silicon oxide film is deposited on the interlayer insulating film 232 by a CVD method or the like, and then the surface is planarized by a CMP method to form an interlayer insulating film 250.

Next, by a single damascene process, a wiring 252 made of Cu that is embedded in the interlayer insulating film 250 and connected to the contact plugs 234A, 234B, 236A, 236B, 238, 244, 260, 246, 238, 242 is formed (FIG. 8 (a)).
The wiring 252 includes a wiring 252A connected to the contact plug 234A, a wiring 252B connected to the contact plug 234B, and a wiring 252C connected to the contact plugs 236A and 236B. The line widths of the wirings 252A, 252B, and 252C are narrower than the line widths of the wirings 252 connected to the contact plugs 238, 240, 242, 244, 246, and 248.

Next, for example, a silicon oxide film is deposited on the interlayer insulating film 250 by a CVD method or the like, and then the surface is planarized by a CMP method to form an interlayer insulating film 254.
Next, a wiring 256 made of Cu embedded in the interlayer insulating film 254 and connected to the wiring 252 is formed by a dual damascene process (FIG. 8B).

Next, for example, a silicon oxide film is deposited on the interlayer insulating film 254 by a CVD method or the like, and then the surface is planarized by a CMP method to form an interlayer insulating film 258.
Next, in the same manner as the contact plug 238 and the like, a contact plug 260 embedded in the interlayer insulating film 258 and connected to the wiring 256 is formed.
Next, after depositing a conductive film such as aluminum (Al) by sputtering or the like, the conductive film is patterned using photolithography and anisotropic dry etching, and the wiring 262 connected to the wiring 256 through the contact plug 260 is used. (FIG. 9).

  Next, an interlayer insulating film 264 made of, for example, a silicon oxide film and a passivation film 266 made of, for example, a silicon nitride film are formed on the interlayer insulating film 258 by CVD or the like (FIG. 10).

  Thereafter, the solid-state imaging device is completed through predetermined steps such as formation of pad openings in the passivation film 266 and the interlayer insulating film 264, formation of color filters, formation of a planarization film, and formation of microlenses.

  One microlens is provided for each of the two photoelectric conversion units PD1 and PD2 included in one pixel 12. A waveguide structure may be provided in the interlayer insulating films 232, 250, 254, 258, and 264 on the photoelectric conversion portions PD1 and PD2. In the waveguide structure, an opening is provided in the interlayer insulating films 232, 250, 254, 258, and 264, and the opening is filled with a material having a higher refractive index than the interlayer insulating films 232, 250, 254, 258, and 264. Can be formed. For example, the interlayer insulating films 232, 250, 254, 258, and 264 can be made of silicon oxide, and the core portion of the waveguide structure can be made of silicon nitride. By providing the waveguide structure, the light collection efficiency can be improved, and optical characteristics such as photosensitivity and F value (Fno) proportionality can be improved.

  As described above, according to the present embodiment, the effective area of the photoelectric conversion unit can be increased without reducing the integration degree of the pixels. Thereby, the sensitivity of the solid-state imaging device and the dynamic range of the output signal can be improved.

[Second Embodiment]
A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to FIGS. 11 and 12. Components similar to those of the solid-state imaging device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified. FIG. 11 is a plan view of the solid-state imaging device according to the present embodiment. FIG. 12 is a plan view of a solid-state imaging device according to a comparative example of the present embodiment.

  In the first embodiment, the solid-state imaging device in which each pixel 12 includes two sets of photoelectric conversion units and transfer transistors has been described. However, the effect of the present invention can also be realized in a solid-state imaging device in which each pixel 12 has a set of photoelectric conversion units and transfer transistors.

  FIG. 11 is an example of a plan view of the pixel 12 when the present invention is applied to a solid-state imaging device in which each pixel 12 has one photoelectric conversion unit and one transfer transistor. That is, as shown in FIG. 11, the pixel 12 of the solid-state imaging device according to the present embodiment includes a photoelectric conversion unit PD, a transfer transistor M1, a reset transistor M3, an amplification transistor M4, and a selection transistor M5.

  In the solid-state imaging device according to the present embodiment, the size of the contact electrode connected to the gate electrode 216 of the transfer transistor M1 is smaller than the size of the contact electrode connected to the other transistors of the pixel 12. That is, the size of the contact portion of the contact plug 234 is smaller than the size of the contact portion of the contact plugs 238, 240, 242, 244, 246, 248. In one example, the diameter or width of the contact plug 234 can be 0.10 μm, and the diameter or width of the contact plugs 238, 240, 242, 244, 246, 248 can be 0.14 μm. By reducing the size of the contact plug 234, the line width of the gate electrode 216 in the gate length direction (Y direction in FIG. 11) can be reduced, and the area of the photoelectric conversion unit PD can be increased correspondingly. it can.

  The line width of the wiring 252A connected to the gate electrode 216 via the contact plug 234 may be narrower than the line width of the wiring 252 connected to other transistors of the pixel 12, for example, as shown in FIG. In one example, the line width of the wiring 252 connected to the contact plugs 238, 240, 242, 244, 246, and 248 can be 0.14 μm, and the line width of the wiring 252A can be 0.12 μm.

  Further, the size of the contact electrode connected to the source (n-type semiconductor region 212) of the transfer transistor M1 may be smaller than the size of the contact electrode connected to the other transistors of the pixel 12. That is, the size of the contact portion of the contact plug 236 may be made smaller than the size of the contact portion of the contact plugs 238, 240, 242, 244, 246, 248. In one example, the diameter or width of the contact plug 236 can be 0.10 μm, and the diameter or width of the contact plugs 238, 240, 242, 244, 246, 248 can be 0.14 μm. Thereby, the area of the n-type semiconductor region 212 can be reduced, and the area of the photoelectric conversion unit PD can be further increased correspondingly.

  As for the line width of the wiring 252C connected to the source (n-type semiconductor region 212) of the transfer transistor M1 via the contact plug 236, for example, as shown in FIG. 11, the wiring 252 connected to another transistor of the pixel 12 It may be narrower than the line width. For example, the line width of the wiring 252 connected to the contact plugs 238, 240, 242, 244, 246, and 248 can be 0.14 μm, and the line width of the wiring 252C can be 0.12 μm.

  12 shows a case where the size of the contact electrode connected to the gate electrode 216 and the source (n-type semiconductor region 212) of the transfer transistor M1 is the same as the size of the contact electrode connected to the other transistors of the pixel 12. FIG. It is a top view. As is clear from a comparison between FIG. 11 and FIG. 12, according to the layout of the present embodiment shown in FIG. 11, the area of the photoelectric conversion unit PD can be greatly increased.

  As described above, according to the present embodiment, the effective area of the photoelectric conversion unit can be increased without reducing the integration degree of the pixels. Thereby, the sensitivity of the solid-state imaging device and the dynamic range of the output signal can be improved.

[Third Embodiment]
An imaging system according to the third embodiment of the present invention will be described with reference to FIG. FIG. 13 is a block diagram illustrating a configuration example of the imaging system according to the present embodiment.

  The solid-state imaging device 100 described in the first and second embodiments can be applied to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and the like. A camera module including an optical system such as a lens and a solid-state imaging device is also included in the imaging system. FIG. 13 illustrates a block diagram of a digital still camera as an example of these.

  An imaging system 1000 illustrated in FIG. 13 includes a solid-state imaging device 100, a lens 1002 that forms an optical image of a subject on the solid-state imaging device 100, a stop 1004 for changing the amount of light passing through the lens 1002, and protection of the lens 1002. A barrier 1006. The lens 1002 and the diaphragm 1004 are optical systems that collect light on the solid-state imaging device 100. The solid-state imaging device 100 is the solid-state imaging device 100 described in the first or second embodiment, converts an optical image formed by the lens 1002 into image data, and outputs it as an image signal. In the solid-state imaging device 100 of the first embodiment, it is also possible to output a focus detection signal in addition to the image signal.

  The imaging system 1000 also includes a signal processing unit 1008 that processes an output signal output from the solid-state imaging device 100. The signal processing unit 1008 performs AD conversion that converts an analog signal output from the solid-state imaging device 100 into a digital signal. In addition, the signal processing unit 1008 performs an operation of outputting image data after performing various corrections and compressions as necessary. The AD conversion unit that is a part of the signal processing unit 1008 may be formed on a semiconductor substrate on which the solid-state imaging device 100 is provided, or may be formed on a semiconductor substrate different from the solid-state imaging device 100. . Further, the solid-state imaging device 100 and the signal processing unit 1008 may be formed on the same semiconductor substrate.

  The imaging system 1000 further includes a memory unit 1014 for temporarily storing image data and an external interface unit (external I / F unit) 1018 for communicating with an external computer or the like. The imaging system 1000 further includes a recording medium 1020 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) for recording or reading to the recording medium 1020. 1016. Note that the recording medium 1020 may be built in the imaging system 1000 or detachable.

  The imaging system 1000 further includes an overall control / arithmetic unit 1012 that controls the overall driving of the digital still camera and various arithmetic processes, a timing generation unit 1010 that outputs various timing signals to the solid-state imaging device 100 and the signal processing unit 1008. Have. Here, the timing signal or the like may be input from the outside, and the imaging system 1000 only needs to include at least the solid-state imaging device 100 and the signal processing unit 1008 that processes the output signal output from the solid-state imaging device 100.

  In this way, by configuring the imaging system 1000 to which the solid-state imaging device 100 according to the first or second embodiment is applied, a high-performance imaging system that can acquire a high-quality image with improved sensitivity and dynamic range. Can be realized.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.
For example, in the above embodiment, the contact plugs 234A, 234B, 236A, and 236B have the same aspect ratio in plan view as that of other contact plugs, but the size is reduced. However, the aspect ratio is not necessarily constant. There is no. For example, in FIG. 3, only the size of the contact plugs 234A, 234B, 236A, 236B in the Y direction may be selectively made smaller than the contact plugs 240,242. Since the size in the Y direction in FIG. 3 affects the effective area of the photoelectric conversion units PD1 and PD2, the present invention can be achieved even when the size of the contact plugs 234A, 234B, 236A, and 236B is selectively reduced. The effects of the invention can be obtained.

  Further, in the above-described embodiment, the case where the sizes of both the contact plugs 234A and 234B connected to the gates of the transfer transistors M1 and M2 and the contact plugs 236A and 236B connected to the sources has been described. However, only one of the contact plugs 234A and 234B and the contact plugs 236A and 236B may be reduced in size. Even when only one of the contact plugs 234A and 234B and the contact plugs 236A and 236B is reduced in size, the effect of increasing the effective area of the photoelectric conversion parts PD, PD1, and PD2 can be obtained.

  In the above embodiment, the example in which the readout circuit of the pixel 12 is configured by an N-type MOS transistor has been described. However, the readout circuit of the pixel 12 may be configured by a P-type MOS transistor. In this case, the conductivity type of each semiconductor region described in the above embodiment is a reverse conductivity type. Note that the names of the source and the drain for each transistor described in the above embodiment are examples, and a part or all of the names may be referred to as opposite names depending on the conductivity type of the transistor, the function of interest, or the like.

  The pixel circuit shown in FIG. 2 is an example, and the present invention is not limited to this. For example, two sets of a reset transistor, an amplification transistor M4, and a selection transistor M5 may be provided in one pixel 12 corresponding to the two photoelectric conversion units PD1 and PD2. In addition, a second transfer transistor may be provided between the transfer transistor M1 and the FD region, and a pixel configuration capable of a global electronic shutter operation may be employed. The planar layout of the pixel 12 shown in FIGS. 3 and 11 is also an example, and the present invention is not limited to this.

  The imaging system shown in the third embodiment is an example of an imaging system to which the solid-state imaging device of the present invention can be applied. An imaging system to which the solid-state imaging device of the present invention can be applied is shown in FIG. The configuration is not limited to that shown.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 10 ... Pixel region 12 ... Pixel 100 ... Solid-state imaging device 200 ... Semiconductor substrate 202 ... P-type semiconductor region 204, 206 ... Active region 208 ... Element isolation region 210, 210A, 210B, 212, 212A, 212B, 218, 220, 222 224, n-type semiconductor regions 216A, 216B, 226, 228, 230 ... gate electrodes 232, 250, 254, 258, 264 ... interlayer insulating films 234, 234A, 234B, 236, 236A, 236B, 238, 240, 242, 244, 246, 248, 260 ... contact plugs 252, 252A, 252B, 252C, 256, 262 ... wiring

Claims (14)

A first photoelectric conversion unit that generates electric charge by photoelectric conversion;
A first transistor that transfers the charge generated in the first photoelectric conversion unit to a charge holding unit;
A second transistor constituting an in-pixel readout circuit that outputs a pixel signal based on the amount of charge held in the charge holding unit;
A first contact electrode connected to the gate electrode of the first transistor;
A second contact electrode connected to the source or drain of the second transistor,
The size of the first contact portion where the first contact electrode is connected to the gate electrode of the first transistor is such that the second contact electrode is connected to the source or the drain of the second transistor. The solid-state imaging device is smaller than the size of the second contact portion. The solid-state imaging device according to claim 1, wherein a power supply voltage is supplied to the second transistor via the second contact electrode. The solid-state imaging device according to claim 2, wherein the second transistor is a reset transistor or an amplification transistor. 4. The solid-state imaging device according to claim 1, wherein the pixel signal is output from the second transistor through the second contact electrode. 5. The solid-state imaging device according to claim 4, wherein the second transistor is a selection transistor. A first wiring connected to the first contact electrode;
A second wiring connected to the second contact electrode; and
6. The solid-state imaging device according to claim 1, wherein a line width of the first wiring is narrower than a line width of the second wiring. A second photoelectric conversion unit that is provided in the same active region as the first photoelectric conversion unit and generates charge by photoelectric conversion;
A third transistor that transfers the charge generated in the second photoelectric conversion unit to the charge holding unit;
A third contact electrode connected to the gate electrode of the third transistor;
6. The size of a third contact portion where the third contact electrode is connected to the gate electrode of the third transistor is smaller than the size of the second contact portion. The solid-state imaging device according to any one of the above. A first wiring connected to the first contact electrode;
A second wiring connected to the second contact electrode; and
The solid-state imaging device according to claim 7, wherein a line width of the first wiring is narrower than a line width of the second wiring. A third wiring connected to the third contact electrode;
The solid-state imaging device according to claim 8, wherein a line width of the third wiring is narrower than a line width of the second wiring. The first wiring and the third wiring are arranged in parallel above the gate electrode of the first transistor and above the gate electrode of the third transistor, respectively. The solid-state imaging device described. A fourth contact electrode connected to the charge holding portion;
11. The size of the fourth contact portion where the fourth contact electrode is connected to the charge holding portion is smaller than the size of the second contact portion. 11. The solid-state imaging device described in 1. A fourth wiring connected to the fourth contact electrode;
The solid-state imaging device according to claim 11, wherein a line width of the fourth wiring is narrower than a line width of the second wiring. The size of the first contact portion is a width of the first contact portion along a direction parallel to a gate length direction of the first transistor. The solid-state imaging device according to item. A solid-state imaging device according to any one of claims 1 to 13,
An image pickup system comprising: a signal processing unit that processes a signal from the solid-state image pickup device.

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