JP2015111604A - Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of efficiently transferring signal charge of a photoelectric conversion part or an electric charge holding part.SOLUTION: A solid-state imaging device comprises: a semiconductor layer 17; a photoelectric conversion part or an electric charge holding part arranged on a light reception surface side of the semiconductor layer 17; a connector 21 formed on the semiconductor layer 17, and to which signal charge generated at the photoelectric conversion part or the electric charge holding part is read out; a charge storage part 23 storing the signal charge read out to the connector 21; a potential barrier part 22 provided between the connector 21 and the charge storage part 23; and an element isolation part 27 consisting of a trench 54 formed on the semiconductor layer 17, and an insulating layer 25 formed in the trench 54. The trench 54 is formed at a position surrounding a lateral face of the connector 21 or a position at least partially contacted with the connector 21 on the lateral face of the connector 21.

Description

  The present technology provides a solid-state imaging device including a photoelectric conversion unit or a charge holding unit outside a semiconductor substrate, and has a configuration for transmitting signal charges from the photoelectric conversion unit or the charge holding unit to the semiconductor substrate, and a method for manufacturing the solid-state imaging device About. The present invention also relates to an electronic device using the solid-state imaging device.

  In recent years, as the pixels of an image sensor have been miniaturized, there has been a problem that the number of sensitive electrons of the pixel decreases and the image quality of the solid-state imaging device deteriorates. A pixel array in which red (R), blue (B), and green (G) color filters, which are currently widely used in image sensors, are arranged in a plane, performs color separation by absorbing light of a specific wavelength. doing. For example, the R pixel has a problem that light of B and G wavelengths is absorbed by the color filter and lost.

  As a solution to this problem, a stacked solid-state imaging device has been proposed. For example, a configuration has been proposed in which photoelectric conversion regions for photoelectrically converting R, B, and G light are stacked in the same pixel space (see, for example, Patent Document 1 below). By using this structure, it is possible to suppress a decrease in sensitivity due to light absorption of the color filter. Furthermore, since no interpolation process is required, false colors do not occur.

  As a technique for changing the characteristics of the image sensor discontinuously, a configuration in which a photoelectric conversion unit, a charge holding unit, or the like is disposed outside the semiconductor substrate has been proposed (see, for example, Patent Document 2 and Patent Document 3). Here, for example, a structure has been proposed in which the photoelectric conversion unit is disposed on the semiconductor substrate and the photoelectric conversion signal is accumulated in the semiconductor substrate. In this configuration, it is possible to greatly change the photoelectric conversion characteristics that have been conventionally determined by the material of the semiconductor substrate. For this reason, application of sensor technology to fields such as far-infrared applications, which has been difficult to realize with conventional image sensors using silicon substrates, is being studied.

  In order to transmit charges generated by the photoelectric conversion unit from the photoelectric conversion unit disposed outside the semiconductor substrate to the semiconductor substrate, it is necessary to electrically connect the photoelectric conversion unit and the semiconductor substrate. For example, an n-type diffusion layer region and a PN junction formed of P-Well are formed on a semiconductor substrate. Then, the electrode of the photoelectric conversion unit and the n-type diffusion region are connected by a contact plug.

The signal charge from the photoelectric conversion unit can be directly accumulated in the diffusion layer region connected to the contact plug. However, in this method, the potential of the diffusion layer region greatly varies depending on the amount of accumulated charge, and the photoelectric conversion unit The voltage applied to fluctuates. As a result, the photoelectric conversion performance of the photoelectric conversion unit varies with the amount of light, and the linearity of the light output deteriorates.
In general, a diffusion layer in which a contact plug is disposed has a high impurity concentration for ohmic connection, and is not depleted by a power supply voltage used in a normal CMOS process or CCD. For this reason, it is difficult to remove the reset noise that occurs when resetting the signal accumulated in the charge accumulation unit, and there is a problem that the noise of the solid-state imaging device increases.

  As a method for solving these problems, the above-described Patent Document 1 proposes a structure in which the charge held by the contact plug of the semiconductor substrate overflows into the charge storage portion. According to this structure, since the photoelectric conversion signal read to the diffusion layer is discharged to the charge storage unit, the potential fluctuation of the contact plug can be reduced. Further, Patent Document 3 proposes a configuration advantageous for expanding the area of the charge storage unit and reading the charge by arranging the photoelectric conversion unit and the vertical overflow structure on the back side of the semiconductor substrate.

Japanese Patent Laid-Open No. 2006-120921 JP 2010-278086 A JP 2011-138927 A

  As described above, in a solid-state imaging device having a configuration in which a photoelectric conversion unit or a charge holding unit is disposed outside a semiconductor substrate, improvement in transfer efficiency of signal charges from the photoelectric conversion unit or the charge holding unit is required.

  In the present technology, a solid-state imaging device capable of efficiently transferring signal charges of a photoelectric conversion unit or a charge holding unit, a manufacturing method thereof, and an electronic apparatus using the solid-state imaging device are provided.

The solid-state imaging device of the present technology includes a semiconductor layer and a photoelectric conversion unit or a charge holding unit disposed on the light receiving surface side of the semiconductor layer. Then, a connection unit that is formed in the semiconductor layer and from which the signal charge generated by the photoelectric conversion unit or the charge holding unit is read out, a charge storage unit in which the signal charge read out by the connection unit is stored, a connection unit and a charge And a potential barrier portion provided between the storage portion and the storage portion. In addition, an element isolation portion including a trench formed in the semiconductor layer and an insulating layer formed in the trench is provided. The trench is formed at a position surrounding the side surface of the connection portion, or at a position where at least part of the side surface of the connection portion is in contact with the connection portion.
Moreover, the electronic device of this technique is provided with the said solid-state imaging device and the signal processing circuit which processes the output signal of a solid-state imaging device.

  Moreover, the manufacturing method of the solid-state imaging device of this technique is a manufacturing method of the solid-state imaging device by which a photoelectric conversion part or an electric charge holding | maintenance part is arrange | positioned at the light-receiving surface side of a semiconductor layer. In this manufacturing method, a semiconductor layer includes a connection unit that reads out signal charges generated by the photoelectric conversion unit or the charge holding unit, a charge storage unit that stores the signal charges read out in the connection unit, and the connection unit and the charge. Forming a potential barrier portion provided between the storage portion and the storage portion. And it has the process of arrange | positioning a photoelectric conversion part or an electric charge holding part to the light-receiving surface side of a semiconductor layer, the process of forming a trench in a semiconductor layer, and the process of forming an insulating layer in a trench. The position where the trench is formed is a position surrounding the side surface of the connecting portion of the semiconductor layer, or a position where at least a part of the side surface of the connecting portion of the semiconductor layer is in contact.

  According to the above-described solid-state imaging device and the solid-state imaging device manufactured by the above-described manufacturing method, the insulating layer is formed in the trench on the side surface of the connection portion that takes out the signal charge from the photoelectric conversion unit or the charge holding unit, or around it. An element isolation portion in which is embedded is formed. By this element isolation part, the signal charge overflowed from the connection part concentrates on the potential barrier part and the charge storage part. For this reason, it becomes possible to efficiently transfer the signal charge of the photoelectric conversion unit or the charge holding unit.

  According to the present technology, a solid-state imaging device capable of efficiently transferring a signal charge of a photoelectric conversion unit or a charge holding unit, a manufacturing method thereof, and an electronic apparatus using the solid-state imaging device are provided. be able to.

A is a cross-sectional view showing a configuration of a conventional solid-state imaging device. B is a plan view showing a configuration of a conventional solid-state imaging device. It is a top view which shows the structure of the solid-state imaging device of 1st Embodiment. It is a top view which shows the schematic planar structure of the solid-state imaging device of 1st Embodiment. FIG. 2A is a cross-sectional view illustrating a configuration of the solid-state imaging device according to the first embodiment. B is a plan view showing the configuration of the solid-state imaging device according to the first embodiment. FIG. A and B are manufacturing process diagrams of the solid-state imaging device of the first embodiment. C and D are manufacturing process diagrams of the solid-state imaging device of the first embodiment. E and F are manufacturing process diagrams of the solid-state imaging device of the first embodiment. FIG. 6A is a cross-sectional view illustrating a configuration of a solid-state imaging device according to a second embodiment. B is a plan view showing the configuration of the solid-state imaging device of the second embodiment. FIG. 7A is a cross-sectional view illustrating a configuration of a solid-state imaging device according to a modification of the second embodiment. FIG. 7B is a plan view illustrating a configuration of a solid-state imaging device according to a modification of the second embodiment. FIG. 7A is a cross-sectional view illustrating a configuration of a solid-state imaging device according to a third embodiment. B is a plan view showing the configuration of the solid-state imaging device of the third embodiment. A and B are manufacturing process diagrams of the solid-state imaging device of the third embodiment. C and D are manufacturing process diagrams of the solid-state imaging device of the third embodiment. FIG. 7A is a cross-sectional view illustrating a configuration of a solid-state imaging device according to a fourth embodiment. B is a plan view showing the configuration of the solid-state imaging device of the fourth embodiment. A and B are manufacturing process diagrams of the solid-state imaging device of the fourth embodiment. C and D are manufacturing process diagrams of the solid-state imaging device of the fourth embodiment. FIG. 7A is a cross-sectional view illustrating a configuration of a solid-state imaging device according to a fifth embodiment. B is a plan view showing the configuration of the solid-state imaging device of the fifth embodiment. A and B are manufacturing process diagrams of the solid-state imaging device of the fifth embodiment. C and D are manufacturing process diagrams of the solid-state imaging device of the fifth embodiment. E and F are manufacturing process diagrams of the solid-state imaging device of the fifth embodiment. FIG. 7A is a cross-sectional view illustrating a configuration of a solid-state imaging device according to a sixth embodiment. B is a plan view showing the configuration of the solid-state imaging device of the sixth embodiment. FIG. 9A is a cross-sectional view illustrating a configuration of a solid-state imaging device according to a first modification of the sixth embodiment. FIG. 7B is a plan view illustrating a configuration of a solid-state imaging device according to a first modification of the sixth embodiment. FIG. 9A is a cross-sectional view illustrating a configuration of a solid-state imaging device according to a second modification of the sixth embodiment. B is a plan view illustrating a configuration of a solid-state imaging device according to a second modification of the sixth embodiment. A and B are manufacturing process diagrams of the solid-state imaging device of the sixth embodiment. C and D are manufacturing process diagrams of the solid-state imaging device of the sixth embodiment. It is a figure which shows the structure of an electronic device.

Hereinafter, examples of the best mode for carrying out the present technology will be described, but the present technology is not limited to the following examples.
The description will be given in the following order.
1. 1. Overview of solid-state imaging device First embodiment (solid-state imaging device)
3. First Embodiment (Method for Manufacturing Solid-State Imaging Device)
4). Second embodiment (solid-state imaging device)
5. Third embodiment (solid-state imaging device)
6). Third Embodiment (Method for Manufacturing Solid-State Imaging Device)
7). Fourth embodiment (solid-state imaging device)
8). Fourth Embodiment (Method for Manufacturing Solid-State Imaging Device)
9. Fifth embodiment (solid-state imaging device)
10. Fifth Embodiment (Method for Manufacturing Solid-State Imaging Device)
11. Sixth embodiment (solid-state imaging device)
12 Sixth Embodiment (Method for Manufacturing Solid-State Imaging Device)
13. Seventh embodiment (electronic device)

<1. Overview of solid-state imaging device>
Prior to the description of the embodiment, an outline of the solid-state imaging device will be described.
The solid-state imaging device having the configuration described in Patent Document 3 described above includes a structure in which a photoelectric conversion unit is disposed outside the semiconductor layer, and signal charges generated by the photoelectric conversion are transmitted to the semiconductor layer. In this structure, the leakage current of the connection portion formed in the semiconductor layer becomes a big problem.
In the structure in which the charge overflows from the connection portion to the charge storage portion, there are problems such as the disappearance of the signal charge and the charge mixing into the region other than the charge storage portion. In addition, noise due to potential fluctuation of the potential barrier portion is also a problem.

  1A and 1B show the configuration of the solid-state imaging device described in Patent Document 3 described above. FIG. 1A is a cross-sectional view illustrating a configuration of one pixel of the solid-state imaging device. FIG. 1B is a plan view of the configuration of one pixel of the solid-state imaging device as viewed from the light receiving surface side of the semiconductor substrate. The solid-state imaging device shown in FIGS. 1A and 1B is a so-called back-illuminated solid-state imaging device having a light incident surface on the surface (back surface) opposite to the circuit forming surface (front surface) side of the semiconductor layer 17.

  As shown in FIG. 1A, the solid-state imaging device includes a first photodiode PD1 and a second photodiode PD2 in the semiconductor layer 17 as a first photoelectric conversion unit and a second photoelectric conversion unit. And the photoelectric conversion film 32 is provided in the back surface side of the light of the semiconductor layer 17 as a 3rd photoelectric conversion part. As shown in FIG. 1B, the first photodiode PD1 and the second photodiode PD2 are stacked in the light incident direction in the semiconductor layer 17.

The first and second photodiodes PD1 and PD2 are wells made of a semiconductor region 17 of the first conductivity type (p-type in this example) of the semiconductor layer 17 of the second conductivity type (n-type in this example) made of silicon or the like. The region (p-well) 16 is formed.
The first photodiode PD1 has an n-type semiconductor region 19 formed of a second conductivity type (n-type in this example) impurity formed on the light-receiving surface side of the semiconductor layer 17 and a part thereof reaching the surface side of the semiconductor layer. It has the extension part 19a formed by extending.
The second photodiode PD2 includes an n-type semiconductor region 20 formed on the surface side of the semiconductor layer 17.

  The photoelectric conversion film 32 is formed through an insulating layer 28 that is an antireflection film formed on the back surface of the semiconductor layer 17. An upper electrode 33 and a lower electrode 31 are formed on the upper and lower surfaces of the photoelectric conversion film 32. The upper electrode 33 and the lower electrode 31 are made of a light transmissive material.

The lower electrode 31 formed on the semiconductor layer 17 side of the photoelectric conversion film 32 is connected to a contact plug 29 that penetrates the insulating layer 28. The contact plug 29 is connected to a signal extraction portion formed from the back surface side to the front surface side of the semiconductor layer 17. The signal extraction unit is configured by a vertical transfer path 50 including a connection unit 21, a potential barrier unit 22, and a charge storage unit 23 formed in the vertical direction from the back surface side to the front surface side of the semiconductor layer 17. .
In addition, as shown in FIG. 1B, the vertical transfer path 50 has a connection portion 21, a potential barrier portion 22, and a charge storage portion 23 stacked in the same region in a planar arrangement on the semiconductor layer 17. The vertical transfer path 50 is formed at a position separated from the first and second photodiodes PD1 and PD2 by the p-well 16.

The connection portion 21 is composed of a high-concentration n-type impurity region formed on the back side of the semiconductor layer 17. The connection portion 21 is configured to establish ohmic connection with the contact plug 29. The signal charges generated by the photoelectric conversion film 32 are read out to the connection unit 21.
The potential barrier unit 22 is formed of a low-concentration p-type impurity region, and serves as a potential barrier between the connection unit 21 and the charge storage unit 23.
The charge accumulation unit 23 is a layer that accumulates signal charges transferred from the photoelectric conversion film 32, and includes an n-type impurity region having a lower concentration than the connection unit 21.

First to third pixel transistors corresponding to the first photodiode PD <b> 1, the second photodiode PD <b> 2, and the photoelectric conversion film 32 are formed on the surface side that is a circuit formation surface of the semiconductor layer 17. In the figure, first to third transfer transistors Tr1, Tr2, Tr3 are shown.
The first transfer transistor Tr1 includes a floating diffusion portion FD1 formed on the surface side of the semiconductor layer adjacent to the extension portion 19a of the first photodiode PD1, and a transfer gate electrode formed on the semiconductor layer 17 via a gate insulating film. 37.
The second transfer transistor Tr2 includes a floating diffusion portion FD2 formed on the surface side of the semiconductor layer adjacent to the second photodiode PD2, and a transfer gate electrode 38 formed on the semiconductor layer 17 via a gate insulating film. Is done.
The third transfer transistor Tr3 includes a floating diffusion portion FD3 formed on the surface side of the semiconductor layer adjacent to the vertical transfer path 50, and a transfer gate electrode 39 formed on the semiconductor layer 17 via a gate insulating film. Is done.
An on-chip lens 35 is formed on the upper electrode 33 through a light shielding film, a planarizing film, or the like (not shown).

In the solid-state imaging device having the above-described configuration, the signal charges generated in the photoelectric conversion film 32 are electrons, the connection portion 21 in the semiconductor layer is an n-type diffusion layer, the overflow portion is a potential barrier portion 22 of a p-type semiconductor, and charge accumulation. The part 23 is formed of an n-type diffusion layer, and the well is formed of a p-type semiconductor.
When the photoelectric conversion film 32 is irradiated with light, signal charges generated by the photoelectric conversion film disposed outside the semiconductor layer 17 are read out to the connection portion 21 formed of the n-type diffusion layer through the contact plug 29. Then, the charge accumulation unit 23 overflows through the p-type potential barrier unit 22.

  Here, when the photoelectric conversion film 32 outside the semiconductor layer 17 is irradiated with a large amount of light, a large amount of signal electrons are injected from the photoelectric conversion film 32 into the n-type connection portion 21. At this time, some of the signal electrons injected into the connection part 21 flow into the p-Well 16 having a polarity opposite to that of the connection part 21, and recombine with holes to disappear. As a result, the transfer efficiency of the signal charge to the charge storage unit 23 is lowered, and the sensitivity of the solid-state imaging device is lowered.

  In addition, as shown in FIG. 1, in the case where a plurality of photoelectric conversion regions or charge accumulation regions that hold charges are included in the semiconductor layer 17, the charges injected from the connection portion 21 into the p-well 16. A part of them is not recombined but mixed into other photoelectric conversion regions or charge storage regions. For example, in the structure of FIG. 1, a first photodiode PD1 and a second photodiode PD2 are disposed below the photoelectric conversion film 32. After photoelectrically converting the light of the first wavelength by the photoelectric conversion film 32, the light transmitted through the photoelectric conversion film 32 is second and third by the first photodiode PD1 and the second photodiode PD2, respectively, due to the difference in absorption coefficient. It absorbs as light of the wavelength.

Here, when a large amount of signal charge is generated in the photoelectric conversion film 32, a large amount of electrons are injected into the n-type connection portion 21 through the contact plug 29, and a part of the charge flows into the p-well 16. At this time, some charges are mixed into the first photodiode PD1 and the second photodiode PD2 before overcoming the potential barrier of the p-Well16 and recombining with the holes in the p-Well16.
As a result, the signal of the photoelectric conversion film 32 is mixed into the signals of the first photodiode PD1 and the second photodiode PD2, and the color reproducibility of the solid-state imaging device is deteriorated.

  As a countermeasure against this problem, there is a method in which the potential barrier of the overflow portion is deepened and a design is made so that an appropriate reverse bias is applied between the connection portion 21 and the p-Well 16. For example, in the configuration of FIG. 1, the p-type impurity concentration of the potential barrier unit 22 is formed to be lower than that of the p-well 16. With this configuration, it is possible to make it difficult for an overflow current to be injected into a region other than the charge storage unit 23.

  However, since the reverse bias between the connection portion 21 and the p-well 16 is strengthened in the above method, the reverse leakage current of the pn junction increases, causing a problem of causing noise. As another countermeasure, in Patent Document 2 described above, the connection portion 21 in the semiconductor layer 17 to which the contact plug 29 is connected is surrounded by the potential barrier portion 22, and the charge storage portion 23 is formed widely below the diffusion layer. A configuration is proposed. With this configuration, the transfer efficiency to the charge storage unit 23 can be increased. However, in this method, it is necessary to form the charge accumulating portion 23 widely, so that it is difficult to miniaturize the charge accumulating portion 23. For this reason, it is difficult to reduce the pixel size. Furthermore, as shown in FIG. 1, when a plurality of photoelectric conversion units such as the first photodiode PD1 and the second photodiode PD2 are arranged in the semiconductor layer 17, it is difficult to ensure the element area. .

  Furthermore, in the structure in which the charge overflows from the connection portion 21 to the charge storage portion 23, noise generated by potential fluctuation of the potential barrier portion 22 becomes a problem. For example, in the configuration of FIG. 1, the p-type potential barrier unit 22 and the n-type charge storage unit 23 are coupled by a pn junction capacitance. When the charge stored in the n-type charge storage unit 23 is read, the voltage of the charge storage unit 23 increases due to the change from the storage state to the depletion state. At this time, as the voltage of the charge storage unit 23 increases, the potential of the potential barrier unit 22 also increases. As a result, the potential barrier of the potential barrier unit 22 viewed from the connection unit 21 is lowered. Then, charges corresponding to the amount of potential fluctuation between the connection portion 21 and the potential barrier portion 22 and the capacitance of the potential barrier portion 22 are injected into the charge storage portion 23. The charge injected into the charge storage unit 23 becomes noise to the signal charge transferred from the photoelectric conversion film 32 to the transistor via the vertical transfer path 50.

Therefore, the present technology provides a solid-state imaging device having a configuration capable of intensively overflowing signal charges generated or held outside the semiconductor layer from the connection portion to the charge storage portion. In this configuration, when a large amount of signal charge is injected into the contact part by intensively overflowing from the connection part to the charge storage part, to other photoelectric conversion regions and charge storage parts formed in the semiconductor layer. The problem that signal charges are mixed can be suppressed. In addition, the potential difference between the connection portion and the well region can be reduced, and leakage current generated at the connection portion can be suppressed.
Furthermore, the element size of the potential barrier portion and the charge storage portion can be reduced.

<2. First Embodiment (Solid-State Imaging Device)>
[Schematic configuration of solid-state imaging device]
FIG. 2 illustrates a CMOS solid-state imaging device 1 as an example of a solid-state imaging device to which the present technology is applied. The configuration in FIG. 2 is a configuration common to the solid-state imaging device according to each embodiment described below. In the present embodiment, a back-illuminated CMOS solid-state imaging device having a light incident surface on the side opposite to the circuit formation surface (front surface) side of the semiconductor substrate will be described.

[Overall configuration of solid-state imaging device]
FIG. 2 is a schematic configuration diagram illustrating the entire CMOS solid-state imaging device 1 according to the first embodiment.
The solid-state imaging device 1 according to the present embodiment includes a pixel region 3 composed of a plurality of pixels 2 arranged on a substrate 11 made of silicon, a vertical drive circuit 4, a column signal processing circuit 5, and a horizontal drive circuit. 6, an output circuit 7, a control circuit 8, and the like.

  The pixels 2 are composed of photodiodes that are photoelectric conversion elements and a plurality of pixel transistors, and a plurality of pixels 2 are regularly arranged in a two-dimensional array on the substrate 11. The pixel transistors constituting the pixel 2 may be four pixel transistors including a transfer transistor, a reset transistor, a selection transistor, and an amplification transistor, or may be three transistors excluding the selection transistor.

  The pixel area 3 is composed of pixels 2 regularly arranged in a two-dimensional array. The pixel region 3 has an effective pixel region that actually receives light, amplifies the signal charge generated by photoelectric conversion, and reads it to the column signal processing circuit 5, and a black for outputting optical black as a reference for the black level. And a reference pixel region (not shown). The black reference pixel region is normally formed on the outer periphery of the effective pixel region.

  The control circuit 8 generates a clock signal, a control signal, and the like that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. The clock signal and control signal generated by the control circuit 8 are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by a shift register, for example, and selectively scans each pixel 2 in the pixel region 3 in the vertical direction sequentially in units of rows. Then, a pixel signal based on the signal charge generated according to the amount of light received in the photodiode of each pixel 2 is supplied to the column signal processing circuit 5 through the vertical signal line 9.

  The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and a signal output from the pixels 2 for one row is sent to the black reference pixel region (not shown, but around the effective pixel region) for each pixel column. Signal processing such as noise removal and signal amplification. A horizontal selection switch (not shown) is provided between the output stage of the column signal processing circuit 5 and the horizontal signal line 10.

The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.
The output circuit 7 performs signal processing on signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals.

[Configuration of main part of solid-state imaging device (plan view)]
FIG. 3 shows a schematic planar configuration of the unit pixel 2 of the solid-state imaging device.
As shown in FIG. 3, the unit pixel 2 includes three layers of first to third photoelectric conversion units that photoelectrically convert light of each wavelength of red (R), green (G), and blue (B). The photoelectric conversion region 15 and a charge reading unit corresponding to each photoelectric conversion unit. In the present embodiment example, the charge readout unit includes first to third pixel transistors TrA, TrB, and TrC corresponding to the first to third photoelectric conversion units. In the solid-state imaging device 1, the unit pixel 2 performs vertical spectroscopy.

  The first to third pixel transistors TrA, TrB, TrC are formed in the periphery of the photoelectric conversion region 15 and each include four MOS transistors. The first pixel transistor TrA outputs a signal charge generated and accumulated by a first photoelectric conversion unit, which will be described later, as a pixel signal, and includes a first transfer transistor Tr1, a reset transistor Tr4, an amplification transistor Tr5, and a selection transistor Tr6. Has been. The second pixel transistor TrB outputs a signal charge generated and accumulated by a second photoelectric conversion unit described later as a pixel signal, and includes a second transfer transistor Tr2, a reset transistor Tr7, an amplification transistor Tr8, and a selection transistor Tr9. Has been. The third pixel transistor TrC outputs a signal charge generated and accumulated by a third photoelectric conversion unit (to be described later) as a pixel signal, and includes a third transfer transistor Tr3, a reset transistor Tr10, an amplification transistor Tr11, and a selection transistor Tr12. Has been.

[Configuration of Pixel Unit of Solid-State Imaging Device]
FIG. 4 shows a schematic configuration of the photoelectric conversion region 15 shown in FIG. FIG. 4A is a cross-sectional configuration of the main part in the photoelectric conversion region of the solid-state imaging device. FIG. 4B is a planar configuration of the semiconductor layer viewed from the light receiving surface side in the photoelectric conversion region of the solid-state imaging device.
In FIG. 4, only the first to third transfer transistors Tr1, Tr2, and Tr3 of the first to third pixel transistors TrA, TrB, and TrC are illustrated, and the other pixel transistors are not illustrated. The solid-state imaging device according to the present embodiment is a back-illuminated solid-state imaging device in which light is incident from the back side opposite to the side where the pixel transistors on the front side of the semiconductor layer 17 are formed. In FIG. 4, the upper side is the light receiving surface side, and the lower side is a circuit forming surface on which peripheral circuits such as pixel transistors and logic circuits are formed.

  As illustrated in FIG. 4A, the solid-state imaging device includes a first photodiode PD1 and a second photodiode PD2 that serve as first and second photoelectric conversion units in the semiconductor layer 17. Further, as shown in FIG. 4B, the first photodiode PD1 and the second photodiode PD2 are stacked in the light incident direction in the semiconductor layer 17. As described above, the solid-state imaging device of this example has a configuration in which the photoelectric conversion film 32, the first photodiode PD1, and the second photodiode PD2 are stacked in the light incident direction.

In addition, the solid-state imaging device of this example includes a photoelectric conversion film 32 serving as a third photoelectric conversion unit on the back side of the semiconductor layer 17.
Instead of the photoelectric conversion film 32 serving as the third photoelectric conversion unit, a charge holding unit capable of holding electrons, such as a capacitor, may be provided. In the following description, an example of the present technology will be described based on the configuration in which the third photoelectric conversion unit includes the photoelectric conversion film 32. However, the photoelectric conversion unit is replaced with the charge holding unit, thereby including the charge holding unit. be able to.

The first and second photodiodes PD1 and PD2 are wells made of a semiconductor region 17 of the first conductivity type (p-type in this example) of the semiconductor layer 17 of the second conductivity type (n-type in this example) made of silicon or the like. The region (p-well) 16 is formed.
The first photodiode PD1 has an n-type semiconductor region 19 formed of a second conductivity type (n-type in this example) impurity formed on the light-receiving surface side of the semiconductor layer 17 and a part thereof reaching the surface side of the semiconductor layer. It has the extension part 19a formed by extending. The extension portion 19a is formed around the photoelectric conversion region where the three layers of photoelectric conversion portions are stacked. A high-concentration p-type semiconductor region (not shown) serving as a hole accumulation layer is formed on the surface of the extension 19a (the surface side of the semiconductor layer 17). The extension portion 19a functions as a layer that draws out signal charges accumulated in the n-type semiconductor region 19 of the first photodiode PD1 to the surface side of the semiconductor layer 17.

The second photodiode PD2 includes an n-type semiconductor region 20 formed on the surface side of the semiconductor layer 17. At the interface of the semiconductor layer 17 on the surface side of the n-type semiconductor region 20, a high-concentration p-type semiconductor region (not shown) serving as a hole accumulation layer is formed.
In the first photodiode PD1 and the second photodiode PD2, by forming a p-type semiconductor region at the interface of the semiconductor layer 17, dark current generated at the interface of the semiconductor layer 17 can be suppressed.

  The second photodiode PD2 formed in a region farthest from the light receiving surface serves as a photoelectric conversion unit that photoelectrically converts light having a red wavelength. The first photodiode PD1 formed on the light receiving surface side serves as a photoelectric conversion unit that photoelectrically converts light having a blue wavelength. And the photoelectric conversion film 32 arrange | positioned on the back surface of the semiconductor layer 17 turns into a photoelectric conversion part which photoelectrically converts the light of a green wavelength.

  The photoelectric conversion film 32 is formed via a first insulating layer 25 formed on the back surface of the semiconductor layer 17 and a second insulating layer 26 provided on the first insulating layer 25. An upper electrode 33 and a lower electrode 31 are formed on the upper and lower surfaces of the photoelectric conversion film 32. The upper electrode 33 and the lower electrode 31 are made of a light transmissive material.

  When the photoelectric conversion film 32 is used as a photoelectric conversion unit that photoelectrically converts light having a green wavelength, the photoelectric conversion film 32 is made of an organic photoelectric conversion material containing, for example, a rhodamine dye, a melocyanine dye, or quinacridone. The upper electrode 33 and the lower electrode 31 are made of a light transmissive material, and are made of a transparent conductive film such as an indium tin (ITO) film or an indium zinc oxide film.

Alternatively, the photoelectric conversion film 32 may be configured of a material that photoelectrically converts light having a blue or red wavelength, and the first photodiode PD1 and the second photodiode PD2 may be configured to correspond to other wavelengths.
For example, when blue light is absorbed by the photoelectric conversion film 32, the first photodiode PD1 formed on the light receiving surface side of the semiconductor layer 17 is set as a photoelectric conversion unit that photoelectrically converts green light. Then, the second photodiode PD2 is set as a photoelectric conversion unit that photoelectrically converts red light. Further, when red light is absorbed by the photoelectric conversion film 32, the first photodiode PD1 formed on the light receiving surface side of the semiconductor layer 17 is set as a photoelectric conversion unit that photoelectrically converts blue light. Then, the second photodiode PD2 is set as a photoelectric conversion unit that photoelectrically converts green light.

  The photoelectric conversion film for photoelectrically converting blue light is composed of an organic photoelectric conversion material containing, for example, a coumaric acid dye, tris-8-hydroxyquinori Al (Alq3), a melocyanine dye, and the like. The photoelectric conversion film that photoelectrically converts red light is composed of an organic photoelectric conversion material containing a phthalocyanine dye.

  In the solid-state imaging device having the above-described configuration, light that is photoelectrically converted in the semiconductor layer 17 is set to a blue wavelength and a red wavelength. And the light photoelectrically converted by the photoelectric conversion film 32 is set as a green wavelength. With such a configuration, the spectral characteristics between the first and second photodiodes PD1 and PD2 can be improved by receiving the green wavelength of the intermediate wavelength by the photoelectric conversion film 32.

  The lower electrode 31 formed on the semiconductor layer 17 side of the photoelectric conversion film 32 is connected to a contact plug 29 that penetrates the first insulating layer 25 and the second insulating layer 26. The contact plug 29 is connected to a vertical transfer path 50 formed from the back surface side to the front surface side of the semiconductor layer 17.

The vertical transfer path 50 includes a connection portion 21, a potential barrier portion 22, and a charge storage portion 23 that are formed in the vertical direction from the back surface side to the front surface side of the semiconductor layer 17.
The connection portion 21 is composed of a high-concentration n-type impurity region formed on the back side of the semiconductor layer 17. The connection portion 21 is configured to establish ohmic connection with the contact plug 29. The potential barrier unit 22 is formed of a low-concentration p-type impurity region, and serves as a potential barrier between the connection unit 21 and the charge storage unit 23. The charge accumulation unit 23 is a layer that accumulates signal charges transferred from the photoelectric conversion film 32, and includes an n-type impurity region having a lower concentration than the connection unit 21. In addition, a p-type semiconductor region (not shown) is formed on the outermost surface of the semiconductor layer 17 from a high-concentration p-type impurity region, and suppresses the generation of dark current at the interface of the semiconductor layer 17.

  When the photoelectric conversion film 32 is irradiated with light, signal charges (electrons) are generated in the photoelectric conversion film 32 disposed outside the semiconductor layer 17. This signal charge is read out from the photoelectric conversion film 32 to the connection part 21 of the n-type diffusion layer via the contact plug 29. Then, the charge accumulation unit 23 overflows through the p-type potential barrier unit 22.

Further, in the vertical transfer path 50 configured to overflow from the connection portion 21 to the charge storage portion 23 via the potential barrier portion 22, the semiconductor layer 17 surrounds the side surface of the vertical transfer path 50, and the vertical transfer path. A buried element isolation portion 27 is formed at a position in contact with the path 50.
In the configuration shown in FIG. 4A, the element isolation portion 27 is formed from the back surface side of the semiconductor layer 17 to a depth exceeding the connection surface between the connection portion 21 and the potential barrier portion 22. For this reason, all the surfaces (side surfaces) of the connection portion 21 are in contact with the element isolation portion 27 except for the back surface (upper surface) side of the semiconductor layer 17 and the surfaces (upper surface and bottom surface) in contact with the potential barrier portion 22.

  Further, the element isolation part 27 is formed to the inner side of the outer periphery of the connection surface between the potential barrier part 22 and the charge storage part 23. For this reason, the element isolation part 27 limits the area of the connection part 21 and the contact area between the connection part 21 and the potential barrier part 22 more than the connection area between the potential barrier part 22 and the charge storage part 23. .

  The element isolation portion 27 includes a groove (trench) 54 formed by etching the semiconductor layer 17 like STI, and a first insulating layer 25 and a second insulating layer 26 embedded in the trench 54. In this example, the insulating layer is formed from two layers of the first insulating layer 25 and the second insulating layer 26. However, the first insulating layer 25 and the second insulating layer 26 are not separated, and a single layer is formed. A structure in which an insulating layer is formed may be employed.

  The first insulating layer 25 and the second insulating layer 26 are made of an insulating film generally used in a semiconductor device. For example, it is composed of a silicon oxide film formed using an HDP (High Density Plasma) method. The first insulating layer 25 and the second insulating layer 26 are, for example, a compound of silicon, germanium, gallium, and metal, and further contain at least one element of oxygen, nitrogen, and carbon. A single layer or a structure in which these films are laminated.

  Further, in the portion where the buried type element isolation portion 27 and the p-well 16 are in contact with each other, there is a possibility that dark current is generated due to insufficient impurity concentration. In this case, it is preferable to dispose a film having a negative fixed charge on the first insulating layer 25, particularly on the sidewall of the trench 54. Examples of the material having a negative fixed charge include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and titanium oxide. In addition to the above materials, lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide Alternatively, a film having a negative fixed charge can be formed from yttrium oxide, an aluminum nitride film, a hafnium oxynitride film, an aluminum oxynitride film, or the like. In the film having a negative fixed charge, silicon (Si) or nitrogen (N) may be added to the film as long as the insulating property is not impaired. The concentration is appropriately determined as long as the insulating properties of the film are not impaired. Thus, by adding silicon (Si) or nitrogen (N), it becomes possible to increase the heat resistance of the film and the ability to prevent ion implantation during the manufacturing process.

  Furthermore, by arranging a low dielectric constant material such as SiOC inside the buried element isolation portion 27, it is possible to further enhance the effect of reducing the capacitance of the n-type diffusion layer. In addition, by forming a cavity in the insulating layer embedded in the element isolation part 27, it is possible to further enhance the effect of reducing the capacitance of the n-type diffusion layer.

  The first insulating layer 25 is in contact with the semiconductor layer (p-Well 16) in the back surface of the semiconductor layer 17 and in the element isolation part 27. Therefore, the first insulating layer 25 and the semiconductor layer 17 are formed by reacting with a material that hardly generates an interface state with the silicon substrate constituting the semiconductor layer 17, for example, silicon. An oxide film or the like may be provided.

As described above, an insulating layer is embedded in the element isolation portion 27. For this reason, in the vertical transfer path 50, the portion where the embedded element isolation unit 27 is disposed is electrically separated. Since the connection part 21 is surrounded by the element isolation part 27, the signal charge injected from the photoelectric conversion film 32 into the connection part 21 does not flow into the p-Well 16 from the connection part 21.
Therefore, the signal charge of the connection part 21 can be intensively overflowed to the charge storage part 23 via the potential barrier part 22 connected to the connection part 21.

In the solid-state imaging device having the above-described configuration, by enclosing the connection portion 21 with the element isolation portion 27, the current overflowing from the connection portion 21 can be concentrated on the potential barrier portion 22 and the charge storage portion 23 disposed below the connection portion 21. Is possible. Therefore, it is possible to reduce the junction cross-sectional area between the potential barrier portion 22 and the charge storage portion 23 and reduce the size of the element.
In addition, by enclosing the connection portion 21 with the element separation portion 27, it is possible to prevent the signal charge from flowing out from the connection portion 21 to the p-Well 16 when the photoelectric conversion film 32 is irradiated with a large amount of light. For this reason, the problem (crosstalk etc.) of the signal mixed into the other photoelectric conversion area | regions (PD1, PD2) and the charge storage part 23 beyond p-Well16 from the connection part 21 can be reduced significantly.
Further, in this structure, the signal charge is unlikely to leak into a region other than the potential barrier portion 22, so that the potential difference between the connection portion 21 and the p-well 16 can be reduced. By reducing the potential difference between the connection part 21 and the p-well 16, it is possible to suppress a leak current generated in the connection part 21.

In the above-described configuration, the embedded element isolation unit 27 is arranged so as to be in direct contact with the connection unit 21. For this reason, a pn junction is not formed between the connection part 21 and p-Well16. Thereby, the leak current generated at the pn junction can be prevented.
Further, since the pn junction area is limited in the element isolation part 27, the depletion capacity in the connection part 21 is reduced. For this reason, it is possible to suppress the noise from being mixed into the connection portion 21 due to the fluctuation of the voltage of the potential barrier portion 22.

  Furthermore, it is possible to suppress a phenomenon in which the signal charge (electrons) flows out of the connection portion 21 to the p-type semiconductor (p-Well 16) and recombines with the holes in the p-Well 16 and disappears when the large amount of light is irradiated. . Alternatively, it is possible to suppress a phenomenon in which holes are injected from the p-well 16 to the connection portion 21 and the sensitive electrons disappear.

The potential difference between the connection portion 21 and the p-Well 16 can be reduced by increasing the p-type impurity concentration of the potential barrier portion 22 or increasing the length of the potential barrier portion 22.
In FIG. 2, the potential barrier portion 22 and the p-well 16 are illustrated separately, but the potential barrier portion 22 and the p-well 16 have no difference in configuration except for the impurity concentration. For this reason, even if the potential barrier portion 22 is configured as the p-well 16, a desired operation as a solid-state imaging device is possible.

4A, the first to third pixel transistors corresponding to the first photodiode PD1, the second photodiode PD2, and the photoelectric conversion film 32 are provided on the surface side of the semiconductor layer 17 serving as a circuit formation surface. It is configured. FIG. 4A shows the first to third transfer transistors Tr3, Tr2, and Tr3.
The first transfer transistor Tr1 includes a floating diffusion portion FD1 formed on the surface side of the semiconductor layer adjacent to the extension portion 19a of the first photodiode PD1, and a transfer gate formed on the semiconductor layer 17 via a gate insulating film. And the electrode 37.
The second transfer transistor Tr2 includes a floating diffusion portion FD2 formed on the surface side of the semiconductor layer adjacent to the second photodiode PD2, and a transfer gate electrode 38 formed on the semiconductor layer 17 via a gate insulating film. Composed.
The third transfer transistor Tr3 includes a floating diffusion portion FD3 formed on the surface side of the semiconductor layer adjacent to the vertical transfer path 50, and a transfer gate electrode 39 formed on the semiconductor layer 17 via a gate insulating film. Is done.
The floating diffusion portions FD1, FD2, and FD3 are all configured by n-type high concentration impurity regions, and the transfer gate electrodes 37, 38, and 39 are configured by, for example, polysilicon.

  In FIG. 4A, the structure on the surface side of the semiconductor layer 17 shows only the structure of the transfer transistor, and the other structures are not shown. On the surface side of the semiconductor layer 17, for example, a multilayer wiring layer having a plurality of wirings stacked via an interlayer insulating film, a support substrate bonded to the multilayer wiring layer, and the like are formed.

  Further, on the light receiving surface side above the upper electrode 33, a light-shielding film that shields the vertical transfer path 50 and the extension portion 19a serving as a charge extraction portion from the first photodiode PD1, a planarizing film, and the like are formed. May be. An on-chip lens 35 is formed on the upper electrode 33 through a light shielding film, a planarizing film, or the like (not shown).

As shown in FIG. 3, actually, reset transistors Tr4, Tr7, Tr10, amplification transistors Tr5, Tr8, Tr11, and selection transistors Tr6, Tr9, Tr12 are formed on the surface side of the semiconductor layer 17. . The reset transistors Tr4, Tr7, Tr10 are composed of source / drain regions 43, 44 and a gate electrode 40. The amplification transistors Tr5, Tr8, Tr11 are composed of source / drain regions 44, 45 and a gate electrode 41. The selection transistors Tr6, Tr9, Tr12 are composed of source / drain regions 45, 46 and a gate electrode.
In these pixel transistors TrA, TrB, TrC, the floating diffusion portions FD1, FD2, FD3 are connected to one of the source / drain regions 43 of the corresponding reset transistors Tr4, Tr7, Tr10. Furthermore, the floating diffusion portions FD1, FD2, and FD3 are connected to the gate electrodes 41 of the corresponding amplification transistors Tr5, Tr8, and Tr11.
Further, the power source voltage wiring VDD is connected to the source / drain region 44 common to the reset transistors Tr4, Tr7, Tr10 and the amplification transistors Tr5, Tr8, Tr11. A selection signal line VSL is connected to one of the source / drain regions 46 of the selection transistors Tr6, Tr9, Tr12.

<3. First Embodiment (Method for Manufacturing Solid-State Imaging Device)>
Next, a method for manufacturing the solid-state imaging device according to the first embodiment will be described. 5 to 7 are manufacturing process diagrams of the solid-state imaging device according to the first embodiment. In particular, FIGS. 5 to 7 are diagrams illustrating manufacturing processes in a region where the photoelectric conversion unit is formed.

  First, as shown in FIG. 5A, a buried oxide film (hereinafter referred to as a BOX layer 52) and a semiconductor layer 17 made of a silicon epitaxial layer are formed on a substrate 51 made of silicon. Then, the p-well 16 is formed at a predetermined position of the semiconductor layer 17. Further, the connection part 21, the charge storage part 23, and the potential barrier part 22 that form the vertical transfer path 50 are formed at predetermined positions in the p-Well 16.

Since the connection portion 21 needs to be in ohmic contact with the contact plug 29 for reading out signal charges from the photoelectric conversion film 32, the connection portion 21 has a concentration of about 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ . A potential barrier portion 22 is formed by ion-implanting p-type impurities at a low concentration in the upper vertical direction of the connection portion 21. Subsequently, the charge storage portion 23 is formed by ion-implanting n-type impurities in the upper vertical direction of the potential barrier portion 22. The impurity concentration of the charge storage portion 23 is lower than that of the connection portion 21 and is formed by stepwise ion implantation so as to gradually increase from the potential barrier portion 22 side to the surface of the semiconductor layer 17.

Further, in the same process as the formation of the vertical transfer path 50, the n-type semiconductor region 19, the extension portion 19a constituting the first photodiode PD1, and the n-type semiconductor region 20 constituting the second photodiode PD2 are formed. .
Further, transfer gate electrodes 37, 38, 39 are formed on the surface side of the semiconductor layer 17 via a gate oxide film (not shown). Then, floating diffusion portions FD1, FD2, and FD3 are formed.

Further, the wiring 24 and the insulating layer 59 are stacked on the surface of the semiconductor layer 17 to form a wiring layer, and the first and second photodiodes PD1 and PD2 and the readout circuit portion of the photoelectric conversion film 32 are formed.
The structure shown in FIG. 5A can be formed using a technique used in a normal CMOS process, such as conventionally known ion implantation or CVD.

  Next, as shown in FIG. 5B, a support substrate 53 made of, for example, silicon is attached to the upper part of the wiring layer. Then, after inverting the element, the substrate 51 constituting the SOI substrate is removed, and the BOX layer 52 is exposed.

  Next, after forming a photoresist on the BOX layer 52, the photoresist in a region where the element isolation portion 27 is to be formed is removed. Then, as shown in FIG. 6C, the BOX layer 52 is selectively removed by etching, and the semiconductor layer 17 is etched using the BOX layer 52 as a hard mask. By this step, a trench 54 for forming the element isolation portion 27 is formed in the semiconductor layer 17. In this step, it is preferable to form the trench 54 to a position deeper than the junction portion between the connection portion 21 and the potential barrier portion 22 in order to enhance the effect of the element isolation portion 27.

  Next, as shown in FIG. 6D, the BOX layer 52 on the semiconductor layer 17 is removed. Then, as shown in FIG. 7E, the first insulating layer 25 and the second insulating layer 26 are formed. The first insulating layer 25 and the second insulating layer 26 are formed using, for example, chemical vapor deposition, sputtering, atomic layer deposition, or the like. The first insulating layer 25 and the second insulating layer 26 fill the inside of the formed trench 54 and further cover the surface of the semiconductor layer 17.

  The first insulating layer 25 is preferably formed using the above-described film having a negative fixed charge, a low dielectric constant material, or the like. In addition, an oxide film or the like formed by reaction with the semiconductor layer 17 that hardly generates interface states may be formed between the semiconductor layer 17 and the first insulating layer 25.

  Note that the first insulating layer 25 may be formed under film forming conditions in which the opening end side of the trench 54 is closed before the inside of the trench 54 is completely filled with the first insulating layer 25. In this method, before the interior of the trench 54 is embedded in the first insulating layer 25, the opening on the upper surface of the trench 54 is closed, no film-forming gas is supplied into the trench 54, and a void (void) is formed in the trench 54. ) Is formed. Thereafter, by further forming the insulating layers 25 and 26, a cavity can be formed in the trench 54 after the insulating layers 25 and 26 are formed. In this way, the element separation portion 27 having a hollow structure may be formed.

Next, as shown in FIG. 7F, a contact plug 29 that penetrates through the first insulating layer 25 and the second insulating layer 26 and is connected to the connecting portion 21 is formed. The contact plug 29 opens a predetermined position of the first insulating layer 25 and the second insulating layer 26 to form a contact hole. Then, a varimetal film is formed on the side wall and bottom of the contact hole, and is formed by embedding a metal material.
The contact plug 29 uses a laminated film of titanium (Ti) and titanium nitride (TiN) as a barrier metal film and tungsten (W) as a buried metal material of the contact hole in order to obtain an ohmic connection with the connection portion 21. It is preferable.

Further, as shown in FIG. 7F, a lower electrode 31 connected to the contact plug 29 is formed. As the transparent electrode, which is the lower electrode 31, for example, an ITO film having a thickness of about 100 nm formed by sputtering is used.
Further, an insulating film made of, for example, silicon oxide is formed so as to cover the lower electrode 31, and an opening through which the lower electrode 31 is exposed is formed in the insulating film. Then, the photoelectric conversion film 32 is formed so as to cover the opening. Thereafter, the upper electrode 33 is formed on the entire upper surface of the photoelectric conversion film 32. Similarly to the lower electrode 31, the upper electrode 33 uses, for example, a sputtering method and an ITO film having a thickness of about 100 nm.
Thereafter, a light shielding film, a flattening film or the like (not shown) is formed on the upper electrode 33, and the on-chip lens 35 is formed on the upper electrode 33.
Through the above steps, the solid-state imaging device shown in FIG. 4 can be manufactured.

  As a means for forming the element isolation portion 27, the BOX layer 52 is temporarily removed in the state shown in FIG. 5B, and a hard mask composed of an oxide film and SIN is generally formed as in the case of forming STI. There is also a method in which the semiconductor layer 17 is used for etching. However, in this example, the number of steps is reduced by using the BOX layer 52 as a hard mask.

<4. Second Embodiment (Solid-State Imaging Device)>
Next, a second embodiment of the solid-state imaging device will be described. The second embodiment differs from the solid-state imaging device of the first embodiment described above in the formation position of the element separation unit 27 and the configuration of the vertical transfer path 50. For this reason, in the following description of the second embodiment, only the configuration of the element isolation unit 27 and the vertical transfer path 50 different from the above-described first embodiment will be described, and the configuration similar to that of the first embodiment will be described. Omitted.

  FIG. 8 shows a schematic configuration of the solid-state imaging device of the second embodiment. FIG. 8A is a cross-sectional configuration of the main part in the photoelectric conversion region of the solid-state imaging device. FIG. 8B is a planar configuration of the semiconductor layer viewed from the light receiving surface side in the photoelectric conversion region of the solid-state imaging device.

  As shown in FIG. 8A, the solid-state imaging device of this example has a configuration in which the connection part 21 and the element separation part 27 of the vertical transfer path 50 do not contact each other. This configuration is the same as the configuration of the solid-state imaging device of the first embodiment described above except for the configuration of the vertical transfer path 50 and the element separation unit 27.

  The element isolation part 27 is formed at a position surrounding the periphery of the vertical transfer path 50. The element isolation portion 27 is formed from the back surface side of the semiconductor layer 17 to a depth exceeding the connection surface between the connection portion 21 and the potential barrier portion 22. In addition, the p-well 16 is disposed between the vertical transfer path 50 and the element isolation unit 27. For this reason, the p-well 16 is disposed between the side surface of the connection portion 21 and the element isolation portion 27 and between the potential barrier portion 22 and the element isolation portion 27.

  As shown in FIGS. 8A and 8B, since the element isolation unit 27 is not formed in contact with the vertical transfer path 50, unlike the first embodiment, the connection unit 21, the potential barrier unit 22, and the charge The storage portions 23 are formed with the same area.

  When the photoelectric conversion film 32 is irradiated with light, signal charges generated by the photoelectric conversion film 32 disposed outside the semiconductor layer 17 are injected into the connection portion 21 formed of the n-type diffusion layer through the contact plug 29. . Then, the signal charge injected from the photoelectric conversion film 32 to the connection portion 21 overflows to the charge storage portion 23 through the potential barrier portion 22.

  In the configuration described above, the connection part 21 and the potential barrier part 22 and the element isolation part 27 are not in contact, but the element isolation part 27 is arranged so as to surround the connection part 21, and the element isolation part 27 is arranged. It is electrically divided at the spot. For this reason, the injection current from the connection part 21 is electrically insulated by the element isolation part 27. For this reason, the charge injected into the connection portion 21 is effectively collected toward the potential barrier portion 22.

  Further, the signal charge that has flowed out of the connection portion 21 to the p-Well 16 is also prevented from moving in the horizontal direction by the element isolation portion 27. For this reason, the signal charge that has flowed out from the connection portion 21 to the p-Well 16 also moves in the vertical direction of the drawing, and is effectively collected in the direction of the potential barrier portion 22 and the charge storage portion 23. At this time, an overflow path 55 from the connection unit 21 to the charge storage unit 23 is formed in the p-Well 16 between the connection unit 21 and the element isolation unit 27. At this time, the p-Well 16 becomes a potential barrier.

In the solid-state imaging device having the above-described configuration, the element separating unit 27 can concentrate the current overflowing from the connection unit 21 on the potential barrier unit 22 and the charge storage unit 23 disposed below the connection unit 21. For this reason, it is possible to reduce the junction cross-sectional area of the potential barrier portion 22 and the charge storage portion 23 and reduce the size of these elements.
Moreover, when the photoelectric conversion film 32 is irradiated with a large amount of light, the outflow of signal charges from the connection portion 21 to the p-Well 16 can be reduced. For this reason, the problem (crosstalk etc.) of the signal mixed into the other photoelectric conversion area | regions (PD1, PD2) and the charge storage part 23 beyond p-Well16 from the connection part 21 can be reduced significantly.
In addition, the potential difference between the connection portion 21 and the p-Well 16 can be reduced, and a leak current generated in the connection portion 21 can be suppressed.

[Modification]
Next, a modification of the above-described second embodiment will be described. In the above-described second embodiment (FIG. 8A), the p-Well 16 is disposed between the connection portion 21 and the element isolation portion 27. However, the p-well 16 and the p-type potential barrier portion 22 differ only in the impurity concentration. Therefore, even if the p-Well 16 between the connection unit 21 and the element isolation unit 27 is replaced with the p-type potential layer barrier unit 22, the same effect as that of the solid-state imaging device of the second embodiment described above can be obtained. .

  FIG. 9 shows a schematic configuration of a solid-state imaging device according to a modification of the second embodiment. FIG. 9A is a cross-sectional configuration of the main part in the photoelectric conversion region of the solid-state imaging device. FIG. 9B is a plan configuration showing the configuration of the light receiving surface side of the semiconductor layer in the photoelectric conversion region of the solid-state imaging device.

As shown in FIG. 9A, a potential barrier portion 56 is formed in the semiconductor layer 17 so as to cover a region where the connection portion 21 is formed. Further, the potential barrier portion 56 is formed between the connection portion 21 and the element isolation portion 27. For this reason, all except the substrate surface of the connection part 21 is in contact with the potential barrier part 56.
Further, as shown in FIGS. 9A and 9B, the potential barrier portion 56 is formed with a larger area than the connection portion 21 and the charge storage portion 23. The areas of the connection part 21 and the charge storage part 23 are the same as those in the second embodiment. The contact area between the potential barrier unit 56 and the charge storage unit 23 is also the same as that in the second embodiment.

Also in the configuration of the above-described modification, the element isolation unit 27 electrically insulates the injected current from the connection unit 21 by the element isolation unit 27, and the signal charge is stored in the potential barrier unit 56 and the charge accumulation below the connection unit 21. It is collected effectively in the direction of the unit 23.
Further, the signal separation that has flowed out from the connection portion 21 to the charge storage portion 23 in the side surface direction is also prevented from moving in the horizontal direction of the drawing by the element isolation portion 27. Therefore, an overflow path 55 through which signal charges are transferred from the connection unit 21 to the charge storage unit 23 is formed in the potential barrier unit 56.

  In addition, the manufacturing method of the solid-state imaging device of the above-described second embodiment and its modification may be changed in the first embodiment by changing the position where the trench is formed. For example, in the step shown in FIG. 6C, the pattern formed in the BOX layer 52 is changed, and the position where the trench 54 is formed is changed to a position where it does not contact the connection portion 21 of the vertical transfer path 50. Thereafter, by manufacturing the solid-state imaging device using the same method as that of the first embodiment, it is possible to manufacture the solid-state imaging device of the second embodiment and its modification.

  Contrary to the above-described modification, the potential barrier unit 56 and the p-well 16 are different only in the impurity concentration. Therefore, the potential barrier unit 56 is not formed and the entire potential barrier unit 56 is entirely formed. You may form with p-Well16. Also in this case, the same effect as the solid-state imaging device of the second embodiment described above can be obtained. Furthermore, also in the first embodiment described above and in each embodiment described below, the potential barrier portion can be replaced with a p-well.

<5. Third Embodiment (Solid-State Imaging Device)>
Next, a third embodiment of the solid-state imaging device will be described. The third embodiment differs from the solid-state imaging device of the second embodiment described above only in the configuration of the insulating layer formed on the vertical transfer path 50. For this reason, in the following description of the third embodiment, only the configuration of the vertical transfer path 50 and the insulating layer, which are different from those of the above-described second embodiment, will be described, and the description of the same configuration as in the second embodiment will be omitted.

  FIG. 10 shows a schematic configuration of the solid-state imaging device of the third embodiment. FIG. 10A is a cross-sectional configuration of the main part in the photoelectric conversion region of the solid-state imaging device. FIG. 10B is a plan configuration showing the configuration of the light receiving surface side of the semiconductor layer in the photoelectric conversion region of the solid-state imaging device.

As shown in FIG. 10A, in the solid-state imaging device of this example, a third insulating layer 57 is formed on the vertical transfer path 50. In the configuration shown in FIG. 10A, the third insulating layer 57 is formed at a position covering the connection portion 21 inside the element isolation portion 27 and the p-Well 16.
The third insulating layer 57 is formed by a manufacturing method in which the interface state can be reduced as compared with the normal film-forming oxidation, such as a buried oxide film (BOX layer) produced by thermally oxidizing silicon at a high temperature.

In the configuration of the first embodiment described above, the pn junction between the connection portion 21 and the potential barrier portion 22 is formed on the side wall of the trench 54 of the embedded element isolation portion 27. In the configuration of the second embodiment described above, the pn junction between the connection portion 21 and the p-well 16 is formed on the back surface interface of the semiconductor layer 17.
In general, since the interface of the semiconductor layer 17 has a high density of defect states, a large amount of leakage current is generated. In order to suppress this, it is desirable to dispose a thermal oxide film or the like formed by reaction with the semiconductor layer 17 (for example, silicon) at the back surface interface of the semiconductor layer 17, for example. However, since various transistors and wirings are formed on the surface side of the semiconductor layer 17, high-temperature heat treatment cannot be performed.
When a film having a negative fixed charge is formed as the first insulating layer 25, a film having a negative fixed charge is also disposed on the connection portion 21 that is an n-type diffusion layer. In this case, there is a problem that the n-type impurity concentration on the surface of the connection portion 21 in contact with the film having a negative fixed charge is lowered.

For this reason, as shown in FIG. 10A, the third insulating layer 57 covering the connection portion 21 is formed of an insulating film capable of reducing the interface state, whereby the signal charge is injected from the photoelectric conversion film 32. Leakage current at the interface of the part 21 can be suppressed. Similarly, leakage current at the interface between the connection portion 21 in the element isolation portion 27 and the p-Well 16 can be suppressed.
Furthermore, even when a film having a negative fixed charge is used as the first insulating layer 25, the third insulating layer 57 can prevent contact between the connection portion 21 and the film having a negative fixed charge. For this reason, it is possible to prevent a decrease in the n-type impurity concentration on the surface of the connection portion 21.

  According to the above-described configuration, an arbitrary film can be formed on the side wall of the trench 54 where the element isolation portion 27 is formed and the back surface interface of the semiconductor layer 17 by the action of the third insulating layer 57. Become. For example, if a film having a negative fixed charge is formed, the p-type impurity concentration at the side wall of the element isolation portion 27 and the back surface interface portion of the p-Well 16 is increased, and the leakage current can be suppressed.

<6. Third Embodiment (Method for Manufacturing Solid-State Imaging Device)>
Next, a method for manufacturing the solid-state imaging device according to the third embodiment will be described. FIGS. 11 to 12 are manufacturing process diagrams of the solid-state imaging device according to the third embodiment, and particularly show manufacturing processes in a region where the photoelectric conversion unit is formed.

First, using the same method as in the first embodiment, the process up to the step of attaching the support substrate 53 and exposing the BOX layer 52 as shown in FIG. 5B is performed. Then, after forming a photoresist on the BOX layer 52, the photoresist in a region where the element isolation portion 27 is to be formed is removed. Then, as shown in FIG. 11A, the BOX layer 52 is selectively removed by etching, and the semiconductor layer 17 is etched using the BOX layer 52 as a hard mask. By this step, a trench 54 for forming the element isolation portion 27 is formed in the semiconductor layer 17. In this step, it is desirable to form the trench 54 to a position deeper than the junction between the connection portion 21 and the potential barrier portion 22 in order to enhance the effect of the element isolation portion 27.
In the third embodiment, the trench 54 is formed at a position away from the connection portion 21 so that the pn junction between the connection portion 21 and the p-well 16 is disposed at the back surface interface of the semiconductor layer 17.

  Next, as shown in FIG. 11B, a photoresist 58 is formed on the portion covering the BOX layer 52 disposed on the connection portion 12. Then, as shown in FIG. 12C, the BOX layer 52 in the region where the photoresist 58 is not formed is removed by etching. In this example, a photoresist is used for selective removal of the BOX layer 52. However, when it is difficult to secure a selection ratio, a hard mask such as SiN is used.

Next, the first insulating layer 25 and the second insulating layer 26 are formed on the surface of the semiconductor layer 17 and the inner surface of the trench 54 constituting the element isolation portion 27. In the present example, since the exposed semiconductor layer 17 is a p-type semiconductor (p-Well 16), the first insulating layer 25 is preferably formed using a film having a negative fixed charge. Alternatively, a hollow portion may be formed in the trench 54 to form the element isolation portion 27 having a hollow structure.
A contact plug 29, a lower electrode 31, a photoelectric conversion film 32, an upper electrode 33, an on-chip lens 35, and the like are formed by the same method as in the first embodiment, and the solid-state imaging device having the configuration shown in FIG. 12D. Can be manufactured.

  In the second embodiment described above, as shown in FIG. 11A, the trench 54 is formed at a position away from the connection portion 21, and the solid-state imaging device is manufactured by performing the subsequent steps as in the first embodiment. it can.

<7. Fourth Embodiment (Solid-State Imaging Device)>
Next, a fourth embodiment of the solid-state imaging device will be described. In the fourth embodiment, the solid-state imaging device of the first embodiment described above, the configuration of the vertical transfer path, the formation position of the third transfer transistor that transfers the signal charge from the vertical transfer path, and the element isolation unit The configuration is different. For this reason, in the following description of the fourth embodiment, only the configuration different from the above-described first embodiment will be described, and the description of the same configuration as in the first embodiment will be omitted.

  FIG. 13 shows a schematic configuration of the solid-state imaging device of the fourth embodiment. FIG. 13A is a cross-sectional configuration of the main part in the photoelectric conversion region of the solid-state imaging device. FIG. 13B is a plan configuration showing the configuration of the light receiving surface side of the semiconductor layer in the photoelectric conversion region of the solid-state imaging device.

As shown in FIGS. 13A and 13B, in the solid-state imaging device of this example, the configuration of the signal extraction portion formed from the back surface side to the front surface side of the semiconductor layer 17 is different from that of the first embodiment.
The signal extraction unit includes a connection unit 61 that reads out signal charges of the photoelectric conversion film 32, a potential barrier unit 62 that is disposed in the lateral direction of the connection unit 61, and a charge storage formed from the back side to the front side of the semiconductor layer 17. The unit 63 is provided.
The third transfer transistor Tr3 is composed of the floating diffusion part FD3 formed on the surface side of the semiconductor layer adjacent to the charge storage part 63 and the transfer gate electrode 39 formed on the semiconductor layer 17 via the gate insulating film. Is done.

The connecting portion 61 is made of a high concentration n-type impurity region formed on the back side of the semiconductor layer 17. The connecting portion 61 is configured to make an ohmic connection with the contact plug 29.
The potential barrier portion 62 is formed on the surface on the back surface side of the semiconductor layer 17 and in contact with the connecting portion 61 in the lateral direction, that is, in the main surface direction of the semiconductor layer 17. The potential barrier unit 62 is formed of a low-concentration p-type impurity region, and serves as a potential barrier between the connection unit 61 and the charge storage unit 63.
The charge accumulation unit 63 is a layer for accumulating signal charges transferred from the photoelectric conversion film 32, and is configured by an n-type impurity region having a lower concentration than the connection unit 61. The charge storage unit 63 is formed at a position in contact with the potential barrier unit 62 in the lateral direction. The charge storage unit 63 is formed from the surface on the back surface side of the semiconductor layer 17 to the vicinity of the surface of the semiconductor layer 17. A high-concentration p-type semiconductor region (not shown) serving as a hole accumulation layer is formed at the interface of the semiconductor layer 17 on the surface side of the charge accumulation unit 63, and suppresses the generation of dark current at the interface of the semiconductor layer 17.
The potential barrier unit 62 and the charge storage unit 63 are formed in a direction different from the direction in which the first photodiode PD1 and the second photodiode PD2 are formed with respect to the connection unit 61.

In the semiconductor layer 17, in the transfer path configured to overflow from the connection portion 61 to the charge storage portion 63 via the potential barrier portion 62, the embedded type is provided at a position surrounding the side surface of the connection portion 61 and in contact with the connection portion 61. The element isolation part 64 is formed.
The element isolation part 64 includes a trench 65 and a first insulating layer 25 and a second insulating layer 26 embedded in the trench 65.
As shown in FIG. 13A, the element isolation part 64 is formed at a position in contact with the connection part 61 between the connection part 61 and the n-type semiconductor region 19 constituting the first photodiode PD1. In addition, the element isolation part 64 is formed from the surface of the semiconductor layer 17 to a depth greater than the connection part 61 is formed.

As shown in FIG. 13B, the element isolation portion 64 is formed in contact with the side surface of the connection portion 61 on all surfaces other than the surface in contact with the potential barrier portion 62 of the connection portion 61. Further, the contact portion 61 is formed in contact with the side surface of the potential barrier portion 62 from the contact surface with the potential barrier portion 62 to the vicinity of the connection surface between the potential barrier portion 62 and the charge storage portion 63.
Accordingly, the connection part 61 is entirely surrounded by the element isolation part 64 except for the connection surface between the connection part 61 and the potential barrier part 62, and the top and bottom surfaces. That is, the connection part 61 is in contact with the p-Well 16 only at the bottom surface.

When the photoelectric conversion film 32 is irradiated with light, signal charges (electrons) are generated in the photoelectric conversion film 32 disposed outside the semiconductor layer 17. This signal charge is injected from the photoelectric conversion film 32 through the contact plug 29 into the connection portion 61 made of an n-type diffusion layer. Then, the signal charge injected into the connection part 61 overflows into the charge storage part 63 through the p-type potential barrier part 62.
Since the connecting portion 61 and the charge storage portion 63 are connected in the main surface direction (lateral direction) of the semiconductor layer 17, the signal charge of the connecting portion 61 moves in the horizontal direction in this configuration.

  And in the side surface direction of the connection part 61, the connection part 61 is electrically interrupted | blocked by p-Well16 by providing the element isolation | separation part 64 between the connection part 61 and p-Well16. For this reason, the overflow current from the connection portion 61 to the portion other than the potential barrier portion 62 is suppressed, and the charge transfer efficiency to the charge storage portion 63 can be improved. Accordingly, the junction cross-sectional area of the potential barrier unit 62 and the charge storage unit 63 can be reduced, and the element size can be reduced.

  Moreover, since the connection part 61 is surrounded by the element isolation part 64, when the photoelectric conversion film 32 is irradiated with a large amount of light, the outflow of signal charges from the connection part 61 to the p-well 16 can be reduced. . For this reason, the problem (crosstalk etc.) of the signal mixed into the other photoelectric conversion regions (PD1, PD2) and the charge storage unit 63 beyond the p-well 16 from the connection unit 61 can be significantly reduced.

  Further, in this structure, the signal charge is less likely to leak into a region other than the potential barrier portion 62, so that the potential difference between the connecting portion 61 and the p-well 16 can be reduced. By reducing the potential difference between the connection portion 61 and the p-Well 16, a leak current generated in the connection portion 61 can be suppressed.

In the above-described configuration, the embedded element isolation unit 64 is arranged so as to be in direct contact with the connection unit 61. For this reason, the pn junction area between the connection part 61 and the p-Well 16 is limited. Thereby, the leakage current generated at the pn junction can be suppressed.
In addition, the depletion capacity at the connection portion 61 is reduced by reducing the pn junction area. For this reason, it is possible to suppress the noise from being mixed into the connecting portion 61 due to the fluctuation of the voltage of the potential barrier portion 62.

  Further, it is possible to suppress a phenomenon in which the signal charge (electrons) flows out of the connection portion 61 to the p-type semiconductor (p-Well 16) and recombines with the holes in the p-Well 16 and disappears when the large amount of light is irradiated. . Alternatively, a phenomenon in which holes are injected from the p-well 16 to the connection portion 61 and the sensitivity electrons disappear can be suppressed.

In the above-described configuration, the configuration in which the connection portion 61 and the element isolation portion 64 are in contact with each other is described. However, as in the configuration of the second embodiment, the connection portion 61 and the element isolation portion 64 are in contact with each other. It is good also as a structure which is not. Also in this case, as shown in FIG. 13B, the element isolation portion 64 surrounding the side surface of the connection portion 61 and the potential barrier portion 62 is formed from the pn junction surface of the connection portion 61 and the potential barrier portion 62 to the potential barrier portion 62. By forming, the same effect as in the second embodiment described above can be obtained.
Further, as in the third embodiment, a third insulating layer may be formed in the n-type diffusion layer so that the connection portion 61 of the n-type diffusion layer and the first insulating layer 25 do not contact each other.

<8. Fourth Embodiment (Method for Manufacturing Solid-State Imaging Device)>
Next, a method for manufacturing the solid-state imaging device according to the fourth embodiment will be described. 14 to 15 are manufacturing process diagrams of the solid-state imaging device according to the fourth embodiment. In particular, FIGS. 14 to 15 are diagrams illustrating manufacturing processes in a region where the photoelectric conversion unit is formed.

First, as shown in FIG. 14A, the configuration of each element such as the semiconductor layer 17 and the wiring layer is formed using the same method as in the first embodiment.
For example, a buried oxide film (hereinafter referred to as a BOX layer 52) and a semiconductor layer 17 made of a silicon epitaxial layer are formed on a substrate 51 made of silicon. Then, the p-well 16 is formed at a predetermined position of the semiconductor layer 17. Further, the connection part 61, the charge storage part 63, and the potential barrier part 62 are formed at predetermined positions in the p-Well 16.

Further, in the step of forming the connection portion 61 and the charge storage portion 63, the n-type semiconductor region 19 constituting the first photodiode PD1, the extension portion 19a, and the n-type semiconductor region 20 constituting the second photodiode PD2 are formed. Form.
Further, transfer gate electrodes 37, 38, 39 are formed on the surface side of the semiconductor layer 17 via a gate oxide film (not shown). Then, floating diffusion portions FD1, FD2, and FD3 are formed.

Then, the wiring 24 and the insulating layer 59 are stacked on the surface of the semiconductor layer 17 to form a wiring layer, and the first and second photodiodes PD1 and PD2 and the readout circuit portion of the photoelectric conversion film 32 are formed. Further, a support substrate 53 made of, for example, silicon is attached on the formed wiring layer. Then, after inverting the element, the substrate 51 constituting the SOI substrate is removed, and the BOX layer 52 is exposed.
The configuration shown in FIG. 14A can be formed using a technique used in a normal CMOS process, such as conventionally known ion implantation or CVD.

  Next, after forming a photoresist on the BOX layer 52, the photoresist in a region where the element isolation portion 64 is to be formed is removed. Then, as shown in FIG. 14B, the BOX layer 52 is selectively removed by etching, and the semiconductor layer 17 is etched using the BOX layer 52 as a hard mask. By this step, a trench 65 for forming the element isolation portion 64 is formed in the semiconductor layer 17. In this step, the trench 65 is formed deeper than the connection portion 61 in order to enhance the effect of the element isolation portion 64.

Next, as shown in FIG. 15C, the BOX layer 52 on the semiconductor layer 17 is removed, and the first insulating layer 25 and the second insulating layer 26 are formed. The first insulating layer 25 and the second insulating layer 26 can be formed by a conventionally known insulating layer. The first insulating layer 25 and the second insulating layer 26 fill the inside of the formed trench 65 and cover the surface of the semiconductor layer 17.
The first insulating layer 25 is preferably formed using the above-described film having a negative fixed charge, a low dielectric constant material, or the like. Further, an oxide film or the like that hardly generates interface states may be formed between the semiconductor layer 17 and the first insulating layer 25.

  Next, the contact plug 29, the lower electrode 31, the photoelectric conversion film 32, the upper electrode 33, the on-chip lens 35, and the like are formed by the same method as in the first embodiment, and the solid-state imaging having the configuration shown in FIG. 15D. The device can be manufactured.

<9. Fifth Embodiment (Solid-State Imaging Device)>
Next, a fifth embodiment of the solid-state imaging device will be described. The fifth embodiment differs from the solid-state imaging device of the fourth embodiment described above in the configuration of the element separation unit. For this reason, in the following description of the fifth embodiment, only the configuration different from the above-described fourth embodiment will be described, and the description of the configuration similar to the fourth embodiment will be omitted.

  FIG. 16 shows a schematic configuration of the solid-state imaging device of the fifth embodiment. FIG. 16A is a cross-sectional configuration of the main part in the photoelectric conversion region of the solid-state imaging device. FIG. 16B is a plan configuration showing the configuration of the light receiving surface side of the semiconductor layer in the photoelectric conversion region of the solid-state imaging device.

  As shown in FIGS. 16A and 16B, the solid-state imaging device of this example has a configuration in which the element separation unit 66 is disposed at a position where both the side surface and the bottom surface of the connection unit 61 and the potential barrier unit 62 are in contact with each other. This configuration is the same as the configuration of the solid-state imaging device of the fourth embodiment described above, except for the configuration of the element isolation unit 66.

  The connection part 61 is surrounded by the element isolation part 66 on all sides except for the surface of the semiconductor layer 17 and the region in contact with the potential barrier part 62. That is, all the connections between the connection unit 61 and the p-Well 16 are blocked by the element isolation unit 66. For this reason, the signal charge injected from the photoelectric conversion film 32 to the connection portion 61 does not flow into the p-Well 16 from the connection portion 61 but overflows intensively to the charge storage portion 63 via the potential barrier portion 62. .

In the solid-state imaging device having the above-described configuration, by enclosing the side surface and the bottom surface of the connection portion 61 with the element isolation portion 66, the potential barrier portion 62 and the charge storage portion 63 disposed on the side surface of the current overflowing from the connection portion 61 are provided. It is possible to concentrate on. Therefore, it is possible to reduce the junction cross-sectional area between the potential barrier unit 62 and the charge storage unit 63 and reduce the size of the element.
In addition, by surrounding the connection portion 61 with the element isolation portion 66, it is possible to prevent the signal charge from flowing out from the connection portion 61 to the p-Well 16. For this reason, the problem (crosstalk etc.) of the signal mixed into the other photoelectric conversion regions (PD1, PD2) and the charge storage unit 63 beyond the p-well 16 from the connection unit 61 can be significantly reduced.
Further, in this structure, the signal charge is unlikely to leak into a region other than the potential barrier portion 62, so that the potential difference between the connection portion 61 and the p-well 16 can be reduced. By reducing the potential difference between the connection portion 61 and the p-Well 16, a leak current generated in the connection portion 61 can be suppressed.

In the above-described configuration, the embedded element isolation portion 66 is disposed so as to be in direct contact with the connection portion 61. For this reason, the pn junction between the connection part 61 and p-Well16 is not formed. Thereby, the leak current generated at the pn junction can be prevented.
Further, since the pn junction area is limited within the element isolation portion 66, the depletion capacity at the connection portion 61 is reduced. For this reason, it is possible to suppress the noise from being mixed into the connecting portion 61 due to the fluctuation of the voltage of the potential barrier portion 62.

  Further, it is possible to suppress a phenomenon in which the signal charge (electrons) flows out of the connection portion 61 to the p-type semiconductor (p-Well 16) and recombines with the holes in the p-Well 16 and disappears when the large amount of light is irradiated. . Alternatively, a phenomenon in which holes are injected from the p-well 16 to the connection portion 61 and the sensitivity electrons disappear can be suppressed.

  In the above-described configuration, the configuration in which the connection portion 61 and the element isolation portion 66 are in contact with each other has been described. However, as in the configuration of the second embodiment and the configuration of the modification of the second embodiment, the connection The part 61 and the element isolation part 66 may not be in contact with each other. In this case, the p-Well 16 is disposed on the side surface and the bottom surface of the connection portion 61 and the potential barrier portion 62. However, similarly to the configuration of the second embodiment described above, even when the p-well 16 is formed in the element isolation unit 66, the charge transfer unit from the connection unit 61 to the charge storage unit 63 is the element isolation unit 66. It becomes the composition surrounded by. Therefore, the signal charge injected from the photoelectric conversion film 32 to the connection portion 61 can be intensively overflowed to the charge storage portion 63 via the potential barrier portion 62 and the p-well 16.

<10. Fifth Embodiment (Manufacturing Method of Solid-State Imaging Device)>
Next, a method for manufacturing the solid-state imaging device according to the fifth embodiment will be described. 17 to 19 are manufacturing process diagrams of the solid-state imaging device according to the fifth embodiment. In particular, FIGS. 17 to 19 are diagrams illustrating manufacturing processes in a region where the photoelectric conversion unit is formed.

First, as shown in FIG. 17A, the structure of each element such as the semiconductor layer 17 and the wiring layer is formed by using the same method as in the first embodiment.
For example, a buried oxide film (hereinafter referred to as a BOX layer 52) and a semiconductor layer 17 made of a silicon epitaxial layer are formed on a substrate 51 made of silicon. Then, the p-well 16 is formed at a predetermined position of the semiconductor layer 17. Further, the connection part 61, the charge storage part 63, and the potential barrier part 62 are formed at predetermined positions in the p-Well 16.
Further, in the same step as the step of forming the connection portion 61 and the charge storage portion 63, the n-type semiconductor region 19 that constitutes the first photodiode PD1, the extension portion 19a, and the n-type semiconductor that constitutes the second photodiode PD2. Region 20 is formed.

  Further, oxygen ions are implanted into a predetermined position of the semiconductor layer 17. In FIG. 17A, oxygen ions are implanted into regions along the bottom surfaces of the connection portion 61 and the potential barrier portion 62 from the side surface of the charge storage portion 63 to a position beyond the side surface of the connection portion 61. Then, after implanting oxygen ions, annealing is performed to form a buried oxide film 67. In this method, a known Partial SIMOX (Separation by Implanted Oxygen) technique is used.

Next, as shown in FIG. 17B, transfer gate electrodes 37, 38, and 39 are formed on the surface side of the semiconductor layer 17 through a gate oxide film (not shown). Then, floating diffusion portions FD1, FD2, and FD3 are formed.
Then, the wiring 24 and the insulating layer 59 are stacked on the surface of the semiconductor layer 17 to form a wiring layer, and the first and second photodiodes PD1 and PD2 and the readout circuit portion of the photoelectric conversion film 32 are formed.

Next, as shown in FIG. 18C, a support substrate 53 made of, for example, silicon is attached to the upper part of the wiring layer. Then, after inverting the element, the substrate 51 constituting the SOI substrate is removed, and the BOX layer 52 is exposed.
Then, after forming a photoresist on the BOX layer 52, the photoresist in a region where the element isolation portion 64 is to be formed is removed. The BOX layer 52 is selectively removed by etching, and the semiconductor layer 17 is etched using the BOX layer 52 as a hard mask. By this step, a trench 68 for forming the element isolation portion 66 is formed in the semiconductor layer 17. In this step, the trench 68 is formed to a depth that reaches the buried oxide film 67 in order to form the element isolation portion 66.

  Next, as shown in FIG. 18D, the buried oxide film 67 is removed from the formed trench 68 to form a cavity 69 in the semiconductor layer 17. The trench 68 and the cavity 69 serve as a region where the element isolation portion 66 is formed. The buried oxide film 67 is removed by wet etching or dry etching.

Next, as shown in FIG. 19E, the BOX layer 52 on the semiconductor layer 17 is removed, and the first insulating layer 25 and the second insulating layer 26 are formed. The first insulating layer 25 and the second insulating layer 26 can be formed by a conventionally known insulating layer. The first insulating layer 25 and the second insulating layer 26 fill the inside of the formed trench 54 and cover the surface of the semiconductor layer 17. As shown in FIG. 19E, the cavity 69 may be filled with the first insulating layer 25, or may be filled with the first insulating layer 25 and the second insulating layer 26.
The first insulating layer 25 is preferably formed using the above-described film having a negative fixed charge, a low dielectric constant material, or the like. Further, an oxide film or the like that hardly generates interface states may be formed between the semiconductor layer 17 and the first insulating layer 25.

Next, as shown in FIG. 15D, the contact plug 29, the lower electrode 31, the photoelectric conversion film 32, the upper electrode 33, the on-chip lens 35, and the like are formed by the same method as in the first embodiment.
Through the above steps, the solid-state imaging device of the fifth embodiment can be manufactured.

<11. Sixth Embodiment (Solid-State Imaging Device)>
Next, a sixth embodiment of the solid-state imaging device will be described. In the sixth embodiment, an electrode formed in the element isolation unit 27 and wiring connected to the electrode are added to the configuration of the solid-state imaging device of the first embodiment described above. For this reason, in the following description of the sixth embodiment, only the configuration different from the above-described first embodiment will be described, and the description of the same configuration as the first embodiment will be omitted.

  FIG. 20 shows a schematic configuration of the solid-state imaging device of the sixth embodiment. FIG. 20A is a cross-sectional configuration of the main part in the photoelectric conversion region of the solid-state imaging device. FIG. 20B is a planar configuration viewed from the light receiving surface side in the photoelectric conversion region of the solid-state imaging device.

  As shown in FIG. 20A, in the solid-state imaging device of this example, the element isolation unit 70 includes the trench 54 formed in the semiconductor layer 17, the first insulating layer 25 covering the inner surface of the trench 54, the trench 54, and the first insulation. The electrode 71 is formed in the layer 25. The wiring 72 is formed on the first insulating layer 25 and connected to the electrode 71. This configuration is the same as the configuration of the solid-state imaging device of the first embodiment described above, except for the configuration of the element isolation unit 70 and the wiring 72.

As shown in FIG. 20B, the wiring 72 formed on the first insulating layer 25 is a vertical transfer path 50 except for the periphery of the contact plug 29 that transmits the signal charge from the photoelectric conversion film 32 to the connection portion 21. It is formed in the position which covers the surface of. In FIG. 20B, the position where the charge accumulation unit 23 of the vertical transfer path 50 formed below the wiring 72 is arranged is indicated by a broken line. The wiring 72 is connected to a driving circuit of the solid-state imaging device by a wiring (contact) (not shown). In addition, a voltage can be applied to the electrode 71 through the wiring 72.
Furthermore, as shown in FIG. 20A, side surfaces of the connection portion 21 and the potential barrier portion 22 are surrounded by the electrode 71. The electrode 71 is formed from the surface of the semiconductor layer 17 to a depth greater than or equal to the connection portion 21, the potential barrier portion 22, and the connection surface. The electrode 71 is preferably formed to have a depth greater than that of the potential barrier portion 22.

  The electrode 71 and the wiring 72 are formed of a metal, a metal oxide, an organic conductive material, and a laminated film made of these materials. In particular, it is preferably made of a material having a light shielding property. The electrode 71 and the wiring 72 are preferably formed with a thickness that can sufficiently block incident light.

  As in the first embodiment, the first insulating layer 25 is a compound of silicon, germanium, gallium, and metal, and further contains at least one element of oxygen, nitrogen, and carbon. A single layer or a structure in which these films are laminated. In particular, it is preferable to use the above-described material having a negative fixed charge. Moreover, it is preferable that the thickness of the first insulating layer 25 be a thickness that allows accumulation of holes, which are majority carriers of the p-well 16 in contact, in a voltage region that does not impair the insulating properties.

In the element isolation part 70, the position where the voltage is applied from the electrode 71 can be controlled to an arbitrary position by changing the thickness of the first insulating layer 25 in the trench 54.
For example, the thickness of the first insulating layer 25 on the side surface of the trench 54 on the connection portion 21 side is made smaller than the thickness of the first insulating layer 25 on the bottom of the trench 54. In this case, the voltage is easily applied to the side surface of the element isolation unit 70. Further, the thickness of the first insulating layer 25 at the bottom of the trench 54 is made smaller than the thickness of the first insulating layer 25 on the side surface of the trench 54. In this case, the voltage is easily applied to the bottom of the element isolation unit 70.

  The configuration of the solid-state imaging device of the sixth embodiment described above is the same as that of the first embodiment, except that the element isolation unit 70 includes the electrode 71 and the wiring 72. For this reason, in the solid-state imaging device of the sixth embodiment, the same effect as that of the solid-state imaging device of the first embodiment can be obtained.

In general, the outermost surface of the semiconductor layer 17 has more bonding defects than the inside of the semiconductor layer 17, and a level that generates and recombines electron-hole pairs in the band gap in a short time. It is known that In the above-described configuration in which the connection portion 21 made of the n-type diffusion layer and the potential barrier portion 22 are adjacent to each other on the surface of the semiconductor layer 17 (the inner surface of the trench 54), and the electric field inside the depletion layer is generated, the connection portion 21 and the potential barrier portion 22. When there is a potential difference between them, the pixel characteristics due to the generation of dark current are affected.
On the other hand, in the above-described configuration, the element isolation unit 70 applies a negative bias to the electrode 71, so that a hole accumulation layer is formed at the interface between the surface of the semiconductor layer 17 (the inner surface of the trench 54) and the first insulating layer 25. Is formed. As a result, the depletion region that is a source of leakage current disappears, and no leakage current is generated.

  As described above, by applying a voltage having a reverse polarity to the electrode 71 and a well facing the electrode 71 via the first insulating layer 25, majority carriers in the well in contact therewith can be accumulated. For this reason, the electric charge injected into the connection part 21 effectively flows into the potential barrier part 22 which is a p-type semiconductor layer, and overflows into the charge storage part 23 located therebelow. Therefore, the transfer efficiency of signal charges from the photoelectric conversion film 32 can be improved. Furthermore, the generation of dark current at the interface can be suppressed.

  Further, in the configuration in which the electrode 71 is formed deeper than the contact surface between the connection portion 21 and the potential barrier portion 22, particularly deeper than the potential barrier portion 22, the potential barrier portion can be adjusted by adjusting the voltage applied to the electrode 71. The 22 barrier potential can be changed. For this reason, the overflow from the connection part 21 to the charge storage part 23 can be controlled by the electrode 71, and the transfer efficiency of the signal charge from the photoelectric conversion film 32 can be improved.

  In the above configuration, the wiring 72 is formed so as to cover the vertical transfer path 50, and the electrode 71 is formed so as to cover the side surfaces of the connection portion 21 and the potential barrier portion 22. For this reason, by forming the electrode 71 and the wiring 72 with a light-shielding material, it is possible to block light incident on the vertical transfer path 50, particularly oblique incident light. In this way, by causing the electrode 71 and the wiring 72 to function as a light shielding film, photoelectric conversion at the connection portion 21, the charge storage portion 23, and the potential barrier portion 22 of the vertical transfer path 50 can be suppressed, and the solid state Generation of false signals from the imaging apparatus can be suppressed.

[First Modification]
Next, a first modification of the above-described sixth embodiment will be described.
FIG. 21 shows a schematic configuration of a solid-state imaging device according to a first modification of the sixth embodiment. FIG. 21A is a cross-sectional configuration of the main part in the photoelectric conversion region of the solid-state imaging device. FIG. 21B is a plan configuration showing the configuration of the light receiving surface side of the semiconductor layer in the photoelectric conversion region of the solid-state imaging device.

  As shown in FIG. 21A, a wiring 73 connected to the electrode 71 is formed on the first insulating layer 25. 21B, the wiring 73 is formed so as to cover the entire formation region of the vertical transfer path 50 except for the periphery of the contact plug 29. The configuration other than the wiring 73 is the same as that in the sixth embodiment.

  The semiconductor layer 17 is formed with a region other than the first photodiode PD1 and the second photodiode PD2 such as the region where the first photodiode PD1 and the second photodiode PD2 are formed and the vertical transfer path 50. An area exists. It is preferable that the wiring 73 is formed at a position where light is shielded except for the region where the first photodiode PD1 and the second photodiode PD2 are formed.

  In the configuration of the solid-state imaging device of the first modified example, the light shielding region by the wiring 73 is widened, so that oblique incident light to the vertical transfer path 50 can be blocked as compared with the configuration of the sixth embodiment described above. Therefore, in addition to the same effects as those of the solid-state imaging device of the sixth embodiment described above, generation of false signals can be further suppressed.

[Second Modification]
Next, a second modification of the above-described sixth embodiment will be described.
FIG. 22 shows a schematic configuration of a solid-state imaging device according to a second modification of the sixth embodiment. FIG. 22A is a cross-sectional configuration of the main part in the photoelectric conversion region of the solid-state imaging device. FIG. 22B is a plan configuration showing the configuration of the light receiving surface side of the semiconductor layer in the photoelectric conversion region of the solid-state imaging device.

  As shown in FIG. 22A, a wiring 74 connected to the electrode 71 is formed on the first insulating layer 25. 22A and 22B, the wiring 73 is formed in a region that covers the entire semiconductor layer 17 except for the periphery of the contact plug 29 and the n-type semiconductor region 20 that constitutes the second photodiode PD2. ing. The configuration other than the wiring 73 is the same as that in the sixth embodiment.

In the configuration of the solid-state imaging device according to the second modified example, the wiring 74 forms a light shielding film that shields the vertical transfer path 50 and the extension portion 19a serving as a charge extraction portion from the first photodiode PD1. For this reason, light-shielding property improves rather than the above-mentioned 6th Embodiment and its 1st modification. Therefore, in addition to the same effects as the solid-state imaging device of the sixth embodiment described above, it is possible to further suppress false signals and the like. In addition, since the light shielding film that opens only the light receiving region is formed by the wiring 74, it is not necessary to configure a light shielding film other than the wiring 74.
In addition to the light shielding film of the wiring 74, a light shielding film including an opening corresponding to the opening of the wiring 74 on the second photodiode PD2 may be formed on the photoelectric conversion film 32.

<12. Sixth Embodiment (Method for Manufacturing Solid-State Imaging Device)>
Next, a method for manufacturing the solid-state imaging device according to the sixth embodiment will be described. 23 to 24 are manufacturing process diagrams of the solid-state imaging device according to the sixth embodiment. In particular, FIGS. 23 to 24 are diagrams illustrating manufacturing processes in a region where the photoelectric conversion unit is formed.

  First, as shown in FIG. 6D described above, a trench 54 for forming the element isolation portion 70 is formed using the same method as in the first embodiment described above. In this step, the trench 54 is formed to a position deeper than the connection surface between the connection portion 21 and the potential barrier portion 22. In addition, it is preferable to form the trench 54 to a position deeper than the potential barrier portion 22 so that the potential barrier can be controlled by the electrode 71 of the element isolation portion 70.

Next, as shown in FIG. 23A, the first insulating layer 25 is formed so as to cover the inner surface of the formed trench 54 and the surface of the semiconductor layer 17. The first insulating layer 25 is formed by using, for example, a chemical vapor deposition method, a sputtering method, an atomic layer deposition method, or the like, which is an insulating layer made of the material described in the first embodiment. The first insulating layer 25 is preferably formed using the above-described film having a negative fixed charge, a low dielectric constant material, or the like. Furthermore, an oxide film or the like formed by reaction and generation with the semiconductor layer 17 that hardly generates interface states may be formed between the semiconductor layer 17 and the first insulating layer 25.
Further, the first insulating layer 25 is formed with a thickness capable of accumulating holes, which are majority carriers of the p-well 16 in contact, in a voltage region that does not impair the insulating properties.

  Next, as shown in FIG. 23B, a conductor layer 75 is formed on the first insulating layer 25. The conductor layer 75 is formed from a conductive material, for example, a metal, a metal oxide, an organic conductive material, and a laminated film thereof. The first insulating layer 25 is formed by, for example, chemical vapor deposition, sputtering, atomic layer deposition, or the like.

The electrode 71 is preferably formed to a position deeper than the connection surface between the connection portion 21 and the potential barrier portion 22 so that pinning by the electrode 71 and control of the potential barrier can be performed.
In addition, in order to prevent photoelectric conversion in the region where the element isolation unit 70 is formed, that is, in the connection unit 21, the potential barrier unit 22, and the charge storage unit 23, the electrode 71 and the wiring 72 are connected to the incident light. And with a thickness sufficient to block light.

Next, as shown in FIG. 24C, the conductor layer 75 is etched to form the electrode 71 embedded in the trench 54 and the wiring 72 connected to the electrode 71. Moreover, the element isolation | separation part 70 is formed by this process.
The wiring 72 is formed at a position that satisfies the light shielding performance of incident light into the element isolation portion 70. For example, it is formed at a position covering the surface of the vertical transfer path 50 shown in FIG. 20B. In addition, as shown in FIG. 21B, all the regions other than the region where the first photodiode PD1 and the second photodiode PD2 are formed may be formed at a light shielding position. Furthermore, as shown in FIG. 22B, it may be formed in a region covering the entire semiconductor layer 17 except on the n-type semiconductor region 20 constituting the second photodiode PD2.
As described above, it is preferable that the wiring 72 is arranged so as not to block desired incident light incident on the first photodiode PD1 and the second photodiode PD2 and to shield other regions.
Further, the wiring 72 is arranged away from the contact plug 29 so that the voltage applied to the electrode 71 and the signal charge from the photoelectric conversion film 32 do not affect each other.

  Then, the contact plug 29, the lower electrode 31, the photoelectric conversion film 32, the upper electrode 33, the on-chip lens 35, and the like are formed by the same method as in the first embodiment, and the solid-state imaging device having the configuration shown in FIG. 24D. Can be manufactured.

As a method of forming the electrode 71 and the wiring 72, there is a method of forming the wiring 72 by planarizing the surface after embedding an electrode material in the trench 54 in which the first insulating layer 25 is formed. In this example, in order to reduce the number of steps, a method of simultaneously embedding the electrode 71 and forming the wiring 72 is shown.
The configurations of the first modification and the second modification can also be manufactured by the above-described manufacturing method by appropriately changing the pattern of the wiring 72 in the wiring 72 formation process.

  In the above-described sixth embodiment, the case where the configuration in which the electrode is disposed in the element separation unit is applied to the solid-state imaging device of the first embodiment is described. However, the configuration in which the electrode is arranged in the element isolation part is the second and third embodiments, and the fourth and fifth embodiments in which the signal charge extraction part is formed in the main surface direction of the semiconductor layer. The present invention can also be applied to the element isolation portion of the embodiment. Also in this case, similarly to the above description, it can be configured by embedding an insulating layer and a conductor layer in a trench constituting the element isolation portion. In the fifth embodiment, an insulating layer may be formed on the surface of the cavity, and a conductive layer may be embedded in the cavity in the insulating layer to form a continuous electrode from the trench to the cavity.

  In the solid-state imaging devices according to the above-described embodiments and modifications, the second conductivity type (for example, p-type) semiconductor region formed on the second conductivity type (for example, n-type) semiconductor substrate has the second conductivity type. An FD region and PD regions of the second conductivity type and the first conductivity type are formed. However, in the present technology, the n-type and p-type conductivity types may be reversed. In the case of this configuration, instead of a configuration in which electrons are used as signal charges, a configuration is used in which holes are used as signal charges. Further, a film having a polarity opposite to that of the semiconductor layer in the region where the photoelectric conversion portion is formed is used instead of the film having a negative fixed charge.

<13. Seventh Embodiment (Electronic Device)>
Next, an embodiment of an electronic device including the above-described solid-state imaging device will be described.
The above-described solid-state imaging device can be applied to electronic devices such as a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or another device having an imaging function. FIG. 25 illustrates a schematic configuration when the solid-state imaging device is applied to a camera capable of capturing a still image or a moving image as an example of an electronic device.

  The camera 80 in this example includes a solid-state imaging device 81, an optical system 82 that guides incident light to a light receiving sensor unit of the solid-state imaging device 81, a shutter device 83 provided between the solid-state imaging device 81 and the optical system 82, a solid state And a drive circuit 84 that drives the imaging device 81. Furthermore, the camera 80 includes a signal processing circuit 85 that processes the output signal of the solid-state imaging device 81.

  The solid-state imaging device 81 can be applied to the solid-state imaging device shown in the above-described embodiments and modifications. The optical system (optical lens) 82 forms image light (incident light) from the subject on an imaging surface (not shown) of the solid-state imaging device 81. Thereby, signal charges are accumulated in the solid-state imaging device 81 for a certain period. The optical system 82 may be composed of an optical lens group including a plurality of optical lenses. The shutter device 83 controls the light irradiation period and the light shielding period of the incident light to the solid-state imaging device 81.

  The drive circuit 84 supplies drive signals to the solid-state imaging device 81 and the shutter device 83. The drive circuit 84 controls the signal output operation to the signal processing circuit 85 of the solid-state imaging device 81 and the shutter operation of the shutter device 83 by the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state imaging device 81 to the signal processing circuit 85 is performed by a drive signal (timing signal) supplied from the drive circuit 84.

  The signal processing circuit 85 performs various signal processes on the signal transferred from the solid-state imaging device 81. The signal (video signal) that has been subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or is output to a monitor (not shown).

  According to the electronic device such as the camera 80 described above, since the signal charge transfer efficiency from the photoelectric conversion film is excellent in the solid-state imaging device 81, an electronic device with improved image quality characteristics can be provided.

In addition, this indication can also take the following structures.
(1) A semiconductor layer, a photoelectric conversion unit or a charge holding unit arranged on the light receiving surface side of the semiconductor layer, and a signal generated in the photoelectric conversion unit or the charge holding unit formed in the semiconductor layer A connection section from which charges are read, a charge storage section in which signal charges read out to the connection section are stored, a potential barrier section provided between the connection section and the charge storage section, and the connection section A solid-state imaging device comprising: a trench that surrounds a side surface of the semiconductor device; and an element isolation portion made of an insulating layer formed in the trench.
(2) A semiconductor layer, a photoelectric conversion unit or charge holding unit disposed on the light receiving surface side of the semiconductor layer, and a signal generated in the photoelectric conversion unit or charge holding unit formed in the semiconductor layer A connection section from which charges are read, a charge storage section in which signal charges read out to the connection section are stored, a potential barrier section provided between the connection section and the charge storage section, and the connection section A solid-state imaging device comprising: a trench formed on a side surface of the semiconductor device and contacting with at least a part of the connection portion; and an element isolation portion including an insulating layer formed in the trench.
(3) The solid-state imaging device according to (1) or (2), wherein the connection portion and the potential barrier portion are stacked in a thickness direction of the semiconductor layer.
(4) The solid-state imaging device according to any one of (1) to (3), wherein the insulating layer is formed of a film having a fixed charge opposite in polarity to the polarity of the semiconductor layer on the side surface of the trench.
(5) The solid-state imaging device according to any one of (1) to (4), wherein an oxide film is provided on the connection portion between the semiconductor layer and the insulating layer.
(6) The solid-state imaging device according to any one of (1) to (5), wherein the element isolation portion includes an electrode formed on the insulating layer in the trench.
(7) The solid-state imaging device according to (6), including a wiring connected to the electrode at a position covering at least a part of the connection portion.
(8) The solid-state imaging device according to (6) or (7), wherein the electrode and the wiring are made of a light-shielding material.
(9) The solid-state imaging device according to any one of (1) to (8), wherein the element isolation part is formed to a position deeper than a connection part between the connection part and the potential barrier part.
(10) A method of manufacturing a solid-state imaging device in which a photoelectric conversion unit or a charge holding unit is disposed on a light receiving surface side of a semiconductor layer, and a signal generated in the semiconductor layer by the photoelectric conversion unit or the charge holding unit Forming a connection part for reading out charge, a charge storage part for storing the signal charge read out in the connection part, and a potential barrier part provided between the connection part and the charge storage part; A step of forming a trench in a position surrounding a side surface of the connection portion of the semiconductor layer, a step of forming an insulating layer in the trench, and the photoelectric conversion portion or the charge holding portion as a light receiving surface of the semiconductor layer A method of manufacturing the solid-state imaging device.
(11) A method of manufacturing a solid-state imaging device in which a photoelectric conversion unit or a charge holding unit is disposed on a light receiving surface side of a semiconductor layer, and a signal generated by the photoelectric conversion unit or the charge holding unit on the semiconductor layer Forming a connection part for reading out charge, a charge storage part for storing the signal charge read out in the connection part, and a potential barrier part provided between the connection part and the charge storage part; , A step of forming a trench at a position where at least a part of the side surface of the connection portion of the semiconductor layer is in contact, a step of forming an insulating layer in the trench, and the photoelectric conversion unit or the charge holding unit as the semiconductor And a step of arranging the layer on the light receiving surface side of the layer.
(12) The method for manufacturing a solid-state imaging device according to (10) or (11), further comprising: forming an electrode on the insulating layer in the trench after forming the insulating layer on the inner surface of the trench.
(13) An electronic apparatus comprising: the solid-state imaging device according to any one of (1) to (9); and a signal processing circuit that processes an output signal of the solid-state imaging device.

  1,81 Solid-state imaging device, 2 pixels, 3 pixel region, 4 vertical drive circuit, 5 column signal processing circuit, 6 horizontal drive circuit, 7 output circuit, 8 control circuit, 9 vertical signal line, 10 horizontal signal line, 11, 51 substrate, 12, 21, 61 connection part, 15 photoelectric conversion region, 16 p-well, 17 semiconductor layer, 19 n-type semiconductor region, 19a extension, 20 n-type semiconductor region, 22, 56, 62, 23, 63 Potential barrier portion, 24, 72, 73, 74 wiring, 25 first insulating layer, 26 second insulating layer, 27, 64, 66, 70 element isolation portion, 28, 59 insulating layer, 29 contact plug, 31 lower electrode, 32 Photoelectric conversion film, 33 Upper electrode, 34 Flattening film, 35 On-chip lens, 37, 38, 39 Transfer gate electrode, 40, 41, 42 Gate electrode, 43, 44, 45 , 46 Source / drain region, 50 vertical transfer path, 52 BOX layer, 53 support substrate, 54, 65, 68 trench, 55 overflow path, 57 third insulating layer, 58 photoresist, 67 buried oxide film, 69 cavity , 71 electrode, 75 conductor layer, 80 camera, 82 optical system, 83 shutter device, 84 drive circuit, 85 signal processing circuit, FD1, FD2, FD3 floating diffusion part, PD1 first photodiode, PD2 second photodiode, Tr1 First transfer transistor, Tr2 Second transfer transistor, Tr3 Third transfer transistor, Tr4, Tr7, Tr10 Reset transistor, Tr5, Tr8, Tr11 Amplifying transistor, Tr6, Tr9, Tr12 Select transistor

Claims (14)

A semiconductor layer;
A photoelectric conversion unit or a charge holding unit disposed on the light receiving surface side of the semiconductor layer;
A connection part that is formed in the semiconductor layer and from which the signal charge generated by the photoelectric conversion part or the charge holding part is read; and
A charge storage unit for storing the signal charges read out in the connection unit;
A potential barrier portion provided between the connection portion and the charge storage portion;
A solid-state imaging device comprising: a trench surrounding a side surface of the connection portion; and an element isolation portion made of an insulating layer formed in the trench. A semiconductor layer;
A photoelectric conversion unit or a charge holding unit disposed on the light receiving surface side of the semiconductor layer;
A connection part that is formed in the semiconductor layer and from which the signal charge generated by the photoelectric conversion part or the charge holding part is read; and
A charge storage unit for storing the signal charges read out in the connection unit;
A potential barrier portion provided between the connection portion and the charge storage portion;
A solid-state imaging device comprising: a trench formed on a side surface of the connection portion and in contact with at least a part of the connection portion; and an element isolation portion including an insulating layer formed in the trench.   The solid-state imaging device according to claim 1, wherein the connection portion and the potential barrier portion are stacked in a thickness direction of the semiconductor layer.   3. The solid-state imaging device according to claim 1, wherein the insulating layer is formed of a film having a fixed charge having a polarity opposite to that of the semiconductor layer on the side surface of the trench.   The solid-state imaging device according to claim 4, wherein an oxide film is provided between the semiconductor layer and the insulating layer on the connection portion.   The solid-state imaging device according to claim 1, wherein the element isolation portion includes an electrode formed on the insulating layer in the trench.   The solid-state imaging device according to claim 6, further comprising a wiring connected to the electrode at a position covering at least a part of the connection portion.   The solid-state imaging device according to claim 6, wherein the electrode and the wiring are made of a light-shielding material.   The solid-state imaging device according to claim 1, wherein the element isolation part is formed to a position deeper than a connection part between the connection part and the potential barrier part. A method of manufacturing a solid-state imaging device in which a photoelectric conversion unit or a charge holding unit is disposed on a light receiving surface side of a semiconductor layer,
A connection unit that reads out signal charges generated by the photoelectric conversion unit or the charge holding unit, a charge storage unit that stores signal charges read out by the connection unit, a connection unit, and the semiconductor layer. Forming a potential barrier portion provided between the charge storage portion and
Forming a trench at a position surrounding a side surface of the connection portion of the semiconductor layer;
Forming an insulating layer in the trench;
Disposing the photoelectric conversion unit or the charge holding unit on a light receiving surface side of the semiconductor layer. A method for manufacturing a solid-state imaging device. A method of manufacturing a solid-state imaging device in which a photoelectric conversion unit or a charge holding unit is disposed on a light receiving surface side of a semiconductor layer,
A connection unit that reads out signal charges generated by the photoelectric conversion unit or the charge holding unit, a charge storage unit that stores signal charges read out by the connection unit, a connection unit, and the semiconductor layer. Forming a potential barrier portion provided between the charge storage portion and
Forming a trench at a position where at least a part of the side surface of the connection portion of the semiconductor layer is in contact;
Forming an insulating layer in the trench;
Disposing the photoelectric conversion unit or the charge holding unit on a light receiving surface side of the semiconductor layer. A method for manufacturing a solid-state imaging device.   The method for manufacturing a solid-state imaging device according to claim 10, further comprising: forming an electrode on the insulating layer in the trench after forming the insulating layer on the inner surface of the trench. A semiconductor layer, a photoelectric conversion unit or a charge holding unit arranged on the light receiving surface side of the semiconductor layer, and a signal charge generated in the photoelectric conversion unit or the charge holding unit formed in the semiconductor layer are read out. A connecting portion, a charge accumulating portion in which the signal charge read out to the connecting portion is accumulated, a potential barrier portion provided between the connecting portion and the charge accumulating portion, and a side surface of the connecting portion. A solid-state imaging device having an enclosing trench and an element isolation portion made of an insulating layer formed in the trench;
An electronic device comprising: a signal processing circuit that processes an output signal of the solid-state imaging device. A semiconductor layer, a photoelectric conversion unit or a charge holding unit arranged on the light receiving surface side of the semiconductor layer, and a signal charge generated in the photoelectric conversion unit or the charge holding unit formed in the semiconductor layer are read out. Connected to the connecting portion, a charge accumulating portion in which the signal charge read out to the connecting portion is accumulated, a potential barrier portion provided between the connecting portion and the charge accumulating portion, and a side surface of the connecting portion A solid-state imaging device having a trench formed and in contact with at least a part of the connection portion and an element isolation portion made of an insulating layer formed in the trench;
An electronic device comprising: a signal processing circuit that processes an output signal of the solid-state imaging device.

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