201143071 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種固體攝像裝置（SOLID STATE IMAGING DEVICE)，尤有關於一種可達成低混色、高靈敏 度、低殘影、低暗電流、低雜訊（noise)、高像素密度化之 固體攝像裝置。 【先前技術】 目前 ’ CCD(Charge-Coupled Device，電荷耦合元件） 及 CMOS(Complementary Metal Oxide Semiconductor ，互 補式金屬氧化物半導體）固體攝像裝置已廣泛應用於攝錄 影機（video camera)、靜物攝影機（still camera)等。再 者’亦經常要求提升固體攝像裝置之高解析度（resolution) 及高靈敏度化等之性能。針對此點，為了實現固體攝像裝 置之高解析度化，已進行運用像素高密度化之技術革新。 此外，為了實現固體攝像裝置之高靈敏度化，則已進行提 南聚光效率、低雜訊化、低暗電流（dark current)、再加 上降低殘影所進行之技術革新。 以下說明習知之固體攝像裝置之動作（參照例如 Sunetra K. Mendis, Sabrina E. Kemeny and Eric R. Fossum : “A 128x128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems” ， IEDM93， Digest Papers, 22.6. l.pp· 583-586(1993))。第 18A 圖係顯示該 CMOS固體攝像裝置之1像素構成圖，第18B圖係顯示沿著 第18A圖中之A-A’線之信號電荷50蓄積時之電位分布。 4 322818 201143071 另外，在第18B中’為了區別，係以陰影顯示已蓄積之電 荷。此i 4象素係由下述構件所構成：信號 部 用以蓄積藉由照射光52所產生之信號電荷5〇之P型半導 體基板53、氧化石夕膜⑽2膜如、及光閑極（ph〇t〇gate) PG導體層所構成；與該信號電荷蓄積部相連之傳送問極 TG ;與傳送閑極TG電極下通道55相連之浮動二極體 (Floating Diode)FD;具有與浮動二極體FD連接之閘極 AG 的放大 MOSOnetal oxide semiconduct〇r，金屬氧化物 半導體）電晶體56 ;與放大M0S電晶體56相連之選擇閘極 (SG)MOS電晶體57 ;設於連接於浮動二極體FD之以〇2膜 54b上的重设（reset)閘極RG ;及具有重設沒極二極體仙 之重設M0S電晶體58。重設M0S電晶體58之重設汲極二 極體RD與放大M0S電晶體56之汲極係連接於電壓vdd之電 源線《再者’選擇閘極（SG)MOS電晶體57之源極係連接於 信號線59。201143071 VI. Description of the Invention: [Technical Field] The present invention relates to a solid-state imaging device (SOLID STATE IMAGING DEVICE), and particularly relates to a low color mixing, high sensitivity, low afterimage, low dark current, low impurity A solid-state imaging device with noise and high pixel density. [Prior Art] Currently, CCD (Charge-Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging devices have been widely used in video cameras and still cameras. (still camera) and so on. Furthermore, it is often required to improve the performance of high resolution and high sensitivity of solid-state imaging devices. In response to this, in order to achieve high resolution of the solid-state imaging device, technological innovations have been made to increase the density of pixels. Further, in order to achieve high sensitivity of the solid-state imaging device, technological innovations such as concentrating efficiency, low noise, low dark current, and reduction of image sticking have been carried out. The operation of the conventional solid-state imaging device will be described below (see, for example, Sunetra K. Mendis, Sabrina E. Kemeny and Eric R. Fossum: "A 128x128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems", IEDM93, Digest Papers, 22.6. .pp. 583-586 (1993)). Fig. 18A is a view showing a configuration of a pixel of the CMOS solid-state imaging device, and Fig. 18B is a view showing a potential distribution when signal charges 50 are accumulated along the A-A' line in Fig. 18A. 4 322818 201143071 In addition, in section 18B, the accumulated charge is shown in shades for the sake of distinction. The i 4 pixel is composed of a member for accumulating a P-type semiconductor substrate 53 of a signal charge generated by the irradiation light 52, a film of the oxidized stone film (10) 2, and an optical idler ( 〇 〇 〇 ) ) PG PG ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG PG Amplified MOS-connected gate AG of the polar body FD is connected to a selected gate (SG) MOS transistor 57 connected to the amplified MOS transistor 56; The pole FD is reset gate RG on the 〇2 film 54b; and the reset MOS transistor 58 is provided with a reset poleless diode. Reset the reset gate of the MOS transistor 58 and the drain of the MOS transistor 56 to the power supply line of the voltage vdd. The source of the gate SG transistor 57 is further selected. Connected to signal line 59.
所照射之光（照射光）52係通過光閘極PG而射入於p 变半導體基板53。藉此所產生之信號電荷50(此時係為電 子），係藉由施加預定電壓於光閘極PG而蓄積在形成於p 犁半導體基板53表面之電位阱51。所蓄積之信號電荷5〇 係藉由施加導通（on)電壓於傳送閘極TG電極而傳送於浮 動二極體FD。藉此，浮游二極體FD之電位即依據信號電 荷50之量而變化。同時與浮游二極體FD相連之放大M0S 電晶體56之閘極電壓亦依信號電何50之量而變化。當施 加導通電壓於選擇閘極（SG)MOS電晶體57之選擇閘極SG 5 322818 201143071 時，與放大M0S電晶體56之閘極ag電壓對應之信號電流 則流通於信號線59 ’且被讀取作為輸出。 以其他固體攝像裝置而言，係與前述第18A圖及第18B 圖所示使用光閘極PG之信號電荷蓄積構造不同，具有藉由 .光二極體（Photo Diode)PD來進行信號電荷蓄積之光二極 體構造（參照例如日本專利申請公開第2000-244818號說 明書、及 R. M. Guidash，T. H. Lee，Ρ· P. K. Lee, D. H. Sackett， C. I.Drowley, M. S. Swenson, L. Arbaugh, R. Hollstein, F. Shapiro, and S. Domer ： “ A 0_ 6um CMOS PinnedThe irradiated light (irradiation light) 52 is incident on the p-variable semiconductor substrate 53 through the optical gate PG. The signal charge 50 (which is an electron in this case) generated thereby is accumulated in the potential well 51 formed on the surface of the p-plow semiconductor substrate 53 by applying a predetermined voltage to the gate PG. The accumulated signal charge 5 传送 is transmitted to the floating diode FD by applying an on voltage to the transfer gate TG electrode. Thereby, the potential of the floating diode FD changes depending on the amount of the signal charge 50. At the same time, the gate voltage of the amplified MOS transistor 56 connected to the floating diode FD also varies depending on the amount of signal power 50. When a turn-on voltage is applied to the select gate SG 5 322818 201143071 of the select gate (SG) MOS transistor 57, the signal current corresponding to the gate ag voltage of the amplified MOS transistor 56 flows through the signal line 59' and is read. Take as output. The other solid-state imaging device differs from the signal charge accumulation structure using the photo-gate PG as shown in FIGS. 18A and 18B, and has a signal charge accumulation by a photodiode PD. Light diode structure (refer to, for example, Japanese Patent Application Laid-Open No. 2000-244818, and RM Guidash, TH Lee, Ρ PK Lee, DH Sackett, CIDrowley, MS Swenson, L. Arbaugh, R. Hollstein, F. Shapiro , and S. Domer : " A 0_ 6um CMOS Pinned
Photodiode Color Imager Technology” ， IEDM Digest Papers，pp. 927-929(1997))。以此種光二極體構造而言， 例如有具備設於光二極體PD表面之P+層、及與P+層連接 而且為了使像素間電性分離而固定（pinning)於接地 (ground)電位之通道擔止層（stopper)P+層之構造（pinned photodiode) ° 在第18A圖所示之習知之CM〇S固體攝像裝ϊ中’光 52係從光閘極PG導體層上入射。在光閘極PG導體層中’ 係使用例如摻雜有雜質之薄詹膜厚之多晶矽（以下也稱為 多晶Si)。然而，在此種構造中’無法避免入射光52中之 藍色波長光之一部分會在多晶Si層被吸收。再加上’由於 光閘極PG係覆蓋P型半導體基板53表面之信號電荷蓄積 部之上而形成，因此無法將信號電荷蓄積部之電位直接傳 送至放大M0S電晶體56之閘極AG。因此，乃設ϊ傳送閘 極TG電極與浮游二極體FD，將蓄積於信號蓄積部之電位 6 322818 201143071 牌51之信號電荷5〇，一旦轉移至浮游二極體FD，再將此 浮游二極體FD之電位供予放大M0S電晶體56之閘極AG。 因此’在像素區域中需有傳送閘極TG電極與浮游二極體 FD。此種區域之附加’即成為損害習知之CMOS固體攝像裝 置之像素南松度化的原因。 此外’例如在日本專利申請公開第2〇〇〇_244818號說 月曰中所。己載之具有釘札光電二極體（panned ph〇t〇di〇de) 構造之固體攝像裝置中，並無前述光閘極pG構造之藍色波 長光靈敏度降低的問題。此外，藉由將光二極體pD之表面 固疋於接地電位’可防止因為將信號電荷傳送於浮游二極 體FD時之彳5號電荷不完全傳送所產生之殘影，及所謂的 WC雜訊的雜訊產生。再者，在光二極體pD表面之p+層係 蓄積有電洞（hole)，而此電洞係與從Si〇2_Si界面位準被 熱性激勵之電子再度結合，而防止電子混入於信號電荷 50。藉此，即可降低暗電流。然而，與前述之光閘極％構 造相同，由於蓄積信號電荷之光二極體pD之表面為由p+ 層所覆蓋，因此無法將蓄積有信號電荷之光二極體電位， 直接傳送至放大用M0S電晶體之閘極。因此，與使用光閘 極PG之仏號電荷蓄積構造相同，需有傳送閘極％電極與 浮游二極體FD區域，而成為阻礙CM〇s固體攝像裝置之像 素高密度化之原因。 此外，以往在CMOS固體攝像裝置中，解析度降低及彩 色攝像之混色亦成為問題。 【發明内容】 322818 7 201143071 [發明所欲解決之課題] 本發明係有鑑於上述問題而研創者，其目的在實現一 種低混色、高靈敏度、低殘影、低暗電流、低雜訊、及高 像素密度之固體攝像裝置。 [解決課題之手段] 本發明之固體攝像裝置係具有〗個或複數個像素者， 其特徵為：前述像素各個係具有：第1半導體層，形成於 基板上，第2半導體層，形成於前述第1半導體層上；第 ^半導體層，從前述第2半導體層之上表面離^形成於 則述第2半導體層之上部側面區域；第3半導體層，從前 述第2半導體層之上表面離開而形成於前述第4半導體層 之内侧面與前述第2半導體層之間；第1絕緣膜’至少开; 成於前述第2半導體層之側面與前述第4半導體層之外侧 面’閘極導體層，間隔前述第丨絕緣膜而形成於前述第2 =導=:側面中未形成有前述第3半導體層之下面侧 體電極，間隔前述第i絕緣膜而形成於前述第4半 η卜r;及第5半導體層’以不與前述第3半導 =2=4層相接U式形成於前述第2半導 =之上表面’至少前述第3半導體層、前述第2半導體 半導體層之上部區域、前述第4半 層係形成二極體;形成以前述第）半= 2半導體層及前述第$半導體層之任-者為=== 322818 8 201143071 為源極、前述二極體為閘極之接合電晶體；形成以前述第 1半導體層為汲極、前述第3半導體層為源極、前述閘極 導體層為閘極之場效電晶體；且具備：蓄積手段，將因為 電磁能量波之照射而在前述像素内產生之信號電荷蓄積於 前述二極體；信號讀取手段，藉由測量依據流通於前述接 合電晶體並且蓄積於前述二極體之信號電荷之量而變化之 電流來測量前述信號電荷之量；及重設手段，將導通電壓 施加於前述場效電晶體之前述閘極導體層，且在包含前述 第1半導體層與前述第3半導體層之間之前述第2半導體 層的區域形成通道’藉此將蓄積於前述二極體之信號電荷 予以去除至前述第1半導體層；將電壓施加於前述導體電 極’以使與蓄積於前述二極體之信號電荷相反極性之電荷 蓄積於前述第4半導體層。 前述第2半導體層較佳為與前述第1半導體層相反導 電型或實質上為本質型；前述第3半導體層係為與前述第 1半導體層相同導電型；前述第4半導體層係為與前述第1 半導體層相反導電型；前述第5半導體層係為與前述第1 半導體層相反導電型。 較佳為復具備配線導體層，用以將相鄰接之前述像素 之前述導體電極彼此在前述閘極導體層附近連接，而且由 遮光性導電性材料所構成。 則述配線導體層較佳為連接前述複數個像素之所有前 述導體電極彼此。 較佳為復具備覆蓋前述閘極導體層所形成之第2絕緣 322818 9 201143071 2絕緣膜而形成為至少與 膜；前述導體電極係間隔前述第 前述閘極導體層之一部分重疊。 人導體層，其係埋人於相鄰接之前述 ❹if導體電_、相鄰接之前述像素之前述問極導 間'或相鄰接之前述像素之前述導體電極間及前述相 妾像素之則述閘極導體層間，而且由遮光性導雷姓 料所構成。 平电丨王何 、較佳為前述第3半導體層與前述第4半導體層與前述 導體電極在從前述第5半導體層朝向前述第丨半導體層之 方向，係形成為前述第3半導體層之上端與前述第4半導 體層之上端與前述導體電極之上端之位置大致一致，或 者，前述第3半導體層與前述第4半導體層與前述導體電 極在從前述第5半導體層朝向前述第丨半導體層之方向， 係形成為前述第3半導體層之上端較前述導體電極之上端 更遠離前述第5半導體層，而前述第4半導體層之上端則 位於刖述第3半導體層之上端與前述導體電極之上端之 間。 刖述重設手段較佳為將電壓施加於前述導體電極，且 以前述第5半導體層之電位、信號電荷未蓄積於前述二極 體時之前述第3半導體層内之最深的電位、將導通電壓施 加於前述場效電晶體之前述閘極導體層時之前述第2半導 體層之通道電位、前述第1半導體層之電位之順序變深之 方式設定電位關係。 前述信號讀取手段較佳為將電壓施加於前述導體電 322818 10 201143071 極’以使前述二極體之空乏層在錢電荷未蓄積於前述二 極體時佔有前述第2半導體層之前述整體上部區域。 [發明之功效] 依據本發明’可提供—種低混色、高靈敏度、低殘影、 低暗電流、低雜訊、及高像素密度之固體攝像裝置。 【實施方式】 以下參照第1A圖至第17C圖說明本發明之實施形態。 (本發明之第1實施形態） 第1A圖及第1B圖係顯示本發明第丨實施形態之固體 攝像裝置100之像素H)之構造。另外，本實施形態之固體 攝像裝置100之像f 10之基本構造，係與記載於國際公開 第2009-034623號之固體攝像裝置之像素構造相同，該國 際公開第2009-034623號所記载之所有内容均被參照引用 於本說明書中。 ' 在第1A圖，於各像素10中係在基板上形成有第工半 導體層N+層1 ’該第1半導體層i係與朝第J掃描方 向延伸之配線XL連接。在第1半導體層n+層【上，係形 成有與第1半導體層N+層1相反導電型之第2半導體層p 層2。在第2半導體層P層2之上部側面區域，係以包圍 第2半導體層P層2之方式形成有與第丨半導體層n+層上 相同導電型之第3半導體層N層5a、5b。另外，第3半"導 體層N層5a、5b係設成為不與第2半導體層p層2之上表 面相接。第3半導體層N層5a、5b、與第3半導體層N層 5a、5b附近之第2半導體層P層2之區域係構成光二極： 322818 11 201143071 、X光及電子束等電磁 112,該光二極體112係蓄積因為光 能量波之照射所產生之信號電荷。 再者，在光二極體112之表面，係以包圍光二極體112 之外周部之方式形成有與第丨半導體層丨相反導電型 之第4半導體層广層6a、6b。另外，第4半導體層？+層 6a、6b亦設成為不與第2半導體層μ 2之上表面相接: 以蓋住第2半導體層ρ層2之侧面與第4半導體層ρ+ 層6a、6b之外側面之方式形成有絕緣膜⑽2膜）如、曰北。 間隔著此絕緣膜3a、3b，於第4半導體層P+層6a、6b之 侧面形成有導體電極7a、7b。 在第2半導體層ρ層2之下部側面，係間隔著絕緣膜 3a、3b而形成有閘極導體層4a、4b。另外，閘極導體層 4a、4b係由金屬膜或具有充分厚度之高濃度雜質多晶^ 等遮光性材料而形成。絕緣膜3a、3b與閘極導體層4a、 4b係構成將第2半導體層ρ層2之下部區域設為通道 (channel)之重設M0S電晶體111。 在第2半導體層P層2之上表面，形成有與第2半導 體層P層2相同導電型之第5半導體層p+層8。另外，第 5半導體層P+層8係與第3半導體層N層5a、5b及第4半 導體層P+層6a、6b隔開而設。此外，第5半導體層p+層 8係連接於朝與第1掃描方向正交之方向延伸之配線yl。 形成有以第1半導體層N+層1附近之第2半導體層ρ 層2與第5半導體層P+層8作為汲極與源極、光二極體il2 作為閘極之放大用接合電晶體。再者，形成有光二極體1 322818 12 201143071 之第2半導體層p層2之上部區域、第3半導體層n層5a、 5b、第4半導體層p+層6a、6b、及第5半導體層P+層8 係形成於島狀形狀内。另外，在本實施形態中，配線XL雖 係為信號線，且配線YL係為像素選擇線，惟配線XL亦可 為像素選擇線，而配線YL則為信號線。 在此種像素10之構造中，由於光二極體112上之導體 電極7a、7b係形成於島狀半導體之侧面，因此入射光12a 會從第5半導體層P+層8直接照射至光二極體區域。藉此， 在本實施形態之固體攝像裝置100中，就不會產生如第 圖所示在習知之固體攝像裝置中所產生之藍色波長光靈敏 度的降低。再者，導體電極73、几係藉由金屬膜或具有充 分厚度之高濃度雜質多晶Si等遮光性材料所形成。藉此， 從第5半導體層p +層8射入於光二極體區域之入射光 12a ’即在導體電極7a、7b中被吸收或反射。此外，由於 導體電極7a、7b係包圍光二極體112之外周部而形成，因 此防止入射光12a與在導體電極7a、7b所反射之反射光 12c洩漏至與該像素相鄰接之像素，而此入射光12a及反 射光12c均可有效地有助於作為信號電荷。藉此，在本固 體攝像裝置100中，係可抑制混色及解析度降低。 在第1A圖所示之固體攝像裝置中，第2半導體層係為 由P型導電型半導體層所構成之p層2。如第丨8圖所示， 第2半導體層亦可為由實質為本質型半導體所構成之i層 2ι，以取代由該P型導電型半導體所構成之p層2。本質 型半導體雖係製造成不混入雜質，惟實際上仍不可避免地 322818 13 201143071 會含有極微量的雜質。構成此第2半導體丨層2丨之實質上 本質型半導制，只要是不會阻礙發揮作為固體攝像裝置 loo力月b之程度，則含有微量的受體（acc印或施k (donor)雜質亦無妨。依據此種構成，第3半導體層N層 5a、5b與第2半導體i層2i係可形成二極體。此外，當 施加充分的電壓於第5半導體層p+層8與屬於信號線之第 1半導體層N+層1之間時，第5半導體層p+層8之電洞 (hole)，即因為在第2半導體丨層2i内部所產生之電位梯 度而朝向第1半導體層N+層1流通。如此，第2半導體i 層2i亦可發揮作為放大用接合電晶體之通道功能。 第2圖係顯示本實施形態之固體攝像裝置1〇〇之電路 構成例。固體攝像裝置100主要具備：排列成2維矩陣 (matrix)狀之複數個像素1〇a至i〇d ;垂直掃描電路201 ; 水平掃描電路202 ;重設電路203 ;像素選擇線yli、YL2 ; 信號線XL1、XL2、重設線（reset Hne)RsL ;信號線M0S 電晶體Trl、Tr2，及相關雙重取樣（c〇rreiated double Sampling ’ CDS)輸出電路204。在本實施形態中，雖就像 素10a至10d排列成2列（row)2行（column)之情形進行說 明’惟本發明之固體攝像裝置並不限定於此。 如第2圖所示’輸入像素選擇信號於各像素1〇a至i〇d 之垂直掃描電路201，係透過像素選擇線YLI、YL2而依每 列（row)連接於各像素i〇a至i〇d。此外，各像素i〇a至i〇d 又依每行（column)透過信號線XL卜XL2而連接於CDS輸出 電路204。配置於各信號線xli、XL2之信號線M0S電晶體 14 322818 201143071Photodiode Color Imager Technology", IEDM Digest Papers, pp. 927-929 (1997). In terms of such a photodiode structure, for example, there is a P+ layer provided on the surface of the photodiode PD, and connected to the P+ layer. The structure of the channel P+ layer pinned to the ground potential in order to electrically separate the pixels (pinned photodiode). The conventional CM〇S solid-state imaging device shown in Fig. 18A In the middle of the ray, the light 52 is incident on the optical gate PG conductor layer. In the optical gate PG conductor layer, for example, a polycrystalline germanium film (hereinafter also referred to as polycrystalline Si) doped with impurities is used. In such a configuration, it is inevitable that a part of the blue wavelength light in the incident light 52 is absorbed in the polycrystalline Si layer. Further, 'the signal charge accumulation on the surface of the P-type semiconductor substrate 53 is covered by the optical gate PG system. The portion is formed above the portion, so that the potential of the signal charge storage portion cannot be directly transmitted to the gate AG of the amplified MOS transistor 56. Therefore, the transfer gate TG electrode and the floating diode FD are accumulated, and the signal is accumulated in the signal accumulation. Ministry potential 6 322818 201143071 The signal charge of 51 is 5 〇, and once transferred to the floating diode FD, the potential of the floating diode FD is supplied to the gate AG of the amplified MOS transistor 56. Therefore, a transfer gate TG is required in the pixel region. The electrode and the floating diode FD. The addition of such a region is a cause of damaging the pixel south of the conventional CMOS solid-state imaging device. Further, for example, Japanese Patent Application Laid-Open No. 2-244818 In the solid-state imaging device having the structure of a pinned phonon diode, there is no problem that the blue wavelength light sensitivity of the above-described optical gate pG structure is lowered. By fixing the surface of the photodiode pD to the ground potential ', it is possible to prevent the afterimage caused by the incomplete transfer of the No. 5 charge when the signal charge is transferred to the floating diode FD, and the so-called WC noise. The noise is generated. Furthermore, a hole is accumulated in the p+ layer of the surface of the photodiode pD, and the hole is recombined with the electrons thermally excited from the Si〇2_Si interface level to prevent electrons from entering. At a signal charge of 50. The dark current is reduced. However, since the surface of the photodiode pD that accumulates signal charges is covered by the p+ layer, the potential of the photodiode that accumulates signal charges cannot be directly transmitted to the same. The gate of the MOS transistor is amplifying. Therefore, similar to the nickname charge accumulation structure using the optical gate PG, it is necessary to have a transfer gate % electrode and a floating diode FD region, which is a hindrance to the CM 〇 solid-state imaging device. The reason for the high density of pixels. Further, in the conventional CMOS solid-state imaging device, the resolution is lowered and the color mixture of color imaging is also a problem. SUMMARY OF THE INVENTION 322818 7 201143071 [Problems to be Solved by the Invention] The present invention has been made in view of the above problems, and aims to achieve a low color mixing, high sensitivity, low afterimage, low dark current, low noise, and High pixel density solid-state imaging device. [Means for Solving the Problem] The solid-state imaging device according to the present invention includes one or a plurality of pixels, and each of the pixels includes a first semiconductor layer formed on a substrate, and a second semiconductor layer formed on the substrate. The first semiconductor layer is formed on the upper surface of the second semiconductor layer from the upper surface of the second semiconductor layer, and the third semiconductor layer is separated from the upper surface of the second semiconductor layer. And formed between the inner side surface of the fourth semiconductor layer and the second semiconductor layer; the first insulating film 'at at least; the side surface of the second semiconductor layer and the side surface of the fourth semiconductor layer 'gate conductor a layer is formed on the second surface of the second semiconductor layer without forming the second insulating film, and is formed on the lower surface of the second semiconductor layer, and is formed in the fourth half of the first insulating film. And the fifth semiconductor layer 'is not formed in the third semiconductor half=2=4 layer, and is formed on the second semiconductor layer=upper surface' at least the third semiconductor layer and the second semiconductor semiconductor layer Upper area, the aforementioned fourth The semi-layer forms a diode; the formation of the first half of the second semiconductor layer and the first semiconductor layer is === 322818 8 201143071 is the source, and the diode is the gate junction transistor Forming a field effect transistor in which the first semiconductor layer is a drain, the third semiconductor layer is a source, and the gate conductor layer is a gate; and an accumulation means is provided, and the electromagnetic energy wave is irradiated The signal charge generated in the pixel is accumulated in the diode; the signal reading means measures the signal charge by measuring a current that varies according to the amount of signal charge flowing through the bonded transistor and accumulated in the diode. And a resetting means for applying an on-voltage to the gate conductor layer of the field effect transistor and forming a region including the second semiconductor layer between the first semiconductor layer and the third semiconductor layer The channel 'by removing the signal charge accumulated in the diode to the first semiconductor layer; applying a voltage to the conductor electrode ' to cause a signal to be accumulated in the diode The charge polarity opposite to the charge accumulated in the fourth semiconductor layer. Preferably, the second semiconductor layer is opposite to the first semiconductor layer or substantially intrinsic; the third semiconductor layer is of the same conductivity type as the first semiconductor layer; and the fourth semiconductor layer is The first semiconductor layer is of a reverse conductivity type; and the fifth semiconductor layer is of a reverse conductivity type to the first semiconductor layer. Preferably, the wiring conductor layer is provided to connect the conductor electrodes of the adjacent pixels to each other in the vicinity of the gate conductor layer, and is made of a light-shielding conductive material. Preferably, the wiring conductor layer is connected to all of the conductor electrodes of the plurality of pixels. Preferably, the second insulating film 322818 9 201143071 2 formed by covering the gate conductive layer is formed to have at least a film, and the conductor electrode is partially overlapped with one of the gate conductive layers. a human conductor layer buried between the adjacent 导体if conductors _, the adjacent inter-derivatives of the adjacent pixels or the adjacent conductors of the adjacent pixels and the aforementioned pixels It is described between the gate conductor layers and by the light-shielding guide material. Preferably, the third semiconductor layer and the fourth semiconductor layer and the conductor electrode are formed on the upper end of the third semiconductor layer in a direction from the fifth semiconductor layer toward the second semiconductor layer. The upper end of the fourth semiconductor layer and the upper end of the conductor electrode substantially coincide with each other, or the third semiconductor layer and the fourth semiconductor layer and the conductor electrode face the second semiconductor layer toward the second semiconductor layer The direction is such that the upper end of the third semiconductor layer is farther from the fifth semiconductor layer than the upper end of the conductor electrode, and the upper end of the fourth semiconductor layer is located at the upper end of the third semiconductor layer and the upper end of the conductor electrode. between. Preferably, the resetting means is to apply a voltage to the conductor electrode, and to turn on the deepest potential in the third semiconductor layer when the potential of the fifth semiconductor layer and the signal charge are not accumulated in the diode. The potential relationship is set such that the channel potential of the second semiconductor layer and the potential of the first semiconductor layer become deeper when a voltage is applied to the gate conductor layer of the field effect transistor. Preferably, the signal reading means applies a voltage to the conductor 322818 10 201143071 pole' such that the depletion layer of the diode occupies the entire upper portion of the second semiconductor layer when the money charge is not accumulated in the diode. region. [Effect of the Invention] According to the present invention, a solid-state imaging device with low color mixing, high sensitivity, low afterimage, low dark current, low noise, and high pixel density can be provided. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to Figs. 1A to 17C. (First embodiment of the present invention) Fig. 1A and Fig. 1B show the structure of a pixel H) of the solid-state imaging device 100 according to the embodiment of the present invention. In addition, the basic structure of the image f 10 of the solid-state imaging device 100 of the present embodiment is the same as that of the solid-state imaging device disclosed in International Publication No. 2009-034623, which is described in the International Publication No. 2009-034623. All contents are referred to in this specification by reference. In Fig. 1A, a first semiconductor layer N+ layer 1' is formed on a substrate in each of the pixels 10. The first semiconductor layer i is connected to a wiring XL extending in the J-scan direction. On the first semiconductor layer n+ layer, a second semiconductor layer p layer 2 of a conductivity type opposite to that of the first semiconductor layer N+ layer 1 is formed. In the upper side surface region of the second semiconductor layer P layer 2, the third semiconductor layer N layers 5a and 5b having the same conductivity type as those of the second semiconductor layer n+ layer are formed so as to surround the second semiconductor layer P layer 2. Further, the third half " conductor layer N layers 5a, 5b are not in contact with the upper surface of the second semiconductor layer p layer 2. The third semiconductor layer N layers 5a and 5b and the second semiconductor layer P layer 2 in the vicinity of the third semiconductor layer N layers 5a and 5b constitute a photodiode: 322818 11 201143071, X-ray and electron beam 112, etc. The photodiode 112 accumulates signal charges generated by irradiation of light energy waves. Further, on the surface of the photodiode 112, a fourth semiconductor layer wide layer 6a, 6b of a conductivity type opposite to that of the second semiconductor layer is formed so as to surround the outer peripheral portion of the photodiode 112. In addition, the fourth semiconductor layer? The + layers 6a and 6b are also disposed so as not to be in contact with the upper surface of the second semiconductor layer μ 2 in such a manner as to cover the side faces of the second semiconductor layer p layer 2 and the outer faces of the fourth semiconductor layer p + layers 6a and 6b. An insulating film (10) 2 film is formed, for example, 曰北. The conductor electrodes 7a and 7b are formed on the side faces of the fourth semiconductor layer P+ layers 6a and 6b with the insulating films 3a and 3b interposed therebetween. Gate conductive layers 4a and 4b are formed on the side surface of the lower portion of the second semiconductor layer p layer 2 with the insulating films 3a and 3b interposed therebetween. Further, the gate conductor layers 4a and 4b are formed of a metal film or a light-shielding material such as a high-concentration impurity polycrystal having a sufficient thickness. The insulating films 3a and 3b and the gate conductor layers 4a and 4b constitute a reset MOS transistor 111 in which a lower portion of the second semiconductor layer p layer 2 is a channel. On the upper surface of the second semiconductor layer P layer 2, a fifth semiconductor layer p+ layer 8 of the same conductivity type as that of the second semiconductor layer P layer 2 is formed. Further, the fifth semiconductor layer P+ layer 8 is provided apart from the third semiconductor layer N layers 5a and 5b and the fourth semiconductor layer P+ layers 6a and 6b. Further, the fifth semiconductor layer p+ layer 8 is connected to the wiring yl extending in a direction orthogonal to the first scanning direction. An amplifying bonding transistor in which the second semiconductor layer ρ layer 2 and the fifth semiconductor layer P+ layer 8 in the vicinity of the first semiconductor layer N+ layer 1 are used as the gate and the source and the photodiode il2 is used as the gate is formed. Further, the upper portion of the second semiconductor layer p layer 2 of the photodiode 1 322818 12 201143071, the third semiconductor layer n layers 5a and 5b, the fourth semiconductor layer p+ layers 6a and 6b, and the fifth semiconductor layer P+ are formed. The layer 8 is formed in an island shape. Further, in the present embodiment, the wiring XL is a signal line, and the wiring YL is a pixel selection line, but the wiring XL may be a pixel selection line, and the wiring YL is a signal line. In the configuration of the pixel 10, since the conductor electrodes 7a, 7b on the photodiode 112 are formed on the side surface of the island-shaped semiconductor, the incident light 12a is directly irradiated from the fifth semiconductor layer P+ layer 8 to the photodiode region. . As a result, in the solid-state imaging device 100 of the present embodiment, the decrease in the sensitivity of the blue wavelength light generated in the conventional solid-state imaging device as shown in the figure is not caused. Further, the conductor electrode 73 is formed of a metal film or a light-shielding material such as a high-concentration impurity polycrystalline Si having a sufficient thickness. Thereby, the incident light 12a' incident from the fifth semiconductor layer p + layer 8 in the photodiode region is absorbed or reflected in the conductor electrodes 7a, 7b. Further, since the conductor electrodes 7a, 7b are formed to surround the outer peripheral portion of the photodiode 112, the incident light 12a and the reflected light 12c reflected by the conductor electrodes 7a, 7b are prevented from leaking to the pixel adjacent to the pixel, and Both the incident light 12a and the reflected light 12c can effectively contribute to the signal charge. As a result, in the solid-state imaging device 100, it is possible to suppress color mixture and lower resolution. In the solid-state imaging device shown in Fig. 1A, the second semiconductor layer is a p-layer 2 composed of a P-type conductivity type semiconductor layer. As shown in Fig. 8, the second semiconductor layer may be an i layer 2 made of a substantially intrinsic type semiconductor, instead of the p layer 2 composed of the P type conductive type semiconductor. Intrinsic semiconductors are manufactured without impurities, but in reality 322818 13 201143071 will contain very small amounts of impurities. The substantially intrinsic semi-conductive system constituting the second semiconductor layer 2丨 contains a trace amount of acceptor (acc or don) as long as it does not hinder the performance of the solid imaging device. According to such a configuration, the third semiconductor layer N layers 5a and 5b and the second semiconductor i layer 2i can form a diode. Further, when a sufficient voltage is applied to the fifth semiconductor layer p+ layer 8 and the signal When the first semiconductor layer N+ layer 1 of the line is between, the hole of the fifth semiconductor layer p+ layer 8 is directed toward the first semiconductor layer N+ layer due to the potential gradient generated inside the second semiconductor germanium layer 2i. In this way, the second semiconductor i-layer 2i can also function as a channel for amplifying the bonded transistor. Fig. 2 is a circuit configuration example of the solid-state imaging device 1 of the present embodiment. The solid-state imaging device 100 is mainly provided. : a plurality of pixels 1 〇 a to i 〇 d arranged in a 2-dimensional matrix; a vertical scanning circuit 201; a horizontal scanning circuit 202; a reset circuit 203; pixel selection lines yli, YL2; signal lines XL1, XL2 Reset line (reset Hne) RsL; signal line M0S transistor Tr1, T R2, and a c双重rreiated double Sampling ' CDS output circuit 204. In the present embodiment, the case where the pixels 10a to 10d are arranged in two rows (column) is described as 'only. The solid-state imaging device according to the invention is not limited thereto. As shown in Fig. 2, the vertical scanning circuit 201 for inputting the pixel selection signal to each of the pixels 1a to i〇d passes through the pixel selection lines YLI and YL2 for each column. Each of the pixels i 〇 a to i 〇 d is connected to the CDS output circuit 204 in accordance with each of the columns through the signal line XL XL 2 . Signal line xli, XL2 signal line M0S transistor 14 322818 201143071
Trl、Tr2之閘極電極，係連接於將信號線選擇信號輸入於 該閘極電極之水平掃描電路202。此外，信號線XL1、XL2 亦連接於切換開關部SW1、SW2。此外，重設動作用之M0S 電晶體之閘極導體層4a、4b，係透過重設線RSL而連接於 將重設信號輸入於閘極導體層4a、4b之重設電路203。再 者，像素10a至10d之光二極體上之導體電極7a、7b，係 與外部電壓VPg相連。藉由本電路構成之動作，各像素10a 至10d之信號電流即逐次從CDS輸出電路204被讀取。 接著參照第1A圖至第3D圖說明本實施形態之固體攝 像裝置100之基本動作。另外，在第3A圖之電位分布圖中， 為了區別，係將蓄積之信號電荷以陰影來顯示。 本裝置之基本動作，係由信號電荷蓄積動作、信號讀 取動作、及重設動作所構成。 在信號電荷蓄積動作中，係將因為光、X光或電子束 等電磁能量波之照射所產生之信號電荷予以蓄積於光二極 體 112。 在信號讀取動作中，係藉由測量流通於第5半導體層 P+層8與第1半導體層N+層1附近之第2半導體層P層2 之間的電流，來測量蓄積於光二極體112之信號電荷。當 將光二極體112設為放大用接合電晶體之閘極時，流通於 第1半導體層N+層1附近之第2半導體層P層2與第5半 導體層P+層8之間的電流，即依據蓄積於光二極體112之 信號電荷而變化。因此，藉由測量該電流，即可讀取所蓄 積之信號電荷的量。 15 322818 201143071 在重設動作中，係將導通電壓施加於重設M〇s電晶體 111之閘極導體層4a、4b而將蓄積於光二極體112之信號 電荷流通於第1半導體層N+層1而予以去除。 第3A圖係顯示信號電荷蓄積動作期間中沿著第1A圖 中之A-A線之電位分布圖。φρΚ係為未蓄積有信號電荷時 之第3半導體層ν層5a、5b内之最深的電位。 在佗號電荷蓄積動作期間中，設定導體電極7a、7b之 電壓VPg，以使第4半導體層P+層6a、肋之電位成為接地 電位或接地電位附近之電位。例如，可設定成導體電極 7b之電壓vPg=〇v、信號線xl之電壓yXLR=〇v、像素選擇線 YL之電壓vYLR=〇v。藉此，成為第3A圖所示之電位分布， 而在第3半導體層！^層5a、5b之區域蓄積信號電荷如陰影 所不，而光二極體電位〇GR係依所蓄積之信號電荷而變化。 此外，藉由將第4半導體層p+層6a、6b之電位設定 為接地電位或接地電位附近之電位，在第4半導體層广層 6a、6b蓄積許多電洞30。此電洞3〇係從位於第4半導體 層P+層6a、6b與第5半導體層广層8之間的第2半導體 層P層2供給。從絕緣膜3a、3b與第4半導體層p+層 6b之界面讀（trap);·熱性產生，而成為暗電流之原因 的電子，係與蓄積於第4半導體層p+層6a、6b之電洞3〇 再度結合而消滅《藉此，可防止暗電流之產生。 為了抑制暗電流，亦可例如將第5半導體層p+層8與 第4半導體層P+層6a、6b連接，且將第4半導體層p+層 6a、6b之電位設定於接地電位。然而，此情形時，由於^ 322818 16 201143071 4半導體層P+層6a、6b並非一直固定於接地電位，因此會 容易受到攝像動作中變動之第5半導體層P+層8之電位= 影響。相對於此，在本實施形態之固體攝像裝置1〇〇中， 由於第4半導體層P+層6a、6b之電位係由導體電極7a、 7b所設定，因此可防止因為第5半導體層广層8之電位變 動所產生之雜訊等所導致圖像特性的降低。 第3B圖係為信號讀取動作期間中之未蓄積信號電荷 於光二極體112時之像素構造圖，該情形之光二極體112 之空乏層（depletion regi〇n)9(9a、9b)係以虛線顯示。在 本實施形態中，於信號電荷未蓄積於光二極體112時光 二極體112之空乏^ 9a、9b，係形成於第2半導體層p層 2中之形成有光二極體112之上部區域之—部分。當信號 電荷蓄積於光二極體112時，如第3C圖所示，空乏層％、 9b之寬度減少，而形成於第2半導體層？層2之放大用接 合電晶體之通道寬度則增大。在信號讀取動作期間中，放 ^接合電晶體之通道寬度，亦即依據所蓄積之信號電荷 之量而變化之電流係流通於該通道。 由於在信賴取動料亦可蚊導體_?a、7b之電 壓以使第4半導體層P、6a、6b之電位大致成為接地電 位，因此可使電洞30蓄積於第4半導體層p+層6a、肋之 表面。藉此’因為重設簡電晶體111之閘極導體層4a、 扑之電壓變動所導致對於光二極體電位的影響即變小，而 本實施形態之固體攝像裝置_即可穩定動作。 第3 D圖係顯示重設動作期間中沿著第i A财之B - B， 322818 17 201143071 線之電位分布圖。在重設動作期間中，以依照第5半導體 層P層8之電位vYLR、未蓄積有信號電荷時之第3半導體 層N層5a 5b内之最深之電位①⑽、導通電壓施加於廳 電晶體之閘極導體層4a、4b時之第2半導體層？層2之重 設M0S電晶體U1之通道電位第】半導體層n+層i 之電位vXLR之順序變深之方式，設定信號線xl之電壓 像素選擇線YL之電壓Vyu、及導體電極7a、7b之電壓i 藉由此種電位關係，蓄積於光二極體112之信號電荷即被 去除至第1半導體層N+層1而不會殘存於光二極體112。 因此’可防止殘影之產生，再者，在信號電荷傳送於信號 =XL之後，由於無流通於重設M〇s電晶體η 1之通道之電 机而防止kTC雜訊之產生。此外，第3半導體層Ν層^、 之電位Φ pm ’係可藉由導體電極7a、之電壓Vpg而控 制。因此，可設定第3半導體層U 5a、5b之電位φρΒ， 以使在重設動作期間中最深之第！半導體層N+層工之電位 “變淺。冑此’即可將固體攝像裝置⑽之驅動電麗降低。 (第2實施形態） - 第4圖係顯示用以說明本發明第2實施形態之固體攝 ^置IGOa之相鄰接2像素1()e、1Gf之像素剖面圖。另 ^對於與第1實施形態之固體攝像裝置_相同的部分 立、賦予相同付號。此外為了區別’對於包含於像素之 部分係賦予aa及ab ’對於包含於像素谢之部分係賦予 a及bb。與第！實施形態之不同點，係為像素1〇卜⑽ 之導體電極7aa、7ab、7ba、7bb在閘極導體層4aa、她、 322818 18 201143071 4ba、4bb附近相連。在本實施形態中，係由導體電極7aa、 7ab、7ba、7bb、及將相鄰接之像素之導體電極7aa、7ab、 7ba、7bb彼此連接之配線導體層至i3c構成像素選擇 線。另外’在本實施形態中，導體電極7aa、7ab、7ba、 7bb與配線導體層13a至i3c係形成一體。 導體電極7aa、7ab、7ba、7bb及配線導體層13a至 13c係由金屬膜或具有充分厚度之高濃度雜質多晶Si等遮 光性材料所形成。因此’例如，射入於像素10e之第5半 導體層P+層8a之光（入射光）i2a，係被導體電極7ab、7ba 及配線導體層13b所反射。該所反射之光（反射光）12c係 在像素10e產生有效的信號電荷。再者，第4圖中虛線箭 頭所示之洩漏至鄰接像素l〇f之洩漏光12b則不會產生。 再者’藉由導體電極7aa、7ab、7ba、7bb在閘極導體層 4aa、4ab、4ba、4bb附近相連，射入於像素間隙11a、lib、 11c之光（洩漏至像素間隙之洩漏光）14，如第4圖所示， 會被配線導體層13a至13c反射或吸收。因此，可防止光 14在到達像素、10f之底部期間從閘極導體層4aa、 4ab、4ba、4bb與導體電極7aa、7ab、7ba、7bb之間隙等 光學路控侵入於像素l〇e、lOf之第2半導體層P層2a、 2b。藉此，可防止混色之產生及解析度之降低。 第4圖雖係顯示導體電極7aa、7ab、7ba、7bb連接朝 圖式所不方向（相對於圖式為水平方向）排列之像素1〇e、 l〇f彼此之情形，惟亦可將相對於圖式朝垂直方向排列之 像素彼此連接。此情形時，同樣可防止混色之產生及解析 322818 19 201143071 度之降低。 再者，如第2圖所不，可將位於本實施形態之固體攝 像裝置100a之感光區域之所有像素i〇a至之導體電極 7a、7b連接，而連接於一個外部電壓Vpg。此情形時，由於 係以蓋住感光區域之像素間隙11a至iic整面之方式形成 導體電極7aa、7ab、7ba、7bb及配線導體層i3a至13c， 因此大致可元全防止射入於像素間隙lla至lie之光射入 於第2半導體層P層2。 (第3實施形態） 第5圖係顯示用以說明本發明第3實施形態之固體攝 像裝置100b之2像素10e、l〇f之像素剖面圖。另外，對 於與第2實施形態之固體攝像裝置i〇〇a相同的部分係賦予 相同符號。在第2實施形態之固體攝像裝置i〇〇a中，係為 導體電極7aa、7ab、7ba、7bb在閘極導體層4aa、4ab、 4ba、4bb附近相連。相對於此，在本實施形態之固體攝像 裝置100b中，係為在各像素l〇e、l〇f之像素間隙1 ia至 lie中，導體電極7aa、7ab、7ba、7bb之間及閘極導體層 4aa、4ab、4ba、4bb之間之兩方或是任一方埋入有埋入導 體層15a至15c、16a至16c埋入。第5圖係顯示在兩方埋 入有埋入導體層15a至15c、16a至16c之情形。此時，導 體電極7aa、7ab、7ba、7bb與閘極導體層4aa、4ab、4ba、 4bb之配線方向係相同。另外，在兩者之配線朝正交之方 向取出時，於第5圖中，係顯示埋入導體層15a至15c、 16a至16c僅在導體電極7aa、7ab、7ba、7bb及閘極導體 20 322818 201143071 層 4aa、4ab、4ba、4bb 之任一方。 埋入導體層15a至15c、16a至16c係由金屬膜或具有 充分厚度之高濃度雜質多晶Si等遮光性材料所形成。因 此，例如，射入於像素l〇e之第5半導體層P+層8a之光 12a，係在閘極導體層4ab、4ba及導體電極7ab、7ba反射。 所反射之光（反射光）12c係在像素10e產生有效的信號電 荷。此外，即使入射光12a及反射光12c從閘極導體層4aa、 4ab、4ba、4bb與導體電極7aa、7ab、7ba、7bb之間隙洩 漏，所洩漏之光也會被埋入導體層15a至15c、16a至16c 反射或吸收。因此，可更有效防止入射光12a及反射光12c 侵入鄰接像素10e、l〇f之第2半導體層p層2a、2b。藉 此，可更有效防止解析度之降低、或混色之產生。 (第4實施形態） 第6圖係顯示用以說明本發明第4實施形態之固體攝 像裝置100c之像素構造。另外’對於與第2實施形態之固 體攝像裝置100a相同之部分係賦予相同符號。本圖係為將 包含第2半導體層P層2a、2b、閘極導體層4ab、4ba、第 3半導體層N層5ab、5ba、第4半導體層p+層6ab、6ba、 導體電極7ab、7ba、及第5半導體層p+層ga、8b之區域 放大之像素剖.面圖。在此，導體電極7ab、7ba係透過配線 導體層13b而彼此連接。與第2實施形態之固體攝像裝置 100a之不同點’係為間隔著以覆蓋閘極導體層4ab、4ba 之方式設置之絕緣膜17ab、17ba，使導體電極7ab、7ba 與閘極導體層4ab、4ba之至少一部分重疊而形成之點。 322818 21 201143071 在本固體攝像裝置100c中，由於在閘極導體層4ab、 4ba與導體電極7ab、7ba之間沒有間隙，因此不會產生從 間隙屬漏光之情形。因此，可更有效防止光茂漏至鄰接像 素。 在本實施形態中，雖係已說明了導體電極7ab、7|^彼 此相連之情形，惟即使如第丨實施形態之固體攝像裝置 ⑽’導體電極7a、7b彼此未相連之情形，藉由導體電極 7a、7b形成為與閘極導體層乜，重疊，與上述相同， 亦可更有效防止光洩漏至鄰接像素。 接著參照第7圖至第15圖說明第4實施形態之固體攝 像裝置100c之製造方法。 百先，如f 7圖所示，在石夕（Si〇2)基板上堆積p型石夕 層301、氮化矽膜3〇2及氧化矽臈3〇3。之後，如第8圖所 不’藉由⑽等形成島狀半導體層3〇4a、3_。接著，例 如在氧氣氛财將基板加熱，並藉由將㊉表面氧化而形成 氧化石夕膜305。接著堆積多晶石夕，並藉由回钱， 如第9，所示形成侧壁(side财⑴狀多晶矽膜3〇6。 接著，藉由以離子注入法等在p型石夕層3〇1注入填等 而，成第1半導體層N層la、lb。之後，將多晶石夕膜3〇6 及氧切膜 _。接著，形餘切膜層307，並藉 由閘極氧化而形成閘極氧化膜·，如第1()圖所示，以藉 由單石夕烧On。廳i lane)(SiH4)之熱分解之⑽The gate electrodes of Trl and Tr2 are connected to a horizontal scanning circuit 202 for inputting a signal line selection signal to the gate electrode. Further, the signal lines XL1, XL2 are also connected to the changeover switch sections SW1, SW2. Further, the gate conductor layers 4a and 4b of the MOS transistor for reset operation are connected to the reset circuit 203 for inputting the reset signal to the gate conductor layers 4a and 4b via the reset line RSL. Further, the conductor electrodes 7a, 7b on the photodiodes of the pixels 10a to 10d are connected to the external voltage VPg. By the operation of this circuit, the signal current of each of the pixels 10a to 10d is sequentially read from the CDS output circuit 204. Next, the basic operation of the solid-state imaging device 100 of the present embodiment will be described with reference to Figs. 1A to 3D. Further, in the potential distribution map of Fig. 3A, in order to distinguish, the accumulated signal charges are displayed by hatching. The basic operation of the device consists of a signal charge accumulation operation, a signal reading operation, and a reset operation. In the signal charge accumulation operation, signal charges generated by irradiation of electromagnetic energy waves such as light, X-rays, or electron beams are accumulated in the photodiode 112. In the signal reading operation, the current stored in the photodiode 112 is measured by measuring the current flowing between the fifth semiconductor layer P+ layer 8 and the second semiconductor layer P layer 2 in the vicinity of the first semiconductor layer N+ layer 1. Signal charge. When the photodiode 112 is a gate of the junction transistor for amplification, the current flowing between the second semiconductor layer P layer 2 and the fifth semiconductor layer P+ layer 8 in the vicinity of the first semiconductor layer N+ layer 1 is It varies depending on the signal charge accumulated in the photodiode 112. Therefore, by measuring the current, the amount of accumulated signal charge can be read. 15 322818 201143071 In the reset operation, the on-voltage is applied to the gate conductor layers 4a and 4b of the reset M〇s transistor 111, and the signal charge accumulated in the photodiode 112 is circulated to the first semiconductor layer N+ layer. 1 and remove it. Fig. 3A is a diagram showing the potential distribution along the A-A line in Fig. 1A during the signal charge accumulation operation. φρΚ is the deepest potential in the third semiconductor layer ν layers 5a and 5b when no signal charge is accumulated. During the 佗 charge accumulation operation period, the voltages VPg of the conductor electrodes 7a and 7b are set such that the potential of the fourth semiconductor layer P+ layer 6a and the ribs becomes a potential near the ground potential or the ground potential. For example, the voltage vPg = 〇v of the conductor electrode 7b, the voltage yXLR = 〇v of the signal line x1, and the voltage vYLR = 〇v of the pixel selection line YL can be set. Thereby, the potential distribution shown in FIG. 3A is obtained, and in the third semiconductor layer! The area of the layers 5a, 5b accumulates signal charges such as shadows, and the photodiode potential 〇GR varies depending on the accumulated signal charge. Further, by setting the potential of the fourth semiconductor layer p+ layers 6a and 6b to the potential near the ground potential or the ground potential, a large number of holes 30 are accumulated in the fourth semiconductor layer wide layers 6a and 6b. This hole 3 is supplied from the second semiconductor layer P layer 2 located between the fourth semiconductor layer P+ layers 6a and 6b and the fifth semiconductor layer wide layer 8. The interface between the insulating films 3a and 3b and the fourth semiconductor layer p+ layer 6b is trapped; the heat is generated, and the electrons which are the cause of the dark current are the holes accumulated in the p+ layers 6a and 6b of the fourth semiconductor layer. 3〇 Combine again and eliminate “by this, it can prevent the generation of dark current. In order to suppress the dark current, for example, the fifth semiconductor layer p+ layer 8 and the fourth semiconductor layer P+ layers 6a and 6b may be connected, and the potential of the fourth semiconductor layer p+ layers 6a and 6b may be set to the ground potential. However, in this case, since the semiconductor layer P+ layers 6a and 6b are not always fixed to the ground potential, the potential of the fifth semiconductor layer P+ layer 8 which fluctuates during the imaging operation is likely to be affected. On the other hand, in the solid-state imaging device 1 of the present embodiment, since the potentials of the fourth semiconductor layer P+ layers 6a and 6b are set by the conductor electrodes 7a and 7b, it is possible to prevent the fifth semiconductor layer from being wide 8 The noise caused by the fluctuation of the potential causes a decrease in image characteristics. FIG. 3B is a pixel structure diagram in the case where the signal charge is not accumulated in the photodiode 112 during the signal reading operation period, and in this case, the depletion layer 9 (9a, 9b) of the photodiode 112 is Shown in dotted lines. In the present embodiment, when the signal charges are not accumulated in the photodiode 112, the vacancies 9a and 9b of the photodiode 112 are formed in the upper portion of the second semiconductor layer p-layer 2 where the photodiode 112 is formed. -section. When the signal charge is accumulated in the photodiode 112, as shown in Fig. 3C, the widths of the depletion layers % and 9b are reduced to form the second semiconductor layer. The width of the channel for amplifying the layer 2 is increased. During the signal reading operation, the channel width of the bonding transistor, that is, the current that varies according to the amount of accumulated signal charge, flows through the channel. Since the potential of the fourth semiconductor layers P, 6a, and 6b can be substantially at the ground potential by the voltage of the mosquito conductors _?a and 7b, the hole 30 can be accumulated in the fourth semiconductor layer p+ layer 6a. The surface of the ribs. In this way, the effect of the gate electrode layer 4a of the simple transistor 111 on the potential of the photodiode is reduced, and the solid-state imaging device of the present embodiment can be stably operated. Figure 3D shows the potential distribution along the B-B, 322818 17 201143071 line of the i-A financial period during the reset action. In the reset operation period, the deepest potential 1 (10) and the on-voltage in the third semiconductor layer N layer 5a 5b when the signal charge is not accumulated in accordance with the potential vYLR of the fifth semiconductor layer P layer 8 and the on-voltage are applied to the hall transistor. The second semiconductor layer in the case of the gate conductor layers 4a, 4b? The layer 2 is reset to the channel potential of the MOS transistor U1. The order of the potential vXLR of the semiconductor layer n+ layer i is deepened, and the voltage Vyu of the voltage pixel selection line YL of the signal line x1 and the conductor electrodes 7a, 7b are set. The voltage i is such that the signal charge accumulated in the photodiode 112 is removed to the first semiconductor layer N+ layer 1 without remaining in the photodiode 112. Therefore, the generation of residual images can be prevented. Further, after the signal charge is transmitted to the signal = XL, the generation of kTC noise is prevented because there is no motor flowing through the channel for resetting the M?s transistor ?1. Further, the potential Φ pm ' of the third semiconductor layer Ν layer can be controlled by the voltage Vpg of the conductor electrode 7a. Therefore, the potential φρΒ of the third semiconductor layers U 5a and 5b can be set so as to be the deepest in the reset operation period! The potential of the N+ layer of the semiconductor layer is “lighter. This can reduce the driving power of the solid-state imaging device (10). (Second embodiment) - Fig. 4 shows a solid for explaining the second embodiment of the present invention. A pixel cross-sectional view of two pixels 1()e and 1Gf adjacent to the IGOa is set. The same part is given to the same portion as the solid-state imaging device of the first embodiment. In the part of the pixel, aa and ab' are given to the part included in the pixel, and a and bb are given. The difference from the second embodiment is that the conductor electrodes 7aa, 7ab, 7ba, and 7bb of the pixel 1 (10) are The gate conductor layer 4aa, her, 322818 18 201143071 4ba, 4bb are connected in the vicinity. In the present embodiment, the conductor electrodes 7aa, 7ab, 7ba, 7bb, and the conductor electrodes 7aa, 7ab, 7ba of the adjacent pixels are connected. The wiring conductor layers 7b and 7b are connected to each other to form a pixel selection line. In the present embodiment, the conductor electrodes 7aa, 7ab, 7ba, and 7bb are integrally formed with the wiring conductor layers 13a to 13c. The conductor electrodes 7aa, 7ab, and 7ba are integrally formed. , 7bb and wiring conductor layer 13a 13c is formed of a metal film or a light-shielding material such as a high-concentration impurity polycrystalline Si having a sufficient thickness. Therefore, for example, light (incident light) i2a incident on the fifth semiconductor layer P+ layer 8a of the pixel 10e is The conductor electrodes 7ab and 7ba and the wiring conductor layer 13b are reflected. The reflected light (reflected light) 12c generates an effective signal charge in the pixel 10e. Further, the dotted arrow in the fourth figure leaks to the adjacent pixel 1. The leakage light 12b of 〇f does not occur. Further, the conductor electrodes 7aa, 7ab, 7ba, and 7bb are connected in the vicinity of the gate conductor layers 4aa, 4ab, 4ba, and 4bb, and are incident on the pixel gaps 11a, lib, and 11c. The light (leakage light leaking to the pixel gap) 14 is reflected or absorbed by the wiring conductor layers 13a to 13c as shown in Fig. 4. Therefore, the light 14 can be prevented from coming from the gate conductor during reaching the bottom of the pixel, 10f. Optical paths such as the gaps between the layers 4aa, 4ab, 4ba, and 4bb and the conductor electrodes 7aa, 7ab, 7ba, and 7bb intrude into the second semiconductor layer P layers 2a and 2b of the pixels 10e and 10f, thereby preventing color mixture. Reduction in production and resolution. Figure 4 shows the conductor electrode 7aa, 7ab, 7ba, 7bb are connected to the pixels 1〇e, l〇f arranged in the direction opposite to the figure (horizontal direction with respect to the drawing), but may be arranged in a vertical direction with respect to the drawing. The pixels are connected to each other. In this case as well, the generation of the color mixture and the reduction of the resolution 322818 19 201143071 can be prevented. Further, as shown in Fig. 2, all the pixels in the photosensitive region of the solid-state imaging device 100a of the present embodiment can be prevented. The conductor electrodes 7a, 7b to i〇a are connected to each other and connected to an external voltage Vpg. In this case, since the conductor electrodes 7aa, 7ab, 7ba, and 7bb and the wiring conductor layers i3a to 13c are formed so as to cover the entire surface of the pixel gaps 11a to iic of the photosensitive region, it is possible to substantially prevent the injection into the pixel gap. The light of lla to lie is incident on the second semiconductor layer P layer 2. (Embodiment 3) FIG. 5 is a cross-sectional view showing a pixel of two pixels 10e and 10f of the solid-state imaging device 100b according to the third embodiment of the present invention. The same components as those of the solid-state imaging device i〇〇a of the second embodiment are denoted by the same reference numerals. In the solid-state imaging device i〇〇a of the second embodiment, the conductor electrodes 7aa, 7ab, 7ba, and 7bb are connected in the vicinity of the gate conductor layers 4aa, 4ab, 4ba, and 4bb. On the other hand, in the solid-state imaging device 100b of the present embodiment, between the pixel gaps 1 ia to lie of the respective pixels l〇e and lf, the conductor electrodes 7aa, 7ab, 7ba, and 7bb and the gate are provided. The buried conductor layers 15a to 15c, 16a to 16c are buried in either or both of the conductor layers 4aa, 4ab, 4ba, and 4bb. Fig. 5 shows the case where the buried conductor layers 15a to 15c, 16a to 16c are buried in both sides. At this time, the wiring directions of the conductor electrodes 7aa, 7ab, 7ba, and 7bb and the gate conductor layers 4aa, 4ab, 4ba, and 4bb are the same. Further, when the wirings of the two are taken out in the direction orthogonal to each other, in Fig. 5, the buried conductor layers 15a to 15c, 16a to 16c are shown only on the conductor electrodes 7aa, 7ab, 7ba, 7bb and the gate conductor 20 322818 201143071 One of the layers 4aa, 4ab, 4ba, 4bb. The buried conductor layers 15a to 15c, 16a to 16c are formed of a metal film or a light-shielding material such as a high-concentration impurity polycrystalline Si having a sufficient thickness. Therefore, for example, the light 12a incident on the fifth semiconductor layer P+ layer 8a of the pixel 10e is reflected by the gate conductor layers 4ab and 4ba and the conductor electrodes 7ab and 7ba. The reflected light (reflected light) 12c produces an effective signal charge at the pixel 10e. Further, even if the incident light 12a and the reflected light 12c leak from the gaps of the gate conductor layers 4aa, 4ab, 4ba, 4bb and the conductor electrodes 7aa, 7ab, 7ba, 7bb, the leaked light is buried in the conductor layers 15a to 15c. , 16a to 16c reflect or absorb. Therefore, it is possible to more effectively prevent the incident light 12a and the reflected light 12c from intruding into the second semiconductor layer p layers 2a and 2b of the adjacent pixels 10e and 10f. As a result, it is possible to more effectively prevent a decrease in resolution or a color mixture. (Fourth Embodiment) Fig. 6 is a view showing a pixel structure for explaining a solid-state imaging device 100c according to a fourth embodiment of the present invention. The same portions as those of the solid-state imaging device 100a of the second embodiment are denoted by the same reference numerals. The figure includes the second semiconductor layer P layers 2a and 2b, the gate conductor layers 4ab and 4ba, the third semiconductor layer N layers 5ab and 5ba, the fourth semiconductor layer p+ layers 6ab and 6ba, and the conductor electrodes 7ab and 7ba. And a cross-sectional view of a pixel enlarged in a region of the fifth semiconductor layer p+ layers ga and 8b. Here, the conductor electrodes 7ab and 7ba are connected to each other through the wiring conductor layer 13b. The difference from the solid-state imaging device 100a of the second embodiment is that the insulating films 17ab and 17ba are provided so as to cover the gate conductor layers 4ab and 4ba, and the conductor electrodes 7ab and 7ba and the gate conductor layer 4ab are arranged. The point at which at least a part of 4ba overlaps. 322818 21 201143071 In the solid-state imaging device 100c, since there is no gap between the gate conductor layers 4ab and 4ba and the conductor electrodes 7ab and 7ba, light leakage from the gap does not occur. Therefore, it is possible to more effectively prevent the light from leaking to the adjacent pixels. In the present embodiment, the case where the conductor electrodes 7ab and 7^ are connected to each other has been described, but the conductor electrodes 7a and 7b of the solid-state imaging device (10) according to the second embodiment are not connected to each other by the conductor. The electrodes 7a and 7b are formed so as to overlap with the gate conductor layer, and as described above, it is possible to more effectively prevent light from leaking to adjacent pixels. Next, a method of manufacturing the solid-state imaging device 100c according to the fourth embodiment will be described with reference to Figs. 7 to 15 . According to Fig. 7, a p-type shoal layer 301, a tantalum nitride film 3〇2, and yttrium oxide 3〇3 are deposited on a Si夕2 substrate. Thereafter, as shown in Fig. 8, the island-shaped semiconductor layers 3a, 4a, and 3_ are formed by (10) or the like. Next, for example, the substrate is heated in an oxygen atmosphere, and the oxidized stone film 305 is formed by oxidizing the surface of the ten. Then, the polycrystalline stone is deposited, and by returning the money, as shown in the ninth, the side wall is formed (the side (1) polycrystalline tantalum film 3〇6. Next, by the ion implantation method or the like in the p-type layer 1 is filled and formed into the first semiconductor layer N layers 1a, 1b, and then, the polycrystalline film 3〇6 and the oxygen cut film_. Next, the shape of the residual film layer 307 is oxidized by the gate. Forming a gate oxide film, as shown in Fig. 1(), by thermal decomposition of (SiH4) by a single stone.
Deposition，化學氣相沉積）法堆積多晶石夕膜3〇9。 接著’在多晶㈣309上之定義_導體層4aa、4ab、4ba、 322818 22 201143071 4bb之區域上形成氧化矽膜（Si〇2膜）31〇。接著，以§1〇2膜 310或阻劑（resist)膜為遮罩（mask)將閘極導體層4aa、 4ab、4ba、4bb以外之多晶矽膜3〇9予以蝕刻去除，且如 第11圖所示’形成閘極導體層4aa、4ab、4ba、4bb。之 後’將Si〇2膜310去除，並將閘極導體層4aa、4ab、4ba、 4bb之多晶石夕氧化’而形成絕緣膜17aa、17ab、17ba、17bb。 接著’藉由離子注入法等將磷等注入於p型矽層3〇1， 形成第3半導體層N層5aa、5ab、5ba、5bb。再者，藉由 離子注入法將硼等注入於第3半導體層N層5aa、5ab、5ba、 5bb，如第12圖所示，形成第4半導體層P+層6aa、6ab、 6ba、6bb。之後’將氮化矽膜302剝離。接著，堆積氧化 石夕或氮化矽，並藉由平坦化及回蝕而形成氧化矽膜311a。 將露出之半導體層予以氧化而形成氧化矽膜312,並藉由 注入硼等，如第13圖所示，形成第5半導體層P+層8a、 8b。之後，如第14圖所示，將氧化矽膜312剝離，將氧化 矽膜311a蝕刻去除至導體電極7ab、7ba與閘極導體層 4ab、4ba重疊之部分的深度而形成氧化矽膜311b。接著， 將閘極導體層4aa、4ab、4ba、4bb之多晶石夕予以氧化。之 後’藉由真空蒸鍍、濺鍍等將金屬膜形成於基板全面，並 藉由將金屬膜予以圖案化，即可如第15圖所示，形成將導 體電極 7aa、7ab、7ba、7bb 與導體電極 7aa、7ab、7ba、 7bb彼此連接之配線導體層i3a至13c。 藉由此種步驟，可獲得第4實施形態之固體攝像裝置 100c之像素構造。 23 322818 201143071 (第5實施形態） 參照第16A圖說明本發明第5實施形態之固體攝像裝 置100d。本圖係為將第1 a圖所示像素1 〇之一部分予以放 大者。 在從第5半導體層p+層8朝向第i半導體層訂層i 之方向，以導體電極7a、7b之電極上端20a、20b、第4 半導體層P+層6a、6b之P+層上端19a、19b、第3半導體 層N層5a、5b之N層上端i8a、i8b的順序從第5半導體 層P+層8離開而形成。 位於導體電極7a、7b之電極上端20a、20b與第4半 導體層P層6a、6b之P+層上端19a、19b之間之第2半導 體層P層2之表面區域21a、21b之電位，係由施加於導體 電極7a、7b之電壓所控制。藉此，第4半導體層p+層6a、 6b之電位，即不易受到在攝像動作期間電壓變化之來自第 5半導體層P+層8之電壓的影響。因此，藉由施加於導體 電極7a、7b之電壓，可穩定地設定第4半導體層p+層、 6b之電位。 再者，由於第3半導體層N層5a、5biN層上端18a、 18b係較第4半導體層p+層6a、6b之p+層上端19a、19b 更遠離第2半導體層p層2之上面而設，因此第4半導體 層P層6a、6b與第2半導體層p層2相接之面積增加。 因此，電洞30從第2半導體層p層2穩定地供給至第4半 導體層P+層6a、6b。在本實施形態中，由於蓄積於光二極 體之信號電荷為電子，因此供給屬於該電子之相反極性之 322818 24 201143071 電荷的電洞。藉此，可穩定地防止暗電流的產生。 此外，如第16B圖所示’第4半導體層？+層h 之P+層上端19a、19b與第3半導體層^ 5a、5b<N芦 上端18a、18b之位置亦可為一致。在此種構成中由於; 洞亦從第2半導體層？層2供給至第4半導體層6心 6b ’因此可防止暗電流的產生。 曰 (第6實施形態） 第ΠΑ圖至第17C圖係顯示用以說明本發明第6實施 形態之固體攝像裝置100e之像素1〇之構造。另外，對= 與第1實施形態之固體攝像裝置1〇〇相同之部分係賦予相 如第17A圖所示，在信號讀取動作期間中，未蓄積作 號電荷於光二極體H2時，光二極體112之空乏層係佔^ 了第2半導體層p層2中形成有光二極體112之上部區域。 此種光二極體112之空乏層9c之狀態，係可藉由適當調整 第3半導體層n層5a、5b及第2半導體層P層2之層厚、 雜質》農度等，並進一步適當設定施加於光二極體112上之 導體電極7a、7b之電壓而形成。 空乏層9c佔有第2半導體層P層2之上部區域時，並 未形成用以使電流流通於放大用接合電晶體之第5半導體 層P+層8與第！半導體層N+層1附近之第2半導體層p 層2之間的通道。 當信號電荷蓄積於光二極體112時，於信號讀取動作 期間中’如第17B圖所示’光二極體112之空乏層9a、％ 322818 25 201143071 =度減少，且在第2半導體層Μ 2形成放大用接 之通道’岐與蓄積信號電荷對應之電流流通於此通道阳 第17C圖係記入有在信號電荷蓄積動作期間中， 奸未蓄積於光二極體112日寺之空乏層9c之像素構造5圖，。 在k號電荷蓄積動作期間中，通常係設定成例如第 體層r層1之電壓Vxu=GV、第5半導體層8之 Vylr=〇V、外部電壓 vpg=：〇v 〇 如第17C圖所示，在信號電荷蓄積動作期間中，未蓄 積有信號電荷時，空乏層9e係佔有第2半導體層？層2之 上部區域而形成。當空乏層9c未佔有第2半導體層;層2 時，在沒有空乏層9c之第2半導體層p層2中所產生之信 號電號即擴散’而到達第5半導體層P+層8或第！半導體 層N+層1。由此在第2半導體層卩層2所產生之信號電荷 在作為信號上即成為無效。相對於此，藉由空乏層9c佔有 第2半導體層p層2之上部區域，信號電荷即有效地蓄積 於光二極體U2。尤其在照射光量少的狀態下，可將所產 生之仏號電荷有效地捕捉並予以蓄積於光二極體Η〗。 此外’在#號電荷蓄積動作期間中，未蓄積有信號電 何時，由於放大用接合電晶體之通道為夾止（pinch ， 因此即使由於例如跳入於像素選擇線之跳入雜訊，而使電 洞欲從第5半導體層P+層8注入於第2半導體層P層2， 亦可藉由空乏層9而防止此種電洞注入。 如此’在信號讀取動作期間及信號電荷蓄積動作期間 t ’藉由在信號電荷未蓄積於光二極體112時形成為光二 26 322818 201143071 極體U2之空乏層％佔有第2半導體層^ 域，可提供-種具有良好低照度特性之固體攝像裝置㈣ 在上述第1至第6實施形態中，雖已說明了第 體層為N+層之情形，惟在藉由將第i半導 ，且將第2半導體層第3半導體層設^芦層、’ 先二極體表面之第4半導體層設為_、第: 層而使半導體層之極性相反之固體攝像裝置中亦= 付相同的作用效果。此時，由於電洞係作為信號電荷蓄ς 於光二極體，因此導體電極之電壓Vpg係設定成在 體層之表面蓄積電子。 千導 此外，在上述第卜第2、第4至第6實施形態中雖 已說明了與第1半導體層^ 1相連之配線及 體層P+層8相連之配線之方向為正交之情形，惟 =層N+層1作為重設動作中之信號電荷去除用沒極 時，則不需要正交。 寻用 在上述第1 S第6實施形態中，雖係使用j個 ^個像素作了說明，惟像素亦可配置複數個成1維或2、1 此外’上述第1至第6實施形態之像素配置 ，素配置中雖可為直線狀、交錯狀等，而在2維像素配置 中雖可為直線格子狀、蜂巢（h_y_b)狀等限 該等形狀。 錢疋於 在本發明之固體攝像裝置中，雖為至少二極 半導體層P+層6a、6b、與第5半導體層P+層8形成於島 322818 27 201143071 狀形狀内，惟該島狀半導體亦可為圓柱、6角形、或其他 形狀。 、 在上述第2至第4實施形態中，雖有區別使用於導體 電極7aa、7ab、7ba、7bb、導體層⑶至❿、埋入導體 層15a至15c、16至16c之材料，惟使用相同材料當然亦 可獲得相同效果。 此外’在上述第1至第6實施形態中，雖已說明了因 光照射而在像素㈣生信號電荷之㈣攝像裝置，惟本發 明當然亦可適用於藉由可視光、紫外線、紅外線、X光7 放射線、電子束等電磁能量波之照射而在像素產生信號電 荷者。 此外，在上述第1至第6實施形態中，重設M〇s電晶 體111雖係以第2半導體層P層2作為通道，惟亦可例如 藉由以離子注入等將雜質注入於第2半導體層之 成通道。 此外’第1半導體層N+層i可在基板上，於像素間連 續形成，亦可依每-像素形成。依每一像素形成第工半導 ㈣N+層1時’第1半導體層1係可彼此藉由其他金 屬配線而連接。此外1 1半導體層N+層i盘第2半導體 層p層2不需全面接觸（接合），亦可為一部分接觸。再者， ^可將第1半導體層N+層1之—部分置換為其他半導體層 等。 此外’在上述第工至第6實施形態中，雖已說明了重 没mos電晶體m之閘極導體層4a、扑及導體電極h、 322818 28 201143071 ’ ._為一金屬 =，r::期間及重設_ 淮八要可將電洞從第2半 畜積於第4半_〇^__\=並 此外，在上述第】至第6實施形態中，雖= 從第5半導體層P、8朝向第導體 ？ 了在 :第4半導體層P、6a，之P+層上端此、二 電極7a，之電極上端2〇a、施之位置對齊之情形彳 層上端⑽、19b較電極上端2〇a、20b更遠離第5半 體層P+層8之情形。惟只要第4半導體層 第5半導體層P+層8係由第2半導體層？層2所隔開^則 電洞即從第2半導體層？層2供給至第4半導體層^ 6a、6b，因此電極上端2〇a、2Gb亦可較p+層上端 更遠離第5半導體層p+層8。 本發明並不限定於上述實施形態，亦可進行各種修正 及應用，元件構造僅係為一例，亦可予以適當變更。 【圖式簡單說明】 第1A圖係為本發明第丨實施形態之固體攝像裝置之像 素構造圖。 第1B圖係為第1實施形態之變形例之固體攝像裝置之 像素構造圖。 & 322818 29 201143071 第2圖係為第1實施形態之固體攝像裝置之電路構成 圖之一例。 僻双 第3A圖係為用以說明第1實施形態之固體攝像裝置之 電位分布圖。 第3β圖係為用以說明第1實施形態之固體攝像裝置之 像素構造圖。 第3C圖係為用以說明第1實施形態之固體攝像裝置之 像素構造圖。 第3D圖係為用以說明第1實施形態之固體攝像裝置之 電位分布圖。 第4圖係為用以說明本發明第2實施形態之固體攝像 裝置之像素構造圖。 第5圖係為用以說明本發明第3實施形態之固體攝像 裝置之像素構造圖。 第6圖係為用以說明本發明第4實施形態之固體攝像 裝置之像素構造之一部分之放大圖。 第7圖係為用以說明第4實施形態之固體攝像裝置之 製造方法之圖。 第8圖係為用以說明第4實施形態之固體攝像裝置之 製造方法之圖。 第9圖係為用以說明第4實施形態之固體攝像裝置之 製造方法之圖。 第10圖係為用以說明第4實施形態之固體攝像裝置之 製造方法之圖。 30 322818 201143071 第11圖係為用以說明第4實施形態之固體攝像裝置之 製造方法之圖。 第12圖係為用以說明第4實施形態之固體攝像裝置之 製造方法之圖。 第13圖係為用以說明第4實施形態之固體攝像裝置之 製造方法之圖。 第14圖係為用以說明第4實施形態之固體攝像裝置之 製造方法之圖。 第15圖係為用以說明第4實施形態之固體攝像裝置之 製造方法之圖。 第16A圖係為本發明第5實施形態之固體攝像裝置之 像素構造之一部分之放大圖。 第16B圖係為第5實施形態之固體攝像裝置之像素構 造之一部分之放大圖。 第17A圖係為用以說明本發明之第6實施形態之固體 攝像裝置之像素構造圖。 第17B圖係為用以說明第6實施形態之固體攝像裝置 之像素構造圖。 第17C圖係為用以說明第6實施形態之固體攝像裝置 之像素構造圖。 第18A圖係為用以說明習知例之固體攝像裝置之像素 構造圖。 第18B圖係為用以說明習知例之固體攝像裝置之電位 分布圖。 31 322818 201143071 【主要元件符號說明】 1、 la、lb 2、 2a、2b 3a、3b、3aa、3ab、3ba 4a、4b、4aa、4ab、4ba 5a、5b、5aa、5ab、5ba 6a 、 6b 、 6aa 、 6ab 、 6ba 7a、7b、7aa、7ab、7ba 8、 8a、8b 9、 9a 至 9c 10、 10a 至 lOf 1 la 至 1 lc 12a ' 69a 12b 、 69b 12c 13a 至 13c 14 第1半導體層N+層 第2半導體層P層 、3bb、63a、63b 絕緣膜（Si〇2膜） 、4bb、64a、64b閘極導體層 、5bb第3半導體層N層 、6bb第4半導體層P+層 、7bb導體電極 第5半導體層P+層 空乏層 像素 像素間隙 反射光（光） 洩漏光（光） 入射光 配線導體層 泡漏至像素間隙之洩漏光 15a至15c、16a至16c埋入導體層 17aa、17ab、17ba、17bb 絕緣膜 18a、18b N層上端 19a、19b P+層上端 20a、20b 21a、21b 電極上端 第2半導體層p層2之表面區域 電洞 322818 32 30 201143071 50 信號電荷 51 信號電荷蓄積部之電位阱 52 照射光（光） 53 P型半導體基板 54a 、 54b 氧化矽膜（Si〇2膜） 55 傳送閘極電極下通道 56 放大M0S電晶體 57 選擇閘極M0S電晶體 58 重設M0S電晶體 59 信號線 60 島狀半導體（像素） 61 信號線N+層 62 P型半導體層 65a 、 65b N型半導體層 66 P+層 67a 、 67b 像素選擇線 68a 、 68b 絕緣層 100 、 100a 至 lOOe 固體攝像裝置 111 重設M0S電晶體（場效電晶體） 112 光二極體 201 垂直掃描電路 202 平掃描電路 203 重設電路 204 相關雙重取樣（CDS)輸出電路 33 322818 201143071 301 P型矽層 302 氮化矽膜 303、310、311a、 311b、312氧化矽膜（Si〇2膜） 304a 、 304b 島狀半導體層 305 氧化矽膜 306 、 309 多晶矽膜 307 氧化矽膜層 308 閘極氧化膜 RSL 重設線 SW1 、 SW2 切換開關 Trl 、 Tr2 信號線MOS電晶體 XL、YL 配線 XL1 、 XL2 信號線 YL1 、 YL2 像素選擇線 34 322818Deposition, chemical vapor deposition) method for depositing polycrystalline lithotripsy 3〇9. Then, a yttrium oxide film (Si 〇 2 film) 31 形成 is formed on the region of the definition of the polycrystalline (tetra) 309 - the conductor layers 4aa, 4ab, 4ba, 322818 22 201143071 4bb. Next, the polysilicon film 3〇9 other than the gate conductor layers 4aa, 4ab, 4ba, and 4bb is etched and removed by using a §1〇2 film 310 or a resist film as a mask, and as shown in FIG. The gate conductor layers 4aa, 4ab, 4ba, 4bb are formed as shown. Thereafter, the Si〇2 film 310 is removed, and the polysilicon of the gate conductor layers 4aa, 4ab, 4ba, and 4bb is oxidized to form insulating films 17aa, 17ab, 17ba, and 17bb. Then, phosphorus or the like is implanted into the p-type germanium layer 3〇1 by an ion implantation method or the like to form third semiconductor layer N layers 5aa, 5ab, 5ba, and 5bb. Further, boron or the like is implanted into the third semiconductor layer N layers 5aa, 5ab, 5ba, and 5bb by ion implantation, and as shown in Fig. 12, the fourth semiconductor layer P+ layers 6aa, 6ab, 6ba, and 6bb are formed. Thereafter, the tantalum nitride film 302 is peeled off. Next, oxide oxide or tantalum nitride is deposited, and the tantalum oxide film 311a is formed by planarization and etch back. The exposed semiconductor layer is oxidized to form a hafnium oxide film 312, and boron or the like is implanted, and as shown in Fig. 13, the fifth semiconductor layer P+ layers 8a and 8b are formed. Thereafter, as shown in Fig. 14, the ruthenium oxide film 311 is peeled off, and the ruthenium oxide film 311a is removed by etching to a depth at a portion where the conductor electrodes 7ab and 7ba overlap with the gate conductor layers 4ab and 4ba to form a ruthenium oxide film 311b. Next, the polycrystals of the gate conductor layers 4aa, 4ab, 4ba, and 4bb are oxidized. Then, the metal film is formed on the entire surface of the substrate by vacuum evaporation, sputtering, or the like, and by patterning the metal film, as shown in FIG. 15, the conductor electrodes 7aa, 7ab, 7ba, and 7bb are formed. The wiring conductor layers i3a to 13c to which the conductor electrodes 7aa, 7ab, 7ba, and 7bb are connected to each other. By such a procedure, the pixel structure of the solid-state imaging device 100c of the fourth embodiment can be obtained. 23 322818 201143071 (Fifth Embodiment) A solid-state imaging device 100d according to a fifth embodiment of the present invention will be described with reference to Fig. 16A. This figure is to enlarge one of the pixels 1 所示 shown in Figure 1 a. In the direction from the fifth semiconductor layer p+ layer 8 toward the i-th semiconductor layer layer i, the electrode upper ends 20a and 20b of the conductor electrodes 7a and 7b, the P+ layer upper ends 19a and 19b of the fourth semiconductor layer P+ layers 6a and 6b, The order of the upper ends i8a and i8b of the N layers of the third semiconductor layer N layers 5a and 5b is formed by leaving the fifth semiconductor layer P+ layer 8. The potentials of the surface regions 21a and 21b of the second semiconductor layer P layer 2 between the electrode upper ends 20a and 20b of the conductor electrodes 7a and 7b and the P+ layer upper ends 19a and 19b of the fourth semiconductor layer P layers 6a and 6b are The voltage applied to the conductor electrodes 7a, 7b is controlled. Thereby, the potential of the fourth semiconductor layer p+ layers 6a and 6b is less likely to be affected by the voltage from the fifth semiconductor layer P+ layer 8 during the imaging operation. Therefore, the potentials of the fourth semiconductor layers p+ and 6b can be stably set by the voltages applied to the conductor electrodes 7a and 7b. Further, since the third semiconductor layer N layers 5a and 5biN layer upper ends 18a and 18b are located farther from the upper surface of the second semiconductor layer p layer 2 than the p+ layer upper ends 19a and 19b of the fourth semiconductor layer p+ layers 6a and 6b, Therefore, the area where the fourth semiconductor layer P layers 6a and 6b are in contact with the second semiconductor layer p layer 2 increases. Therefore, the hole 30 is stably supplied from the second semiconductor layer p layer 2 to the fourth semiconductor layer P+ layers 6a and 6b. In the present embodiment, since the signal charge accumulated in the photodiode is an electron, a hole belonging to the opposite polarity of the electron 322818 24 201143071 is supplied. Thereby, the generation of dark current can be stably prevented. Further, as shown in Fig. 16B, the 'fourth semiconductor layer? The positions of the P+ layer upper ends 19a and 19b of the layer h and the third semiconductor layers 5a and 5b<N reed upper ends 18a and 18b may also coincide. In this configuration, the hole is also from the second semiconductor layer? The layer 2 is supplied to the core 6b of the fourth semiconductor layer 6 so that generation of dark current can be prevented. (Embodiment 6) FIG. 17 to FIG. 17C are views showing a structure of a pixel 1A of the solid-state imaging device 100e according to the sixth embodiment of the present invention. In addition, the same portion as the solid-state imaging device 1A of the first embodiment is provided as shown in Fig. 17A, and when the signal charge is not accumulated in the photodiode H2 during the signal reading operation period, the light is The vacant layer of the polar body 112 occupies the upper portion of the second semiconductor layer p layer 2 where the photodiode 112 is formed. The state of the depletion layer 9c of the photodiode 112 can be appropriately adjusted by appropriately adjusting the layer thickness of the third semiconductor layer n layers 5a and 5b and the second semiconductor layer P layer 2, the impurity degree, and the like. The voltage applied to the conductor electrodes 7a and 7b on the photodiode 112 is formed. When the depletion layer 9c occupies the upper portion of the second semiconductor layer P layer 2, the fifth semiconductor layer P+ layer 8 for causing a current to flow through the amplifying bonding transistor is not formed! A channel between the second semiconductor layer p layer 2 in the vicinity of the semiconductor layer N+ layer 1. When the signal charge is accumulated in the photodiode 112, during the signal reading operation, as shown in FIG. 17B, the depletion layer 9a, % 322818 25 201143071 of the photodiode 112 is reduced in degree, and in the second semiconductor layer. 2, the channel for amplifying the connection is formed, and the current corresponding to the accumulated signal charge flows through the channel. The 17C picture is recorded during the signal charge accumulation operation, and the vacant layer 9c of the temple is not accumulated in the photodiode 112. Pixel construction 5 diagram. In the k-charge accumulation operation period, for example, the voltage Vxu=GV of the first layer r layer 1 , Vylr=〇V of the fifth semiconductor layer 8, and the external voltage vpg=:〇v are generally set as shown in FIG. 17C. When the signal charge is not accumulated during the signal charge accumulation operation period, the depletion layer 9e occupies the second semiconductor layer. Formed in the upper region of layer 2. When the depletion layer 9c does not occupy the second semiconductor layer or the layer 2, the signal electric number generated in the second semiconductor layer p layer 2 without the depletion layer 9c is diffused and reaches the fifth semiconductor layer P+ layer 8 or the first! Semiconductor layer N+ layer 1. As a result, the signal charge generated in the second semiconductor layer germanium layer 2 is ineffective as a signal. On the other hand, the depletion layer 9c occupies the upper region of the p layer 2 of the second semiconductor layer, and the signal charge is efficiently accumulated in the photodiode U2. In particular, in the state where the amount of irradiation light is small, the generated nickname charge can be efficiently captured and accumulated in the photodiode. In addition, during the period of the charge accumulation operation of ##, when the signal is not accumulated, since the channel for amplifying the bonded transistor is pinched (pinch, even if, for example, jumping into the pixel selection line jumps into the noise, The hole is to be implanted into the second semiconductor layer P layer 2 from the fifth semiconductor layer P+ layer 8, and such hole injection can be prevented by the depletion layer 9. Thus, during the signal reading operation and during the signal charge accumulation operation t' is formed as a light when the signal charge is not accumulated in the photodiode 112. 26 322818 201143071 The dilute layer % of the polar body U2 occupies the second semiconductor layer, and a solid-state imaging device having good low illumination characteristics can be provided (4) In the above-described first to sixth embodiments, the case where the first layer is the N+ layer has been described, but by the ith semiconductor, the third semiconductor layer is provided with the third semiconductor layer, The fourth semiconductor layer on the surface of the diode is set to _, the first layer, and the solid-state imaging device having the opposite polarity of the semiconductor layer also has the same effect. In this case, the hole is stored as a signal charge in the light. Polar body The voltage Vpg of the electrode is set to accumulate electrons on the surface of the bulk layer. Further, in the above-described second, fourth, and sixth embodiments, the wiring and the bulk layer P+ connected to the first semiconductor layer 1 have been described. In the case where the direction in which the layers 8 are connected is orthogonal, if the layer N+ layer 1 is used as the signal charge removal in the reset operation, no orthogonality is required. The first embodiment is applied to the first S sixth embodiment. Although the description has been made using j pixels, the pixels may be arranged in a plurality of dimensions in one or two, and the pixel arrangement in the first to sixth embodiments may be linear. In a two-dimensional pixel arrangement, the shape may be a linear lattice shape or a honeycomb (h_y_b) shape, etc. In the solid-state imaging device of the present invention, at least a two-pole semiconductor layer P+ is used. The layers 6a and 6b and the fifth semiconductor layer P+ layer 8 are formed in the shape of the island 322818 27 201143071, but the island-shaped semiconductor may have a columnar shape, a hexagonal shape, or another shape. In the second to fourth embodiments described above In the case, there are differences in the use of the conductor electrodes 7aa, 7ab, 7ba, 7bb, the conductor layer (3) to the germanium, and the materials embedded in the conductor layers 15a to 15c, 16 to 16c, but the same effect can be obtained by using the same material. Further, in the first to sixth embodiments described above, a (four) imaging device that generates a signal charge in a pixel (four) due to light irradiation, but the present invention can of course be applied to generating a signal in a pixel by irradiation of electromagnetic energy waves such as visible light, ultraviolet light, infrared light, X-ray 7 radiation, electron beam, or the like. In the above-described first to sixth embodiments, the M 〇s transistor 111 is reset by using the second semiconductor layer P layer 2 as a channel, but may be implanted by ion implantation or the like, for example. A channel formed in the second semiconductor layer. Further, the first semiconductor layer N+ layer i may be formed on the substrate continuously between the pixels, or may be formed per pixel. When the semiconductor semiconductor is formed for each pixel (4) N+ layer 1, the first semiconductor layer 1 can be connected to each other by other metal wiring. Further, the semiconductor layer N+ layer i-disk second semiconductor layer p-layer 2 does not need to be in full contact (joining), and may be partially contacted. Further, the portion of the first semiconductor layer N+ layer 1 may be replaced with another semiconductor layer or the like. Further, in the above-described sixth to sixth embodiments, the gate conductor layer 4a of the MOS transistor m and the conductor electrode h, 322818 28 201143071 '. have been described as a metal =, r:: In the above-mentioned ninth to sixth embodiments, the hole is removed from the fifth semiconductor layer P. , 8 toward the first conductor? In the fourth semiconductor layer P, 6a, the upper end of the P+ layer, the second electrode 7a, the upper end of the electrode 2〇a, the position of the application is aligned. The upper ends (10) and 19b of the layer are farther from the upper ends 2〇a, 20b of the electrode. The case of the fifth half-layer P+ layer 8. However, as long as the fourth semiconductor layer, the fifth semiconductor layer P+ layer 8 is composed of the second semiconductor layer? The layer 2 is separated by ^, then the hole is from the second semiconductor layer? The layer 2 is supplied to the fourth semiconductor layers 6a, 6b, so that the upper ends 2a, 2Gb of the electrodes may be further away from the fifth semiconductor layer p+ layer 8 than the upper end of the p+ layer. The present invention is not limited to the above embodiment, and various modifications and applications can be made. The device structure is merely an example and can be appropriately changed. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a diagram showing a pixel structure of a solid-state imaging device according to a third embodiment of the present invention. Fig. 1B is a view showing a pixel structure of a solid-state imaging device according to a modification of the first embodiment. < 322818 29 201143071 Fig. 2 is an example of a circuit configuration diagram of the solid-state imaging device according to the first embodiment. Fig. 3A is a potential distribution diagram for explaining the solid-state imaging device according to the first embodiment. The 3rd figure is a pixel structure diagram for explaining the solid-state imaging device of the first embodiment. Fig. 3C is a view showing a pixel structure of the solid-state imaging device according to the first embodiment. Fig. 3D is a potential distribution diagram for explaining the solid-state imaging device according to the first embodiment. Fig. 4 is a view showing a pixel structure of a solid-state imaging device according to a second embodiment of the present invention. Fig. 5 is a view showing a pixel structure of a solid-state imaging device according to a third embodiment of the present invention. Fig. 6 is an enlarged view of a part of a pixel structure of a solid-state imaging device according to a fourth embodiment of the present invention. Fig. 7 is a view for explaining a method of manufacturing the solid-state imaging device according to the fourth embodiment. Fig. 8 is a view for explaining a method of manufacturing the solid-state imaging device according to the fourth embodiment. Fig. 9 is a view for explaining a method of manufacturing the solid-state imaging device according to the fourth embodiment. Fig. 10 is a view for explaining a method of manufacturing the solid-state imaging device according to the fourth embodiment. 30 322818 201143071 Fig. 11 is a view for explaining a method of manufacturing the solid-state imaging device according to the fourth embodiment. Fig. 12 is a view for explaining a method of manufacturing the solid-state imaging device according to the fourth embodiment. Figure 13 is a view for explaining a method of manufacturing the solid-state imaging device according to the fourth embodiment. Fig. 14 is a view for explaining a method of manufacturing the solid-state imaging device according to the fourth embodiment. Fig. 15 is a view for explaining a method of manufacturing the solid-state imaging device according to the fourth embodiment. Fig. 16A is an enlarged view of a part of a pixel structure of a solid-state imaging device according to a fifth embodiment of the present invention. Fig. 16B is an enlarged view showing a part of the pixel structure of the solid-state imaging device of the fifth embodiment. Fig. 17A is a view showing a pixel structure of a solid-state imaging device according to a sixth embodiment of the present invention. Fig. 17B is a view showing a pixel structure of the solid-state imaging device according to the sixth embodiment. Fig. 17C is a view showing a pixel structure of the solid-state imaging device according to the sixth embodiment. Fig. 18A is a view showing a pixel configuration of a solid-state imaging device of a conventional example. Fig. 18B is a diagram showing the potential distribution of the solid-state imaging device of the conventional example. 31 322818 201143071 [Description of main components] 1. la, lb 2, 2a, 2b 3a, 3b, 3aa, 3ab, 3ba 4a, 4b, 4aa, 4ab, 4ba 5a, 5b, 5aa, 5ab, 5ba 6a, 6b, 6aa , 6ab , 6ba 7a , 7b , 7aa , 7ab , 7ba 8 , 8a , 8b 9 , 9a to 9c 10 , 10a to 10f 1 la to 1 lc 12a ' 69a 12b , 69b 12c 13a to 13c 14 1st semiconductor layer N+ Layer second semiconductor layer P layer, 3bb, 63a, 63b insulating film (Si〇2 film), 4bb, 64a, 64b gate conductor layer, 5bb third semiconductor layer N layer, 6bb fourth semiconductor layer P+ layer, 7bb conductor Electrode fifth semiconductor layer P+ layer depletion layer pixel pixel gap reflected light (light) leakage light (light) incident light wiring conductor layer leakage leakage light 15a to 15c, 16a to 16c buried in the conductor layer 17aa, 17ab, 17ba, 17bb insulating film 18a, 18b N layer upper end 19a, 19b P+ layer upper end 20a, 20b 21a, 21b electrode upper end second semiconductor layer p layer 2 surface area hole 322818 32 30 201143071 50 signal charge 51 signal charge accumulation portion Potential well 52 illuminating light (light) 53 P-type semiconductor substrate 54a, 54b yttrium oxide Membrane (Si〇2 film) 55 Transmitting gate electrode lower channel 56 Amplifying M0S transistor 57 Selecting gate M0S transistor 58 Resetting M0S transistor 59 Signal line 60 Island semiconductor (pixel) 61 Signal line N+ layer 62 P type Semiconductor layer 65a, 65b N-type semiconductor layer 66 P+ layer 67a, 67b pixel selection line 68a, 68b insulating layer 100, 100a to 100e solid-state imaging device 111 reset MOS transistor (field effect transistor) 112 light diode 201 vertical scanning Circuit 202 Flat Scan Circuit 203 Reset Circuit 204 Correlated Double Sampling (CDS) Output Circuit 33 322818 201143071 301 P-type germanium layer 302 tantalum nitride film 303, 310, 311a, 311b, 312 yttrium oxide film (Si 〇 2 film) 304a 304b island-shaped semiconductor layer 305 yttrium oxide film 306, 309 polysilicon film 307 yttrium oxide film layer 308 gate oxide film RSL reset line SW1, SW2 switch Tr1, Tr2 signal line MOS transistor XL, YL wiring XL1, XL2 signal Line YL1, YL2 pixel selection line 34 322818