CN103384916A - Solid-state image pickup apparatus - Google Patents

Abstract

The present invention provides a solid-state imaging device in which a plurality of pixels are arranged two-dimensionally in a pixel region. The pixels are formed in island-shaped semiconductors. In this island ^- shaped semiconductor, an N region ( 4), P ⁺ area (5). On the P region (3), a P ⁺ region (6) is formed. By setting the P ⁺ area (5) and P ⁺ area (6) to a low level voltage, and setting the signal line N ⁺ area (2) to a higher level voltage with a lower level voltage, the storage in The signal charges in the N region (4) are removed in the signal line N ⁺ region (2) via the P region (3).

Description

Solid-state imaging device

technical field

The present invention relates to a solid-state imaging device, and more particularly, to a solid-state imaging device that achieves higher pixel density, lower power consumption, and lower light leakage.

Background technique

At present, solid-state imaging devices have been widely used in video cameras, still cameras, etc. Solid-state imaging devices have been required to improve performance such as higher pixel density, higher resolution, lower color mixing in color imaging, and higher sensitivity. In view of this point, in order to achieve high resolution of solid-state imaging devices, technical innovations such as high pixel density have been carried out.

9A and 9B show a conventional solid-state imaging device.

9A is a cross-sectional view showing a conventional solid-state imaging device in which one pixel is formed by one island-shaped semiconductor (see, for example, Patent Document 1). As shown in FIG. 9A, in the island-shaped semiconductor 100 constituting this pixel, a signal line N ⁺ region 102 is formed on a substrate 101 (hereinafter, the "N ⁺ region" is referred to as a semiconductor region containing many donor (donar) impurities. ). A P region 103 is formed on the signal line N ⁺ region 102 (hereinafter, a semiconductor region containing acceptor (acceptor) impurities is referred to as a “P region”), and an insulating layer 104 is formed on the outer periphery of the P region 103 , A gate conductor layer 105 is formed through the insulating layer 104 . On the outer peripheral portion of the P region 103 above the gate conductor layer 105 , an N region (hereinafter, a semiconductor region containing donor impurities is referred to as “N region”) 106 is formed. On the N region 106 and the P region 103 , a P ⁺ region (hereinafter, a semiconductor region containing many acceptor impurities is referred to as a “P ⁺ region”) 107 is formed. The P ⁺ region 107 is connected to the pixel selection line conductor layer 108 . The insulating layers 104 described above are connected to each other while surrounding the outer peripheral portion of the island-shaped semiconductor 100 . Like the insulating layer 104 , the gate conductor layer 105 is also connected to each other while surrounding the outer peripheral portion of the island-shaped semiconductor 100 .

In this solid-state imaging device, a photodiode (photo diode) region is formed by a P region 103 and an N region 106 in the island-shaped semiconductor 100 . Here, when light enters from the side of the P ⁺ region 107 on the island-shaped semiconductor 100 , signal charges (free electrons in this case) are generated in the photoelectric conversion region of the photodiode region. Furthermore, the signal charge is mainly stored in the N region 106 of the photodiode region.

In addition, in the island-shaped semiconductor 100, a junction field effect transistor having the N region 106 as a gate, the P ⁺ region 107 as a source, and the P region 103 near the signal line N ⁺ region 102 as a drain is formed. . Furthermore, in this solid-state imaging device, the drain-source current (output signal) of the junction field effect transistor changes in accordance with the amount of signal charge stored in the N region 106, and is transmitted from the signal line N ⁺ region 102 Take out as a signal output.

Furthermore, in the island-shaped semiconductor 100, there are formed the N region 106 of the photodiode region as the source, the gate conductor layer 105 as the reset gate (reset gate), and the signal line N ⁺ region 102 as the drain. , a reset MOS (Metal-Oxide Semiconductor, Metal-Oxide Semiconductor) transistor using the P region 103 between the N region 106 and the signal line N ⁺ region 102 as a channel (hereinafter the gate conductor layer is referred to as "reset gate polar conductor layer"). Furthermore, in this solid-state imaging device, the signal charge stored in the N region 106 is applied to the reset gate conductor layer 105 of the reset MOS transistor by applying an ON voltage (high level voltage) , while being removed in the signal line N ⁺ region 102.

In addition, the so-called "high-level voltage" here means a higher level of positive voltage when the signal charges are free electrons, and the "low-level voltage" used below in this specification refers to The "high level voltage" is a low voltage. On the other hand, when the signal charge is a hole, the "high level voltage" refers to a lower level of negative voltage, and the "low level voltage" refers to a voltage closer to 0V than the "high level voltage".

The imaging operation of this solid-state imaging device is composed of the following operations: in the state where a ground voltage (=0V) is applied to the signal line N ⁺ region 102, and the gate conductor layer 105 and the P ⁺ region 107 are reset, A signal charge storage operation that stores signal charges generated in the photoelectric conversion region (photodiode region) in the N region 106 due to incident light from the upper surface of the island-shaped semiconductor 100; when the ground voltage is applied to the signal line N ⁺ region 102 and the heavy When the gate conductor layer 105 is set and a positive voltage is applied to the P ⁺ region 107, the source-drain current of the junction field effect transistor modulated by the potential of the N region 106 that changes according to the amount of stored signal charge A signal charge reading operation as a signal current is read; and after the signal charge reading operation, a ground voltage is applied to the P ⁺ region 107 and a positive voltage is applied to the reset gate conductor layer 105 and the signal line N ⁺ region 102 In the reset state, the signal charges stored in the N region 106 are removed in the signal line N ⁺ region 102 .

FIG. 9B is a conventional example showing a pixel region in which island-shaped semiconductors P11 to P33 (corresponding to the island-shaped semiconductor 100 in FIG. 9A ) constituting a pixel are arranged in a two-dimensional shape, and a drive-output circuit around the pixel region. A schematic plan view of a solid-state imaging device. Here, a cross-sectional structure along line FF' in FIG. 9B is shown in FIG. 9A . Island-shaped semiconductors P11 to P33 constituting pixels are formed on signal line N ⁺ regions 102 a , 102 b , and 102 c (corresponding to signal line N ⁺ region 102 in FIG. 9A ). Pixel selection line conductor layers 108a, 108b, 108c (corresponding to pixel selection line conductor layer 108 in FIG. , and connected to the pixel selection line vertical scanning circuit 110 arranged around the pixel area. Similarly, reset gate conductor layers 105 a , 105 b , and 105 c (corresponding to reset gate conductor layer 105 in FIG. 9A ) are formed on each row extending in the horizontal direction of island-shaped semiconductors P11 to P33 constituting pixels. , are connected to each other, and connected to the reset line vertical scanning circuit 112 provided around the pixel area. The lower part of each signal line N ⁺ region 102a, 102b, 102c is connected to a switch MOS transistor 115a, 115b, 115c, and the gate of each switch MOS transistor 115a, 115b, 115c is connected to a signal line horizontal scanning circuit 116. Furthermore, the drains of the switching MOS transistors 115 a , 115 b , and 115 c are connected to the output circuit 117 . Furthermore, the switching circuits 118a, 118b, and 118c are configured to be connected to the upper parts of the signal line N ⁺ regions 102a, 102b, and 102c, and are applied with a ground voltage (=0V) during the signal charge storage operation, and are applied with the signal charge readout operation. A floating voltage is applied, and a high-level voltage Vr for resetting conduction (reset on) is applied when the signal is removed.

The signal charge storage operation is to apply a ground voltage to the signal line N ⁺ region 102a, 102b, 102c, apply a low-level voltage for reset to the reset gate conductor layer 105a, 105b, 105c, and apply a low-level voltage to the pixel selection line conductor layer. 108a, 108b, 108c are executed with the ground voltage applied.

In addition, the signal charge reading operation is performed by applying a low-level voltage for reset off (reset off) to the reset gate conductor layers 105a, 105b, and 105c, and selecting pixels from which signal charges are read. A high-level voltage is applied to the line conductor layers 108a, 108b, and 108c, and a turn-on voltage is applied to the gates of the switching MOS transistors 115a, 115b, and 115c connected to the signal line N ⁺ regions 102a, 102b, and 102c of the pixel from which the signal voltage is read. (high-level voltage), and in the state where the output terminals of the switch circuits 118a, 118b, and 118c are floating voltages and the input terminal of the output circuit 117 is a low-level voltage, the junction field effect transistor of the read pixel The source-drain current of is taken into the output circuit 117 .

In addition, the signal charge removal operation is performed as follows: when all the pixel selection line conductor layers 108a, 108b, and 108c are at the ground voltage, and all the switching MOS transistors 115a, 115b, and 115c are off, the island-shaped semiconductors P11 to P33 Among them, a high-level voltage for reset conduction is applied to the reset gate conductor layers 105a, 105b, and 105c connected to the pixels from which the stored signal charges are removed, so that the output terminals of the switch circuits 118a, 118b, and 118c become reset. High-level voltage Vr for conduction.

As shown in FIG. 9A, the height of the island-shaped semiconductor 100 is mainly determined by the height Ld of the N layer 106 of the photodiode. Here, light enters from the upper surface of the P ⁺ layer 107 on the island-shaped semiconductor 100 . The signal charge generation rate due to the incident light has a characteristic of decreasing exponentially from the upper surface of the P ⁺ layer 121 with respect to the depth of Si. In a solid-state imaging device that senses visible light, in order to efficiently extract signal charges that contribute to sensitivity, the depth of the photoelectric conversion region needs to be 2.5 to 3 μm (see, for example, Non-Patent Document 1). Therefore, the height Ld of the N layer 106 of the photoelectric conversion photodiode needs to be at least 2.5 to 3 μm. A reset gate conductor layer 105 is formed under the N layer 106 . The reset gate conductor layer 105 is formed in a region close to the bottom of the island-shaped semiconductor 100 because the normal operation of the solid-state imaging device can be performed even if the reset gate conductor layer 105 is, for example, 0.1 μm.

As shown in Figure 9B, since the reset gate conductor layers 105a, 105b, and 105c are formed independently for each row, it is necessary to form the reset gate conductor layer 105a at the bottom of the island-shaped semiconductors P11 to P33 with a height of 2.5 to 3 μm. , 105b, 105c. The formation of the reset gate conductor layers 105a, 105b, and 105c requires more microfabrication as the pixel integration degree is higher, making it difficult to manufacture the solid-state imaging device.

FIG. 10A and FIG. 10B are a schematic diagram of a pixel and an action potential variation diagram of a CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) solid-state imaging device, respectively. FIG. 10A is a schematic diagram of a pixel shown in FIG. 1 of Non-patent Document 2. FIG. One pixel is formed in a region A surrounded by a dotted line in FIG. 10A . Here, an N region 121 forming a photodiode and a P ⁺ region 122 on the N region 121 are formed in the P region 120 . Furthermore, a gate insulating layer 124 is formed on the P region 120 , and a transfer electrode Φt is formed on the gate insulating layer 124 adjacent to the N region 121 . The N ⁺ region 123 is formed on the surface of the P region 120 in a state adjacent to the conversion electrode ΦT. P ⁺ region 122 is fixed at ground potential. A photodiode is formed by a P region 120 and an N region 121 . In this way, the switching MOS transistor M1 is formed with the N region 121 as the source, the N ⁺ region 123 as the drain, and the switching electrode ΦT as the gate. Furthermore, the gate of the amplification MOS transistor M3 and the source of the reset MOS transistor M2 are connected to the N ⁺ region 123 , and the source of the amplification MOS transistor M3 and the drain of the reset MOS transistor M1 are connected to the power voltage line VDD. In addition, the source of the column selection MOS transistor M4 is connected to the drain of the amplification MOS transistor M3 , and the drain is connected to the signal line 125 .

In this pixel, light incident from the P ⁺ region 122 side is photoelectrically converted in the photodiode region to generate signal charges (free electrons in this case). This signal charge is stored in the N region 121 . Afterwards, a turn-on voltage (high level voltage) is applied to the conversion electrode ΦT, and the signal charge stored in the N region 121 is transferred to the N ⁺ region 123 . Through such an operation, the potential of the gate electrode of the amplifier MOS transistor M3 changes according to the amount of signal charge. Next, when a turn-on voltage (high level voltage) is applied to the gate electrode ΦS of the column selection MOS transistor M4, the signal current modulated by the potential of the gate electrode of the amplifying MOS transistor M3 passes through the amplifying MOS transistor M3 and The column selection MOS transistor M4 flows from the power supply voltage line VDD to the signal line 125, and this signal current is read as a pixel signal. Moreover, when a turn-on voltage (high-level voltage) is applied to the gate electrode ΦR of the reset MOS transistor M2, the signal charge existing in the N ⁺ region 123 is removed on the power supply voltage line VDD.

FIG. 10B is a graph showing potential distribution changes of the photodiode N region 121 , the switch MOS transistor M1 , and the reset MOS transistor M2 (for example, refer to FIG. 2 of Non-Patent Document 3). (a) of FIG. 10B is a cross-sectional view showing the photodiode formed by the P region 120 and the N region 121 , the switching MOS transistor M1 region, and the reset MOS transistor M2 region. In addition, there is an N ⁺ region 123 forming a floating diode FD adjacent to the gate electrode Tx of the switch MOS transistor M1 (corresponding to the switch electrode ΦT in FIG. 10A ), and a reset MOS transistor M2 adjacent to the N ⁺ region 123 The reset electrode RST (equivalent to the gate electrode ΦR of the reset MOS transistor in FIG. 10A ), and the reset MOS transistor M2 connected to the power supply voltage line VDD is formed on the surface of the P region 120 adjacent to the reset electrode. N ⁺ region 126 of the drain.

(b) of FIG. 10B shows the potential distribution along the G-G' line of FIG. 10B (a) during the signal charge storage operation. The solid line shows the bottom of the potential of each region, and the oblique line shows charges (in this case, free electrons). In the N region 121 there are stored signal charges 128 , while in the N ⁺ regions 123 , 126 there are a plurality of charges 129 b , 129 b (free electrons at this time). A turn-off voltage (low-level voltage) is applied to the conversion electrode Tx and the reset electrode RST, so that the stored signal charge 128 cannot be transferred from the photodiode N region 121 to the N ⁺ region 123 and the drain N ⁺ region 126 of the reset MOS transistor. .

(c) of FIG. 10 shows the potential distribution when the signal charge 128 stored in the N region 121 of the photodiode is transferred to the N ⁺ region 123 . This transfer is performed by applying a conduction voltage (high-level voltage) to the transfer electrode Tx. The stored signal charges 128 are transferred from the N region 121 to the N ⁺ region 123 through the surface layer of the P region 123 below the transfer electrode Tx. During this transfer, as shown in (c) of FIG. 10B , the signal charge 130 a of the N region 121 increases, and the signal charge 130 c of the N ⁺ region 123 increases. Furthermore, when the signal charges 130a and 130b are exhausted, the signal charge transfer operation ends. When the signal charge 128 is transferred to the N ⁺ region 123, the potential of the gate electrode of the amplifying MOS transistor M3 connected to the N ⁺ region 123 changes, and the signal current flowing through the signal line 125 during the signal charge reading operation changes according to this. It changes according to the amount of potential change, and is read as a signal output.

After the signal charge reading operation, as shown in (d) of FIG. 10B, a turn-on voltage (high level voltage) is applied to the gate electrode RST of the reset MOS transistor M2, and then the floating diode N ⁺ region 123 The signal charge 130c is removed at the N ⁺ region 126 belonging to the drain of the reset MOS transistor M2. When this signal charge removal operation is performed, the potential of the N ⁺ region 123 is reset to be the same potential as the potential 131 of the surface layer of the P region 120 below the reset electrode RST.

As described above, in the solid-state imaging device having the pixel shown in FIG. 10A, the switching MOS transistor M1 and the reset MOS transistor M2 are required in the pixel. Due to the existence of the switching MOS transistor M1 and the reset MOS transistor M2, the pixel integration degree will be reduced.

Hereinafter, a signal charge removing operation in a CCD (Charge Coupled Device, Charge Coupled Device) solid-state imaging device will be described with reference to FIGS. 11A and 11B . FIG. 11A shows a cross-sectional structure of one pixel in a CCD solid-state imaging device (see, for example, FIG. 1 of Non-Patent Document 4). A P-region well 141 is formed on the N-region substrate 140 , and an N-region 142 is formed on the P-region well 141 . A photodiode portion is formed by the P region well 141 and the N region 142 . Furthermore, a P ⁺ region 143 is formed on the N region 142 , and this P ⁺ region 143 is at ground potential (=0 V). In addition, a CCD portion is formed adjacent to the photodiode portion. On the surface of the P region well 141 of the CCD part, a P region 144 and an N region 145 serving as a channel of the CCD part are formed. In the surface layer of the P region well 141 between the channel of the CCD part and the photodiode N region 142, a transfer channel 146 for transferring the signal charge stored in the photodiode part to the N region 145 of the CCD part channel is formed. . An insulating film 147 is formed on the P ⁺ region 143 , the transfer channel 146 , and the N region 145 of the CCD channel. Furthermore, a CCD transfer electrode 148 is formed in the insulating film 147 of the CCD part, and a light-shielding metal layer 149 is formed on the top thereof so as to cover the CCD part. Furthermore, a transparent resin microlens (micro lens) 150 is formed above the photodiode portion and the CCD portion. One pixel is constituted by the photodiode portion and the CCD portion shown in FIG. 1A . The pixels are arranged two-dimensionally across the entire pixel area of the CCD solid-state imaging device. Furthermore, the N-region substrate 140 and the P-region well 141 are continuously formed across the entire pixel region.

The above-mentioned operation of transferring the signal charge stored in the photodiode portion to the CCD portion is performed by applying a predetermined voltage to the CCD transfer electrode 148 . The signal charge removal operation is performed as follows: after the signal charge storage operation, the signal charge stored in the N region 142 is removed from the N region substrate 140 by applying a high level voltage to the N region substrate 140 . In addition, the signal charge storage operation and the signal charge removal operation are performed synchronously in the pixels of the entire pixel area, and the timing of the shutter operation can be changed by changing the signal charge storage time. This shutter action is called an electronic shutter.

FIG. 11B shows the potential distribution when the signal charge is removed along the HH' line of FIG. 11A (please refer to FIG. 14 of the non-patent literature). The P ⁺ region 143 is fixed at the ground potential Vs (=0V). During the signal charge storage operation, a potential distribution 151 a is obtained in which the low-level voltage VRL is applied to the N-region substrate 140 . During this operation, the signal charge 152a generated by the light irradiated from the microlens 150 side (in this figure, the signal charge is represented by "e-" contained in Non-Patent Document 3, which is the same as that in FIG. 10B The signal charges 128 , 130 a , 130 b , and 130 c shown by the oblique lines are the same) are stored in potential wells located in the N region 142 and the P region well 141 . Furthermore, when the signal charge removal operation is performed, the potential distribution 152b in which the high-level voltage VRH is applied to the N-region substrate 140 becomes deeper from the P ⁺ region 143 at the ground potential toward the N-region substrate 140 . Thus, the stored signal charge 152 b is removed to the N-region substrate 140 .

In the above-mentioned signal charge storage operation, since the signal charge generated in the potential well is effective as a signal, and the signal charge generated in the P region well 141 and the N region substrate 140 located below the potential well is removed at the N region. Area substrate 140 is therefore inactive as a signal. The depth Lph of this potential well is 2.5 to 3 μm as described in Non-Patent Document 1 for the required spectral sensitivity characteristics. In addition, in the potential distribution during the signal charge removal operation, it is not desirable to generate a potential barrier when the signal charge 151 is transferred from the P ⁺ region 143 to the N region substrate 140 . Therefore, the applied voltage VRH to the N-region substrate 140 is set to 18 to 30V. This is because the photoelectric conversion region formed by the N region 142 and the P region well 141 overlaps with the signal charge removal region formed by the P region well 141 and the N region substrate 140 . Compared with the solid-state imaging device shown in FIG. 9A and FIG. 10A, the voltage applied to the reset gate conductor layer 105 and the gate electrode ΦR of the reset MOS transistor M2 can be operated at 2 to 3 V when signal charge is removed. , is a very large value. As a result, the power consumption of the CCD solid-state imaging device will increase.

In the solid-state imaging device shown in FIG. 9A and FIG. 10A, which read pixel signals in the X-Y address (address) (dot sequence) method and the row address (line sequence) method, it is impossible to simultaneously perform pixel signals on all pixels in the pixel area. The charge reading operation and the removal operation of the pixel signal charge. Therefore, the above-described signal charge removal operation (electronic shutter operation) in the CCD solid-state imaging device cannot be performed. As described above, in the CMOS solid-state imaging device of FIG. 10A , in order to perform this signal charge removal operation (electronic shutter operation), a special transistor is added (see, for example, Non-Patent Document 5). The addition of such transistors will reduce the pixel integration level.

[Prior Art Literature]

[Patent Document]

Patent Document 1: Japanese International Publication No. 2009/034623

[Non-patent literature]

Non-Patent Document 1: G.Agranov, R.Mauritzson; J.Ladd, A.Dokoutchaev, X.fan, X.Li, Z.Yin, R.Johnson, V.Lenchenkov, S.Nagaraja, W.Gazeley, J. .Bai, H.Lee, Longze Yishun; "Pixel Size Reduction and Characteristic Comparison of CMOS Image Sensors", ITE Technical Report No. 33, Episode 38, No. 9 - 12 pages (September 2009).

Non-Patent Document 2: H. Takahashi, M. Kinoshita, K. Morita, T. Shirai, T. Sato, T. Kimura, H. Yuzurihara, S. Inoue, S. Matsumoto: "A 3.9 µm Pixel Pitch VGA Format 10-B Digital Output CMOS Image Sensor With 1.5 Transistors/Pixel (A3.9-μm Pixel Pitch VGA Format10-b Digital Output CMOS Image Sensor With 1.5 Transistor/Pixel)", IEEE Journal of Solid-State Circuits (IEEE Journal of Solid-State Circuits) ), Issue 39, Episode 12, pp. 2417-2425 (2004).

Non-Patent Document 3: P.P.K.Lee R.C.Gee, R.M.Guidash, T-H.Lee, E.R.Fossum: "An Active Pixel Sensor Fabricated Using CMOS/CCD Process Technology" in the program IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors (in Program IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors), (1995).

Non-Patent Document 4: I. Murakami, T. Nakano, K. Hatano, Y. Nakashiba, M. Furumiya, T. Nagata, T. Kawasaki, H. Utsumi, S. Uchiya, K. Arai, N. Mutoh, A. .Kohno, N, teranishi, Y. Hokari: "Technologies to Improve Photo-Sensitivity and Reduce VOD Shutter Voltage for CCD ImageSensors" to Improve Photo-Sensitivity and Reduce VOD Shutter Voltage for CCD ImageSensors, IEEE Electronics IEEE Transactions on Electron Devices, Issue 47, Episode 8, Pages 1566-1572 (2000).

Non-Patent Document 5: K. Yasutomi, T. Tamura, M. Furuta, S. Itoh, S. Kawahito: "A High-Speed CMOS Image Sensor with Global Electronic Shutter Pixels Using Fixed Diodes with Global Electronic Shutter PixelUsing Pinned Diodes), IEEJ Transactions (IEEJ Trans.SM), No. 129, Episode 10, pp. 321-327 (2009).

Contents of the invention

[Problems to be Solved by the Invention]

In the solid-state imaging device in which one pixel is formed by one island-shaped semiconductor shown in FIG. 9A , the height of the island-shaped semiconductor 100 is mainly determined by the height Ld of the N layer 106 of the photodiode. The signal charge generation rate due to light irradiation has a characteristic of decreasing along an exponential function curve with respect to the Si depth from the top of the P ⁺ layer 121, so in a solid-state imaging device that senses visible light, in order to contribute to In order to efficiently extract signal charges for sensitivity, the depth of the photoelectric conversion region needs to be 2.5 to 3 μm (see, for example, Non-Patent Document 1). Therefore, the height Ld of the N layer 106 of the photoelectric conversion photodiode needs to be at least 2.5 to 3 μm. A reset gate conductor layer 105 is formed under the N layer 106 . Since the reset gate conductor layer 105 can normally operate even if it is, for example, 0.1 μm, the reset gate conductor layer 105 is formed almost at the bottom of the island-shaped semiconductor 100 . Furthermore, as shown in FIG. 9B, since the reset gate conductor layers 105a, 105b, 105c are formed independently for each row, it is necessary to form the reset gate at the bottom of the island-shaped semiconductors P11 to P33 having a height of 2.5 to 3 μm. Conductor layers 105a, 105b, 105c. Because of the existence of the reset gate conductor layers 105a, 105b, 105c, the higher the pixel integration degree is, the more difficult it is to manufacture the solid-state imaging device.

Furthermore, in the CMOS solid-state imaging device having the pixel shown in FIG. 10A, a reset MOS transistor M2 is required within the pixel. Because of the existence of the reset MOS transistor M2, the integration degree of the pixel is reduced.

In the CCD solid-state imaging device shown in FIG. 11A, the depth Lph of the potential well storing signal charges as shown in FIG. 11B is 2.5 to 3 μm as disclosed in Non-Patent Document 1 from the perspective of the required spectral sensitivity characteristics. . Furthermore, in the potential distribution when performing the signal charge removal operation, it is necessary to generate a potential barrier in the transfer of the signal charge 151 from the P ⁺ region 143 to the N region substrate 140 . Therefore, a high applied voltage of 18 to 30V is required for the applied voltage VRH of the N-region substrate 140 . Accordingly, the power consumption of the CCD solid-state imaging device increases.

[means to solve the problem]

The solid-state imaging device in which a plurality of pixels of the present invention are arranged in a two-dimensional shape in the pixel area is characterized by:

a first semiconductor region formed on the substrate;

a second semiconductor region formed on the first semiconductor region;

a third semiconductor region formed on the upper side of the second semiconductor region;

A fourth semiconductor region that is formed on a side surface of the third semiconductor region that does not face a side surface of the second semiconductor region and that is opposite in conductivity to that of the third semiconductor region; and

On the aforementioned second semiconductor region is a fifth semiconductor region with opposite conductivity to that of the aforementioned third semiconductor region;

The aforementioned second semiconductor region includes a semiconductor or an intrinsic semiconductor having an opposite conductivity to that of the aforementioned third semiconductor region;

At least the upper part of the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region form an island-shaped semiconductor;

forming a photodiode through the second semiconductor region and the third semiconductor region;

performing a signal charge storage operation of storing signal charges generated by electromagnetic energy waves incident on the photodiode region in the third semiconductor region;

forming a junction field effect transistor with one of the first semiconductor region and the fifth semiconductor region as a drain, the other as a source, and the third semiconductor region storing the signal charge as a gate;

performing a pixel signal reading operation of reading the current flowing between the source and the drain of the junction field effect transistor as a signal output according to the amount of signal charge stored in the third semiconductor region;

performing a signal charge removal operation, wherein the fourth semiconductor region and the fifth semiconductor region are set to a low-level voltage, and the first semiconductor region is set to a high-level voltage higher than the low-level voltage, by This eliminates the potential barrier in the second semiconductor region existing between the first semiconductor region and the third semiconductor region, and transfers the signal stored in the third semiconductor region through the barrier-free second semiconductor region. Charges are removed from the third semiconductor region to the first semiconductor region.

Preferably, the fourth semiconductor region is connected to the fifth semiconductor region.

Preferably, the structure is such that the third semiconductor region and the fourth semiconductor region are separated from the fifth semiconductor region, and the first conductor layer is formed on the outer periphery of the fourth semiconductor region via an insulating layer. While the signal charges stored in the third semiconductor region are removed to the first semiconductor region, the fourth semiconductor region becomes a low-level voltage lower than the high-level voltage, and a high-level voltage is applied to the first semiconductor region. level voltage, and a predetermined voltage for storing the signal charge is applied to the first conductive layer.

Preferably, the first semiconductor region includes a sixth semiconductor region serving as the source or drain of the junction field effect transistor, and a seventh semiconductor region for removing signal charges stored in the third semiconductor region;

The second semiconductor region extends between the sixth semiconductor region and the seventh semiconductor region.

Preferably, the voltage applied to the seventh semiconductor region during the execution of the signal charge storage operation and the pixel signal read operation is set to be higher than the voltage applied to the seventh semiconductor region during the execution of the signal charge removal operation. The voltage is lower.

Preferably, the following actions are performed: the aforementioned pixels are arranged in a 2-dimensional shape, and the signal currents of at least one row of pixels arranged in the 2-dimensionally arranged pixels are arranged along a column including pixels arranged in a vertical direction. And the signal lines connecting the aforementioned first semiconductor regions to each other are simultaneously read into the row pixel signal acquisition circuit arranged outside the aforementioned pixel region, and the signals of the pixels arranged in the aforementioned at least one row are output from the pixels arranged in the aforementioned row The output circuit of the pixel signal acquisition circuit is read; and during the execution of the aforementioned signal charge removal operation, the aforementioned low-level voltage is applied to the pixel selection line connected to the aforementioned fifth semiconductor region of the pixels arranged in the aforementioned at least one row, And the aforementioned high-level voltage is applied to the pixel selection lines connected to pixels arranged in other rows, and during the high-level voltage application period in which the high-level voltage is applied, the aforementioned signal lines connected to the columns including the aforementioned pixels are Apply a high level voltage.

Preferably, an insulating layer is formed to surround the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, and a light-shielding conductor layer is formed to surround the insulating layer.

Preferably, the light-shielding conductor layer is formed on the side surface of the island-shaped semiconductor of the pixel in the pixel region, and is formed continuously across the entirety of the pixel region.

Preferably, the light-shielding conductor layer is formed on pixels in the pixel region and continuously formed across the pixel region, and a ground voltage or the low-level voltage is applied to the light-shielding conductor layer.

Preferably, the light-shielding conductor layer is connected to the pixels of the pixel region and formed across the entire pixel region, and the light-shielding conductor layer is connected to the aforementioned signal charge removing operation during the period of performing the signal charge removal operation. The above-mentioned high-level voltage is applied in such a way that a part of or all of the period during which the high-level voltage is applied to the aforementioned signal line overlaps, and during the period that does not include the period during which the aforementioned signal charge removal operation is performed, it is applied to the aforementioned signal line. Ground voltage or low-level voltage.

Preferably, the light-shielding conductor layer is formed as an insulating layer surrounding the outer peripheries of the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, and is separated into at least two independent parts.

Preferably, the light-shielding conductor layer is connected to the fifth semiconductor layer.

[Efficacy of the invention]

According to the present invention, in the solid-state imaging device, it is not necessary to reset the semiconductor, and the degree of integration of pixels is improved, so that the manufacture of the solid-state imaging device becomes easy.

In addition, there is no need to have a reset MOS transistor of a CMOS solid-state imaging device in a pixel, and the degree of integration of the pixel is increased, thereby reducing the applied voltage in the signal charge removing operation.

Description of drawings

1A is a cross-sectional view of a pixel structure of a solid-state imaging device according to a first embodiment of the present invention.

Fig. 1B shows potential distributions during a signal charge accumulating operation and a signal charge removing operation along line A-A' of Fig. 1A in the solid-state imaging device according to the first embodiment.

2A is a schematic plan view of a solid-state imaging device according to a second embodiment of the present invention.

2B is a schematic circuit plan view of a solid-state imaging device according to a second embodiment.

2C is a voltage waveform diagram showing the relationship between the driving voltage waveform applied to the pixel selection lines ΦP1 to ΦP3 and the signal lines Φs1 to Φs3 and the voltage waveform at the signal output terminal Vout of the solid-state imaging device according to the second embodiment.

3A is a cross-sectional view of a pixel structure of a solid-state imaging device according to a third embodiment of the present invention.

3B is a schematic plan view of a solid-state imaging device according to a third embodiment.

4A is a schematic plan view of a solid-state imaging device according to a fourth embodiment of the present invention.

4B is a graph showing the relationship between the pulse voltage source Φn voltage waveform of the solid-state imaging device according to the fourth embodiment, the driving voltage waveform applied to the pixel selection lines Φp1 to Φp3 and the signal lines Φs1 to Φs3, and the voltage waveform at the signal output terminal Vout. Voltage waveform diagram.

Fig. 4C is a diagram showing changes in potential distribution of signal charges in a region along line C-C' in the cross-sectional pixel structure diagram of Fig. 3A in the solid-state imaging device according to the fourth embodiment of the present invention.

5A is a cross-sectional view of a pixel structure of a solid-state imaging device according to a fifth embodiment of the present invention.

5B is a schematic plan view of a solid-state imaging device according to a fifth embodiment.

6A is a cross-sectional view of a pixel structure of a solid-state imaging device according to a sixth embodiment of the present invention.

6B is a schematic plan view of a solid-state imaging device according to a sixth embodiment.

7A is a cross-sectional view of a pixel structure of a solid-state imaging device according to a seventh embodiment of the present invention.

7B is a cross-sectional view of a pixel structure of a solid-state imaging device according to a seventh embodiment.

8 is a cross-sectional view of a pixel structure of a solid-state imaging device according to an eighth embodiment of the present invention.

9A is a cross-sectional view of a pixel structure of a conventional solid-state imaging device.

9B is a schematic plan view of a conventional solid-state imaging device.

FIG. 10A is a schematic diagram of pixels of a conventional CMOS solid-state imaging device.

FIG. 10B is a graph showing changes in potential distribution during a signal charge storage operation and a signal charge removal operation in a conventional CMOS solid-state imaging device.

11A is a cross-sectional view of a pixel structure of a conventional solid-state imaging device.

FIG. 11B is a graph showing changes in potential distribution during a signal charge storage operation and a signal charge removal operation in a conventional CMOS solid-state imaging device.

(Description of main component symbols)

SP, P11 to P33, 100 (constituting the pixel) island-shaped semiconductors

1 Substrate

2, 2a, 2b, 2c, D11 to D33 signal line N ⁺ area

3 P areas

4. 4a N area

5, 5a, 6, S11 to S33 P ⁺ regions

7, 7a, 7b, 7c Pixel selection line conductor layer

8 insulation layer

10, 12, 21a, 21b Signal charge

13 pixel selection line vertical scanning circuit

14 rows of pixel signal input-output circuit

15 horizontal scanning circuit

16a, 16b, 16c switch circuit

Φp1, Φp2, Φp3 Pixel selection line

Φs1, Φs2, Φs3 signal lines

Vout Signal output terminal

Th1 During the first horizontal scan

Th2 during the second horizontal scan

Thb1 1st invalid blank period

The1 1st period of validity

Trl1 1st pixel signal reading period

Trl2 2nd pixel signal reading period

Tre1 1st signal charge removal period

18, 18a, 26 light-shielding conductor layer

Φn pulse voltage source

20, 22a, 22b, 23a, 23b Potential distribution

25a The first light-shielding conductor layer

25b The second layer of light-shielding conductor layer

26, 26a, 26b, 26c light-shielding pixel selection line conductor layer

28 Signal line P ⁺ area

30 signal line N ⁺ area

29 Signal charge removal N ⁺ region.

Detailed ways

A solid-state imaging device according to an embodiment of the present invention will be described below with reference to the drawings.

(first embodiment)

1A and 1B show a solid-state imaging device according to a first embodiment. FIG. 1A is a cross-sectional structural view showing one pixel of a solid-state imaging device. A signal line N ⁺ region 2 is formed on the substrate 1 , and an island-shaped semiconductor SP is formed on the signal line N ⁺ region 2 . A P region 3 is formed on the signal line N ⁺ region 2 of the island-shaped semiconductor SP, and an N region 4 is formed on the upper peripheral portion of the P region 3 . Furthermore, a P ⁺ region 5 is formed on the side surface of the island-shaped semiconductor SP surrounding the N region 4 . The P ⁺ region 7 connected to the P ⁺ region 5 is formed on the upper surface of the island-shaped semiconductor SP. Furthermore, a pixel selection line conductor layer 7 is connected to the P ⁺ region 6 . Furthermore, the insulating layer 8 is formed to surround the outer periphery of the signal line N ⁺ region 2 and the island-shaped semiconductor SP. In the solid-state imaging device of the present invention, there is no relocation conductor layer 105 required in the conventional solid-state imaging device shown in FIG. 9A . In addition, the P ⁺ region 5 formed on the outer periphery of the N region 4 is connected to the P ⁺ region 6 of the island-shaped semiconductor SP.

In this solid-state imaging device, the photodiode region is formed by the P region 3 and the N region 4, and when incident light is irradiated from the P ⁺ region 6 side of the island semiconductor SP, signal charges (here, free electrons). Furthermore, the signal charge is mainly stored in the N region 4 of the above-mentioned photodiode region. In addition, in the island-shaped semiconductor SP, a junction field effect is formed in which the N region 4 is used as a gate, the P ⁺ region 6 is used as a source, and the P region 3 near the N ⁺ region 2 of the signal line is used as a drain. transistor. Furthermore, the drain-source current (output signal) of the junction field effect transistor changes according to the amount of signal charge stored in the N region 4, and is read from the signal line N ⁺ region 2 as a signal output. Furthermore, the signal charge stored in the N region 4 is removed in the signal line N + region 102 ^by setting the P ⁺ region 6 at the ground potential (=0V) and applying a high-level voltage to the signal line N ⁺ region 2 .

FIG. 1B shows potential distributions during a signal charge storage operation and a signal charge removal operation along line AA' of FIG. 1A . (a) of FIG. 1B is an enlarged cross-sectional view along line AA' of FIG. 1A . On one side of the P region 3, an N region 4 for a photodiode and a P ⁺ region 5 connected to the P ⁺ region 6 are formed, while an N ⁺ region 2 for a signal line is formed on the other side. Furthermore, an insulating layer 8 is formed on the P ⁺ region 5 , the signal line N ⁺ region 2 , and the P region 3 present therebetween.

(b) of FIG. 1B shows the potential distribution 9 a during the signal charge storage operation. This potential distribution 9 a is represented by the potential at the bottom of the conduction band where free electrons belonging to signal charges exist or move. During this signal charge storage operation, the potential of the P ⁺ area 5 and the signal line N ⁺ area 2 is the ground potential (=0V). In addition, in the signal line N ⁺ region 2, there are many free electrons 11a. Furthermore, in the N region 4 of the photodiode, a potential distribution 9a with a potential well is created. Here, the signal charge 10 a generated by light irradiation is stored in the potential well, and does not move in the signal line N ⁺ region 2 .

(c) of FIG. 1B shows the potential distribution 9 b during the signal charge removal operation. During this signal charge removal operation, the P ⁺ region 5 is at the ground potential, and the high-level voltage Vrh is applied to the signal line N ⁺ region 2 . Here, a potential distribution 9 b in which the potential becomes higher from the N region 4 toward the signal line N ⁺ region 2 is formed. Thus, the signal charges 10b in the N region 4 are removed in the signal line N ⁺ region 2 . In addition, the potential distribution 9 b of the P region 3 between the N region 4 and the signal line N ⁺ region 2 is configured so as not to generate a potential barrier against the movement of signal charges (free electrons). In the conventional example shown in FIG. 11A , the photoelectric conversion region constituted by the N region 142 and the P region well 141 overlaps with the signal charge removal region constituted by the P region well 141 and the N region substrate 140 . In contrast, in this embodiment, as shown in FIG. 1A, the photoelectric conversion region is formed by the N region 4 of the photodiode, and the signal charge removal region is formed by the N region 4 and the signal line N ⁺ region 2. The P region 3 is formed so that the regions respectively forming the photoelectric conversion region and the signal charge removal region do not overlap with each other. Therefore, the signal charge removal region passes through the P region 3 between the N region 4 and the signal line N ⁺ region 2, and forms a potential distribution 9a (potential well) shown in (b) of FIG. 1B during the signal charge storage operation. In addition, as shown in (c) of FIG. 1B, the potential of the P region 3 between the N region 4 and the signal line N ⁺ region 2 satisfies the condition that no potential barrier is generated with respect to the movement of signal charges (free electrons) , the length of the P region 3 between the N region 4 and the signal line N ⁺ region 2 can be shortened as much as possible. Therefore, the voltage Vrh applied to the N ⁺ region 2 can be made smaller than that of the CCD solid-state imaging device shown in FIG. 11A , that is, the voltage can be reduced to, for example, 3 to 5V. This suppresses an increase in power consumption of the solid-state imaging device of the present embodiment, and achieves a signal charge removal operation.

Furthermore, in the solid-state imaging device of this embodiment, the solid-state imaging device shown in FIG. 9A and FIG. 9B is not required, and the bottoms of the island-shaped semiconductors 100, P11 to P33 are more necessary when the pixel integration degree increases. Microfabricated reset conductor layers 105, 105a, 105b, 105c. Thereby, the degree of pixel integration is improved, and the manufacture of the solid-state imaging device becomes easy. Furthermore, in one pixel in the solid-state imaging device of the conventional example shown in FIG. 9A, the signal line N ⁺ layer 102, the P ⁺ layer 107 connected to the pixel selection line conductor layer 108, and the reset gate The three terminals of the conductor layer 105 are driven to perform the signal charge storage operation, the signal charge reading operation, and the signal charge removal operation. In the solid-state imaging device of this embodiment, the signal line N ⁺ layer 2 and the pixel selection line The same series of operations can be achieved by driving the two terminals of the P ⁺ layer 6 connected to the conductor layer 7 . Thus, the reset line vertical scanning circuit 112 disposed around the pixel area in FIG. 9B is no longer needed. Thereby, reduction in the area of the semiconductor substrate on which the solid-state imaging device is formed and reduction in price of the solid-state imaging device are achieved. Furthermore, in the pixel of the present embodiment, there is no need for a reset MOS transistor that lowers the integration degree of the pixel in the conventional CMOS solid-state imaging device shown in FIG. 10A .

(Second Embodiment)

2A to 2C show a driving method of the solid-state imaging device according to the second embodiment.

FIG. 2A is a schematic plan view showing the solid-state imaging device of the present embodiment. The cross-sectional structure along the line BB' in the figure corresponds to FIG. 1A . On the signal line N ⁺ layers 2a, 2b, 2c (corresponding to the signal line N ⁺ layer 2 in FIG. 1A ), 3×3 pixel island-shaped semiconductors P11 to P33 (corresponding to the island-shaped semiconductor SP in FIG. 1A ) are formed. . Pixel selection line conductor layers 7 a , 7 b , and 7 c (corresponding to 7 in FIG. 1A ) are formed on each row of the island-shaped semiconductors P11 to P33 extending in the horizontal direction, which are connected to each other and connected to the pixel selection lines around the pixel area. Line vertical scanning circuit 13. The lower part of the signal line N ⁺ layers 2 a , 2 b , 2 c is connected to a row pixel signal input-output circuit 14 . The row pixel signal input-output circuit 14 simultaneously acquires signals of one column in the vertical direction of the island-shaped semiconductors P11 to P33. Furthermore, the row pixel signal input-output circuit 14 is driven by the horizontal scanning circuit 15 connected thereto. During the horizontal active period, the output signals of one pixel column of the island semiconductors P11 to P33 are sequentially transmitted from the signal output terminal 17 is read out. In addition, in order to connect to the upper part of each signal line N ⁺ region 2a, 2b, 2c, a ground voltage (=0V) is applied during the signal charge storage operation, a floating voltage is applied during the signal charge read operation, and a signal charge removal operation is formed. Switching circuits 16a, 16b, and 16c that apply a high-level voltage Vrh for reset conduction during operation.

FIG. 2B is a schematic circuit plan view showing the solid-state imaging device of the present embodiment. The signal lines Φs1, Φs2, and Φs3 are connected to the N ⁺ layers D11 to D33 of the island-shaped semiconductors P11 to P33 (corresponding to the signal line N ⁺ layer 2 in FIG. 1A ), the row pixel signal input-output circuit 14, and the switch circuit 16a , 16b, 16c. Furthermore, the pixel selection lines Φp1, Φp2, Φp3 (corresponding to the pixel selection line conductor layers 7a, 7b, 7c in FIG. 2A ) are connected to the P + layers S11 to S33 of the island-shaped semiconductors P11 to P33 (corresponding to the P ⁺ layers S11 to S33 in FIG. 1A ). ⁺ layer 6), and the pixel selection line vertical scanning circuit 13. Furthermore, the signal output from the row pixel signal input-output circuit 14 is read from the signal output terminal Vout (corresponding to 17 in FIG. 2A ). The island-shaped semiconductors P11 to P33 are driven by driving voltages applied to pixel selection lines Φp1 , Φp2 , Φp3 , and signal lines Φs1 , Φs2 , Φs3 .

2C shows the relationship between the waveform of the driving voltage applied to the pixel selection lines Φp1 , Φp2 , Φp3 , and the signal lines Φs1 , Φs2 , Φs3 and the waveform of the voltage in the signal output terminal Vout. A second horizontal scanning period Th2 is set following the first horizontal scanning period Th1. The first horizontal scanning period Th1 is composed of a first invalid blanking period Thb1 and a first valid period The1. In the first invalid blank period Thb1 , pixel signals from the island-shaped semiconductors P11 , P12 , and P13 connected to the pixel selection line Φp1 are taken into the row pixel signal take-in-output circuit 14 . The first invalid blank period Thb1 consists of the first pixel signal reading period Tr11 for reading the pixel signals of the pixels P11, P12, and P13 (during this period, the stored signal charges of the island-shaped semiconductors P11, P12, and P13 are stored in the island-shaped semiconductor P11 , P12, P13), removing the stored signal charge of the island-shaped semiconductors P11, P12, P13 in the signal charge removal period Tre1 of the signal line Φs1, Φs2, Φs3, and reading the signal charge removal of the island-shaped semiconductors P11, P12, P13 The second pixel signal reading period Tr12 of the subsequent pixel signal is constituted. Furthermore, for example, a correlated double sampling (sampling) CDS (Correlated double sampling) circuit is used to generate a difference signal between the pixel signal of the first pixel signal reading period Tr11 and the pixel signal of the second pixel signal reading period Tr12, and in In the first horizontal effective period The1, the pixel signals s1, s2, and s3 of the island-shaped semiconductors P11, P12, and P13 are read from the output terminal Vout. The above operation is performed in the second horizontal scanning period Th2 following the first horizontal scanning period Th1, and the pixel signals of the island-shaped semiconductors P21, P22, and P23 are read. By continuously performing this operation, pixel signals of the island-shaped semiconductors P11 to P33 constituting 3×3 pixels can be obtained.

In the first signal charge removal period Tre1, the accumulated signal charges of the island-shaped semiconductors P11, P12, and P13 are set to ground potential (=0V) through the pixel selection line Φp1, and a reset high level is applied to the signal lines Φs1, Φs2, and Φs3 voltage Vrh to remove. At this time, the accumulated signal charges of the island-shaped semiconductors P21, P22, P23, P31, P32, and P33 other than the island-shaped semiconductors P11, P12, and P13 must not be removed. Such a state is realized by applying a voltage to the pixel selection lines Φp2 and Φp3 during the period tph before and after the period tsh in which the high-level voltage Vrh is applied to the signal line Φs1 included in the first signal charge removal period Tre1. The high-level voltage Vrh is applied to the signal lines Φs2 and Φs3 for the same period tsh as that of the signal line Φs1, and the same high-level voltage Vrh is applied thereto. In the periods tsl1 and tsl2 before and after the signal charge removal period tsh, the pixel selection lines Φp2 and Φp3 have a high-level voltage Vrh, and the signal lines Φs1 , Φs2 and Φs3 have a ground potential. At this time, the accumulated signal charges of the island-shaped semiconductors P21, P22, P23, P31, P32, and P33 other than the island-shaped semiconductors P11, P12, and P13 are held in the island-shaped semiconductors P21, P22, P23, P31, P32, and P33. In the internal state, the JFET current flows through the signal lines Φs1, Φs2, and Φs3 to the switch circuits 16a, 16b, and 16c at the ground potential. Furthermore, during the period tph, since the high-level voltage Vrh is applied to the pixel selection lines Φp2, Φp3 and the signal lines Φs2, Φs3, the accumulated signal charges in the island-like semiconductors P21, P22, P23, P31, P32, P33 are In the held state, the JFET current does not flow. In this way, in the first signal charge removal period Tre1 , only the accumulated signal charges of the island-shaped semiconductors P11 , P12 , and P13 connected to the pixel selection line Φp1 are removed.

(third embodiment)

The solid-state imaging device according to the third embodiment will be described below with reference to FIGS. 3A and 3B . Compared with the solid-state imaging device of the first embodiment, the solid-state imaging device of the present embodiment has a feature of reducing leakage of light entering the island-shaped semiconductors SP, P11, P12, and P13 constituting a pixel to adjacent pixels.

FIG. 3A is a cross-sectional view showing a pixel structure of the solid-state imaging device according to the present embodiment. At the bottom of the island-shaped semiconductor SP formed on the substrate 1, a signal line N ⁺ region 2 is formed. A P region 3 is formed on the signal line N ⁺ region 2 , and an N region 4 is formed on the upper peripheral portion of the P region 3 . Furthermore, surrounding this N region 4, a P ⁺ region 5 is formed on the side surface of the island-shaped semiconductor SP. The P ⁺ region 6 is connected to the P ⁺ region 5 and formed on the upper surface of the island-shaped semiconductor SP. Furthermore, a pixel selection line conductor layer 7 is connected to the P ⁺ region 6 . Furthermore, the insulating layer 8 is formed to surround the outer periphery of the signal line N ⁺ region 2 and the island-shaped semiconductor SP. On the outer peripheral portion of the insulating layer 8 , a light-shielding conductor layer 18 is formed so as to surround the P region 3 , the N region 4 , and the P ⁺ region 5 . The light-shielding conductor layer 18 surrounds the island-shaped semiconductors P11 , P12 , P13 , P21 , P22 , P23 , P31 , P32 , and P33 in the entire pixel region, and is formed so as to be connected to each other.

FIG. 3B is a schematic plan view showing the solid-state imaging device of this embodiment. Island-shaped semiconductors P11 to P33 surround the entire pixel area, and form a light-shielding conductor layer 18a (corresponding to the light-shielding conductor layer 18 in FIG. 3A ) connected to each other across the entire pixel area. This light-shielding conductor layer 18a is ground potential (=0V). Except for the light-shielding conductor layer 18a, the schematic plan view of the solid-state imaging device is the same as that shown in FIG. 2A.

In the cross-sectional structure diagram of the pixel shown in FIG. 1A , there is no light-shielding conductor layer 18 . At this time, it is necessary to prevent light incident from the P ⁺ region 6 side of the island-shaped semiconductor SP from leaking to the adjacent island-shaped semiconductors. In the embodiment shown in FIG. 1A , in order to prevent such light leakage, it is necessary to set a light-shielding layer with a gap on the P ⁺ region 6 on the upper part of the island-shaped semiconductor SP, and to form the light-shielding layer above the light-shielding layer The shape of the microlens is optically designed so that incident light does not leak to adjacent island-shaped semiconductors. However, such correspondence between the design and formation of the light-shielding layer and the microlens leads to a reduction in the light-gathering efficiency with respect to the island-shaped semiconductor SP. In this regard, in this embodiment having the light-shielding conductor layer 18 , it is possible to easily prevent the light incident on the island-shaped semiconductor SP from leaking to the adjacent island-shaped semiconductors. Thereby, the solid-state imaging device of the third embodiment can significantly reduce light leakage to the adjacent island-shaped semiconductors compared to the solid-state imaging device of the first embodiment shown in FIG. 1A .

In addition, as shown in FIG. 3B, in the solid-state imaging device of this embodiment, since the light-shielding conductor layer 18a is only required to be formed so as to be connected to each other across the entire pixel area, it is no longer necessary to use the solid-state imaging device shown in FIGS. 9A and 10B. In the solid-state imaging device of the conventional example shown, microfabrication in the pixel region is necessary when forming the gate conductor layers 105, 105a, 105b, and 105c.

(Fourth Embodiment)

The solid-state imaging device according to the fourth embodiment will be described below with reference to FIGS. 4A , 4B, and 4C. Compared with the solid-state imaging device of the third embodiment, the solid-state imaging device of the present embodiment has the feature of realizing further low power consumption for driving the solid-state imaging device.

FIG. 4A is a schematic plan view showing the solid-state imaging device of this embodiment. In the third embodiment shown in FIG. 3B, the potential of the light-shielding conductor layer 18a is set to the ground potential, but in the solid-state imaging device of this embodiment, a pulse (pulse) voltage source Φn is connected to the light-shielding conductor layer 18a. for applying pulse voltage.

4B shows the relationship between the voltage waveform of the pulse voltage source Φn, the driving voltage waveform applied to the pixel selection lines Φp1, Φp2, Φp3, and the signal lines Φs1, Φs2, Φs3, and the voltage waveform in the signal output terminal Vout. In the first signal charge removal period Tre1, a high-level voltage Vb and a higher-level high-level voltage Vrh1 than the high-level voltage Vb are applied to the signal lines Φs1, Φp2, and Φp3 (the application period is tsh) During the period tph of , the high-level voltage Vrh1 is applied to the pixel selection lines Φp2 and Φp3, and the same high-level voltage Vrh1 is applied to the signal lines Φs2 and Φs3 during the same period tsh as the signal line Φs1. In addition, the voltage of the pulse voltage source Φn becomes the high-level voltage Va during the period tph applied to the pixel selection lines Φp2 and Φp3 in the first invalid blank period Thb1. In addition, also in the second invalid blank period thb2, the same operation as above is repeated.

(a) to (d) of FIG. 4C show changes in potential distribution of the signal charge in the area along line CC′ in the cross-sectional structure diagram of the pixel shown in FIG. 3A . (a) of FIG. 4C is an enlarged view of a region along line CC' of FIG. 3A . On one side of the P region 3, an N region 4 for a photodiode and a P ⁺ region 5 connected to the P ⁺ region 6 exist, while an N ⁺ region 2 for a signal line exists on the other side. Furthermore, an insulating layer 8 is formed on the surfaces of the P ⁺ region 5 , the P region 3 , and the signal line N ⁺ region 2 . Furthermore, a light-shielding conductor layer 18 a is formed on the insulating layer 8 .

(b) of FIG. 4C shows the potential distribution 20 during the signal charge storage operation. During this operation, the potentials of the P ⁺ region 5 , the signal line N ⁺ region 2 , and the light-shielding conductor layer 18 a are the ground potential. Here, in the signal line N ⁺ region 2 , a state exists in which many free electrons exist. Furthermore, in the N region 4 of the photodiode, a potential distribution 20 with a potential well is generated. Here, the signal charge 21 a generated by light irradiation is stored in the potential well, and does not move in the signal line N ⁺ region 2 .

(c) of FIG. 4C shows potential distributions 22 a and 22 b in the first null blank period Thb1 . Also, the potential distribution 22a of the first signal charge removal period Tre1 in which the voltage of the pulse voltage source Φn is the high-level voltage Va and the signal lines Φs1, Φs2, and Φs3 are the low-level voltage Vb is shown by a solid line. In addition, the voltage of the pulse voltage source Φn, the potential distribution 22b when any of the pixel selection lines Φp1, Φp2, Φp3, and the signal lines Φs1, Φs2, Φs3 are ground potentials are shown by dotted lines (corresponding to the third embodiment) . In this embodiment, by applying a high-level voltage Va to the light-shielding conductor layer 18a, the potential between the photodiode N region 4 and the signal line N ⁺ region 2 will be lower than that of the light-shielding conductor layer as shown in the potential distribution 22a. The potential distribution 22b is higher when 18a is at the ground potential.

Next, (d) of FIG. 4C shows the potential distribution 23 a in the signal charge removal period tsh during which the high-level voltage Vrh1 is applied to the signal lines Φs1 , Φs2 , and Φs3 by a solid line. In addition, the potential distribution 23b (corresponding to the third embodiment) when the pulse voltage source Φn is at the ground potential and the high-level voltage Vrh is applied to the signal lines Φs1, Φs2, and Φs3 is shown by a dotted line. In this way, the potential distribution 23b shown by the dotted line changes to the potential distribution 23a shown by the solid line, and the stored signal charge 21b is removed in the signal line N ⁺ region 2 . In this case, when the stored signal charge 21b moves to the signal line N ⁺ region 2, in order not to form a potential barrier in the potential distribution of the P region 3 between the N region 4 and the signal line N ⁺ region 2, it is necessary to A sufficient high-level voltage Vrh1 is applied to the signal line N ⁺ region 2 . This high-level voltage Vrh1 is due to the increase in the potential of the P region 3 formed by applying the high-level voltage Va to the light-shielding conductor layer 18a shown in (c) of FIG. A lower voltage than the high-level voltage Vrh of the signal line N ⁺ region 2 required. The voltage applied to the N ⁺ region of this signal line is reduced to a maximum of about 1V. Such lowering of 1V greatly contributes to the reduction of driving power consumption of the solid-state imaging device when the driving voltage of the signal line N ⁺ region 2 is 3 to 5V. Furthermore, lowering of the drive voltage of the solid-state imaging device is promoted, and further reduction of power consumption of the solid-state imaging device of this embodiment is promoted.

In addition, in FIG. 4B, before and after the period tsh in which the high-level voltage Vrh1 is applied to the signal lines Φs1, Φs2, and Φs3, the high-level voltage Vrh1 is applied to the pixel selection lines Φp2, Φp3 during the same period tph. The case where the level voltage Va is applied to the pulse power supply Φn has been described. The potential distribution 23 a shown in (d) of FIG. 4C is realized as long as Va is applied to the light-shielding conductor layer 18 a and the high-level voltage Vrh1 is applied to the signal line N ⁺ region 2 . Therefore, the effect of this embodiment can be obtained as long as the period during which the high-level voltage Vrh1 is applied to the signal lines Φs1, Φs2, and Φs3 overlaps with the period during which the high-level voltage Va is applied to the pulse power supply Φn.

In FIG. 4B, in the periods before and after the period tsh in the first signal charge removal period Tre1, although the low-level voltage Vb is applied to the signal lines Φs1, Φp2, and Φp3, a ground voltage (=0V) may also be applied. to replace it. At this time, a voltage to the extent that free electrons do not move from the signal line N ⁺ region 2 to the N region 4 is applied to the light-shielding conductor layer 18 a.

In FIG. 4B , the signal lines Φs1 , Φs2 , and Φs3 are at the ground potential during periods other than the period tph, but the low-level voltage Vb may be applied to the signal lines Φs1 , Φs2 , and Φs3 . During the period in which the low-level voltage Vb is applied, the potential distribution in which the signal charge 21 a is stored in the potential well shown in (b) of FIG. 4C is obtained. Therefore, the voltage Vrh1 applied to the signal lines Φs1 , Φs2 , and Φs3 during the first signal charge removal period Tre1 can be reduced.

(fifth embodiment)

The solid-state imaging device according to the fifth embodiment will be described below with reference to FIGS. 5A and 5B . Compared with the solid-state imaging device of the fourth embodiment, the solid-state imaging device of this embodiment has the characteristics of realizing more reliable signal charge removal operation and high-speed driving.

FIG. 5A is a cross-sectional view showing a pixel structure of the solid-state imaging device according to the present embodiment. On the substrate 1, a signal line N ⁺ region 2 is formed, and an island-shaped semiconductor SP is formed on the signal line N ⁺ region 2 . A P region 3 is formed on the signal line N ⁺ region 2 of the island-shaped semiconductor SP, and an N region 4 is formed on the upper peripheral portion of the P region 3 . Furthermore, surrounding this N region 4, a P ⁺ region 5 is formed on the side surface of the island-shaped semiconductor SP. An insulating layer 8 is formed to surround the P ⁺ region 5 , the P region 3 , and the signal line N ⁺ region 2 on the outer periphery of the island-shaped semiconductor SP. The P ⁺ region 6 is connected to the P ⁺ region 5 and formed on the upper surface of the island-shaped semiconductor SP. Furthermore, a pixel selection line conductor layer 7 is connected to the P ⁺ region 6 . A first light-shielding conductor layer 25 a is formed to surround the insulating layer 8 of the P region 3 formed between the N region 4 and the signal line N ⁺ region 2 . Further, a second light-shielding conductor layer 25 b is formed to surround the insulating layer 8 formed on the outer peripheral portions of the N region 4 and the P ⁺ region 5 . The second light-shielding conductor layer 25 b is separated from the pixel selection line conductor layer 7 . Each of the 1st light-shielding conductor layer 25a and the 2nd light-shielding conductor layer 25b is mutually connected over the whole area|region of a pixel area.

FIG. 5B is a schematic plan view showing the solid-state imaging device of this embodiment. The cross-sectional structure along line E-E' in Fig. 5B corresponds to Fig. 5A. The first light-shielding conductor layer 25 a surrounds the island-shaped semiconductors P11 to P33 in the pixel region, and is formed to be connected to each other across the entire pixel region. To this first light-shielding conductor layer 25a, a pulse voltage source Φn is connected, similarly to the fourth embodiment. In addition, the light-shielding conductor layer 25 b of the second layer surrounds the island-shaped semiconductors P11 to P33 in the pixel region, and is formed so as to be connected to each other across the entire pixel region. Here, a ground potential is applied to the second light-shielding conductor layer 25a. A voltage having the same waveform as the voltage applied to the pulse power supply Φn shown in FIG. 4B is applied to the light-shielding conductor layer 25 a of the first layer. Furthermore, as described above, in the solid-state imaging device of this embodiment, it is only necessary to form the entire pixel area together with the first light-shielding conductor layer 25a and the second light-shielding conductor layer 25b. Similar to the third and fourth embodiments, microfabrication of pixel regions required for forming gate conductor layers 105, 105a, 105b, and 105c in conventional solid-state imaging devices as shown in FIGS. 9A and 9B is no longer necessary.

In the solid-state imaging device of this embodiment, the light-shielding conductor layer 25a of the first layer and the light-shielding conductor layer 25b of the second layer are separated, and the load capacitance of the pulse voltage power supply Φn during the signal charge removal operation is connected to the second layer. One layer of light shields the capacitance of the conductor layer 25a. This load capacitance is mainly a capacitance formed by the first layer of light shielding the insulating layer 8 between the conductive layer 25 a and the P region 3 . The heights of the island-shaped semiconductors SP, P11 to P33 constituting the pixel are mainly determined by the height Ld of the N region 4 of the photodiode from which the spectral sensitivity characteristics are required. The second light-shielding conductor layer 25 b is formed so as to surround the N region 4 . Therefore, compared with the solid-state imaging device of the fourth embodiment shown in FIG. 4A , the load capacitance of the pulse voltage power supply Φn during the signal charge removal operation is greatly reduced. This reduces the rise and fall time between the ground potential of the pulse voltage power supply Φn and the high-level voltage Va during the signal charge removal operation. Thereby, a reliable signal charge removing operation can be realized. In addition, in the high-speed imaging operation of the solid-state imaging device, shortening of each operation time is required, so this embodiment also contributes to the speedup of such a solid-state imaging device.

(sixth embodiment)

The solid-state imaging device according to the sixth embodiment will be described below with reference to FIGS. 6A and 6B . In this embodiment, the pixel selection line conductor layer 7 of the first embodiment shown in FIG. Features of neighboring pixels.

FIG. 6A is a cross-sectional view showing a pixel structure of the solid-state imaging device according to the present embodiment. At the bottom of the island-shaped semiconductor SP formed on the substrate 1, a signal line N ⁺ region 2 is formed. A P region 3 is formed on the signal line N ⁺ region 2 , and an N region 4 is formed on the upper peripheral portion of the P region 3 . Furthermore, surrounding this N region 4, a P ⁺ region 5 is formed on the side surface of the island-shaped semiconductor SP. The P ⁺ region 6 is connected to the P ⁺ region 5 and formed on the upper surface of the island-shaped semiconductor SP. Furthermore, the insulating layer 8 is formed to surround the outer periphery of the signal line N ⁺ region 2 and the island-shaped semiconductor SP. On the outer peripheral portion of the insulating layer 8 , a light-shielding pixel selection line conductor layer 26 is formed to surround the P region 3 , the N region 4 , and the P ⁺ region 5 and connected to the P ⁺ region 6 . Thus, in this embodiment, the pixel selection line conductor layer 26 has both the function as a pixel selection line and the function of preventing light from leaking to adjacent island-shaped semiconductors.

FIG. 6B is a schematic plan view showing the solid-state imaging device of this embodiment. The pixel cross-sectional structure diagram along the line F-F' in FIG. 6B corresponds to FIG. 6A. The pixel selection line conductor layers 7a, 7b, and 7c in the schematic plan view of the solid-state imaging device according to the second embodiment shown in FIG. 2A are changed to light-shielding pixel selection line conductor layers 26a, 26b, 26c. Other than that, the configuration shown in FIG. 6B is the same as that in FIG. 2A . Thus, in this embodiment, there is no need to separately form the pixel selection line conductor layers 7, 7a, 7b, 7c and the light-shielding conductor layers 18, 18a as shown in FIGS. 3A and 3B, and the light-shielding pixel selection line conductor layer 26a , 26b, 26c can have both functions. This facilitates the manufacture of the solid-state imaging device.

In addition, this embodiment is also applicable to the case where the second light-shielding conductor layer 25b and the pixel selection line conductor layer 7 of the fifth embodiment shown in FIG. 5A are integrated. In addition, in FIG. 6A, although the bottom of the light-shielding pixel selection line conductor layer 26 is formed to be located at the upper end of the signal line N ⁺ region 2 of the island-shaped semiconductor SP constituting the pixel, it may also be located at the signal line N ⁺ region 2. The upper or lower part of the upper end.

(the seventh embodiment)

The solid-state imaging device according to the seventh embodiment will be described below with reference to FIGS. 7A and 7B .

7A is a cross-sectional structure showing a first solid-state imaging device according to a seventh embodiment. On the substrate 1, a band-shaped semiconductor 27 composed of a signal line P ⁺ region 28, a P region 3, and a signal charge removing N ⁺ region 29 is formed. An island-shaped semiconductor SP is formed on the strip-shaped semiconductor 27 . The P region 3 is formed so as to be connected to the island-shaped semiconductor SP on the band-shaped semiconductor 27 . An N region 4 is formed on the outer peripheral portion above the P region 3 . Furthermore, surrounding this N region 4, a P ⁺ region 5 is formed on the side surface of the island-shaped semiconductor SP. The P ⁺ region 7 is connected to the P ⁺ region 5 and formed on the upper surface of the island-shaped semiconductor SP. Furthermore, a pixel selection line conductor layer 7 is connected to the P ⁺ region 6 . Furthermore, the insulating layer 8 is formed to surround the outer periphery of the signal line N+ region 2 and the island-shaped semiconductor SP.

In the solid-state imaging device of this embodiment, a photodiode region composed of a P region 3 and an N region 4 is formed. Here, when light is irradiated from the P ⁺ region 6 side of the island-shaped semiconductor SP, signal charges (free electrons in this case) are generated in the photoelectric conversion region of the photodiode region. Furthermore, the signal charges are mainly stored in the N region 4 of the photodiode region. In addition, a junction field effect transistor having the N region 4 as a gate, the P ⁺ region 6 as a source, and the signal line P ⁺ region 28 as a drain is formed in the island-shaped semiconductor SP. Furthermore, the drain-source current (output signal) of the JFET changes according to the amount of signal charge stored in the N region 4 and is read from the signal line P ⁺ region 28 as a signal output. Furthermore, the signal charge stored in the N region 4 is removed to the signal charge removal N region 29 by setting the P ⁺ region 6 at the ground potential (=0 V) and applying a positive ON voltage to the signal charge removal N ⁺ region 29 . ⁺ Area 29.

In FIG. 1A , the signal line N ⁺ region 2 has a function of taking out a drain-source current (output signal) of the junction field effect transistor and a function of removing signal charges. On the other hand, in this embodiment, instead of the signal line N + region 2, the signal line P ⁺ region 28, the P region 3, and the signal charge removal ^{N + region} 29 are formed. Furthermore, the drain-source current (output signal) of the junction field effect transistor is taken out by the signal line P ⁺ region 28 , and the signal charge removal is performed by the signal charge removing N ⁺ region 29 . Thus, in the solid-state imaging device shown in FIG. 1A, the drain-source voltage of the junction field effect transistor for starting to flow the drain-source current of the junction field effect transistor is In this ^embodiment , the signal line is set to be P ⁺ region 28, whereby it can be lowered to around 0V. Due to this reduction in driving voltage, the driving power consumption of the solid-state imaging device is reduced. In addition, since the signal charge removal can be performed in the signal charge removal N ⁺ region 29 independent from the signal line P ⁺ region 28, in the signal charge storage period, by setting a higher level than that applied in the signal charge removal period tsh If a low-level voltage of a lower level than the voltage Vph is applied to the signal charge removal N ⁺ region 29, the signal charge removal N ⁺ region 29 will be damaged by light incident on the island-shaped semiconductor SP with an excessive illuminance. The generated excess signal charges are removed.

FIG. 7B shows a cross-sectional structure of the second solid-state imaging device of the present embodiment. In this second solid-state imaging device, the signal line P ⁺ region 28 in FIG. 7A is used as the signal line N ⁺ region 30 . Other configurations are the same as in FIG. 7A . In this embodiment, a signal line N ⁺ region 30, a P region 3, and a signal charge removal N ⁺ region 29 are formed to replace the signal line N ⁺ region 2, and the signal line N ⁺ region 30 performs the drain of the junction field effect transistor. The extraction operation of the electrode-source current (output signal), and the signal charge removal N ⁺ region 29 executes the signal charge removal operation. The solid-state imaging device shown in FIG. 1A has both the function of extracting the drain-source current (output signal) of the junction field effect transistor and the function of removing signal charges. On the other hand, in this embodiment, , the function of taking out the output signal and the function of removing the signal charge are separated in the same way as in FIG. 7A . Although the solid-state imaging device of this embodiment does not have the advantage that the solid-state imaging device shown in FIG. 7A can be driven with low power consumption, it has the following advantages compared with the solid-state imaging device shown in FIG. While the ⁺ region 30 is reading the signal current, the signal charge removal N ⁺ region 29 is also held at a predetermined voltage, and excess signal charges generated by excessive light irradiation can be removed from the signal charge removal N ⁺ region 29. remove.

(eighth embodiment)

A solid-state imaging device according to an eighth embodiment will be described below with reference to FIG. 8 .

FIG. 8 shows a cross-sectional structure of the solid-state imaging device of this embodiment. As shown in FIG. 8, a signal line N ⁺ region 2 is formed. Island-shaped semiconductors SP constituting pixels are formed on the signal line N ⁺ region 2 . A P region 3 is formed on the signal line N ⁺ region 2 of the island-shaped semiconductor SP, and an N region 4 a is formed on the outer periphery of the upper portion of the P region 3 . Furthermore, a P ⁺ region 5 a is formed around the N region 4 a and on the side surface of the island-shaped semiconductor SP. Furthermore, the insulating layer 8 is formed to surround the outer periphery of the signal line N ⁺ region 2 and the island-shaped semiconductor SP. Conductive layer 31 is formed on the outer periphery of N region 4 a and P ⁺ region 5 a via insulating layer 8 . P ⁺ region 7 is separated from N region 4 a and P ⁺ region 5 a and formed on the upper surface of island-shaped semiconductor SP. A pixel selection line conductor layer 7 is connected to the P ⁺ region 6 . Furthermore, the conductor layer 31 is formed to be separated from the pixel selection line conductor layer 7 .

Referring to FIG. 8 , in the solid-state imaging device according to this embodiment, after the P ⁺ region 5a on the outer peripheral portion of the island-shaped semiconductor SP becomes a low-level voltage, a voltage for storing holes is applied to the conductive layer 31 . Furthermore, a ground voltage is applied to the P ⁺ region 6 and a high level voltage is applied to the signal line N ⁺ region 2 , and the signal charges stored in the N region 4 a are removed to the signal line N ⁺ region 2 . In this way, by applying a voltage to the conductive layer 31, the signal charges accumulated in the N region 4a can be removed to the signal line N ⁺ region 2 similarly to the solid-state imaging device shown in FIG. 1A. The conductive layer 31 has a function of a light-shielding conductive layer that prevents light incident on the island-shaped semiconductor SP from leaking to adjacent island-shaped semiconductors.

In ^addition , in the ^first embodiment, although the signal line N ⁺ region 2 is provided as shown in FIG. 1A , even in FIG. A solid-state imaging device in which the N region 4 is a P region, the P regions 5 and 6 are N ⁺ regions, and the semiconductors in all semiconductor regions are of the opposite conductivity type can also obtain the same effect as the present embodiment. This point is applicable to all the above-mentioned embodiments in common.

As shown in FIG. 1A , in the first embodiment, a signal line N ⁺ region 2 is formed on a substrate 1 . However, it is not limited thereto, and the substrate 1 may be an insulating layer or a semiconductor layer, and may be a material layer capable of performing the operation of the solid-state imaging device in each of the above-described embodiments. This type can be commonly applied to all the above-mentioned embodiments.

In the description of the first embodiment using FIG. 1A, although the case where the pixel selection line conductor layer 7 is connected to the P ⁺ region 7 from the side surface of the island-shaped semiconductor SP has been described, the pixel selection conductor layer can also be formed using, for example, an oxide layer. A transparent conductive material such as indium tin (InSnO) is connected to the P ⁺ region 7 from the upper surface of the island-shaped semiconductor SP. This type can be commonly applied to all the above-mentioned embodiments.

The driving method shown in FIG. 2C for explaining the second embodiment is, of course, also applicable to the embodiments of the present invention after the second embodiment. In addition, when the signal line semiconductor regions 28, 30 and the signal charge removal N ⁺ region 29 are separated in the seventh embodiment shown in FIGS. 7A and 7B , the voltages applied to the signal lines Φs1, Φs2, and Φs3 in FIG. 2C waveform is applied to the signal charge removal N ⁺ region 29 .

In the first embodiment, as shown in FIG. 1B , the ground voltage (=0V) is applied to the signal line N ⁺ region 2 during the signal charge storage operation, but a low-level voltage may be applied instead. In this state, the signal charges 10 a stored in the N region 4 are not removed from the signal line N ⁺ region 2 . In addition, in the first signal charge removal period Tre1 in FIG. 2C , a low-level voltage may be applied while the ground voltage is applied to the signal lines Φs1 , Φs2 , and Φs3 . This type can also be commonly applied in each of the above-mentioned embodiments.

In addition, here, a structure may be employed in which a metal layer or a silicide layer is provided between the substrate 1 and the signal line N ⁺ region 2 to lower the resistance value of the signal line N ⁺ region. This mode is also applicable to each of the above-mentioned embodiments in the same manner.

In the first embodiment shown in FIG. 1A, the P region 2 may also be composed of an intrinsic type semiconductor layer. The so-called intrinsic semiconductor is actually a semiconductor composed of one element. Intrinsic semiconductors are manufactured so that no impurities are mixed in, but in fact, they inevitably contain extremely small amounts of impurities. The P region 2 made of this intrinsic semiconductor may contain a small amount of acceptor or donor impurities as long as it does not hinder the function as a solid-state imaging device. This type can also be commonly applied in each of the above-mentioned embodiments.

In Fig. 1A of the first embodiment, although it is shown that the N ⁺ region 2 is connected to the signal line, and the P ⁺ region 6 is connected to the solid-state imaging device with the pixel selection line, but the N ⁺ region may also be connected to the pixel selection line, And the P ⁺ region 6 is connected with signal lines. This form is applicable to all the above-mentioned embodiments in common.

In FIG. 1A of the first embodiment, N region 4 and P ⁺ region 6 are connected. However, it is not limited thereto, and the same effect can be obtained even if the N region 4 and the P ⁺ region 6 are separated.

In each of the above-mentioned embodiments, although a solid-state imaging device composed of one pixel or 3×3 pixels is used, the technical idea of the present invention can of course also be applied to a solid-state imaging device in which pixels are arranged one-dimensionally or two-dimensionally. camera device.

In the solid-state imaging device to which the technical idea of the present invention is applied, the arrangement of pixels is preferably linear, zigzag, etc. as long as it is a one-dimensional pixel arrangement, and preferably linear lattice or honeycomb as long as it is a two-dimensional pixel arrangement. (honeycomb) shape, etc., but not limited to these shapes.

In addition, the shapes of the island-shaped semiconductors SP, P11, and P33 in each of the above-mentioned embodiments may be cylindrical, hexagonal, or other shapes.

The operation shown by the voltage waveform shown in FIG. 2C is assumed to ^be the solid-state imaging device with the cross ^- sectional structure shown ⁱⁿ FIG. The solid-state imaging device in which the potential relationship of 6 is obtained during the signal charge removal period can be applied to each of the above-mentioned embodiments.

In FIG. 3B , a ground voltage (=0 V) is applied to the light-shielding conductor layer 18 a. However, it is not limited thereto, and the same effects as those of the above-described embodiments can be obtained even when a low-level voltage close to the ground voltage is applied.

In addition, in each of the above-mentioned embodiments, although a solid-state imaging device is used to generate signal charges in pixels by light irradiation, the technical concept of the present invention can of course be applied to imaging devices that generate signal charges by visible light, ultraviolet rays, infrared rays, X-rays, Other semiconductor devices that generate signal charges in pixels by irradiation with electromagnetic energy waves such as electromagnetic rays, radiation rays, and electron rays.

In summary, although the present invention has been described in detail by citing a plurality of embodiments, the scope of the present invention is not limited to the above-mentioned respective embodiments. Improvements, substitutions, combinations, etc. made by those skilled in the art are included in the scope of the present invention as long as they do not exceed the technical idea of the present invention.

Claims (12)

1. A solid-state imaging device in which a plurality of pixels are arranged in a 2-dimensional shape in a pixel region, characterized in that it has: a first semiconductor region formed on the substrate; a second semiconductor region formed on the first semiconductor region; a third semiconductor region formed on the upper side of the second semiconductor region; a fourth semiconductor region formed on a side surface of the third semiconductor region that does not face a side surface of the second semiconductor region and having an opposite conductivity to that of the third semiconductor region; and On the aforementioned second semiconductor region is a fifth semiconductor region with opposite conductivity to that of the aforementioned third semiconductor region; The aforementioned second semiconductor region includes a semiconductor or an intrinsic semiconductor having an opposite conductivity to that of the aforementioned third semiconductor region; At least the upper part of the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region form an island-shaped semiconductor; forming a photodiode through the second semiconductor region and the third semiconductor region; performing a signal charge storage operation of storing signal charges generated by electromagnetic energy waves incident on the photodiode region in the third semiconductor region; forming a junction field effect transistor with one of the first semiconductor region and the fifth semiconductor region as a drain, the other as a source, and the third semiconductor region storing the signal charge as a gate; performing a pixel signal reading operation of reading the current flowing between the source and the drain of the junction field effect transistor as a signal output according to the amount of signal charge stored in the third semiconductor region; performing a signal charge removing operation, wherein the fourth semiconductor region and the fifth semiconductor region are set to a low-level voltage, and the first semiconductor region is set to a high-level voltage higher than the low-level voltage, Thereby, the potential barrier is eliminated in the second semiconductor region existing between the first semiconductor region and the third semiconductor region, and the energy stored in the third semiconductor region is stored in the third semiconductor region through the second semiconductor region without potential barrier. Signal charges are removed from the third semiconductor region to the first semiconductor region. 2. The solid-state imaging device according to claim 1, wherein the fourth semiconductor region is connected to the fifth semiconductor region. 3. The solid-state imaging device according to claim 1, wherein the third semiconductor region and the fourth semiconductor region are separated from the fifth semiconductor region and separated from the outer periphery of the fourth semiconductor region. The first conductor layer is formed next to the insulating layer, and the fourth semiconductor region becomes a low voltage lower than the high level voltage while the signal charges stored in the third semiconductor region are removed to the first semiconductor region. A flat voltage is applied, and a high-level voltage is applied to the first semiconductor region, and a predetermined voltage for storing the signal charge is applied to the first conductive layer. 4. The solid-state imaging device according to claim 1, wherein the first semiconductor region has a sixth semiconductor region to be a source or a drain of the junction field effect transistor, and a sixth semiconductor region for removing data stored in the first semiconductor region. The 7th semiconductor region of the signal charge of the 3 semiconductor regions; The second semiconductor region extends between the sixth semiconductor region and the seventh semiconductor region. 5. The solid-state imaging device according to claim 4, wherein the voltage applied to the seventh semiconductor region during the execution of the signal charge storing operation and the pixel signal reading operation is set to be higher than the voltage applied to the seventh semiconductor region during the execution of the aforementioned signal charge storage operation and the pixel signal reading operation. The voltage applied to the seventh semiconductor region is lower during the signal charge removal operation. 6. The solid-state imaging device according to claim 1, wherein the aforementioned plurality of pixels are arranged in a 2-dimensional shape, and the signal currents of at least one row of pixels arranged in the 2-dimensionally arranged pixels are passed along the The signal line arranged along the column including the pixels arranged in the vertical direction and connecting the aforementioned first semiconductor regions to each other is simultaneously read into the row pixel signal taking circuit provided outside the aforementioned pixel region, and will be arranged in the aforementioned at least The operation of reading the signal output of pixels in one row from the output circuit provided in the pixel signal acquisition circuit of the aforementioned row, and during the execution of the signal charge removal operation, for the aforementioned first pixel connected to the pixels arranged in the aforementioned at least one row 5. The aforementioned low-level voltage is applied to the pixel selection lines of the semiconductor region, and the aforementioned high-level voltage is applied to the pixel selection lines connected to pixels arranged in other rows, and during the high-level voltage application period in which the high-level voltage is applied In this case, a high-level voltage is applied to the signal line connected to the column including the pixel. 7. The solid-state imaging device according to claim 1, wherein an insulating layer is formed to surround the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, and a light-shielding conductor layer is formed to surround the insulating layer. layer. 8. The solid-state imaging device according to claim 7, wherein the light-shielding conductor layer is formed on a side surface of the island-shaped semiconductor of a pixel in the pixel region, and is continuously formed across the entire pixel region. 9. The solid-state imaging device according to claim 7, wherein the light-shielding conductor layer is formed on the pixels in the pixel region and continuously formed across the pixel region, and the light-shielding conductor layer is formed continuously. Apply ground voltage or the aforementioned low-level voltage. 10. The solid-state imaging device according to claim 7, wherein the light-shielding conductor layer is connected to pixels in the pixel region and formed across the entire pixel region, and the light-shielding conductor layer is formed in During the period during which the signal charge removal operation is performed, the high-level voltage is applied so as to overlap with a part or all of the period during which the high-level voltage is applied to the signal line, and the signal charge removal operation is not performed. During the period of operation, a ground voltage or a low-level voltage is applied to the aforementioned signal line. 11. The solid-state imaging device according to claim 7, wherein the light-shielding conductor layer is formed as an insulating layer surrounding the outer peripheries of the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, and is separated from each other. for at least 2 separate parts. 12. The solid-state imaging device according to claim 7, wherein the light-shielding conductor layer is connected to the fifth semiconductor layer.

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