JP2008147486A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device which has a high integration and a high resolution by utilizing both of a pair of electron/hole produced due to a photoelectric effect. <P>SOLUTION: The solid-state imaging device includes a first conduction type semiconductor substrate 11, a second conduction type hole accumulation/transfer area 13 which is located in the surface area of the semiconductor substrate 11, a first conduction type light receiving area 12 which is located in the hole accumulation/transfer area 13, a first conduction type electron transfer area 14 which is located in the surface area in the hole accumulation/transfer area 13 at a predetermined space from the light receiving area 12, a gate oxide film 15 which is formed on the surface of the semiconductor substrate 11, a first transfer gate electrode 16 which is formed on the gate oxide film 15 at a position corresponding between the light receiving area 12 and the hole accumulation/transfer area 13, an electron detection circuit 17 which is connected to the electron transfer area, means 13-1, 21 which extract holes accumulated in the hole accumulation/transfer area, and a hole detection circuit 18 to which the hole extracted by the means is supplied. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a highly integrated and high-resolution solid-state imaging device.

In recent years, solid-state imaging devices have become higher in resolution / multiple pixels, and the area of one pixel has been reduced accordingly. This means that since the light receiving portion that actually contributes to the photoelectric effect is reduced, the output obtained from one pixel is reduced even in the same brightness environment. If the noise does not improve greatly, if the output is reduced, the noise will increase relatively, causing image quality degradation. In conventional solid-state imaging devices, only electrons out of the electron / hole pairs generated by the photoelectric effect As the output, and the charge of the holes generated by the incident light was not utilized.
JP 2000-269618 A

  An object of the present invention is to provide a solid-state imaging device with high integration and high resolution by utilizing both electron / hole pairs generated by the photoelectric effect.

  A solid-state imaging device according to the present invention includes a first conductivity type semiconductor substrate, a second conductivity type hole accumulation / transfer region provided in a surface region of the semiconductor substrate, and a hole accumulation / transfer region in the hole conductivity / transfer region. A first-conductivity-type light-receiving region provided, and a first-conductivity-type electron-transfer region provided in a surface region within the hole accumulation / transfer region at a predetermined interval with respect to the light-receiving region; A gate oxide film formed on the surface of the semiconductor substrate; a first transfer gate electrode formed on the gate oxide film at a position corresponding to between the light receiving region and the hole accumulation / transfer region; An electron detection circuit connected to the electron transfer region; means for extracting the holes accumulated in the hole accumulation / transfer region; and a hole detection circuit to which the holes extracted by the means are supplied. It is characterized by this.

  By using both electron / hole pairs generated by the photoelectric effect, a solid-state imaging device structure with high integration and high resolution can be obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a plan view showing a configuration of a light receiving unit corresponding to one pixel of a solid-state imaging device and a readout circuit for photoelectrically converted image information. FIG. 2 is a cross-sectional view taken along a broken line AA ′ in FIG.

  As shown in these drawings, for example, a light receiving portion 12 made of an N type semiconductor region is formed at a certain depth from the surface of an N type Si semiconductor substrate 11. The light receiving unit 12 has a shape in which two adjacent corners of a substantially square shape are removed. Around the light receiving portion 12, a hole accumulation / transfer region 13 for accumulating / transferring holes is formed of a P-type semiconductor region partially reaching the surface of the semiconductor substrate 11. As shown in FIG. 1, the hole accumulation / transfer region 13 has a substantially square shape, but one corner is enlarged. In the expanded hole accumulation / transfer region 13, an electron transfer region 14 for transferring electrons is formed slightly spaced from the light receiving unit 12. The electron transfer region 14 is composed of an N-type semiconductor region that partially reaches the surface of the semiconductor substrate 11. The planar shape of the electron transfer region 14 is substantially a triangle as shown in FIG. 1, and its one side is opposed to the removed corner of the light receiving unit 12 with a certain interval. Is arranged.

A gate oxide film 15 made of SiO ₂ is formed on the surface of the semiconductor substrate 11 where these regions are formed. On the gate oxide film 15, a transfer gate (TG) electrode 16 having a substantially rectangular planar shape is disposed in a portion between the light receiving unit 12 and the electron transfer region 14. A gate control line TGn is connected to the transfer gate electrode 16. Although not shown, the gate control line TGn is multi-layered on the insulating film that covers the transfer gate electrode 16 and the surface of the semiconductor substrate 11.

  The electron transfer region 14 is provided with an electron takeout terminal 14-1, which is connected to an input terminal of an electron detection circuit 17 constituted by an N-ch transistor for detecting electrons. The hole accumulation / transfer area 13 is provided with a hole extraction terminal 13-1, which is connected to an input terminal of a hole detection circuit 18 constituted by a P-ch transistor for detecting holes. Yes. The output terminals S1 and S2 of the electron detection circuit 17 and the hole detection circuit 18 are connected to the input terminal of the A / D converter 19, respectively, and a digital output signal is taken out on the output side. A signal line S for signal reading is also connected to the output terminals s1 and s2 of the electron detection circuit 17 and the hole detection circuit 18.

  1 and FIG. 2 show only a circuit device (cell) for one pixel, but in an actual device, cells corresponding to a plurality of pixels are arranged in a line or matrix, The gate control line TGn, the signal line S, and the A / D converter 19 are commonly used for these cells.

  Next, the operation of the solid-state imaging device configured as described above will be described with reference to FIGS. When incident light L from the subject is incident on the light receiving unit 12, an electron / hole pair is generated by this, and the holes are mainly discharged to the substrate in the conventional apparatus, and do not contribute to the signal output. In the present embodiment, the light is accumulated in the hole accumulation / transfer region 13 surrounding the light receiving unit 12. In the solid-state imaging device according to this embodiment, the potential of the gate control line TGn is set to the ground level, that is, the Low level in the steady state before and after the incident light L is incident. In this state, the holes accumulated in the hole accumulation / transfer area 13 are extracted outside via the hole extraction terminal 13-1 and supplied to the hole detection circuit 18. The hole detection circuit 18 detects the supplied holes and generates a positive analog potential output corresponding to the amount at the output terminal s2.

  On the other hand, the electrons in the electron / hole pair generated in the light receiving unit 12 by the incidence of the incident light L make the transfer gate TG a predetermined positive potential, that is, a high level, whereby the light receiving unit 12 and the electron transfer region 14 It is taken out to the outside through the N channel and electron take-out terminal 14-1 formed in the surface region of the hole accumulation / transfer region 13 between them. Electrons extracted outside through the electron extraction terminal 14-1 are supplied to the input terminal of the electron detection circuit 17. The electron detection circuit 17 detects the supplied electrons and generates a positive analog potential output corresponding to the amount at the output terminal s1.

  Both positive analog potential outputs generated at the output terminal s1 of the electron detection circuit 17 and the output terminal s2 of the hole detection circuit 18 are added to each other by being supplied to the input terminal of the A / D converter 19, and digitally output to the output terminal. A converted signal output is obtained. This output is read out to the signal line S.

  As described above, the output terminal of the A / D converter 19 outputs a signal obtained by adding the output of the electron detection circuit 17 and the output of the hole detection circuit 18 as an output signal of the solid-state imaging device. Up to twice as much output can be obtained as compared with the output of a single case.

(Embodiment 2)
FIG. 5 is a plan view showing a second embodiment of the solid-state imaging device of the present invention, and shows a configuration of a light receiving unit corresponding to one pixel and a readout circuit for photoelectrically converted image information. FIG. 6 is a cross-sectional view taken along the broken line BB ′ in FIG. In these drawings, components corresponding to those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. Hereinafter, different portions will be mainly described.

  In this embodiment, a portion of the semiconductor substrate 11 that is slightly away from the hole accumulation / transfer region 13 is a P-type semiconductor region that reaches the surface of the semiconductor substrate 11 and transfers holes. A hole transfer region 21 is formed. A P channel region 22 is formed on the surface portion of the semiconductor substrate 11 between the hole accumulation / transfer region 13 and the hole transfer region 21. A second transfer gate electrode TG 2 is provided on the gate oxide film 15 corresponding to the position between the hole accumulation / transfer region 13 and the hole transfer region 21. Here, the first transfer gate electrode T1 provided between the light receiving unit 12 and the electron transfer region 14 corresponds to the transfer gate (TG) electrode 16 in FIGS. As shown in FIG. 5, the plane shape of the hole transfer region 21 is substantially a triangle, and is arranged so that one side of the hole transfer region 21 is opposed to the removed corner of the light receiving unit 12 at a certain interval. Has been. Further, the planar shape of the second transfer gate electrode TG2 is substantially rectangular like the first transfer gate electrode T1.

  A first gate control line TGn is connected to the first transfer gate electrode T1. The first gate control line TGn corresponds to the gate control line TGn shown in FIG. 1 or FIG. On the other hand, a second gate control line TGn ′ is connected to the second transfer gate electrode TG2. Although not shown, the second gate control line TGn ′ is an insulating material that covers the first transfer gate electrode T1, the second transfer gate electrode TG2, and the surface of the semiconductor substrate 11 in the same manner as the first gate control line TGn. Multi-layer wiring is provided on the film. Control voltages having opposite polarities are applied to the first gate control line TGn and the second gate control line TGn ′.

  As described above, the electron transfer region 14 is provided with the electron takeout terminal 14-1, and the first signal line S1 is connected to the terminal 14-1. The terminal 14-1 is also connected to an input terminal of an electron detection circuit 17 constituted by an N-ch transistor that detects electrons. The hole transfer region 21 is provided with a hole extraction terminal 21-1, and the second signal line S2 is connected to this terminal. The terminal 21-1 is also connected to an input terminal of a hole detection circuit 23 configured by an N-ch transistor that detects holes. The output terminals s1 and s2 of the electron detection circuit 17 and the hole detection circuit 23 are connected to the input terminals of the first A / D converter 24 and the second A / D converter 25, respectively, and a digital output signal is output on the output side. It is taken out. The output signals of the first and second A / D converters 24 and 25 are supplied to the input terminal of the difference circuit 26, and the output signal 27 of the solid-state imaging device is obtained at the output terminal.

  Next, the operation of the solid-state imaging device configured as described above will be described with reference to FIGS. When incident light L from the subject is incident on the light receiving unit 12, an electron / hole pair is generated by this, and the holes are mainly discharged to the substrate in the conventional apparatus, and do not contribute to the signal output. In the present embodiment, the light is accumulated in the hole accumulation / transfer region 13 surrounding the light receiving unit 12. During this charge accumulation, the first gate control line TGn is supplied with a low level voltage, and the second gate control line TGn ′ is supplied with a high level voltage. As a result, a high level potential is applied to the second transfer gate electrode TG2 to invert the P channel 22 immediately below the second transfer gate electrode TG2, and from the hole accumulation / transfer region 13 to the hole transfer region 21. Block the movement of holes. In this state, since a low level potential is applied to the first transfer gate electrode T1, no inversion occurs in the N-type semiconductor substrate 11 immediately below the first transfer gate electrode T1. Therefore, the electrons generated in the hole accumulation / transfer area 13 do not move to the electron transfer area 14.

  Next, at the time of signal readout, the first gate control line TGn is supplied with a high level voltage and the second gate control line TGn ′ is supplied with a low level voltage. As a result, since a high level potential is applied to the first transfer gate electrode T1, the P-type hole accumulation / transfer region 13 immediately below the first transfer gate electrode T1 is inverted, and an N channel is formed. . Therefore, the electrons generated in the hole accumulation / transfer area 13 are transferred to the electron transfer area 14 and taken out to the outside via the electron takeout terminal 14-1. The extracted electrons are supplied to the input terminal of the electron detection circuit 17 configured by an N-ch transistor, and converted into an analog signal corresponding to the amount of extracted electrons.

  At the time of reading this signal, a low level potential is applied to the second transfer gate electrode TG2, and the P channel region 22 immediately below the second transfer gate electrode TG2 is not inverted. Holes are transferred from the region 13 to the hole transfer region 21. The holes that have moved to the hole transfer region 21 are extracted through the hole extraction terminal 21-1 and supplied to the input terminal of the hole detection circuit 23 configured by an N-ch transistor.

  Here, before the electrons are transferred to the electron transfer region 14 and the holes are transferred to the transfer region 21, the first signal line S1 is reset to the high level potential, and the second signal line S2 is set to the low level potential. And the outputs of the first and second A / D converters 24 and 25 are held as reference signal potentials. When the charge is read, the output of the first A / D converter 24 (ADC1) becomes higher than the reference signal potential, and the output of the second A / D converter 25 (ADC2) becomes lower than the reference signal potential. The difference from the signal potential becomes the output potential of the first and second A / D converters 24 and 25. The output signals of the first and second A / D converters 24 and 25 are supplied to the input terminal of the difference circuit 26, and the output signal 27 of the solid-state imaging device is obtained at the output terminal.

  FIG. 9 is a graph showing output potentials of the first and second A / D converters 24 and 25 with respect to the amount of incident light. As can be seen from the figure, ADC1 and ADC2, which are output potentials of the first and second A / D converters 24 and 25, both increase in proportion to the amount of incident light, but their polarities are opposite to each other. For this reason, if the difference between the outputs of ADC1 and ADC2 is taken, the amplitude will be doubled at maximum compared to the case of the output of only the electrons.

  According to this embodiment, as in the first embodiment, a signal obtained by adding the output of the electron detection circuit 17 and the output of the hole detection circuit 23 is output as the output signal of the solid-state imaging device. Compared to the output of an electron alone, the maximum output is doubled.

  In addition, according to this embodiment, since both the electron detection circuit 17 and the hole detection circuit 23 can be configured by N-channel transistors, the device isolation region in the pixel formation region centered on the light receiving unit 12 is reduced. This can reduce the area of the solid-state imaging device.

  In this embodiment, the electron detection circuit 17 and the hole detection circuit 23 are configured by N-channel transistors, but these can also be configured by P-channel transistors.

It is a top view which shows the structure of the readout circuit of the image information photoelectrically converted and the light-receiving part corresponding to 1 pixel of the solid-state imaging device concerning the Example of this invention. FIG. 2 is a cross-sectional view taken along a broken line AA ′ in FIG. 1. It is sectional drawing for demonstrating operation | movement of the solid-state imaging device shown in FIG. It is sectional drawing for demonstrating operation | movement of the solid-state imaging device similarly shown in FIG. It is a top view which shows the structure of the light-receiving part corresponding to 1 pixel of the solid-state imaging device which concerns on the 2nd Embodiment of this invention, and the readout circuit of the photoelectrically converted image information. FIG. 6 is a cross-sectional view taken along a broken line BB ′ in FIG. 5. It is sectional drawing for demonstrating operation | movement of the solid-state imaging device shown in FIG. FIG. 6 is a cross-sectional view for explaining the operation of the solid-state imaging device shown in FIG. 5. FIG. 9 is a graph showing output potentials of the first and second A / D converters 24 and 25 with respect to the amount of incident light of the solid-state imaging device shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 12 ... Light-receiving part 13 ... Hole accumulation / transfer area 14 ... Electron transfer area 15 ... Gate oxide film 16 ... Transfer gate electrode 17 ... Electron detection circuit 18 ... Hole detection circuit 19 ... A / D converter

Claims (5)

  A first conductivity type semiconductor substrate, a second conductivity type hole accumulation / transfer region provided in a surface region of the semiconductor substrate, and a first conductivity type provided in the hole accumulation / transfer region A first conductivity type electron transfer region provided on a surface region in the hole accumulation / transfer region at a predetermined interval with respect to the light receiving region, and a surface of the semiconductor substrate. A gate oxide film, a first transfer gate electrode formed on the gate oxide film at a position corresponding to the space between the light receiving region and the hole accumulation / transfer region, and electrons connected to the electron transfer region A solid-state imaging device comprising: a detection circuit.   2. The device according to claim 1, further comprising: means for taking out holes accumulated in the hole accumulation / transfer region; and a hole detection circuit to which holes taken out by the means are supplied. Solid-state imaging device.   The electron detection circuit is composed of a first conductivity type MOS transistor, the hole detection circuit is composed of a second conductivity type MOS transistor, and the hole extraction means is connected to the hole accumulation / transfer region. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is a solid conductor.   The hole extraction means includes a second conductivity type hole transfer region formed in a surface region of the semiconductor substrate at a predetermined interval with respect to the hole accumulation / transfer region, and the hole transfer A channel region of a second conductivity type formed in a surface region of the semiconductor substrate between the region and the hole accumulation / transfer region, and the hole transfer region and the hole accumulation / transfer on the gate oxide film 3. The solid-state imaging device according to claim 2, comprising a second transfer gate electrode formed at a position corresponding to between the regions.   The electron detection circuit and the hole detection circuit are composed of first conductivity type MOS transistors, and one of the first transfer gate and the second transfer gate electrode is set to a high level potential and the other is set to a low level potential. 5. The solid-state imaging device according to claim 4, wherein a signal corresponding to the accumulated charge is read out by resetting to a reference signal potential.

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