JP4693183B2 - Method for manufacturing solid-state imaging device - Google Patents

Method for manufacturing solid-state imaging device Download PDF

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JP4693183B2
JP4693183B2 JP2007057403A JP2007057403A JP4693183B2 JP 4693183 B2 JP4693183 B2 JP 4693183B2 JP 2007057403 A JP2007057403 A JP 2007057403A JP 2007057403 A JP2007057403 A JP 2007057403A JP 4693183 B2 JP4693183 B2 JP 4693183B2
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diffusion layer
semiconductor substrate
floating diffusion
amplification transistor
forming
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JP2007150361A (en
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幹也 内田
誠之 松長
誠 稲垣
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パナソニック株式会社
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  The present invention relates to a method for manufacturing a solid-state imaging device including an area image sensor used for home video cameras, digital still cameras, mobile phone cameras, and the like.

  FIG. 13 is a circuit diagram showing a configuration of a conventional solid-state imaging device 90. Photosensitive cells 98 including photodiodes 95, transfer gates 96, amplification transistors 92, and reset transistors 97 are arranged in a matrix of 3 rows × 3 columns.

  The drains of the amplification transistor 92 and the reset transistor 97 are connected to the common drain line 306. The source of the amplification transistor 92 is connected to the vertical signal line 15 as shown in FIG. A load transistor 305 is connected to one end of the vertical signal line 15, and a noise suppression circuit 12 is connected to the other end. The output of the noise suppression circuit 12 is connected to a horizontal transistor 14 driven by a horizontal driver circuit 13. Each photosensitive cell 98 is driven by a vertical driver circuit 11.

  FIG. 14 is a plan view showing the configuration of the photosensitive cell 98 provided in the conventional solid-state imaging device 90. FIG. The signal of the photodiode 95 is read out to the floating diffusion layer 91 through the transfer gate 96. The signal converted in voltage in the floating diffusion layer 91 is applied from the floating diffusion layer contact 203 to the gate 304 of the amplification transistor 92. The source / drain of the amplification transistor 92 is connected to the common drain line 306 and the vertical signal line 15. The signal charge in the floating diffusion layer 91 is discharged to the common drain line 306 through the reset transistor 97.

  FIG. 15 is a cross-sectional view along the plane XYZW shown in FIG. A photodiode 95 including an n-type photodiode diffusion layer 402 and a p-type leak blocking layer 403 is formed on the P-type semiconductor substrate 9.

  The gate electrodes of the MOS transistors constituting the transfer gate 96, the reset transistor 97, and the amplification transistor 92 have a double structure of the polysilicon layer 406 and the salicide layer 407.

  The floating diffusion layer 91 has a salicide layer 407 on top of a double diffusion layer composed of an LDD diffusion layer 404 and a source / drain diffusion layer 405.

  The source / drain of the MOS transistor has a salicide layer 407 on top of a double diffusion layer composed of an LDD diffusion layer 404 and a source / drain diffusion layer 405. Since the salicide layer 407 does not transmit light, it is removed from the upper portion of the photodiode 301.

  16 to 19 are cross-sectional views illustrating a method for manufacturing the conventional solid-state imaging device 90. As shown in FIG. 16, after the element isolation layer 502 is formed on the semiconductor substrate 9, a resist 501 is formed in a predetermined pattern by a photolithography process, and an n-type photodiode diffusion layer 402 and a p-type leak prevention layer are formed by ion implantation. 403 is formed.

  Then, after removing the resist 501, as shown in FIG. 17, a polysilicon layer 406 to be a gate electrode of a MOS transistor constituting the transfer gate 96, the reset transistor 97 and the amplification transistor 92 is formed. Thereafter, a salicide block film 503 is formed so as to cover the photodiode 95, and then an LDD diffusion layer 404 is formed so as to be self-aligned with the polysilicon layer 406 by an ion implantation process.

Then, as shown in FIG. 18, an LDD oxide film 504 is deposited so as to cover the salicide block film 503, the polysilicon layer 406, and the LDD diffusion layer 404. Next, as shown in FIG. 19, when the LDD oxide film 504 is removed by anisotropic etching, part of the LDD oxide film 504 remains at both ends of the polysilicon layer 406 thickly deposited in the vertical direction. A source / drain diffusion layer 405 is formed so as to be self-aligned with the LDD oxide film. Thereafter, when a metal material such as titanium (Ti) and cobalt (Co) is deposited by a sputtering process and a thermal process is applied, only the exposed portions of the semiconductor substrate and polysilicon are reacted to salicide, and the salicide layer 407 is salicided. Remains.
JP-A-8-335688

  However, in the configuration of the photosensitive cell of the conventional solid-state imaging device described above, the floating diffusion layer 91 temporarily stores the signal of the photodiode 95. At this time, if there is a reverse leakage current of the pn junction in the floating diffusion layer 91, the signal is output. Superimpose noise.

  Since the signal charge stays shorter than the photodiode 95 that photoelectrically converts incident light and stores it, the pn-junction reverse leakage current is not as strict as the photodiode, but the method is the same as for the source and drain of other transistors. As a result, the pn junction reverse leakage current increases, which also causes serious noise. When this noise is large, the sensitivity of the solid-state imaging device is lowered, and the S / N ratio of the signal is deteriorated.

  An object of the present invention is to provide a method for manufacturing a solid-state imaging device with low noise and high sensitivity.

  A method for manufacturing a solid-state imaging device according to the present invention is a method for manufacturing a solid-state imaging device according to the present invention, comprising: forming the photodiode, the transfer transistor, and the amplification transistor on the semiconductor substrate; and Forming a resist in a predetermined pattern so as to cover the diode, the transfer transistor, and the amplification transistor; and implanting ions into the semiconductor substrate using the resist as a mask to form the floating diffusion layer; Removing the resist to form a salicide block film so as to cover the floating diffusion layer and the photodiode; forming a source / drain diffusion layer of the amplification transistor; Forming a salicide layer so as to cover the drain diffusion layer. And wherein the door.

  Another manufacturing method of the solid-state imaging device according to the present invention is a manufacturing method of the solid-state imaging device according to the present invention, in which a resist is formed in a predetermined pattern on the semiconductor substrate, and the photodiode is formed. For implanting ions using the resist as a mask, removing the resist, forming the transfer transistor and the amplification transistor on the semiconductor substrate, and a first salicide so as to cover the photodiode. Forming a block film; implanting ions into the semiconductor substrate to form the floating diffusion layer and the source / drain diffusion layer of the amplification transistor; and a second salicide to cover the floating diffusion layer. A step of forming a block film, and a salicide layer so as to cover the source / drain diffusion layer of the amplification transistor Characterized in that it comprises the step of forming.

  According to the manufacturing method of the solid-state imaging device, the salicide layer is not formed on the surface of the floating diffusion layer. Therefore, the reverse leakage current of the pn junction is reduced in the floating diffusion layer. As a result, a solid-state imaging device with low noise and high sensitivity can be obtained.

  In the solid-state imaging device manufacturing method of the present invention, it is preferable that the impurity concentration of the floating diffusion layer is lower than the impurity concentration of the source / drain diffusion layer of the amplification transistor.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a solid-state imaging device 100 according to the present embodiment. Photosensitive cells 8 constituted by photodiodes 5, transfer gates 6, amplification transistors 2 and reset transistors 7 are arranged in a matrix of 3 rows × 3 columns.

  The drains of the amplification transistor 2 and the reset transistor 7 are connected to the common drain line 306. The source of the amplification transistor 2 is connected to the vertical signal line 15 as shown in FIG. A load transistor 305 is connected to one end of the vertical signal line 15, and a noise suppression circuit 12 is connected to the other end. The output of the noise suppression circuit 12 is connected to a horizontal transistor 14 driven by a horizontal driver circuit 13. Each photosensitive cell 8 is driven by a vertical driver circuit 11.

  FIG. 2 is a plan view showing a configuration of the photosensitive cell 8 provided in the solid-state imaging device 100. The signal of the photodiode 5 is read out to the floating diffusion layer 1 through the transfer gate 6. The voltage-converted signal in the floating diffusion layer 1 is applied to the gate 304 of the amplification transistor 2 from the floating diffusion layer contact 203. The source / drain of the amplification transistor 2 is connected to the common drain line 306 and the vertical signal line 15. The signal charge in the floating diffusion layer 1 is discharged to the common drain line 306 through the reset transistor 7.

  3-5 is sectional drawing which shows the manufacturing method of the solid-state imaging device 100 which concerns on this Embodiment. Referring to FIG. 3, a polysilicon layer 406 of the gate electrode of the MOS transistor constituting the transfer gate 6, the reset transistor 7 and the amplification transistor 2 is formed. Thereafter, a resist 701 formed so as to leave a portion that becomes a floating diffusion layer is formed by a photolithography process. Then, the low concentration floating diffusion layer 1 is formed by ion implantation using the resist 701 as a mask.

  Referring to FIG. 4, after that, a salicide block film 503 is formed so as to cover the photodiode 5 and the floating diffusion layer 1.

  Referring to FIG. 5, thereafter, the source / drain layer 3 and the salicide layer 4 are formed by the same method as the above-described conventional technique.

  FIG. 6 is a graph showing the frequency of junction leakage current in the solid-state imaging device 100. The horizontal axis indicates the magnitude of the junction leakage current, and the vertical axis indicates the number of pn junction floating diffusion layers indicating the junction leakage current on the horizontal axis. The distribution indicated by the dark solid line 601 indicates the distribution in which the salicide layer 4 is formed on the floating diffusion layer 1, and the thin dotted line 602 indicates that the salicide layer 4 is not formed on the floating diffusion layer 1. Distribution is shown. In the case where the salicide layer 4 is formed, the distribution is not only moved to the larger junction leakage current as compared with the case where the salicide layer 4 is not formed, but also the local junction leakage current is very high. There is a large distribution 603 of. This becomes a point defect in a solid-state imaging device and becomes a defective product.

FIG. 7 is a graph showing the relationship between the impurity concentration of the floating substance diffusion layer 1 and the junction leakage current in the solid-state imaging device 100. The horizontal axis indicates the impurity concentration of the suspended matter diffusion layer 1, and the vertical axis indicates the junction leakage current. When the impurity concentration of the floating substance diffusion layer 1 becomes 1 × 10 18 cm −3 or more, the junction leakage current increases rapidly.

  As described above, according to the present embodiment, the source / drain diffusion layer 3 provided in the amplification transistor 2 is covered with the salicide layer 4 so that the floating diffusion layer 1 is exposed on the surface of the semiconductor substrate 9. Is formed. For this reason, the salicide layer 4 is not formed on the surface of the floating diffusion layer 1. Therefore, the reverse leakage current of the pn junction in the floating diffusion layer 1 is reduced. As a result, a solid-state imaging device with low noise and high sensitivity can be obtained.

  8-10 is sectional drawing which shows the other manufacturing method of the solid-state imaging device based on this Embodiment. The same components as those described above with reference to FIGS. 3 to 5 are denoted by the same reference numerals. Therefore, detailed description of these components is omitted.

  Referring to FIG. 8, an LDD diffusion layer is formed in the same manner as in FIGS. 4 and 5 described above. Referring to FIG. 9, the second salicide block film 801 is formed so as to cover the floating diffusion layer 1. Referring to FIG. 10, thereafter, the source / drain layer 3 and the salicide layer 4 are formed by the same method as the above-described conventional technique.

  FIG. 11 is a plan view showing a configuration of a main part of another solid-state imaging device according to the present embodiment. The same components as those described above with reference to FIG. 2 are denoted by the same reference numerals. Therefore, detailed description of these components is omitted.

  Instead of removing the salicide layer in all the regions of the floating diffusion layer 1 to lower the diffusion layer impurity concentration, the salicide layer may be removed in some regions to lower the diffusion layer impurity concentration. In FIG. 11, it is effective to reduce the concentration by removing the salicide layer except for the periphery 901 of the contact portion 203 of the floating diffusion layer 1.

  FIG. 12 is a circuit diagram showing a configuration of a dynamic logic circuit provided in the solid-state imaging device according to the present embodiment. Since CMOS logic has become the mainstream of semiconductors in recent years, MOS type imaging devices are often composed of CMOS logic. In CMOS logic, the process is long and the process is determined by miniaturization, and it is very difficult to change the process for the sensor.

  In particular, it is difficult to operate a p-type channel transistor in a miniaturized process. The reason is that boron, which is a p-type impurity, is light and easy to move, so it is difficult to make it small inside the semiconductor. Therefore, in order to produce a manufacturing process peculiar to a sensor using a particularly miniaturized transistor, it is advantageous to configure only with NMOS.

  When an NMOS-only circuit is used, the power consumption is generally larger than that of a CMOS, so a circuit called dynamic logic is used. This dynamic logic circuit performs an operation called booting in which the voltage is increased by the capacitance of the MOS, but the MOS capacitance portion also does not operate when the leakage current increases. That is, it exactly matches the purpose of reducing the leakage current of the present invention.

  In particular, an image sensor applied to a digital still camera in recent years includes a mode in which long-time exposure is performed so as to operate very slowly. Therefore, element isolation with a low leakage current is indispensable also in an NMOS dynamic logic circuit. An example of a shift register circuit constituted by a dynamic logic circuit is shown in FIG. Although description of the operation is omitted here, if the leakage current of the MOS capacitor 902 is large, the operation cannot be performed slowly. It is very effective to use the element isolation of the present invention for element isolation of the MOS capacitor 902.

  That is, when a solid-state imaging device is miniaturized, when establishing a low-leakage current technology aiming at high performance such as element isolation, a p-ch that is difficult to make a fine transistor is eliminated, and only an N-chMOS is used. In order to design a dynamic logic circuit for the same low power consumption, it is essential to reduce the leakage current. Fine transistors, n-channel only MOS, low-leakage element isolation, and dynamic logic circuits are on the shortest course for realizing a high-performance solid-state imaging device.

  According to the present invention, it is possible to manufacture a solid-state imaging device with low noise and high sensitivity.

The circuit diagram which shows the structure of the solid-state imaging device concerning this Embodiment The top view which shows the structure of the principal part of the solid-state imaging device concerning this Embodiment. Sectional drawing which shows the manufacturing method of the solid-state imaging device concerning this Embodiment Sectional drawing which shows the manufacturing method of the solid-state imaging device concerning this Embodiment Sectional drawing which shows the manufacturing method of the solid-state imaging device concerning this Embodiment Graph showing the frequency of junction leakage current in the solid-state imaging device according to the present embodiment The graph which shows the relationship between the impurity concentration of a floating substance diffusion layer and junction leakage current in the solid-state imaging device concerning this embodiment Sectional drawing which shows the other manufacturing method of the solid-state imaging device concerning this Embodiment. Sectional drawing which shows the other manufacturing method of the solid-state imaging device concerning this Embodiment. Sectional drawing which shows the other manufacturing method of the solid-state imaging device concerning this Embodiment. The top view which shows the structure of the principal part of the other solid-state imaging device concerning this Embodiment. The circuit diagram which shows the composition of the dynamic logic circuit provided in the solid-state image sensing device concerning this embodiment Circuit diagram showing configuration of conventional solid-state imaging device The top view which shows the structure of the principal part of the conventional solid-state imaging device Sectional drawing which shows the structure of the conventional solid-state imaging device Sectional drawing which shows the manufacturing method of the conventional solid-state imaging device Sectional drawing which shows the manufacturing method of the conventional solid-state imaging device Sectional drawing which shows the manufacturing method of the conventional solid-state imaging device Sectional drawing which shows the manufacturing method of the conventional solid-state imaging device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Floating diffusion layer 2 Amplification transistor 3 Source drain layer 4 Salicide layer 5 Photodiode 6 Transfer transistor 7 Reset transistor 8 Photosensitive cell 9 Semiconductor substrate 11 Vertical driver 12 Noise suppression circuit 13 Horizontal driver circuit 14 Horizontal transistor 15 Vertical signal line 16 Dynamic logic Circuit 100 Solid-state imaging device

Claims (4)

  1. A plurality of photosensitive cells arranged in a matrix in a photosensitive region on a semiconductor substrate, and each photosensitive cell is exposed on the surface of the semiconductor substrate to accumulate signal charges obtained by photoelectrically converting incident light. A photodiode formed in such a manner, a transfer transistor formed on the semiconductor substrate for transferring the signal charge accumulated by the photodiode, and temporarily storing the signal charge transferred by the transfer transistor A solid-state imaging device having a floating diffusion layer formed on the semiconductor substrate and an amplification transistor formed on the semiconductor substrate to amplify the signal charge temporarily stored in the floating diffusion layer A manufacturing method comprising:
    Forming the photodiode, the gate electrode of the transfer transistor, and the gate electrode of the amplification transistor on the semiconductor substrate;
    Forming a resist in a pattern covering the photodiode, the transfer transistor formation region and the amplification transistor formation region and having an opening in the floating diffusion layer formation region;
    Implanting ions into the semiconductor substrate using the resist as a mask to form the floating diffusion layer;
    Forming a salicide block film so as to cover the floating diffusion layer and the photodiode after removing the resist;
    Forming an LDD diffusion layer of the amplification transistor;
    Forming a source / drain diffusion layer of the amplification transistor;
    And a step of forming a salicide layer so as to cover the source / drain diffusion layer of the amplification transistor.
  2.   2. The method of manufacturing a solid-state imaging device according to claim 1, wherein an impurity concentration of the floating diffusion layer is lower than an impurity concentration of a source / drain diffusion layer of the amplification transistor.
  3. A plurality of photosensitive cells arranged in a matrix in a photosensitive region on a semiconductor substrate, and each photosensitive cell is exposed on the surface of the semiconductor substrate to accumulate signal charges obtained by photoelectrically converting incident light. A photodiode formed in such a manner, a transfer transistor formed on the semiconductor substrate for transferring the signal charge accumulated by the photodiode, and temporarily storing the signal charge transferred by the transfer transistor A solid-state imaging device having a floating diffusion layer formed on the semiconductor substrate and an amplification transistor formed on the semiconductor substrate to amplify the signal charge temporarily stored in the floating diffusion layer A manufacturing method comprising:
    Forming a resist in a predetermined pattern on the semiconductor substrate;
    Implanting ions using the resist as a mask to form the photodiode;
    Removing the resist and forming a gate electrode of the transfer transistor and a gate electrode of the amplification transistor on the semiconductor substrate;
    Forming a first salicide block film so as to cover the photodiode;
    Implanting ions into the semiconductor substrate to form the floating diffusion layer and the LDD diffusion layer of the amplification transistor;
    Forming a second salicide block film so as to cover the floating diffusion layer;
    Forming a source / drain diffusion layer of the amplification transistor;
    And a step of forming a salicide layer so as to cover the source / drain diffusion layer of the amplification transistor.
  4.   The method of manufacturing a solid-state imaging device according to claim 3, wherein an impurity concentration of the floating diffusion layer is lower than an impurity concentration of a source / drain diffusion layer of the amplification transistor.
JP2007057403A 2007-03-07 2007-03-07 Method for manufacturing solid-state imaging device Expired - Fee Related JP4693183B2 (en)

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US7932120B2 (en) 2008-08-28 2011-04-26 Samsung Electronics Co., Ltd. Methods of manufacturing CMOS image sensors
JP5422455B2 (en) * 2010-03-23 2014-02-19 パナソニック株式会社 Solid-state imaging device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10257389A (en) * 1997-03-11 1998-09-25 Toshiba Corp Amplifier-type solid-state image-pickup unit and operating method therefor
JP2001111022A (en) * 1999-08-05 2001-04-20 Canon Inc Photoelectric conversion device and method of fabrication thereof, image information processor
JP2001345439A (en) * 2000-03-28 2001-12-14 Toshiba Corp Solid-state image sensing device and its manufacturing method
JP2002190586A (en) * 2000-12-22 2002-07-05 Mitsubishi Electric Corp Solid-state image pickup device and method of manufacturing the same
JP2002270808A (en) * 2001-03-13 2002-09-20 Matsushita Electric Ind Co Ltd Mos-type image sensor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10257389A (en) * 1997-03-11 1998-09-25 Toshiba Corp Amplifier-type solid-state image-pickup unit and operating method therefor
JP2001111022A (en) * 1999-08-05 2001-04-20 Canon Inc Photoelectric conversion device and method of fabrication thereof, image information processor
JP2001345439A (en) * 2000-03-28 2001-12-14 Toshiba Corp Solid-state image sensing device and its manufacturing method
JP2002190586A (en) * 2000-12-22 2002-07-05 Mitsubishi Electric Corp Solid-state image pickup device and method of manufacturing the same
JP2002270808A (en) * 2001-03-13 2002-09-20 Matsushita Electric Ind Co Ltd Mos-type image sensor

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