WO2021033454A1 - Semiconductor device and electronic apparatus - Google Patents

Semiconductor device and electronic apparatus Download PDF

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Publication number
WO2021033454A1
WO2021033454A1 PCT/JP2020/026908 JP2020026908W WO2021033454A1 WO 2021033454 A1 WO2021033454 A1 WO 2021033454A1 JP 2020026908 W JP2020026908 W JP 2020026908W WO 2021033454 A1 WO2021033454 A1 WO 2021033454A1
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semiconductor layer
semiconductor device
region
back gate
gate terminal
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PCT/JP2020/026908
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French (fr)
Japanese (ja)
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場色　正昭
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2021033454A1 publication Critical patent/WO2021033454A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the technology according to the present disclosure (the present technology) relates to a technology for reducing random noise such as a MOS field effect transistor (MOSFET) suitable for a solid-state image sensor represented by a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
  • MOSFET MOS field effect transistor
  • CMOS Complementary Metal Oxide Semiconductor
  • Examples of the solid-state image sensor that captures an image include a CCD (Charge Coupled Device) image sensor and a CMOS image sensor.
  • CCD Charge Coupled Device
  • CMOS image sensors that can be manufactured by existing CMOS processes without requiring special capital investment have attracted attention, and are rapidly being adopted in camera systems and surveillance systems built into mobile phones. It is progressing.
  • the CMOS image sensor has an AD conversion unit that AD (Analog to Digital) converts an analog electrical signal output by a pixel that performs photoelectric conversion.
  • the AD conversion unit of the CMOS image sensor can perform AD conversion in parallel to electrical signals output by two or more pixels, such as all of a plurality of pixels lined up in a row, in response to a request for high-speed processing.
  • a type AD conversion unit (hereinafter, also referred to as “column parallel AD conversion unit”) is adopted.
  • the column-parallel AD converter is configured by, for example, arranging a plurality of analog-to-digital converters (ADCs) having the same number of pixels as the number of columns arranged side by side in the row direction.
  • the ADC in each row performs AD conversion of the electrical signal output by the pixels in that row.
  • the ADC constituting the column-parallel AD conversion unit includes, for example, a comparator and a counter, and AD conversion of an electric signal is performed by comparing a predetermined reference signal with an electric signal output by a pixel. There is a so-called reference signal comparison type ADC that is performed.
  • a reference signal comparison type ADC for example, there is a single slope type ADC (see Patent Document 1).
  • a single-slope ADC a differential input transistor composed of MOSFETs and a comparator consisting of an active load compare a reference signal whose level changes with a constant inclination such as a lamp signal and a pixel signal output by a pixel. By counting the time required for the level of the reference signal to change until the levels of the reference signal and the electric signal match in the counter, the electric signal output by the pixel is AD-converted.
  • the lander noise of the MOSFET is almost determined by flicker noise (1 / f noise), random telegraph noise (RTN), and thermal noise (see Non-Patent Document 1). Of these, the flicker noise and RTN noise levels are known to be inversely proportional to the gate electrode area of the MOSFET.
  • the MOSFET that is the noise source has a multi-finger structure in which multiple MOSFETs are connected in parallel, and the gate electrode area of the entire MOSFET is increased to increase flicker noise and RTN. It is possible to reduce the temporal variation of the sensed image data (see Patent Document 2).
  • CMOS image sensors As the application of CMOS image sensors to various fields progresses, miniaturization and higher performance are required.
  • One of the requirements is to reduce the noise of the CMOS image sensor, but the means of increasing the gate electrode area of the MOSFET, which is the noise source, also increases the circuit area, making it difficult to achieve both miniaturization of the sensor. .. against this background, there is a demand for a technique for reducing noise without increasing the circuit area. In response to such a requirement, a structure in which the gate electrode and the back gate are electrically shared is disclosed (see Patent Document 3).
  • the purpose of this technology is to provide semiconductor devices and electronic devices that achieve both low noise and miniaturization without complicating the manufacturing process.
  • the semiconductor device is provided on the first semiconductor layer and the first semiconductor layer, and is opposite to the first semiconductor layer and has first and second main electrode regions, and first and second.
  • a gate electrode provided on a channel region sandwiched between the main electrode regions and a back gate terminal electrically connected to the gate electrode are provided, and the first and second main electrode regions and the back gate terminal are separated from each other.
  • the gist is that they are in the same active region partitioned by regions.
  • the electronic devices according to one aspect of the present technology are provided on the first semiconductor layer and the first semiconductor layer, and are opposite to the first semiconductor layer and have first and second main electrode regions, and first and second main electrode regions. It has a semiconductor device including a gate electrode provided on a channel region sandwiched between main electrode regions and a back gate terminal electrically connected to the gate electrode, and has first and second main electrode regions and a back gate.
  • the gist is that the terminals are in the same active region partitioned by the element separation region.
  • the "first main electrode region" of the semiconductor device constituting the semiconductor device including the solid-state imaging device is an insulated gate type field effect transistor (MISFET) such as a MOSFET or an insulated gate type electrostatic induction transistor (MISSIT). ) Or a semiconductor region that is either a source region or a drain region such as a high electron mobility transistor (HEMT).
  • the “second main electrode region” means a semiconductor region such as a MISFET that is either a source region or a drain region that does not become the first main electrode region. As described above, when the "first main electrode region” is the source region, the "second main electrode region” means the drain region.
  • first conductive type means one of the p-type or the n-type
  • second conductive type means one of the p-type or the n-type different from the “first conductive type”.
  • third conductive type means one of the p-type or the n-type different from the “first conductive type”.
  • the definition of the vertical direction in the following description is merely a definition for convenience of explanation, and does not limit the technical idea of the present technology. For example, if the object is rotated by 90 ° and observed, the top and bottom are converted to left and right and read, and if the object is rotated by 180 ° and observed, the top and bottom are reversed and read.
  • the solid-state image sensor 100 includes a pixel array unit 110 and peripheral circuits for reading an electric signal from the pixel array unit 110 and performing predetermined signal processing.
  • the solid-state image sensor 100 generates a row selection circuit 120 for controlling row addresses and row scans, a horizontal transfer scanning circuit 130 for controlling column addresses and column scans, and an internal clock as control circuits.
  • the timing control circuit 140 is provided.
  • the solid-state imaging device 100 according to the first embodiment includes an ADC group 150 as peripheral circuits, a digital-to-analog converter (DAC) 160 as a lamp signal generator, an amplifier circuit 170, a signal processing circuit 180, and horizontal transfer. It has a line 190.
  • the solid-state image sensor 100 according to the first embodiment has a DC power supply circuit (not shown) as a peripheral circuit.
  • the pixel array unit 110 is configured by arranging a large number of pixels 30 in an array shape (matrix shape).
  • the pixel 30 has, for example, a photoelectric conversion element D1 made of, for example, a photodiode (PD), as shown in FIG.
  • the pixel 30 has four transistors, a transfer transistor T1, a reset transistor T2, an amplification transistor T3, and a selection transistor T4, as active elements with respect to the photoelectric conversion element D1.
  • the constant current source load 31 is connected to the vertical signal line (LSGN) in which the pixel 30 is shared in the column direction.
  • LSGN vertical signal line
  • the photoelectric conversion element D1 photoelectrically converts the incident light into an electric charge (electrons in this case) in an amount corresponding to the amount of the light.
  • the transfer transistor T1 as a transfer element is connected between the photoelectric conversion element D1 and the floating diffusion FD as an input node, and a transfer signal TRG which is a control signal is given to the gate (transfer gate) through the transfer control line LTRG. .. As a result, the transfer transistor T1 transfers the electrons photoelectrically converted by the photoelectric conversion element D1 to the floating diffusion FD.
  • the reset transistor T2 is connected between the power supply line L VDD to which the power supply voltage VDD is supplied and the floating diffusion FD, and the reset signal RST, which is a control signal, is given to the gate through the reset control line LRST.
  • the reset transistor T2 as the reset element resets the potential of the floating diffusion FD to the potential of the power supply line L VDD.
  • the gate of the amplification transistor T3 as an amplification element is connected to the floating diffusion FD. That is, the floating diffusion FD functions as an input node of the amplification transistor T3 as an amplification element.
  • the amplification transistor T3 and the selection transistor T4 are connected in series between the power supply line L VDD to which the power supply voltage VDD is supplied and the signal line LSGN. In this way, the amplification transistor T3 is connected to the signal line LSGN via the selection transistor T4, and constitutes a constant current source IS outside the pixel portion and a source follower.
  • the selection signal SEL which is a control signal corresponding to the address signal
  • the selection transistor T4 is turned on.
  • the amplification transistor T3 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the signal line LSGN.
  • the voltage output from each pixel through the signal line LSGN is output to the ADC group 150. Since, for example, the gates of the transfer transistor T1, the reset transistor T2, and the selection transistor T4 are connected in row units, these operations are performed simultaneously for each pixel for one row.
  • the reset control line LRST, the transfer control line LTRG, and the selection control line LSEL wired to the pixel array unit 110 are wired as a set for each row of the pixel array.
  • the reset control line LRST, the transfer control line LTRG, and the selection control line LSEL are each provided with M lines. These reset control line LRST, transfer control line LTRG, and selection control line LSEL are driven by the row selection circuit 120.
  • the comparator 151 has a differential amplifier circuit including differential input transistors T21 and T22 forming a differential pair and active load transistors T11 and T12 including a current mirror circuit.
  • the differential input transistors T21 and T22 are composed of n-type MOSFETs (hereinafter, also referred to as “nMOS”), and the active load transistors T11 and T12 are composed of p-type MOSFETs (hereinafter, also referred to as “pMOS”).
  • nMOS n-type MOSFETs
  • pMOS p-type MOSFETs
  • the active load transistors T11 and T12 and the differential input transistors T21 and T22 serve as noise sources.
  • the comparator 151 includes a reference voltage (DAC side input) Vslop, which is a ramp waveform obtained by changing the reference voltage generated by the DAC 160 in a stepwise manner, and an analog signal obtained from a pixel via the vertical signal line LSGN for each line. (VSL (Vertical Signal Line) side input) is compared.
  • VSL Very Signal Line
  • the counter 152 shown in FIG. 1 counts the comparison time of the comparator 151.
  • the ADC group 150 has an n-bit digital signal conversion function and is arranged for each vertical signal line (row line) to form a row-parallel ADC block.
  • the output of each latch 153 is connected to, for example, a horizontal transfer line 190 having a width of 2 n bits. Then, 2n amplifier circuits 170 and signal processing circuits 180 corresponding to the horizontal transfer lines 190 are arranged.
  • FIG. 5 shows a layout diagram of each circuit constituting the solid-state image sensor according to the first embodiment on the semiconductor chip.
  • the pixel array unit 201, the constant current source load 205, the comparator 206, the counter / latch circuit 207, and the horizontal transfer scanning circuit 208 are arranged from the upper side to the lower side.
  • a row selection circuit 202 is arranged adjacent to the pixel array unit 201.
  • the DAC 203 is arranged adjacent to the constant current source load 205 and the comparator 206.
  • a timing control circuit 204 is arranged adjacent to the counter / latch circuit 207 and the horizontal transfer scanning circuit 208.
  • a DC supply circuit 209 is arranged adjacent to the pixel array unit 201. Further, a signal processing circuit 210 is arranged adjacent to the pixel array unit 201, the constant current source load 205, the comparator 206, the counter / latch circuit 207, and the horizontal transfer scanning circuit 208.
  • Each circuit constituting the solid-state imaging device according to the first embodiment is configured by connecting semiconductor devices such as photodiodes, MOSFETs, bipolar transistors, resistance elements, and capacitive elements formed on a semiconductor substrate with multilayer wiring.
  • semiconductor devices such as photodiodes, MOSFETs, bipolar transistors, resistance elements, and capacitive elements formed on a semiconductor substrate with multilayer wiring.
  • a general CMOS process can be adopted as a method for forming each circuit constituting the solid-state image sensor according to the first embodiment on the semiconductor substrate.
  • an n-type well 2 and a p-type well 3 are provided on the p-type semiconductor substrate 1.
  • An STI region 4 is provided in a part of the upper part of the p-type well 3, and the active regions A1 and A2 are respectively partitioned by the STI region 4.
  • an n + type source region 11 and an n + type drain region 12 of the MOSFET are provided above the p-type well 3.
  • a p + type back gate terminal 13 is provided above the p type well 3.
  • Svg gate input conversion noise
  • the applied structure is shown in FIGS. 9 and 10.
  • the column-parallel AD conversion circuit one AD conversion circuit (column circuit) is arranged for each column of the pixel array unit 110. Therefore, as shown in FIG. 1, the column circuits are arranged at arbitrary intervals (column circuits) in the horizontal direction. It is repeatedly arranged at the column pitch).
  • the differential input transistors constituting the comparator are also repeatedly arranged at equal intervals.
  • the p-type well 3 needs to be electrically separated between the columns.
  • N-type well 2 is provided in order to electrically separate the p-type well 3 between columns.
  • an n-type well 17 is provided directly below the STI region 4 between the p-type wells 3 between the columns.
  • the n-type well 17 can usually be formed by ion-implanting n-type impurities into the semiconductor substrate 1 and then performing heat treatment to activate the impurities, but the width W1 of the n-type well 17 is reduced to a certain width or less. If this happens, the pressure resistance between the p-type wells 3 adjacent to the n-type well 17 will drop sharply. When the withstand voltage characteristic deteriorates, a leak current flows between the column circuits, which causes a defective operation. In order to keep the withstand voltage above a certain level, it is necessary to increase the impurity concentration of the n-type well 17. However, since high-temperature heat treatment is performed after ion implantation, it is difficult to form an n-type well 17 that is deep from the Si substrate surface, has a high impurity concentration, and has a narrow width W1.
  • Patent Document 3 discloses a technique for improving the withstand voltage between wells between adjacent MOSFETs in a layout in which MOSFETs are repeatedly arranged at narrow intervals.
  • this technique as shown in FIG. 11, with respect to the n-type well 2 that separates the p-type semiconductor substrate 1 and the p-type well (back gate) 3, the joint surface between the p-type well 3 and the n-type well 2 is formed. It is formed so as to be shallower than the bottom surface of the STI region 4.
  • the distance between the adjacent p-type wells 3 (shown by the broken line arrow) can be increased, so that the element separation withstand voltage can be improved as compared with the structures shown in FIGS. 9 and 10. Can be done.
  • the STI region 4 becomes a wall, and it becomes impossible to secure a path for pulling out the p-type well 3 constituting the back gate to the upper surface of the semiconductor substrate 1.
  • the depth of the STI region 4x that is a wall is formed to be shallower than that of the surrounding STI region 4, so that the shallow STI region 4x A structure is adopted in which the back gate is taken out on the upper surface of the semiconductor substrate 1 by passing under the bottom.
  • the semiconductor device according to the first embodiment includes a semiconductor substrate 1 made of a p-type Si substrate and an n-type well which is an n-type semiconductor layer provided on the semiconductor substrate 1. 2 and a p-type well 3 which is a p-type semiconductor layer provided on the n-type well 2 are provided.
  • the n-type well 2 has a function of separating the semiconductor substrate 1 and the p-type well 3.
  • the p-type well 3 functions as a back gate region.
  • the p-type well 3 is provided with an n + type source region 11 and an n + type drain region 12 separated from each other.
  • a gate electrode 5 is provided on the channel region sandwiched between the source region 11 and the drain region 12 via a gate insulating film (not shown).
  • a gate insulating film not shown.
  • the material of the gate electrode 5 polysilicon having a high impurity concentration can be used, and a metal material other than polysilicon can also be used.
  • the p-type well 3 is provided with a p + type back gate terminal 13 separated from the source region 11 and the drain region 12.
  • the back gate terminal 13 is composed of a well tap region having a higher impurity concentration than the p-type well 3.
  • the STI region 4 is not interposed between the back gate terminal 13 and the source region 11 and the drain region 12. That is, the back gate terminal 13, the source region 11, and the drain region 12 are provided in the same active region A0 surrounded by the STI region 4.
  • the joint surface between the n-type well 2 and the p-type well 3 is provided so as to be shallower than the STI region 4 and deeper than the source region 11 and the drain region 12. Therefore, the electrical withstand voltage between the MOSFETs constituting the adjacent comparator 151 is secured.
  • metal contacts 31 and 32 are arranged on the source region 11.
  • Metal contacts 33 and 34 are arranged on the drain region 12.
  • a metal contact 35 is arranged on the gate electrode 5.
  • Metal contacts 36 and 37 are arranged on the back gate terminal 13.
  • the back gate terminal 13 is electrically common (same potential) as the gate electrode 5. Although not shown, the back gate terminal 13 is electrically connected to the gate electrode 5 via metal contacts such as metal contacts 35, 36, 37 and multi-layer wiring. As shown in FIG. 14, the source region 11, the drain region 12, and the upper portions of the back gate terminal 13 are provided with the VDD layers 21, 22, and 23, respectively.
  • the material of the silicide layers 21, 22, and 23 is, for example, cobalt (Co) silicide or nickel (Ni) silicide. In the plane layout of FIG. 13, the silicide layers 21, 22, 23 and the multilayer wiring shown in FIG. 14 are omitted.
  • a separation film (0045 block layer) 6 is provided on the p-type well 3 sandwiched between the source region 11 and the back gate terminal 13.
  • the separation membrane 6 has a function of preventing the formation of a silicide layer directly under the separation membrane 6 and preventing a short circuit between the source region 11 and the drain region 12 and the back gate terminal 13 via the silicide layer.
  • a silicide process for reducing the contact resistance between the semiconductor substrate 1 made of Si and the metal contacts 31 to 36 is generally used, but when this process is used, it is made of Si not covered by the STI region 4. With respect to the surface of the semiconductor substrate 1, all the regions where the separation layer 6 for preventing the formation of VDD is not arranged are silicidized.
  • the separation membrane 6 is made of the same material as the gate electrode 5, for example, and can be formed at the same time as the gate electrode 5.
  • the gate electrode 5 is often a conductor such as polycrystalline Si, and the separation membrane 6 is made of a metal contact, wiring, etc. (not shown) so that the potential does not fluctuate. It is preferable to electrically connect to the semiconductor substrate 1 or the like to fix the potential.
  • the separation membrane 6 may have a laminated structure of a layer of the same material as the gate electrode 5 and a gate insulating film (not shown).
  • the separation membrane 6 can also use an insulating material such as a nitride or a silicon (Si) -based oxide such as silicon dioxide (SiO 2).
  • an insulating material such as a nitride or a silicon (Si) -based oxide such as silicon dioxide (SiO 2).
  • the source region 11 and drain region 12 of the MOSFET and the back gate terminal 13 are provided in the same active region A0 surrounded by the STI region 4. Therefore, as compared with the structure shown in FIG. 12, the back gate terminal 13 can be provided without partially changing the depth of the STI region 4, which facilitates the manufacturing process. Further, the semiconductor device according to the first embodiment has a structure suitable for miniaturization of a circuit because a withstand voltage between wells between adjacent MOSFETs can be secured. Therefore, it is possible to achieve both low noise and miniaturization of the circuit without increasing the manufacturing cost.
  • the semiconductor device according to the first embodiment is suitable for a MOSFET as a noise source among the MOSFETs constituting the solid-state image sensor.
  • the semiconductor device according to the first embodiment by applying the semiconductor device according to the first embodiment to the differential input transistors T21 and T22 of the comparator 151 shown in FIG. 4, the random noise of the peripheral circuit is reduced by about 13% with respect to the conventional structure. I confirmed that I could do it.
  • the semiconductor device according to the first modification of the first embodiment is different from the semiconductor device according to the first embodiment shown in FIG. 14 in that the semiconductor device is composed of pMOS.
  • the semiconductor device according to the first modification of the first embodiment includes a p-type semiconductor substrate 1 and an n-type well 7 which is an n-type semiconductor layer provided on the semiconductor substrate 1.
  • a p + type source region 41 and a p + type drain region 42 are provided above the n-type well 7.
  • a gate electrode 5 is provided on the channel region sandwiched between the source region 41 and the drain region 42 via a gate insulating film (not shown).
  • the joint surface between the n-type well 7 and the semiconductor substrate 1 is shallower than the STI region 4 and deeper than the source region 41 and the drain region 42.
  • n + type back gate terminal 43 is provided above the n-type well 7 so as to be separated from the source region 41 and the drain region 42.
  • the back gate terminal 43 is composed of a well tap region having a higher impurity concentration than the n-type well 7.
  • the back gate terminal 43 is electrically connected to the gate electrode 5 and has the same potential.
  • the STI region 4 does not intervene between the back gate terminal 43 and the source region 41 and the drain region 42. That is, the back gate terminal 43, the source region 41, and the drain region 42 are provided in the same active region A0 surrounded by the STI region 4.
  • a separation membrane 6 is provided on the n-type well 7 between the back gate terminal 43 and the source region 41 and the drain region 42.
  • Silicide layers 21, 22, and 23 are provided above the back gate terminal 43, the source region 41, and the drain region 42, respectively. When the salicide step is not carried out in the CMOS process, the silicide layers 21, 22, and 23 may not be provided. Since other configurations of the semiconductor device according to the first modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
  • the semiconductor device even when the semiconductor device is composed of pMOS, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment. ..
  • the semiconductor device according to the second modification of the first embodiment is an n-type semiconductor device provided between the p-type semiconductor substrate 1 and the n-type well (backgate region) 7. It differs from the semiconductor device according to the first embodiment shown in FIG. 14 in that it further includes an n-type well 8 which is a semiconductor layer and a p-type well 9 which is a p-type semiconductor layer.
  • the joint surface between the n-type well 7 and the p-type well 9 is provided at a position shallower than the STI region 4 and deeper than the source region 11 and the drain region 12.
  • a circuit that produces noise may be surrounded by wells to ensure strong electrical separation so that signal interference does not occur between the circuits formed on the semiconductor substrate 1.
  • the n-type well 8 electrically separates the semiconductor substrate 1 and the n-type well 7.
  • the p-type well 9 electrically separates the n-type well 8 and the n-type well 7. Since other configurations of the semiconductor device according to the second modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
  • An n-type semiconductor substrate may be used instead of the p-type semiconductor substrate 1.
  • a p-type well, an n-type well, and a p-type well are provided on an n-type semiconductor substrate, and an n + type source region and n + are provided in the p-type well (back gate region).
  • a mold drain region and a p + type backgate terminal may be provided.
  • a p-type well and an n-type well (back gate region) are provided on the n-type semiconductor substrate, and the p + type source region, p + type drain region, and n are provided in the n-type well (back gate region).
  • a + type back gate terminal may be provided.
  • the semiconductor device according to the third modification of the first embodiment does not have a well-tap region (diffusion layer) having a high impurity concentration constituting the back gate terminal 13a, as shown in FIG. It is different from the semiconductor device according to the first embodiment.
  • the back gate terminal 13a sandwiches the p-type well 3 directly under the separation membrane 6 together with the source region 11. It is composed of a part. Since other configurations of the semiconductor device according to the third modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
  • the semiconductor device instead of forming the back gate terminal 13a with a well tap region (diffusion layer) having a high impurity concentration for lowering the resistance, the p-type well 3 Even when it is composed of a part of the above, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment. Further, since there is no well-tapped region (diffusion layer) having a high impurity concentration opposite to that of the source region 11 in the vicinity of the source region 11, the bonding capacitance of the source region 11 can be reduced.
  • the semiconductor device according to the fourth modification of the first embodiment does not have a well-tap region (diffusion layer) having a high impurity concentration constituting the back gate terminal 43a, as shown in FIG. It is different from the semiconductor device according to the first modification of the first embodiment. Further, the semiconductor device according to the fourth modification of the first embodiment is different from the semiconductor device according to the third modification of the first embodiment shown in FIG. 17 in that the semiconductor device is composed of pMOS.
  • the back gate terminal 43a sandwiches the n-type well 7 directly under the separation membrane 6 together with the source region 41, and the n-type well 7 It is composed of a part. Since other configurations of the semiconductor device according to the fourth modification of the first embodiment are the same as those of the semiconductor device according to the first modification of the first embodiment shown in FIG. 15, duplicated description will be omitted.
  • the semiconductor device is composed of pMOS, and the back gate terminal 43a is provided with a well-tap region (diffusion layer) having a high impurity concentration for lowering the resistance.
  • a well-tap region diffusion layer
  • the semiconductor device is composed of pMOS, and the back gate terminal 43a is provided with a well-tap region (diffusion layer) having a high impurity concentration for lowering the resistance.
  • FIG. 19 the planar patterns of the convex portions 4a and 4b directly below the separation membrane 6 are schematically shown by broken lines.
  • FIG. 20 shows a cross section seen from the direction of AA passing over the convex portion 4a of FIG.
  • FIG. 21 shows a cross section seen from the BB direction passing between the convex portions 4a and 4b of FIG. 20.
  • the depths of the convex portions 4a and 4b are equivalent to the depths of the surrounding STI regions 4. Since other configurations of the semiconductor device according to the fifth modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIGS. 13 and 14, duplicate description will be omitted.
  • the semiconductor device According to the semiconductor device according to the fifth modification of the first embodiment, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment. Further, the STI region 4 has convex portions 4a and 4b extending between the back gate terminal 13 and the source region 11 of the MOSFET on a plane pattern, so that the p-type is sandwiched between the source region 11 and the back gate terminal 13. Since the well 3 is narrowed, the junction capacity of the source region 11 can be reduced.
  • the semiconductor device is composed of nMOS is illustrated, but the semiconductor device may be configured by pMOS.
  • the semiconductor device according to the sixth modification of the first embodiment has no separation membrane on the p-type well 3 between the back gate terminal 13 and the source region 11 of the MOSFET. It is different from the semiconductor device according to the first embodiment shown in.
  • the silicide layer is not provided above the back gate terminal 13, the source region 11, and the drain region 12. Since other configurations of the semiconductor device according to the sixth modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
  • the back gate terminal 13 and the source region 11 of the MOSFET are electrically connected. It is not necessary to provide a separation membrane for separation. Even in this case, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment.
  • the semiconductor device according to the seventh modification of the first embodiment has no separation film on the n-type well 7 between the back gate terminal 43 and the source region 41 of the MOSFET. It is different from the semiconductor device according to the first modification of the first embodiment shown in. Further, the semiconductor device according to the seventh modification of the first embodiment is different from the semiconductor device according to the sixth modification of the first embodiment shown in FIG. 22 in that the semiconductor device is composed of pMOS.
  • the silicide layer is not provided above the back gate terminal 43, the source region 41, and the drain region 42. Since other configurations of the semiconductor device according to the seventh modification of the first embodiment are the same as those of the semiconductor device according to the first modification of the first embodiment shown in FIG. 15, duplicated description will be omitted.
  • the back gate terminal 43 and the source region 41 of the MOSFET are electrically connected. It is not necessary to provide a separation membrane for separation. Even in this case, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment.
  • the semiconductor device constitutes a planar MOSFET
  • the semiconductor device according to the present technology is not limited to the planar MOSFET.
  • the semiconductor device is a fin-type MOSFET (hereinafter, also referred to as “FinFET”)
  • FinFET fin-type MOSFET
  • an n-channel FinFET will be illustrated.
  • FIG. 24 is a planar pattern of the semiconductor device according to the second embodiment, the cross section of FIG. 24 seen from the AA direction corresponds to FIG. 25, and the cross section of FIG. 24 seen from the BB direction is FIG. 26.
  • the semiconductor device according to the second embodiment is provided on the p-type semiconductor substrate 1, the n-type well 2 provided on the semiconductor substrate 1, and the n-type well 2. It is provided with a p-type well 3.
  • FIG. 25 a case where the upper surface of the p-type well 3 is located above the upper surface of the STI region 4 is illustrated.
  • the joint surface between the n-type well 2 and the p-type well 3 is provided so as to be shallower than the STI region 4 and deeper than the source region 11 and the drain region 12.
  • the p-type well 3 is provided with an n + type source region 11 and an n + type drain region 12 separated from each other.
  • a gate electrode 5 is provided via a gate insulating film (not shown) so as to surround the channel region sandwiched between the source region 11 and the drain region 12.
  • the cross-sectional shape of the gate electrode 5 may be an inverted U shape that surrounds the upper surface and both side surfaces of the channel region.
  • the channel region surrounded by the gate electrode 5 has a fin shape.
  • the shape of the gate electrode 5 is not limited to this.
  • the gate electrode 5 may have a cross-sectional shape such as an M-shape or a ⁇ -shape that divides a plurality of fin-shaped channel regions.
  • the p-type well 3 is provided with a p + type back gate terminal 13 separated from the source region 11 and the drain region 12.
  • the back gate terminal 13 is composed of a well tap region (diffusion layer) having a higher impurity concentration than the p-type well 3.
  • the back gate terminal may be formed by a part of the p-type well 3 without the well tap region (diffusion layer) constituting the back gate terminal 13.
  • Silicide layers 21, 22, and 23 are provided above the source region 11, the drain region 12, and the back gate terminal 13, respectively. It should be noted that the silicide layers 21, 22, and 23 may not be provided.
  • a separation membrane 6 is provided on the p-type well 3 sandwiched between the source region 11 and the drain region 12 and the back gate terminal 13.
  • the shape of the separation membrane 6 may be the same as the shape of the gate electrode 5, for example.
  • the cross-sectional shape of the separation membrane 6 may be an inverted U shape surrounding the upper surface and both side surfaces of the fin-shaped p-shaped well 3.
  • the separation membrane 6 may be made of a material different from that of the gate electrode 5, and may be made of, for example, an insulating material. Further, when the silicide layers 21, 22, and 23 are not provided, the separation membrane 6 may be omitted.
  • a fin-shaped p-type well 3 is interposed between the back gate terminal 13 and the source region 11, and is not electrically separated by the STI region 4. That is, the back gate terminal 13, the source region 11, and the drain region 12 are provided in the same active region A0 surrounded by the STI region 4.
  • the back gate terminal 13 is electrically connected to the gate electrode 5 via a metal contact (not shown) and multi-layer wiring, and has the same potential as the gate electrode 5.
  • the semiconductor device even when the semiconductor device is composed of FinFETs, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment.
  • the semiconductor device according to the modified example of the second embodiment is the second embodiment shown in FIGS. 24 to 26 in that the semiconductor device is composed of a p-channel type FinFET. It is different from the semiconductor device according to the form.
  • the p-type semiconductor substrate 1 is provided with the n-type well 7.
  • the joint surface between the n-type well 7 and the semiconductor substrate 1 is shallower than the STI region 4 and deeper than the source region 41 and the drain region 42.
  • a p + type source region 41 and a p + type drain region 42 are provided above the n-type well 7.
  • a gate electrode 5 is provided via a gate insulating film (not shown) so as to surround the channel region sandwiched between the source region 41 and the drain region 42.
  • a back gate terminal 43 composed of an n + type well tap region is provided above the n-type well 7 so as to be separated from the source region 41 and the drain region 42.
  • the back gate terminal 43 is electrically connected to the gate electrode 5 and has the same potential.
  • a fin-shaped n-shaped well 7 is interposed between the back gate terminal 43 and the source region 41. That is, the back gate terminal 43, the source region 41, and the drain region 42 are provided in the same active region A0 surrounded by the STI region 4.
  • a separation membrane 6 is provided on the n-type well 7 between the back gate terminal 43 and the source region 41 and the drain region 42.
  • Silicide layers 21, 22, and 23 are provided above the back gate terminal 43, the source region 41, and the drain region 42, respectively. Since other configurations of the semiconductor device according to the modified example of the second embodiment are the same as those of the semiconductor device according to the second embodiment shown in FIGS. 24 to 26, duplicate description will be omitted.
  • the semiconductor device even when the semiconductor device is composed of a p-channel type FinFET, it is possible to realize low noise and miniaturization of the circuit as in the second embodiment. It becomes.
  • the semiconductor device according to the third embodiment is composed of nMOS.
  • An n-type well 2 and a p-type well (back gate region) 3 are provided on the p-type semiconductor substrate 1.
  • An embedded insulating film (BOX layer) 14 is provided on the upper surface of a part of the p-type well 3.
  • the joint surface between the n-type well 2 and the p-type well 3 is provided so as to be shallower than the STI region 4 and deeper than the source region 11 and the drain region 12.
  • a thin p-type semiconductor layer (SOI layer) 15 made of Si is provided on the embedded insulating film 14.
  • the embedded insulating film 14 is electrically separated from the p-type well 3 and the SOI layer 15 constituting the back gate region.
  • the SOI layer 15 is provided with an n + type source region 11 and an n + type drain region 12 separated from each other.
  • a gate electrode 5 is provided on a channel region sandwiched between a source region 11 and a drain region 12 via a gate insulating film (not shown).
  • a p + type back gate terminal 13 is provided on the upper portion of the p-type well 3 which is not covered with the embedded insulating film 14.
  • Silicide layers 21, 22, and 23 are provided on the upper surfaces of the source region 11, the drain region 12, and the back gate terminal 13, respectively.
  • a sidewall (not shown) is formed on the side wall of the source region 11 and the embedded insulating film 14, and the source region 11 and the back gate terminal 13 are electrically separated by this sidewall.
  • the back gate terminal 13 is composed of a well tap region (diffusion layer) having a higher impurity concentration than the p-type well 3.
  • the well tap region (diffusion layer) constituting the back gate terminal 13 is formed by removing a part of the embedded insulating film 14, implanting ions into the exposed upper surface of the p-type well 3, and then performing heat treatment. It is possible.
  • the back gate terminal may be formed by a part of the p-type well 3 without the well tap region (diffusion layer) constituting the back gate terminal 13.
  • the STI region 4 does not intervene between the back gate terminal 13 and the source region 11. That is, the back gate terminal 13, the source region 11, and the drain region 12 are provided in the same active region A0 surrounded by the STI region 4.
  • the back gate terminal 13 is electrically connected to the gate electrode 5 via a metal contact (not shown) and multi-layer wiring, and has the same potential as the gate electrode 5.
  • the semiconductor device even when the semiconductor device is composed of the SOI type MOSFET, it is possible to realize low noise and miniaturization of the circuit as in the first and second embodiments. ..
  • the semiconductor device according to the first modification of the third embodiment is common to the semiconductor device according to the third embodiment shown in FIG. 29 in that the semiconductor device is composed of nMOS. ..
  • the semiconductor device according to the first modification of the third embodiment is different from the semiconductor device according to the third embodiment shown in FIG. 29 in that the n-type well 7 constitutes a back gate region.
  • the embedded insulating film 14 is electrically separated from the n-type well 7 and the SOI layer 15 constituting the back gate region. Therefore, the polarity of the back gate region does not depend on the polarity of the SOI layer 15.
  • the back gate terminal 43 is composed of an n + type well tap region (diffusion layer) having a higher impurity concentration than the n type well 7. Since other configurations of the semiconductor device according to the first modification of the third embodiment are the same as those of the semiconductor device according to the third embodiment shown in FIG. 29, duplicate description will be omitted.
  • the semiconductor device even when the n-type well 7 constitutes the back gate region, it is possible to realize low noise and miniaturization of the circuit as in the third embodiment. It becomes.
  • the semiconductor device according to the second modification of the third embodiment is different from the semiconductor device according to the third embodiment shown in FIG. 29 in that the semiconductor device is composed of pMOS.
  • the embedded insulating film 14 is electrically separated from the p-type well 3 and the n-type SOI layer 16 constituting the back gate region. Therefore, the polarity of the SOI layer 16 does not depend on the polarity of the back gate region.
  • the SOI layer 16 is provided with a p + type source region 41 and a p + type drain region 42. Since other configurations of the semiconductor device according to the second modification of the third embodiment are the same as those of the semiconductor device according to the third embodiment shown in FIG. 29, duplicate description will be omitted.
  • the semiconductor device even when the semiconductor device is composed of pMOS, it is possible to realize low noise and miniaturization of the circuit as in the third embodiment. ..
  • the semiconductor device according to the third modification of the third embodiment has a point that the semiconductor device is composed of pMOS and a point that the n-type well 7 constitutes a back gate region. It is different from the semiconductor device according to the third embodiment shown in.
  • the embedded insulating film 14 is electrically separated from the n-type well 7 and the n-type SOI layer 16 constituting the back gate region.
  • the SOI layer 16 is provided with a p + type source region 41 and a p + type drain region 42.
  • the back gate terminal 43 is composed of an n + type well tap region (diffusion layer) having a higher impurity concentration than the n type well 7. Since other configurations of the semiconductor device according to the third modification of the third embodiment are the same as those of the semiconductor device according to the third embodiment shown in FIG. 29, duplicate description will be omitted.
  • the semiconductor device even when the semiconductor device is composed of pMOS and the n-type well 7 constitutes the back gate region, the noise is low as in the third embodiment. It is possible to realize miniaturization and miniaturization of circuits.
  • the solid-state image sensor according to the fourth embodiment includes a pixel array unit 322 in which pixels 321 are arranged in a two-dimensional array on a semiconductor substrate 311 using, for example, silicon (Si) as a semiconductor. ..
  • the pixel array unit 322 has a time code transfer unit 323 that transfers the time code generated by the time code generation unit 326 to each pixel 321.
  • a pixel drive circuit 324, a DAC (D / A Converter) 325, a time code generator 326, a vertical drive circuit 327, an output unit 328, and a timing generation circuit 329 are arranged around the pixel array unit 322 on the semiconductor substrate 311. ing.
  • each of the pixels 321 arranged in a two-dimensional array is provided with a pixel circuit 341 and an ADC 342.
  • the pixel 321 generates a charge signal according to the amount of light received by a light receiving element (for example, a photodiode) in the pixel, converts it into a digital pixel signal SIG, and outputs it.
  • a light receiving element for example, a photodiode
  • the pixel drive circuit 324 drives the pixel circuit 341 in the pixel 321.
  • the DAC 325 generates a reference signal (reference voltage signal) REF, which is a slope signal whose level (voltage) monotonically decreases with the passage of time, and supplies it to each pixel 321.
  • the time code generation unit 326 generates a time code used when each pixel 321 converts an analog pixel signal SIG into a digital signal (AD conversion), and supplies the time code to the corresponding time code transfer unit 323.
  • a plurality of time code generation units 326 are provided for the pixel array unit 322. In the pixel array unit 322, as many time code transfer units 323 as the number corresponding to the time code generation unit 326 are provided. That is, the time code generation unit 326 and the time code transfer unit 323 that transfers the time code generated by the time code generation unit 326 have a one-to-one correspondence.
  • the vertical drive circuit 327 controls the output unit 328 to output the digital pixel signal SIG generated in the pixel 321 to the output unit 328 in a predetermined order based on the timing signal supplied from the timing generation circuit 329.
  • the digital pixel signal SIG output from the pixel 321 is output from the output unit 328 to the outside of the solid-state image sensor.
  • the output unit 328 performs predetermined digital signal processing such as black level correction processing for correcting the black level and correlation double sampling (CDS) processing as necessary, and then outputs the digital signal to the outside.
  • the timing generation circuit 329 is configured by a timing generator or the like that generates various timing signals, and supplies the generated various timing signals to the pixel drive circuit 324, the DAC 325, the vertical drive circuit 327, or the like.
  • the pixel circuit 341 outputs a charge signal corresponding to the amount of received light to the ADC 342 as an analog pixel signal SIG.
  • the ADC 342 converts the analog pixel signal SIG supplied from the pixel circuit 341 into a digital signal.
  • the ADC 342 is composed of a comparison circuit 351 and a data storage unit 352.
  • the comparison circuit 351 compares the reference signal REF supplied from the DAC 325 with the pixel signal SIG, and outputs an output signal VCO as a comparison result signal representing the comparison result.
  • the comparison circuit 351 inverts the output signal VCO when the reference signal REF and the pixel signal SIG have the same voltage.
  • the comparison circuit 351 is composed of a differential input circuit 361, a voltage conversion circuit 362, and a positive feedback circuit (PFB) 363.
  • the vertical drive circuit 327 indicates that the operation is a pixel signal writing operation and that the pixel signal reading operation is RD.
  • the signal and the WORD signal that controls the read timing of the pixel 321 during the read operation of the pixel signal are supplied from the vertical drive circuit 327.
  • the time code generated by the time code generation unit 326 is also supplied via the time code transfer unit 323.
  • the data storage unit 352 is composed of a latch control circuit 371 that controls a time code writing operation and a reading operation based on a WR signal and an RD signal, and a latch storage unit 372 that stores the time code.
  • the latch control circuit 371 is updated every unit time supplied from the time code transfer unit 323 while the high (H) output signal VCO is input from the comparison circuit 351.
  • the time code is stored in the latch storage unit 372.
  • the latch storage unit 372 holds the time code stored in the latch storage unit 372.
  • the time code stored in the latch storage unit 372 represents the time when the pixel signal SIG and the reference signal REF become equal, and data indicating that the pixel signal SIG was the reference voltage at that time, that is, digitization. Represents the light intensity value.
  • the operation of the pixel 321 is changed from the writing operation to the reading operation.
  • the latch control circuit 371 is based on the WORD signal that controls the reading timing, and when the pixel 321 reaches its own reading timing, the time code stored in the latch storage unit 372 ( The digital pixel signal SIG) is output to the time code transfer unit 323.
  • the time code transfer unit 323 sequentially transfers the supplied time code in the column direction (vertical direction) and supplies it to the output unit 328.
  • the differential input circuit 361 compares the pixel signal SIG output from the pixel circuit 341 in the pixel 321 with the reference signal REF output from the DAC 325, and determines when the pixel signal SIG is higher than the reference signal REF. Output a signal (current).
  • the differential input circuit 361 serves as a constant current source for supplying transistors 381 and 382 as differential pairs, transistors 383 and 384 constituting the current mirror, and a current IB corresponding to the input bias current Vb.
  • the transistor 385 and the transistor 386 that outputs the output signal HVO of the differential input circuit 361 are configured.
  • the transistors 381, 382, 385 are composed of nMOS transistors, and the transistors 383, 384, 386 are composed of pMOS transistors.
  • the reference signal REF output from the DAC 325 is input to the gate of the transistor 381, and the pixel output from the pixel circuit 341 in the pixel 321 is input to the gate of the transistor 382.
  • the signal SIG is input.
  • the source of the transistors 381 and 382 is connected to the drain of the transistor 385, and the source of the transistor 385 is connected to a predetermined voltage VSS.
  • the drain of the transistor 381 is connected to the gate of the transistors 383 and 384 and the drain of the transistor 383 constituting the current mirror circuit, and the drain of the transistor 382 is connected to the drain of the transistor 384 and the gate of the transistor 386.
  • the source of the transistors 383,384,386 is connected to the first power supply voltage VDD1.
  • the voltage conversion circuit 362 is composed of, for example, an nMOS type transistor 391.
  • the drain of the transistor 391 is connected to the drain of the transistor 386 of the differential input circuit 361, the source of the transistor 391 is connected to a predetermined connection point in the positive feedback circuit 363, and the gate of the transistor 386 is connected to the bias voltage VBIAS. It is connected.
  • the transistors 381 to 386 constituting the differential input circuit 361 are circuits that operate at a high voltage up to the first power supply voltage VDD1, and the positive feedback circuit 363 has a second power supply voltage VDD2 lower than the first power supply voltage VDD1. It is a working circuit.
  • the voltage conversion circuit 362 converts the output signal HVO input from the differential input circuit 361 into a low voltage signal (conversion signal) LVI in which the positive feedback circuit 363 can operate, and supplies the output signal HVO to the positive feedback circuit 363.
  • the bias voltage VBIAS may be any voltage that converts the transistors 401 to 405 of the positive feedback circuit 363 that operates at a constant voltage into a voltage that does not destroy them.
  • the bias voltage VBIAS can be the same voltage as the second power supply voltage VDD2 of the positive feedback circuit 363.
  • the positive feedback circuit 363 reverses when the pixel signal SIG is higher than the reference signal REF based on the conversion signal LVI in which the output signal HVO from the differential input circuit 361 is converted into a signal corresponding to the second power supply voltage VDD2. Outputs the comparison result signal. Further, the positive feedback circuit 363 speeds up the transition speed when the output signal VCO output as the comparison result signal is inverted.
  • the positive feedback circuit 363 is composed of five transistors 401 to 405.
  • the transistors 401, 402, and 404 are composed of pMOS transistors
  • the transistors 403 and 405 are composed of nMOS transistors.
  • the source of the transistor 391, which is the output end of the voltage conversion circuit 362, is connected to the drain of the transistors 402 and 403 and the gate of the transistors 404 and 405.
  • the source of the transistors 401 and 404 is connected to the second power supply voltage VDD2, the drain of the transistor 401 is connected to the source of the transistor 402, and the gate of the transistor 402 is the output end of the positive feedback circuit 363. It is connected to the drain of.
  • the sources of transistors 403,405 are connected to a predetermined voltage VSS.
  • the initialization signal INI is supplied to the gates of the transistors 401 and 403.
  • the transistors 404 and 405 form an inverter circuit, and the connection point between the drains thereof is an output end at which the comparison circuit 351 outputs an output signal VCO.
  • the pixel circuit 341 is composed of a photodiode (PD) 421 as a photoelectric conversion element, an emission transistor 422, a transfer transistor 423, a reset transistor 424, and a floating diffusion layer (FD) 425.
  • PD photodiode
  • FD floating diffusion layer
  • the discharge transistor 422 is used when adjusting the exposure period. Specifically, when the emission transistor 422 is turned on when the exposure period is desired to be started at an arbitrary timing, the electric charge accumulated in the photodiode 421 up to that point is discharged, so that the emission transistor 422 is turned off. After that, the exposure period will start.
  • the transfer transistor 423 transfers the electric charge generated by the photodiode 421 to the FD425.
  • the reset transistor 424 resets the charge held in the FD425.
  • the FD425 is connected to the gate of the transistor 382 of the differential input circuit 361.
  • the transistor 382 of the differential input circuit 361 also functions as an amplification transistor of the pixel circuit 341.
  • the source of the reset transistor 424 is connected to the gate of the transistor 382 of the differential input circuit 361 and the drain of the FD425, and the drain of the reset transistor 424 is connected to the drain of the transistor 382. Therefore, there is no fixed reset voltage to reset the charge on the FD425. This is because the reset voltage for resetting the FD425 can be arbitrarily set by using the reference signal REF by controlling the circuit state of the differential input circuit 361.
  • the solid-state image sensor according to the fourth embodiment as shown in FIG. 36, two semiconductor chips of the upper substrate 301 and the lower substrate 302 are overlapped, and one of the wirings of the upper and lower chips is provided by TSV (through-silicon via). It is composed of a laminated image sensor whose parts are electrically connected.
  • the pixel circuit 303 is mounted on the upper substrate 301, and peripheral circuits 304 other than the pixel circuit 303 are mounted on the lower substrate 302.
  • the broken line region 300 indicates the TSV connection location. That is, the source of the reset transistor 424 and the gate of the transistor 382 of the differential input circuit 361 are TSV-connected. The drain of the reset transistor 424 is TSV-connected to the drain of the transistor 382.
  • the differential input circuit 361 shown in FIG. 35 becomes a noise source of random noise.
  • differential input transistors 381 and 382 composed of nMOS.
  • the active regions A3 and A4 of the differential input transistors 381 and 382 are partitioned by the STI region 4 and electrically separated from each other.
  • An n-type well 2 and a p-type well 3 are provided on the p-type semiconductor substrate 1.
  • the differential input transistor 381 has a multi-finger structure in which a plurality of source regions 11a and 11b are arranged.
  • the differential input transistor 381 has n + type source regions 11a and 11b, n + type drain regions 12a, and p + type back gate terminals 13a provided above the p-type well 3.
  • a gate electrode 5a is provided on the channel region sandwiched between the source region 11a and the drain region 12a via a gate insulating film (not shown).
  • a gate electrode 5b is provided on the channel region sandwiched between the source region 11b and the drain region 12a via a gate insulating film (not shown).
  • a separation membrane 6a is provided on the p-type well 3 sandwiched between the source region 11b and the back gate terminal 13a.
  • Silicide layers 21a, 21b, 22a, and 23a are provided above the source regions 11a and 11b, the drain region 12a, and the back gate terminal 13a, respectively.
  • the differential input transistor 382 has a multi-finger structure in which a plurality of source regions 11c and 11d are arranged.
  • the differential input transistor 382 has n + type source regions 11c and 11d, n + type drain regions 12b, and p + type back gate terminals 13b provided above the p-type well 3.
  • a gate electrode 5c is provided on the channel region sandwiched between the source region 11c and the drain region 12b via a gate insulating film (not shown).
  • a gate electrode 5d is provided on the channel region sandwiched between the source region 11d and the drain region 12b via a gate insulating film (not shown).
  • a separation membrane 6b is provided on the p-type well 3 sandwiched between the source region 11d and the back gate terminal 13b.
  • Silicide layers 21d, 21d, 22b, and 23b are provided above the source regions 11c and 11d, the drain region 12b, and the back gate terminal 13b, respectively.
  • n-type well 7 is provided on the p-type semiconductor substrate 1.
  • the n-type well 7 corresponds to the n-type well 2 shown in FIG. 38.
  • the active load transistor 383 has a multi-finger structure in which a plurality of source regions 41a and 41b are arranged.
  • the active load transistor 383 has p + type source regions 41a and 41b, p + type drain regions 42a, and n + type backgate terminals 43a provided above the n-type well 7.
  • a gate electrode 5a is provided on the channel region sandwiched between the source region 41a and the drain region 42a via a gate insulating film (not shown).
  • a gate electrode 5b is provided on the channel region sandwiched between the source region 41b and the drain region 42a via a gate insulating film (not shown).
  • a separation membrane 6a is provided on the n-type well 7 sandwiched between the source region 41b and the back gate terminal 43a.
  • Silicide layers 21a, 21b, 22a, and 23a are provided above the source regions 41a and 41b, the drain region 42a, and the back gate terminal 43a, respectively.
  • the active load transistor 384 has a multi-finger structure in which a plurality of source regions 41c and 41d are arranged.
  • the active load transistor 384 has p + type source regions 41c and 41d, p + type drain regions 42b, and n + type backgate terminals 43b provided above the n-type well 7.
  • a gate electrode 5c is provided on the channel region sandwiched between the source region 41c and the drain region 42b via a gate insulating film (not shown).
  • a gate electrode 5d is provided on the channel region sandwiched between the source region 41d and the drain region 42b via a gate insulating film (not shown).
  • a separation membrane 6b is provided on the n-type well 7 sandwiched between the source region 41d and the back gate terminal 43b.
  • Silicide layers 21d, 21d, 22b, and 23b are provided above the source regions 41c and 41d, the drain region 42b, and the back gate terminal 43b, respectively.
  • the differential input transistors 381 and 382 and the transistor 385 as a constant current source may be arranged on the upper substrate 301.
  • the area 300 surrounded by the broken line in FIG. 41 is the TSV connection point.
  • the differential input transistors 381 and 382 and the transistor 385 as a constant current source are arranged on the upper substrate 301, the differential input transistors 381 and 382 arranged on the upper substrate 301 are shown in FIGS. 37 and 38.
  • the structure shown in the above can be applied to reduce the noise of the circuit.
  • the semiconductor device according to the present technology can be applied to MOSFETs constituting a general comparator.
  • a general comparator includes active load transistors T31 and T32 and differential input transistors T41 and T42, and has a configuration of active load transistors T31 and T32 and differential input transistors T41 and T42.
  • the semiconductor device according to this technology can be applied.
  • the comparator can be made less noisy.
  • Such a comparator is applied to an analog switch used in various sensor circuits such as light, temperature, and odor. For example, when the comparator is applied to a photodetector, as shown in FIGS.
  • the comparator 401 compares the detection signal Vd detected using the photodiode with the reference voltage Vref, and the comparator 401 compares the detection signal Vd and the reference voltage Vref. By outputting the voltage Vout according to the comparison result, it is determined whether or not light is detected.
  • the semiconductor device according to the present technology is suitable for a MOSFET that constitutes a comparator in which a detection signal Vd is weak and a high S / N ratio is required.
  • the semiconductor device according to this technology can be applied to a DA converter.
  • the semiconductor device according to the present technology shows a weight resistance type DA converter as shown in FIG. 46, which is an example of a DA converter.
  • the weighted resistance type DA converter uses an adder circuit including a comparator 402 and a resistance element Rf to create a weight of an output voltage in proportion to each bit in proportion to resistance and convert it into an analog signal.
  • the semiconductor device according to the present technology can be applied to the MOSFETs constituting the comparator 402.
  • the semiconductor devices according to this technology can be applied to MOSFETs used in various electronic devices such as various measuring instruments, AV devices, and home appliances.
  • the present technology can have the following configurations.
  • the bonding surface between the first semiconductor layer and the second semiconductor layer or the semiconductor substrate is shallower than the element separation region and deeper than the first and second main electrode regions.
  • the separation membrane is made of the same material as the gate electrode.
  • the separation membrane is made of an insulating material.
  • the element separation region has a convex portion extending between one of the first and second main electrode regions and the back gate terminal on a plane pattern.
  • the channel region has a fin shape A part of the first semiconductor layer sandwiched between one of the first and second main electrode regions and the back gate terminal has a fin shape.
  • the second semiconductor layer provided in the active region and An embedded insulating film selectively provided on a part of the second semiconductor layer, With more The first semiconductor layer and the first and second main electrode regions are provided on the embedded insulating film.
  • the back gate terminal is provided in another part of the second semiconductor layer.
  • the second semiconductor layer is the same conductive type as the first semiconductor layer.
  • the back gate terminal is of the same conductive type as the second semiconductor layer, and is composed of a well-tap region having a higher impurity concentration than the second semiconductor layer.
  • the second semiconductor layer is an opposite conductive type to the first semiconductor layer.
  • the back gate terminal is of the same conductive type as the second semiconductor layer, and is composed of a well-tap region having a higher impurity concentration than the second semiconductor layer.
  • the semiconductor device according to (11) above. (14) It is provided below the second semiconductor layer, is in contact with the second semiconductor layer, and further includes a third semiconductor layer or a semiconductor substrate that is opposite to the second semiconductor layer. The bonding surface between the second semiconductor layer and the third semiconductor layer or the semiconductor substrate is shallower than the element separation region and deeper than the first and second main electrode regions.
  • Horizontal transfer scanning circuit 140, 204 ... Timing control circuit, 150 ... ADC group, 151,206 ... Comparer (comparator), 152 ... Counter, 153 latch, 160 ... Digital-analog converter, 170 ... Amplifier circuit , 180, 210 ... Signal processing circuit, 190 ... Horizontal transfer line, 207 ... Counter / latch circuit, 209 ... DC supply circuit, 301 ... Upper board, 302 ... Lower board, 303 ... Pixel circuit, 304 ... Peripheral circuit, 311 ... Semiconductor substrate, 321 ... Pixels, 322 ... Pixel array unit, 323 ... Time code transfer unit, 324 ... Pixel drive circuit, 325 ... Pixel drive circuit, 326 ...
  • Time code generator 327 ... Vertical drive circuit, 328 ... Output unit , 329 ... Timing generation circuit, 341 ... Pixel circuit, 351 ... Comparison circuit, 352 ... Data storage unit, 361 ... Differential input circuit, 362 ... Voltage conversion circuit, 363 ... Positive feedback circuit, 370 ... Amplifier circuit, 371 ... Latch Control circuit, 372 ... Latch storage, 381 to 386, 391, 401 to 405 ... Transistor, 421 ... Photo diode, 422 ... Ejection transistor, 423 ... Transfer transistor, 424 ... Reset transistor, 501, 502 ... Comparer, A0 to A6 ... active region, C1, C2 ... sampling capacitance, D1 ...
  • photoelectric conversion element FD ... floating diffusion, IS ... constant current source, LRST ... reset control line, LSEL ... selection control line, LSGN ... signal line, LSGN ... vertical signal Line, LTRG ... Transfer control line, L VDD ... Power supply line, Rf ... Resistance element, T1 to T4, T11, T12, T21, T22, T31, T32, T41, T42 ... Transistor

Abstract

Provided is a semiconductor device capable of simultaneously achieving noise reduction and downsizing without complicating a manufacturing process thereof. This semiconductor device is provided with: a first semiconductor layer; first and second main electrode regions of a conductivity type opposite to that of the first semiconductor layer; a gate electrode provided over a channel region interposed between the first and second main electrode regions; and a back gate terminal electrically connected to the gate electrode, wherein the first and second main electrode regions and the back gate terminal are located in the same active region partitioned by element separation regions.

Description

半導体装置及び電子機器Semiconductor devices and electronic devices
　本開示に係る技術（本技術）は、ＣＭＯＳ（Complementary Metal Oxide Semiconductor）イメージセンサに代表される固体撮像装置等に好適なＭＯＳ電界効果型トランジスタ（ＭＯＳＦＥＴ）等のランダムノイズを低減する技術に関する。 The technology according to the present disclosure (the present technology) relates to a technology for reducing random noise such as a MOS field effect transistor (MOSFET) suitable for a solid-state image sensor represented by a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
　画像を撮像する固体撮像装置としては、例えば、ＣＣＤ（Charge Coupled Device）イメージセンサやＣＭＯＳイメージセンサがある。近年は、特別な設備投資を必要とすることなく、既存のＣＭＯＳプロセスで製造することが可能なＣＭＯＳイメージセンサが注目され、携帯電話に内蔵されたカメラシステムや監視システム等への採用が急速に進んでいる。 Examples of the solid-state image sensor that captures an image include a CCD (Charge Coupled Device) image sensor and a CMOS image sensor. In recent years, CMOS image sensors that can be manufactured by existing CMOS processes without requiring special capital investment have attracted attention, and are rapidly being adopted in camera systems and surveillance systems built into mobile phones. It is progressing.
　ＣＭＯＳイメージセンサは、光電変換を行う画素が出力するアナログの電気信号をＡＤ（Analog to Digital）変換するＡＤ変換部を有する。ＣＭＯＳイメージセンサのＡＤ変換部としては、処理の高速化等の要請から、一行に並ぶ複数の画素の全部等の２以上の画素が出力する電気信号を、並列にＡＤ変換することができる列並列型のＡＤ変換部（以下、「列並列ＡＤ変換部」ともいう）が採用されている。 The CMOS image sensor has an AD conversion unit that AD (Analog to Digital) converts an analog electrical signal output by a pixel that performs photoelectric conversion. The AD conversion unit of the CMOS image sensor can perform AD conversion in parallel to electrical signals output by two or more pixels, such as all of a plurality of pixels lined up in a row, in response to a request for high-speed processing. A type AD conversion unit (hereinafter, also referred to as “column parallel AD conversion unit”) is adopted.
　列並列ＡＤ変換部は、例えば、画素の列数と同一の数等の複数のアナログ・デジタル変換器（ＡＤＣ）を、行方向に並べて配置することにより構成される。各列のＡＤＣは、その列の画素が出力する電気信号のＡＤ変換を行う。列並列ＡＤ変換部を構成するＡＤＣとしては、例えば、比較器（コンパレータ）とカウンタとを有し、所定の参照信号と画素が出力する電気信号とを比較することにより、電気信号のＡＤ変換を行う、いわゆる参照信号比較型のＡＤＣがある。 The column-parallel AD converter is configured by, for example, arranging a plurality of analog-to-digital converters (ADCs) having the same number of pixels as the number of columns arranged side by side in the row direction. The ADC in each row performs AD conversion of the electrical signal output by the pixels in that row. The ADC constituting the column-parallel AD conversion unit includes, for example, a comparator and a counter, and AD conversion of an electric signal is performed by comparing a predetermined reference signal with an electric signal output by a pixel. There is a so-called reference signal comparison type ADC that is performed.
　参照信号比較型のＡＤＣとしては、例えば、シングルスロープ型ＡＤＣがある（特許文献１参照）。シングルスロープ型ＡＤＣでは、ＭＯＳＦＥＴで構成される差動入力トランジスタと、能動負荷からなるコンパレータにおいて、ランプ信号等の一定の傾きでレベルが変化する参照信号と画素が出力する画素信号とが比較され、カウンタにおいて、参照信号と電気信号とのレベルが一致するまでの、参照信号のレベルの変化に要する時間がカウントされることにより、画素が出力する電気信号がＡＤ変換される。 As a reference signal comparison type ADC, for example, there is a single slope type ADC (see Patent Document 1). In a single-slope ADC, a differential input transistor composed of MOSFETs and a comparator consisting of an active load compare a reference signal whose level changes with a constant inclination such as a lamp signal and a pixel signal output by a pixel. By counting the time required for the level of the reference signal to change until the levels of the reference signal and the electric signal match in the counter, the electric signal output by the pixel is AD-converted.
　ところで、ＣＭＯＳイメージセンサの画質の良し悪しを示す指標として、センシングした画像の時間的なチラつきがある。これは、検出した画像データ信号が、回路を伝搬する過程において、何らかの要因によって、信号レベルが時間的にランダムなバラツキを持つことにより起こる。その原因の一つとしては、コンパレータを構成しているＭＯＳＦＥＴからなる差動入力トランジスタや能動負荷トランジスタ自体が発生させるランダムノイズが大きいと、センシングした画像データの時間的なバラつきが大きくなること分かっている。 By the way, there is a temporal flicker of the sensed image as an index indicating the quality of the image quality of the CMOS image sensor. This is caused by the detected image data signal having a random variation in the signal level in time due to some factor in the process of propagating the circuit. It was found that one of the causes is that if the random noise generated by the differential input transistor consisting of MOSFETs constituting the comparator or the active load transistor itself is large, the temporal variation of the sensed image data becomes large. There is.
　この画像データの時間的バラつきを低減するためには、ノイズ源となっているＭＯＳＦＥＴのランダムノイズを減らすことが必要である。ＭＯＳＦＥＴのランダノイズは、フリッカーノイズ（１／ｆノイズ）、ランダム・テレグラフ・ノイズ（ＲＴＮ）及び熱雑音でほぼ決定される（非特許文献１参照）。これらのうち、フリッカーノイズやＲＴＮのノイズレベルは、ＭＯＳＦＥＴのゲート電極面積に反比例することが分かっている。 In order to reduce the temporal variation of this image data, it is necessary to reduce the random noise of the MOSFET, which is the noise source. The lander noise of the MOSFET is almost determined by flicker noise (1 / f noise), random telegraph noise (RTN), and thermal noise (see Non-Patent Document 1). Of these, the flicker noise and RTN noise levels are known to be inversely proportional to the gate electrode area of the MOSFET.
　そこで、回路を構成しているＭＯＳＦＥＴのうち、ノイズ源となっているＭＯＳＦＥＴを、複数のＭＯＳＦＥＴを並列接続させたマルチフィンガー構造にしてＭＯＳＦＥＴ全体のゲート電極面積を大きくすることで、フリッカーノイズやＲＴＮを低減し、センシングした画像データの時間的バラつきを低減することができる（特許文献２参照）。しかし、ＣＭＯＳイメージセンサが様々な分野への応用が進むにつれて、小型化及び高性能化が求められている。ＣＭＯＳイメージセンサの低ノイズ化もその要求の一つであるが、ノイズ源となるＭＯＳＦＥＴのゲート電極面積を大きくする手段は、同時に回路面積も大きくしてしまい、センサの小型化との両立が難しい。このような背景から、回路面積を増加させることなく、低ノイズ化する技術が要求されている。このような要求に対して、ゲート電極とバックゲートを電気的に共通化した構造が開示されている（特許文献３参照）。 Therefore, among the MOSFETs that make up the circuit, the MOSFET that is the noise source has a multi-finger structure in which multiple MOSFETs are connected in parallel, and the gate electrode area of the entire MOSFET is increased to increase flicker noise and RTN. It is possible to reduce the temporal variation of the sensed image data (see Patent Document 2). However, as the application of CMOS image sensors to various fields progresses, miniaturization and higher performance are required. One of the requirements is to reduce the noise of the CMOS image sensor, but the means of increasing the gate electrode area of the MOSFET, which is the noise source, also increases the circuit area, making it difficult to achieve both miniaturization of the sensor. .. Against this background, there is a demand for a technique for reducing noise without increasing the circuit area. In response to such a requirement, a structure in which the gate electrode and the back gate are electrically shared is disclosed (see Patent Document 3).
特開２０１３－９０３０５号公報Japanese Unexamined Patent Publication No. 2013-90305 特開２０１０－９３６４１号公報JP-A-2010-93641 特開２０１２－１６０６５２号公報Japanese Unexamined Patent Publication No. 2012-160652
　P. Martin-Gonthier, et al., “RTS noise impact in CMOS image sensors readout circuit”, ICECS2009, p928-931 P. Martin-Gonthier, et al., “RTS noise impact in CMOS image sensors readout circuit”, ICECS2009, p928-931
　しかしながら、特許文献３に記載の半導体装置では、バックゲート端子とＭＯＳＦＥＴのソース領域及びドレイン領域との間のＳＴＩ（Shallow Trench Isolation）領域を、ＭＯＳＦＥＴの周囲のＳＴＩ領域よりも浅く形成する必要がある。このため、製造プロセスが複雑化するという問題がある。 However, in the semiconductor device described in Patent Document 3, it is necessary to form the STI (Shallow Trench Isolation) region between the back gate terminal and the source region and drain region of the MOSFET shallower than the STI region around the MOSFET. .. Therefore, there is a problem that the manufacturing process is complicated.
　本技術は、製造プロセスを複雑化せずに、低ノイズと小型化を両立させた半導体装置及び電子機器を提供することを目的とする。 The purpose of this technology is to provide semiconductor devices and electronic devices that achieve both low noise and miniaturization without complicating the manufacturing process.
　本技術の一態様に係る半導体装置は、第１半導体層と、第１半導体層に互いに設けられ、第１半導体層と反対導電型の第１及び第２主電極領域と、第１及び第２主電極領域に挟まれたチャネル領域上に設けられたゲート電極と、ゲート電極と電気的に接続されたバックゲート端子とを備え、第１及び第２主電極領域並びにバックゲート端子が、素子分離領域で区画された同一の活性領域内にあることを要旨とする。 The semiconductor device according to one aspect of the present technology is provided on the first semiconductor layer and the first semiconductor layer, and is opposite to the first semiconductor layer and has first and second main electrode regions, and first and second. A gate electrode provided on a channel region sandwiched between the main electrode regions and a back gate terminal electrically connected to the gate electrode are provided, and the first and second main electrode regions and the back gate terminal are separated from each other. The gist is that they are in the same active region partitioned by regions.
　本技術の一態様に係る電子機器は、第１半導体層と、第１半導体層に互いに設けられ、第１半導体層と反対導電型の第１及び第２主電極領域と、第１及び第２主電極領域に挟まれたチャネル領域上に設けられたゲート電極と、ゲート電極と電気的に接続されたバックゲート端子とを備える半導体装置を有し、第１及び第２主電極領域並びにバックゲート端子が、素子分離領域で区画された同一の活性領域内にあることを要旨とする。 The electronic devices according to one aspect of the present technology are provided on the first semiconductor layer and the first semiconductor layer, and are opposite to the first semiconductor layer and have first and second main electrode regions, and first and second main electrode regions. It has a semiconductor device including a gate electrode provided on a channel region sandwiched between main electrode regions and a back gate terminal electrically connected to the gate electrode, and has first and second main electrode regions and a back gate. The gist is that the terminals are in the same active region partitioned by the element separation region.
第１実施形態に係る固体撮像装置の等価回路図である。It is an equivalent circuit diagram of the solid-state image pickup apparatus which concerns on 1st Embodiment. 第１実施形態に係る画素アレイ部の等価回路図である。It is an equivalent circuit diagram of the pixel array part which concerns on 1st Embodiment. 第１実施形態に係る画素の等価回路図である。It is the equivalent circuit diagram of the pixel which concerns on 1st Embodiment. 第１実施形態に係る比較器の等価回路図である。It is an equivalent circuit diagram of the comparator which concerns on 1st Embodiment. 第１実施形態に係る固体撮像装置のチップ領域の概略図である。It is the schematic of the chip region of the solid-state image sensor which concerns on 1st Embodiment. 比較例に係る半導体装置の平面図である。It is a top view of the semiconductor device which concerns on a comparative example. 図６のＡ－Ａ´方向から見た断面図である。It is sectional drawing seen from the AA'direction of FIG. ＭＯＳＦＥＴの標準構造、及びゲート電極とバックゲートを共通化した構造のそれぞれのノイズスペクトルを表すグラフである。It is a graph which shows each noise spectrum of the standard structure of MOSFET and the structure which shared the gate electrode and the back gate. 比較器を構成する差動入力トランジスタの平面図である。It is a top view of the differential input transistor which constitutes a comparator. 図９のＡ－Ａ´方向から見た断面図である。It is sectional drawing seen from the direction of AA'in FIG. 比較例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on a comparative example. 比較例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on a comparative example. 第１実施形態に係る半導体装置の平面図である。It is a top view of the semiconductor device which concerns on 1st Embodiment. 図１３のＡ－Ａ´方向から見た断面図である。It is sectional drawing seen from the AA'direction of FIG. 第１実施形態の第１変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 1st modification of 1st Embodiment. 第１実施形態の第２変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 2nd modification of 1st Embodiment. 第１実施形態の第３変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 3rd modification of 1st Embodiment. 第１実施形態の第４変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 4th modification of 1st Embodiment. 第１実施形態の第５変形例に係る半導体装置の平面図である。It is a top view of the semiconductor device which concerns on 5th modification of 1st Embodiment. 図１９のＡ－Ａ´方向から見た断面図である。It is sectional drawing seen from the AA'direction of FIG. 図１９のＢ－Ｂ´方向から見た断面図である。It is sectional drawing seen from the BB'direction of FIG. 第１実施形態の第６変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 6th modification of 1st Embodiment. 第１実施形態の第７変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 7th modification of 1st Embodiment. 第２実施形態に係る半導体装置の平面図である。It is a top view of the semiconductor device which concerns on 2nd Embodiment. 図２４のＡ－Ａ´方向から見た断面図である。It is sectional drawing seen from the AA'direction of FIG. 図２４のＢ－Ｂ´方向から見た断面図である。It is sectional drawing seen from the BB'direction of FIG. 第２実施形態の変形例に係る半導体装置の平面図である。It is a top view of the semiconductor device which concerns on the modification of 2nd Embodiment. 図２７のＡ－Ａ´方向から見た断面図である。It is sectional drawing seen from the AA'direction of FIG. 27. 第３実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 3rd Embodiment. 第３実施形態の第１変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 1st modification of 3rd Embodiment. 第３実施形態の第２変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 2nd modification of 3rd Embodiment. 第３実施形態の第３変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 3rd modification of 3rd Embodiment. 第４実施形態に係る固体撮像装置の概略構成図である。It is a schematic block diagram of the solid-state image sensor which concerns on 4th Embodiment. 第４実施形態に係る画素の概略構成図である。It is a schematic block diagram of the pixel which concerns on 4th Embodiment. 第４実施形態に係る画素回路及び比較回路の等価回路図である。It is an equivalent circuit diagram of the pixel circuit and the comparison circuit which concerns on 4th Embodiment. 第４実施形態に係る上側基板及び下側基板の概略図である。It is the schematic of the upper substrate and the lower substrate which concerns on 4th Embodiment. 第４実施形態に係る差動入力トランジスタの平面図である。It is a top view of the differential input transistor which concerns on 4th Embodiment. 図３７のＡ－Ａ´方向から見た断面図である。It is sectional drawing seen from the direction of AA'in FIG. 37. 第４実施形態に係る能動負荷トランジスタの平面図である。It is a top view of the active load transistor which concerns on 4th Embodiment. 図３９のＡ－Ａ´方向から見た断面図である。It is sectional drawing seen from the direction of AA'in FIG. 39. 第４実施形態に係る画素回路及び比較回路の他の等価回路図である。It is another equivalent circuit diagram of the pixel circuit and the comparison circuit which concerns on 4th Embodiment. 第５実施形態に係る比較器の等価回路図である。It is an equivalent circuit diagram of the comparator which concerns on 5th Embodiment. 第５実施形態に係る比較器の等価回路図である。It is an equivalent circuit diagram of the comparator which concerns on 5th Embodiment. 第５実施形態に係る比較器の入力信号及び出力信号の時間変化を表すグラフである。It is a graph which shows the time change of the input signal and the output signal of the comparator which concerns on 5th Embodiment. 第５実施形態に係る重み抵抗型ＤＡコンバータの等価回路図である。It is an equivalent circuit diagram of the weight resistance type DA converter which concerns on 5th Embodiment.
　以下において、図面を参照して本技術の第１～第５実施形態を説明する。以下の説明で参照する。図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率等は現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることは勿論である。なお、本明細書中に記載された効果はあくまで例示であって限定されるものでは無く、また他の効果があってもよい。 Hereinafter, the first to fifth embodiments of the present technology will be described with reference to the drawings. See below for reference. In the description of the drawings, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that the drawings include parts having different dimensional relationships and ratios from each other. The effects described in the present specification are merely examples and are not limited, and other effects may be obtained.
　本明細書において、固体撮像装置を含む半導体装置を構成する半導体装置の「第１主電極領域」とは、ＭＯＳＦＥＴ等の絶縁ゲート型電界効果トランジスタ（ＭＩＳＦＥＴ）、絶縁ゲート型静電誘導トランジスタ（ＭＩＳＳＩＴ）又は高電子移動度トランジスタ（ＨＥＭＴ）等のソース領域又はドレイン領域のいずれか一方となる半導体領域を意味する。「第２主電極領域」とは、ＭＩＳＦＥＴ等の上記第１主電極領域とはならないソース領域又はドレイン領域のいずれか一方となる半導体領域を意味する。このように、「第１主電極領域」がソース領域であれば、「第２主電極領域」はドレイン領域を意味する。 In the present specification, the "first main electrode region" of the semiconductor device constituting the semiconductor device including the solid-state imaging device is an insulated gate type field effect transistor (MISFET) such as a MOSFET or an insulated gate type electrostatic induction transistor (MISSIT). ) Or a semiconductor region that is either a source region or a drain region such as a high electron mobility transistor (HEMT). The “second main electrode region” means a semiconductor region such as a MISFET that is either a source region or a drain region that does not become the first main electrode region. As described above, when the "first main electrode region" is the source region, the "second main electrode region" means the drain region.
　また、「第１導電型」はｐ型又はｎ型の一方であり、「第２導電型」はｐ型又はｎ型のうちの「第１導電型」とは異なる一方を意味する。また、「ｎ」や「ｐ」に付す「＋」や「－」は、「＋」及び「－」が付記されていない半導体領域に比して、それぞれ相対的に不純物濃度が高い又は低い半導体領域であることを意味する。但し、同じ「ｎ」と「ｎ」とが付された半導体領域であっても、それぞれの半導体領域の不純物濃度が厳密に同じであることを意味するものではない。 Further, the "first conductive type" means one of the p-type or the n-type, and the "second conductive type" means one of the p-type or the n-type different from the "first conductive type". Further, "+" and "-" attached to "n" and "p" are semiconductors having a relatively high or low impurity concentration as compared with the semiconductor regions to which "+" and "-" are not added. It means that it is an area. However, even in the semiconductor regions with the same "n" and "n", it does not mean that the impurity concentrations in the respective semiconductor regions are exactly the same.
　また、以下の説明における上下等の方向の定義は、単に説明の便宜上の定義であって、本技術の技術的思想を限定するものではない。例えば、対象を９０°回転して観察すれば上下は左右に変換して読まれ、１８０°回転して観察すれば上下は反転して読まれることは勿論である。 In addition, the definition of the vertical direction in the following description is merely a definition for convenience of explanation, and does not limit the technical idea of the present technology. For example, if the object is rotated by 90 ° and observed, the top and bottom are converted to left and right and read, and if the object is rotated by 180 ° and observed, the top and bottom are reversed and read.
　（第１実施形態）
　＜固体撮像装置の全体構成＞
　第１実施形態として、本技術に係る半導体装置を、固体撮像装置（ＣＭＯＳイメージセンサ）に適用する場合を例示する。第１実施形態に係る固体撮像装置１００は、図１に示すように、画素アレイ部１１０と、画素アレイ部１１０からの電気信号の読み取りや所定の信号処理を行う周辺回路を備える。 (First Embodiment)
<Overall configuration of solid-state image sensor>
As a first embodiment, a case where the semiconductor device according to the present technology is applied to a solid-state image sensor (CMOS image sensor) will be illustrated. As shown in FIG. 1, the solid-state image sensor 100 according to the first embodiment includes a pixel array unit 110 and peripheral circuits for reading an electric signal from the pixel array unit 110 and performing predetermined signal processing.
　第１実施形態に係る固体撮像装置１００は、周辺回路として、行アドレスや行走査を制御する行選択回路１２０、列アドレスや列走査を制御する水平転送走査回路１３０、制御回路として内部クロックを生成するタイミング制御回路１４０を備える。更に、第１実施形態に係る固体撮像装置１００は、周辺回路として、ＡＤＣ群１５０、ランプ信号発生器としてのデジタル－アナログ変換装置（ＤＡＣ）１６０、アンプ回路１７０、信号処理回路１８０、及び水平転送線１９０を有する。更に、第１実施形態に係る固体撮像装置１００は、周辺回路として、図示しないＤＣ電源供給回路を有する。 The solid-state image sensor 100 according to the first embodiment generates a row selection circuit 120 for controlling row addresses and row scans, a horizontal transfer scanning circuit 130 for controlling column addresses and column scans, and an internal clock as control circuits. The timing control circuit 140 is provided. Further, the solid-state imaging device 100 according to the first embodiment includes an ADC group 150 as peripheral circuits, a digital-to-analog converter (DAC) 160 as a lamp signal generator, an amplifier circuit 170, a signal processing circuit 180, and horizontal transfer. It has a line 190. Further, the solid-state image sensor 100 according to the first embodiment has a DC power supply circuit (not shown) as a peripheral circuit.
　画素アレイ部１１０は、図２に示すように、多数の画素３０がアレイ状（マトリックス状）に配列されて構成されている。画素３０は、例えば図３に示すように、例えばフォトダイオード（ＰＤ）からなる光電変換素子Ｄ１を有する。画素３０は、光電変換素子Ｄ１に対して、転送トランジスタＴ１、リセットトランジスタＴ２、増幅トランジスタＴ３、及び選択トランジスタＴ４の４つのトランジスタを能動素子として有する。また、画素３０からの信号を電圧変動として取り出すために、画素３０が列方向で共有化されている垂直信号線（ＬＳＧＮ）に定電流源負荷３１が接続されている。 As shown in FIG. 2, the pixel array unit 110 is configured by arranging a large number of pixels 30 in an array shape (matrix shape). The pixel 30 has, for example, a photoelectric conversion element D1 made of, for example, a photodiode (PD), as shown in FIG. The pixel 30 has four transistors, a transfer transistor T1, a reset transistor T2, an amplification transistor T3, and a selection transistor T4, as active elements with respect to the photoelectric conversion element D1. Further, in order to take out the signal from the pixel 30 as a voltage fluctuation, the constant current source load 31 is connected to the vertical signal line (LSGN) in which the pixel 30 is shared in the column direction.
　光電変換素子Ｄ１は、入射光をその光量に応じた量の電荷（ここでは電子）に光電変換する。転送素子としての転送トランジスタＴ１は、光電変換素子Ｄ１と入力ノードとしてのフローティングディフュージョンＦＤとの間に接続され、転送制御線ＬＴＲＧを通じてそのゲート（転送ゲート）に制御信号である転送信号ＴＲＧが与えられる。これにより、転送トランジスタＴ１は、光電変換素子Ｄ１で光電変換された電子をフローティングディフュージョンＦＤに転送する。 The photoelectric conversion element D1 photoelectrically converts the incident light into an electric charge (electrons in this case) in an amount corresponding to the amount of the light. The transfer transistor T1 as a transfer element is connected between the photoelectric conversion element D1 and the floating diffusion FD as an input node, and a transfer signal TRG which is a control signal is given to the gate (transfer gate) through the transfer control line LTRG. .. As a result, the transfer transistor T1 transfers the electrons photoelectrically converted by the photoelectric conversion element D1 to the floating diffusion FD.
　リセットトランジスタＴ２は、電源電圧ＶＤＤが供給される電源ラインＬＶＤＤとフローティングディフュージョンＦＤとの間に接続され、リセット制御線ＬＲＳＴを通してそのゲートに制御信号であるリセット信号ＲＳＴが与えられる。これにより、リセット素子としてのリセットトランジスタＴ２は、フローティングディフュージョンＦＤの電位を電源ラインＬＶＤＤの電位にリセットする。 The reset transistor T2 is connected between the power supply line L VDD to which the power supply voltage VDD is supplied and the floating diffusion FD, and the reset signal RST, which is a control signal, is given to the gate through the reset control line LRST. As a result, the reset transistor T2 as the reset element resets the potential of the floating diffusion FD to the potential of the power supply line L VDD.
　フローティングディフュージョンＦＤには、増幅素子としての増幅トランジスタＴ３のゲートが接続されている。即ち、フローティングディフュージョンＦＤは増幅素子としての増幅トランジスタＴ３の入力ノードとして機能する。増幅トランジスタＴ３と選択トランジスタＴ４は電源電圧ＶＤＤが供給される電源ラインＬＶＤＤと信号線ＬＳＧＮとの間に直列に接続されている。このように、増幅トランジスタＴ３は、選択トランジスタＴ４を介して信号線ＬＳＧＮに接続され、画素部外の定電流源ＩＳとソースフォロアを構成している。そして、選択制御線ＬＳＥＬを通してアドレス信号に応じた制御信号である選択信号ＳＥＬが選択トランジスタＴ４のゲートに与えられ、選択トランジスタＴ４がオンする。選択トランジスタＴ４がオンすると、増幅トランジスタＴ３はフローティングディフュージョンＦＤの電位を増幅してその電位に応じた電圧を信号線ＬＳＧＮに出力する。信号線ＬＳＧＮを通じて、各画素から出力された電圧は、ＡＤＣ群１５０に出力される。これらの動作は、例えば転送トランジスタＴ１、リセットトランジスタＴ２、及び選択トランジスタＴ４の各ゲートが行単位で接続されていることから、１行分の各画素について同時に行われる。 The gate of the amplification transistor T3 as an amplification element is connected to the floating diffusion FD. That is, the floating diffusion FD functions as an input node of the amplification transistor T3 as an amplification element. The amplification transistor T3 and the selection transistor T4 are connected in series between the power supply line L VDD to which the power supply voltage VDD is supplied and the signal line LSGN. In this way, the amplification transistor T3 is connected to the signal line LSGN via the selection transistor T4, and constitutes a constant current source IS outside the pixel portion and a source follower. Then, the selection signal SEL, which is a control signal corresponding to the address signal, is given to the gate of the selection transistor T4 through the selection control line LSEL, and the selection transistor T4 is turned on. When the selection transistor T4 is turned on, the amplification transistor T3 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the signal line LSGN. The voltage output from each pixel through the signal line LSGN is output to the ADC group 150. Since, for example, the gates of the transfer transistor T1, the reset transistor T2, and the selection transistor T4 are connected in row units, these operations are performed simultaneously for each pixel for one row.
　画素アレイ部１１０に配線されているリセット制御線ＬＲＳＴ、転送制御線ＬＴＲＧ、及び選択制御線ＬＳＥＬが一組として画素配列の各行単位で配線されている。リセット制御線ＬＲＳＴ、転送制御線ＬＴＲＧ及び選択制御線ＬＳＥＬはそれぞれＭ本ずつ設けられている。これらのリセット制御線ＬＲＳＴ、転送制御線ＬＴＲＧ、及び選択制御線ＬＳＥＬは、行選択回路１２０により駆動される。 The reset control line LRST, the transfer control line LTRG, and the selection control line LSEL wired to the pixel array unit 110 are wired as a set for each row of the pixel array. The reset control line LRST, the transfer control line LTRG, and the selection control line LSEL are each provided with M lines. These reset control line LRST, transfer control line LTRG, and selection control line LSEL are driven by the row selection circuit 120.
　図１に示したＡＤＣ群１５０は、比較器（コンパレータ）１５１、カウンタ１５２、及びラッチ１５３を有するシングルスロープ型ＡＤＣが複数列配列されている。比較器１５１は、例えば図４に示すように、差動対を構成する差動入力トランジスタＴ２１，Ｔ２２と、カレントミラー回路からなる能動負荷トランジスタＴ１１，Ｔ１２を含む差動増幅回路を有する。差動入力トランジスタＴ２１，Ｔ２２はｎ型ＭＯＳＦＥＴ（以下、「ｎＭＯＳ」ともいう）で構成され、能動負荷トランジスタＴ１１，Ｔ１２はｐ型ＭＯＳＦＥＴ（以下、「ｐＭＯＳ」ともいう）で構成される。第１実施形態に係る固体撮像装置の周辺回路においては、能動負荷トランジスタＴ１１，Ｔ１２及び差動入力トランジスタＴ２１，Ｔ２２がノイズ源となる。 In the ADC group 150 shown in FIG. 1, a plurality of single-slope ADCs having a comparator 151, a counter 152, and a latch 153 are arranged in a plurality of rows. As shown in FIG. 4, for example, the comparator 151 has a differential amplifier circuit including differential input transistors T21 and T22 forming a differential pair and active load transistors T11 and T12 including a current mirror circuit. The differential input transistors T21 and T22 are composed of n-type MOSFETs (hereinafter, also referred to as “nMOS”), and the active load transistors T11 and T12 are composed of p-type MOSFETs (hereinafter, also referred to as “pMOS”). In the peripheral circuit of the solid-state image sensor according to the first embodiment, the active load transistors T11 and T12 and the differential input transistors T21 and T22 serve as noise sources.
　比較器１５１の２つの差動入力端子には、それぞれにサンプリング容量Ｃ１，Ｃ２が直列に接続されている。比較器１５１は、ＤＡＣ１６０により生成される参照電圧を階段状に変化させたランプ波形である参照電圧（ＤＡＣ側入力）Ｖｓｌｏｐと、行線毎に画素から垂直信号線ＬＳＧＮを経由し得られるアナログ信号（ＶＳＬ（Vertical Signal Line）側入力）を比較する。 Sampling capacitances C1 and C2 are connected in series to the two differential input terminals of the comparator 151, respectively. The comparator 151 includes a reference voltage (DAC side input) Vslop, which is a ramp waveform obtained by changing the reference voltage generated by the DAC 160 in a stepwise manner, and an analog signal obtained from a pixel via the vertical signal line LSGN for each line. (VSL (Vertical Signal Line) side input) is compared.
　図１に示したカウンタ１５２は、比較器１５１の比較時間をカウントする。ＡＤＣ群１５０は、ｎビットデジタル信号変換機能を有し、垂直信号線（列線）毎に配置され、列並列ＡＤＣブロックが構成される。各ラッチ１５３の出力は、例えば２ｎビット幅の水平転送線１９０に接続されている。そして、水平転送線１９０に対応した２ｎ個のアンプ回路１７０、及び信号処理回路１８０が配置される。 The counter 152 shown in FIG. 1 counts the comparison time of the comparator 151. The ADC group 150 has an n-bit digital signal conversion function and is arranged for each vertical signal line (row line) to form a row-parallel ADC block. The output of each latch 153 is connected to, for example, a horizontal transfer line 190 having a width of 2 n bits. Then, 2n amplifier circuits 170 and signal processing circuits 180 corresponding to the horizontal transfer lines 190 are arranged.
　第１実施形態に係る固体撮像装置を構成する各回路の半導体チップ上の配置図を図５に示す。図５の左右方向の中央位置において、上側から下側に向かって、画素アレイ部２０１、定電流源負荷２０５、比較器２０６、カウンタ／ラッチ回路２０７及び水平転送走査回路２０８が配置されている。図５の左側には、画素アレイ部２０１に隣接して行選択回路２０２が配置されている。また、定電流源負荷２０５及び比較器２０６に隣接してＤＡＣ２０３が配置されている。また、カウンタ／ラッチ回路２０７及び水平転送走査回路２０８に隣接して、タイミング制御回路２０４が配置されている。図５の右側には、画素アレイ部２０１に隣接してＤＣ供給回路２０９が配置されている。また、画素アレイ部２０１、定電流源負荷２０５、比較器２０６、カウンタ／ラッチ回路２０７及び水平転送走査回路２０８に隣接して、信号処理回路２１０が配置されている。 FIG. 5 shows a layout diagram of each circuit constituting the solid-state image sensor according to the first embodiment on the semiconductor chip. At the center position in the left-right direction of FIG. 5, the pixel array unit 201, the constant current source load 205, the comparator 206, the counter / latch circuit 207, and the horizontal transfer scanning circuit 208 are arranged from the upper side to the lower side. On the left side of FIG. 5, a row selection circuit 202 is arranged adjacent to the pixel array unit 201. Further, the DAC 203 is arranged adjacent to the constant current source load 205 and the comparator 206. Further, a timing control circuit 204 is arranged adjacent to the counter / latch circuit 207 and the horizontal transfer scanning circuit 208. On the right side of FIG. 5, a DC supply circuit 209 is arranged adjacent to the pixel array unit 201. Further, a signal processing circuit 210 is arranged adjacent to the pixel array unit 201, the constant current source load 205, the comparator 206, the counter / latch circuit 207, and the horizontal transfer scanning circuit 208.
　第１実施形態に係る固体撮像装置を構成する各回路は、半導体基板上に形成されたフォトダイオード、ＭＯＳＦＥＴ、バイポーラトランジスタ、抵抗素子、容量素子等の半導体デバイスを多層配線で接続することで構成される。第１実施形態に係る固体撮像装置を構成する各回路を半導体基板上に形成する方法としては、一般的なＣＭＯＳプロセスを採用可能である。 Each circuit constituting the solid-state imaging device according to the first embodiment is configured by connecting semiconductor devices such as photodiodes, MOSFETs, bipolar transistors, resistance elements, and capacitive elements formed on a semiconductor substrate with multilayer wiring. To. A general CMOS process can be adopted as a method for forming each circuit constituting the solid-state image sensor according to the first embodiment on the semiconductor substrate.
　＜半導体装置の具体的構成＞
　次に、本技術に係る半導体装置の具体的構成を比較例と対比しながら説明する。ＣＭＯＳイメージセンサが様々な分野への応用が進むにつれて、小型化及び高性能化が求められており、回路面積を増加させることなく、低ノイズ化が可能な技術が要求されている。 <Specific configuration of semiconductor devices>
Next, a specific configuration of the semiconductor device according to the present technology will be described in comparison with a comparative example. As the application of CMOS image sensors to various fields progresses, miniaturization and higher performance are required, and a technique capable of reducing noise without increasing the circuit area is required.
　このような要求に対して、我々の研究の結果、図６及び図７に示すように、ＭＯＳＦＥＴのゲート電極（ＦＧ）５とバックゲート領域（ＢＧ）を構成するｐ型ウェル３とを電気的に共通化した構造（ＦＧ＝ＢＧ構造）が低ノイズ化に有効であることが分かった。図６及び図７では、ｐ型の半導体基板１上に、ｎ型ウェル２及びｐ型ウェル３が設けられている。ｐ型ウェル３の上部の一部にはＳＴＩ領域４が設けられており、ＳＴＩ領域４により活性領域Ａ１，Ａ２がそれぞれ区画されている。活性領域Ａ１においては、ｐ型ウェル３の上部にＭＯＳＦＥＴのｎ＋型のソース領域１１及びｎ＋型のドレイン領域１２が設けられている。一方、活性領域Ａ２において、ｐ型ウェル３の上部にｐ＋型のバックゲート端子１３が設けられている。 In response to such demands, as a result of our research, as shown in FIGS. 6 and 7, the gate electrode (FG) 5 of the MOSFET and the p-type well 3 constituting the back gate region (BG) are electrically connected. It was found that the structure common to the above (FG = BG structure) is effective for noise reduction. In FIGS. 6 and 7, an n-type well 2 and a p-type well 3 are provided on the p-type semiconductor substrate 1. An STI region 4 is provided in a part of the upper part of the p-type well 3, and the active regions A1 and A2 are respectively partitioned by the STI region 4. In the active region A1, an n + type source region 11 and an n + type drain region 12 of the MOSFET are provided above the p-type well 3. On the other hand, in the active region A2, a p + type back gate terminal 13 is provided above the p type well 3.
　図８は、ＭＯＳＦＥＴの標準構造の場合と、ＭＯＳＦＦＴのＦＧ＝ＧＢ構造とした場合のそれぞれのフリッカーノイズのスペクトルを示す。図８に示すように、ＦＧ＝ＧＢ構造とすることにより、ＭＯＳＦＥＴの素子面積を大きくすることなく、ゲート入力換算ノイズ（Ｓｖｇ）で約半分のノイズ低減効果を確認した。 FIG. 8 shows the spectra of flicker noise in the case of the standard structure of MOSFET and the case of FG = GB structure of MOSFFT. As shown in FIG. 8, by setting FG = GB structure, it was confirmed that the noise reduction effect of about half of the gate input conversion noise (Svg) was confirmed without increasing the element area of the MOSFET.
　このＦＧ＝ＧＢ構造のＭＯＳＦＥＴを、図１に示した列並列ＡＤ変換部を構成するＡＤＣ１５１のノイズ源となっている、図４に示した比較器１５１を構成する差動入力トランジスタＴ２１，Ｔ２２に適用した構造を図９及び図１０に示す。列並列ＡＤ変換回路は、画素アレイ部１１０の列毎に対してＡＤ変換回路（カラム回路）が１個配置されるため、図１に示すように、カラム回路が水平方向に、任意の間隔（カラムピッチ）で繰り返し配置される。このような回路レイアウトでは、コンパレータを構成する差動入力トランジスタに関しても、図９及び図１０に示すように、等間隔で繰り返し配置されたレイアウトになる。 This MOSFET having an FG = GB structure is used in the differential input transistors T21 and T22 constituting the comparator 151 shown in FIG. 4, which is a noise source of the ADC 151 constituting the column-parallel AD conversion unit shown in FIG. The applied structure is shown in FIGS. 9 and 10. In the column-parallel AD conversion circuit, one AD conversion circuit (column circuit) is arranged for each column of the pixel array unit 110. Therefore, as shown in FIG. 1, the column circuits are arranged at arbitrary intervals (column circuits) in the horizontal direction. It is repeatedly arranged at the column pitch). In such a circuit layout, as shown in FIGS. 9 and 10, the differential input transistors constituting the comparator are also repeatedly arranged at equal intervals.
　各カラム回路には、それぞれの列に配置された画素からの独立した電気信号が伝わるため、差動入力トランジスタＴ２１，Ｔ２２をＦＧ＝ＢＧ構造にした場合、ゲート電極５と電気的に繋がっているｐ型ウェル３は、カラム間で電気的に分離する必要がある。カラム間でｐ型ウェル３を電気的に分離するためには、差動入力トランジスタＴ２１，Ｔ２２がｎＭＯＳである場合は、ｐ型の半導体基板１とバックゲートであるｐ型ウェル３との間に、ｎ型ウェル２が設けられる。更に、カラム間のｐ型ウェル３の間には、ＳＴＩ領域４の直下にｎ型ウェル１７が設けられる。 Since independent electrical signals from the pixels arranged in each row are transmitted to each column circuit, when the differential input transistors T21 and T22 have an FG = BG structure, they are electrically connected to the gate electrode 5. The p-type well 3 needs to be electrically separated between the columns. In order to electrically separate the p-type well 3 between columns, when the differential input transistors T21 and T22 are nMOS, between the p-type semiconductor substrate 1 and the p-type well 3 which is a back gate. , N-type well 2 is provided. Further, an n-type well 17 is provided directly below the STI region 4 between the p-type wells 3 between the columns.
　ところで、ＣＭＯＳイメージセンサの高解像化を達成すべく、画素の微細化が進んでいる。画素の微細化か進むと、画素ピッチが縮小され、それに伴いカラムピッチも縮小する。しかし、図９及び図１０に示したＦＧ＝ＢＧ構造において、カラムピッチを縮小する場合に、差動入力トランジスタＴ２１，Ｔ２２のチャネル幅Ｗ３を縮小させると、ゲート電極５の面積が縮小することなり、ランダムノイズを悪化させてしまう。このため、カラムピッチを縮小させる場合には、カラム間のＳＴＩ領域４の幅Ｗ２と、ＳＴＩ領域４の下のｎ型ウェル１７の幅Ｗ１を縮小する必要がある。 By the way, in order to achieve high resolution of CMOS image sensors, pixel miniaturization is progressing. As the pixel miniaturization progresses, the pixel pitch is reduced, and the column pitch is also reduced accordingly. However, in the FG = BG structure shown in FIGS. 9 and 10, when the column pitch is reduced and the channel width W3 of the differential input transistors T21 and T22 is reduced, the area of the gate electrode 5 is reduced. , Exacerbates random noise. Therefore, when reducing the column pitch, it is necessary to reduce the width W2 of the STI region 4 between the columns and the width W1 of the n-type well 17 under the STI region 4.
　ｎ型ウェル１７は、通常、半導体基板１にｎ型不純物をイオン注入した後、熱処理を行い不純物を活性化させることにより形成可能であるが、ｎ型ウェル１７の幅Ｗ１をある幅以下に縮小してしまうと、ｎ型ウェル１７に隣接するｐ型ウェル３間の耐圧が急激に低下する。耐圧特性が低下すると、カラム回路間でリーク電流が流れて、不良動作の原因となる。その耐圧を一定以上に保つためには、ｎ型ウェル１７の不純物濃度をより高くする必要がある。しかし、イオン注入後に高温の熱処理を行うため、Ｓｉ基板表面から深くて、高不純物濃度で、且つ幅Ｗ１の狭いｎ型ウェル１７を形成することは難しい。 The n-type well 17 can usually be formed by ion-implanting n-type impurities into the semiconductor substrate 1 and then performing heat treatment to activate the impurities, but the width W1 of the n-type well 17 is reduced to a certain width or less. If this happens, the pressure resistance between the p-type wells 3 adjacent to the n-type well 17 will drop sharply. When the withstand voltage characteristic deteriorates, a leak current flows between the column circuits, which causes a defective operation. In order to keep the withstand voltage above a certain level, it is necessary to increase the impurity concentration of the n-type well 17. However, since high-temperature heat treatment is performed after ion implantation, it is difficult to form an n-type well 17 that is deep from the Si substrate surface, has a high impurity concentration, and has a narrow width W1.
　これに対して、特許文献３では、ＭＯＳＦＥＴが狭い間隔で繰り返し配置されたレイアウトに対して、隣接ＭＯＳＦＥＴ間のウェル間耐圧を向上される技術が開示されている。この技術は、図１１に示すように、ｐ型の半導体基板１とｐ型ウェル（バックゲート）３を分離しているｎ型ウェル２に関して、ｐ型ウェル３とｎ型ウェル２の接合面がＳＴＩ領域４の底面より浅い位置になるように形成する。このような構造にすれば、隣接するｐ型ウェル３間の距離（破線の矢印で図示）を長くすることができるので、図９及び図１０に示した構造よりも素子分離耐圧を向上させることができる。ただし、この構造の場合、ＳＴＩ領域４が壁となって、バックゲートを構成するｐ型ウェル３を半導体基板１の上面まで引き出す経路が確保できなくなってしまう。 On the other hand, Patent Document 3 discloses a technique for improving the withstand voltage between wells between adjacent MOSFETs in a layout in which MOSFETs are repeatedly arranged at narrow intervals. In this technique, as shown in FIG. 11, with respect to the n-type well 2 that separates the p-type semiconductor substrate 1 and the p-type well (back gate) 3, the joint surface between the p-type well 3 and the n-type well 2 is formed. It is formed so as to be shallower than the bottom surface of the STI region 4. With such a structure, the distance between the adjacent p-type wells 3 (shown by the broken line arrow) can be increased, so that the element separation withstand voltage can be improved as compared with the structures shown in FIGS. 9 and 10. Can be done. However, in the case of this structure, the STI region 4 becomes a wall, and it becomes impossible to secure a path for pulling out the p-type well 3 constituting the back gate to the upper surface of the semiconductor substrate 1.
　図１１に示した構造に対して、特許文献３では、図１２に示すように、壁となっているＳＴＩ領域４ｘの深さを周辺のＳＴＩ領域４より浅く形成することで、浅いＳＴＩ領域４ｘの下をくぐりぬけて、バックゲートを半導体基板１の上面に取り出した構造を採用している。しかしながら、このような構造を形成するためには、深さの異なるＳＴＩ領域４，４ｘを形成する必要があるため、製造プロセスが複雑化し、製造コストが増大する。 In contrast to the structure shown in FIG. 11, in Patent Document 3, as shown in FIG. 12, the depth of the STI region 4x that is a wall is formed to be shallower than that of the surrounding STI region 4, so that the shallow STI region 4x A structure is adopted in which the back gate is taken out on the upper surface of the semiconductor substrate 1 by passing under the bottom. However, in order to form such a structure, it is necessary to form STI regions 4, 4x having different depths, which complicates the manufacturing process and increases the manufacturing cost.
　これに対して、製造プロセスを複雑化せずに、低ノイズ化と小型化を両立することが可能な第１実施形態に係る半導体装置の構造を説明する。第１実施形態に係る半導体装置は、図１３及び図１４に示すように、ｐ型のＳｉ基板からなる半導体基板１と、半導体基板１上に設けられたｎ型の半導体層であるｎ型ウェル２と、ｎ型ウェル２上に設けられたｐ型の半導体層であるｐ型ウェル３とを備える。 On the other hand, the structure of the semiconductor device according to the first embodiment, which can achieve both low noise and miniaturization without complicating the manufacturing process, will be described. As shown in FIGS. 13 and 14, the semiconductor device according to the first embodiment includes a semiconductor substrate 1 made of a p-type Si substrate and an n-type well which is an n-type semiconductor layer provided on the semiconductor substrate 1. 2 and a p-type well 3 which is a p-type semiconductor layer provided on the n-type well 2 are provided.
　ｎ型ウェル２は、半導体基板１とｐ型ウェル３とを分離する機能を有する。ｐ型ウェル３は、バックゲート領域として機能する。ｐ型ウェル３には、ｎ＋型のソース領域１１及びｎ＋型のドレイン領域１２が互いに離間して設けられている。ソース領域１１及びドレイン領域１２で挟まれるチャネル領域上には、ゲート絶縁膜（不図示）を介してゲート電極５が設けられている。ゲート電極５の材料としては、高不純物濃度のポリシリコンを使用可能であり、ポリシリコン以外の金属材料も使用可能である。 The n-type well 2 has a function of separating the semiconductor substrate 1 and the p-type well 3. The p-type well 3 functions as a back gate region. The p-type well 3 is provided with an n + type source region 11 and an n + type drain region 12 separated from each other. A gate electrode 5 is provided on the channel region sandwiched between the source region 11 and the drain region 12 via a gate insulating film (not shown). As the material of the gate electrode 5, polysilicon having a high impurity concentration can be used, and a metal material other than polysilicon can also be used.
　ｐ型ウェル３には、ソース領域１１及びドレイン領域１２と離間してｐ＋型のバックゲート端子１３が設けられている。バックゲート端子１３は、ｐ型ウェル３よりも高不純物濃度のウェルタップ領域で構成されている。バックゲート端子１３と、ソース領域１１及びドレイン領域１２との間にはＳＴＩ領域４が介在していない。即ち、バックゲート端子１３、ソース領域１１及びドレイン領域１２は、ＳＴＩ領域４で囲まれた同一の活性領域Ａ０内に設けられている。 The p-type well 3 is provided with a p + type back gate terminal 13 separated from the source region 11 and the drain region 12. The back gate terminal 13 is composed of a well tap region having a higher impurity concentration than the p-type well 3. The STI region 4 is not interposed between the back gate terminal 13 and the source region 11 and the drain region 12. That is, the back gate terminal 13, the source region 11, and the drain region 12 are provided in the same active region A0 surrounded by the STI region 4.
　ｎ型ウェル２と、ｐ型ウェル３との接合面は、ＳＴＩ領域４よりも浅く、ソース領域１１及びドレイン領域１２より深い位置になるように設けられている。このため、隣接する比較器１５１を構成するＭＯＳＦＥＴとの間の電気的な耐圧が確保される。 The joint surface between the n-type well 2 and the p-type well 3 is provided so as to be shallower than the STI region 4 and deeper than the source region 11 and the drain region 12. Therefore, the electrical withstand voltage between the MOSFETs constituting the adjacent comparator 151 is secured.
　図１３に示すように、ソース領域１１上には、メタルコンタクト３１，３２が配置されている。ドレイン領域１２上には、メタルコンタクト３３，３４が配置されている。ゲート電極５上には、メタルコンタクト３５が配置されている。バックゲート端子１３上には、メタルコンタクト３６，３７が配置されている。 As shown in FIG. 13, metal contacts 31 and 32 are arranged on the source region 11. Metal contacts 33 and 34 are arranged on the drain region 12. A metal contact 35 is arranged on the gate electrode 5. Metal contacts 36 and 37 are arranged on the back gate terminal 13.
　バックゲート端子１３は、ゲート電極５と電気的に共通（同電位）である。図示を省略するが、バックゲート端子１３は、メタルコンタクト３５，３６，３７等のメタルコンタクト及び多層配線を介してゲート電極５と電気的に接続されている。図１４に示すように、ソース領域１１、ドレイン領域１２及びバックゲート端子１３の上部には、シリサイド層２１，２２，２３がそれぞれ設けられている。シリサイド層２１，２２，２３の材料としては、例えばコバルト（Ｃｏ）シリサイドや、ニッケル（Ｎｉ）シリサイドからなる。なお、図１３の平面レイアウトでは、図１４に示したシリサイド層２１，２２，２３や多層配線を省略している。 The back gate terminal 13 is electrically common (same potential) as the gate electrode 5. Although not shown, the back gate terminal 13 is electrically connected to the gate electrode 5 via metal contacts such as metal contacts 35, 36, 37 and multi-layer wiring. As shown in FIG. 14, the source region 11, the drain region 12, and the upper portions of the back gate terminal 13 are provided with the VDD layers 21, 22, and 23, respectively. The material of the silicide layers 21, 22, and 23 is, for example, cobalt (Co) silicide or nickel (Ni) silicide. In the plane layout of FIG. 13, the silicide layers 21, 22, 23 and the multilayer wiring shown in FIG. 14 are omitted.
　図１３及び図１４に示すように、ソース領域１１と、バックゲート端子１３との間に挟まれたｐ型ウェル３上には、分離膜（シリサイドブロック層）６が設けられている。分離膜６は、分離膜６直下のシリサイド層の形成を防止し、ソース領域１１及びドレイン領域１２とバックゲート端子１３とのシリサイド層を介した短絡を防止する機能を有する。ＣＭＯＳプロセスでは、Ｓｉからなる半導体基板１とメタルコンタクト３１～３６の接触抵抗を低減するシリサイドプロセスが用いることは一般的だが、このプロセスを用いた場合、ＳＴＩ領域４により被覆されていないＳｉからなる半導体基板１表面に関しては、シリサイドの形成を防止する分離層６を配置しない領域は、全てシリサイド化される。 As shown in FIGS. 13 and 14, a separation film (0045 block layer) 6 is provided on the p-type well 3 sandwiched between the source region 11 and the back gate terminal 13. The separation membrane 6 has a function of preventing the formation of a silicide layer directly under the separation membrane 6 and preventing a short circuit between the source region 11 and the drain region 12 and the back gate terminal 13 via the silicide layer. In the CMOS process, a silicide process for reducing the contact resistance between the semiconductor substrate 1 made of Si and the metal contacts 31 to 36 is generally used, but when this process is used, it is made of Si not covered by the STI region 4. With respect to the surface of the semiconductor substrate 1, all the regions where the separation layer 6 for preventing the formation of VDD is not arranged are silicidized.
　分離膜６は、例えばゲート電極５と同一材料からなり、ゲート電極５と同時に形成可能である。分離膜６がゲート電極５と同一材料の場合、ゲート電極５は多結晶Ｓｉ等の導電体である場合が多く、電位が揺れないように、分離膜６を、図示しないメタルコンタクトや配線等で半導体基板１等に電気的に接続して電位固定することが好ましい。分離膜６は、ゲート電極５と同一材料の層と、ゲート絶縁膜（不図示）との積層構造であってもよい。分離膜６は、ゲート電極５と同一材料以外にも、窒化物や二酸化シリコン（ＳｉＯ２）等のシリコン（Ｓｉ）系酸化物等の絶縁材料も使用可能である。分離膜６を絶縁材料で形成する場合には、分離膜６の電位を固定させなくてよい。 The separation membrane 6 is made of the same material as the gate electrode 5, for example, and can be formed at the same time as the gate electrode 5. When the separation membrane 6 is made of the same material as the gate electrode 5, the gate electrode 5 is often a conductor such as polycrystalline Si, and the separation membrane 6 is made of a metal contact, wiring, etc. (not shown) so that the potential does not fluctuate. It is preferable to electrically connect to the semiconductor substrate 1 or the like to fix the potential. The separation membrane 6 may have a laminated structure of a layer of the same material as the gate electrode 5 and a gate insulating film (not shown). In addition to the same material as the gate electrode 5, the separation membrane 6 can also use an insulating material such as a nitride or a silicon (Si) -based oxide such as silicon dioxide (SiO 2). When the separation membrane 6 is formed of an insulating material, the potential of the separation membrane 6 does not have to be fixed.
　第１実施形態に係る半導体装置によれば、ＭＯＳＦＥＴのソース領域１１及びドレイン領域１２とバックゲート端子１３とが、ＳＴＩ領域４で囲まれた同一の活性領域Ａ０内に設けられている。このため、図１２に示した構造と比較して、ＳＴＩ領域４の深さを部分的に変えずにバックゲート端子１３を設けることが可能であり、製造プロセスが容易となる。また、第１実施形態に係る半導体装置では、隣接ＭＯＳＦＥＴ間のウェル間耐圧も確保でき、回路の小型化にも適した構造である。したがって、製造コストを増加させることなく、低ノイズ化と回路の小型化の両立が可能となる。 According to the semiconductor device according to the first embodiment, the source region 11 and drain region 12 of the MOSFET and the back gate terminal 13 are provided in the same active region A0 surrounded by the STI region 4. Therefore, as compared with the structure shown in FIG. 12, the back gate terminal 13 can be provided without partially changing the depth of the STI region 4, which facilitates the manufacturing process. Further, the semiconductor device according to the first embodiment has a structure suitable for miniaturization of a circuit because a withstand voltage between wells between adjacent MOSFETs can be secured. Therefore, it is possible to achieve both low noise and miniaturization of the circuit without increasing the manufacturing cost.
　第１実施形態に係る半導体装置は、固体撮像装置を構成するＭＯＳＦＥＴのうち、ノイズ源となるＭＯＳＦＥＴに好適である。例えば、第１実施形態に係る半導体装置を、図４に示した比較器１５１の差動入力トランジスタＴ２１，Ｔ２２に適用することにより、周辺回路のランダムノイズが従来構造に対して約１３％程度低減できることを確認した。 The semiconductor device according to the first embodiment is suitable for a MOSFET as a noise source among the MOSFETs constituting the solid-state image sensor. For example, by applying the semiconductor device according to the first embodiment to the differential input transistors T21 and T22 of the comparator 151 shown in FIG. 4, the random noise of the peripheral circuit is reduced by about 13% with respect to the conventional structure. I confirmed that I could do it.
　＜第１実施形態の第１変形例＞
　第１実施形態の第１変形例に係る半導体装置は、図１５に示すように、半導体装置がｐＭＯＳで構成されている点が、図１４に示した第１実施形態に係る半導体装置と異なる。第１実施形態の第１変形例に係る半導体装置は、ｐ型の半導体基板１と、半導体基板１上に設けられたｎ型の半導体層であるｎ型ウェル７とを備える。 <First modification of the first embodiment>
As shown in FIG. 15, the semiconductor device according to the first modification of the first embodiment is different from the semiconductor device according to the first embodiment shown in FIG. 14 in that the semiconductor device is composed of pMOS. The semiconductor device according to the first modification of the first embodiment includes a p-type semiconductor substrate 1 and an n-type well 7 which is an n-type semiconductor layer provided on the semiconductor substrate 1.
　ｎ型ウェル７の上部には、ｐ＋型のソース領域４１及びｐ＋型のドレイン領域４２が設けられている。ソース領域４１及びドレイン領域４２に挟まれたチャネル領域上には、ゲート絶縁膜（不図示）を介してゲート電極５が設けられている。ｎ型ウェル７と半導体基板１との接合面は、ＳＴＩ領域４よりも浅く、ソース領域４１及びドレイン領域４２よりも深い。 A p + type source region 41 and a p + type drain region 42 are provided above the n-type well 7. A gate electrode 5 is provided on the channel region sandwiched between the source region 41 and the drain region 42 via a gate insulating film (not shown). The joint surface between the n-type well 7 and the semiconductor substrate 1 is shallower than the STI region 4 and deeper than the source region 41 and the drain region 42.
　ｎ型ウェル７の上部には、ソース領域４１及びドレイン領域４２から離間して、ｎ＋型のバックゲート端子４３が設けられている。バックゲート端子４３は、ｎ型ウェル７よりも高不純物濃度のウェルタップ領域で構成されている。バックゲート端子４３は、ゲート電極５に電気的に接続されて同電位となる。バックゲート端子４３と、ソース領域４１及びドレイン領域４２との間にはＳＴＩ領域４が介在しない。即ち、バックゲート端子４３と、ソース領域４１及びドレイン領域４２とは、ＳＴＩ領域４に囲まれた同一の活性領域Ａ０内に設けられている。 An n + type back gate terminal 43 is provided above the n-type well 7 so as to be separated from the source region 41 and the drain region 42. The back gate terminal 43 is composed of a well tap region having a higher impurity concentration than the n-type well 7. The back gate terminal 43 is electrically connected to the gate electrode 5 and has the same potential. The STI region 4 does not intervene between the back gate terminal 43 and the source region 41 and the drain region 42. That is, the back gate terminal 43, the source region 41, and the drain region 42 are provided in the same active region A0 surrounded by the STI region 4.
　バックゲート端子４３と、ソース領域４１及びドレイン領域４２の間のｎ型ウェル７上には分離膜６が設けられている。バックゲート端子４３、ソース領域４１及びドレイン領域４２の上部には、シリサイド層２１，２２，２３がそれぞれ設けられている。ＣＭＯＳプロセスにおいてサリサイド工程を実施しない場合には、シリサイド層２１，２２，２３は設けられていなくてもよい。第１実施形態の第１変形例に係る半導体装置の他の構成は、図１４に示した第１実施形態に係る半導体装置と同様であるので、重複した説明を省略する。 A separation membrane 6 is provided on the n-type well 7 between the back gate terminal 43 and the source region 41 and the drain region 42. Silicide layers 21, 22, and 23 are provided above the back gate terminal 43, the source region 41, and the drain region 42, respectively. When the salicide step is not carried out in the CMOS process, the silicide layers 21, 22, and 23 may not be provided. Since other configurations of the semiconductor device according to the first modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
　第１実施形態の第１変形例に係る半導体装置によれば、半導体装置がｐＭＯＳで構成されている場合でも、第１実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。 According to the semiconductor device according to the first modification of the first embodiment, even when the semiconductor device is composed of pMOS, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment. ..
　＜第１実施形態の第２変形例＞
　第１実施形態の第２変形例に係る半導体装置は、図１６に示すように、ｐ型の半導体基板１と、ｎ型ウェル（バックゲート領域）７との間に設けられた、ｎ型の半導体層であるｎ型ウェル８、及びｐ型の半導体層であるｐ型ウェル９を更に備える点が、図１４に示した第１実施形態に係る半導体装置と異なる。ｎ型ウェル７とｐ型ウェル９との接合面は、ＳＴＩ領域４より浅く、ソース領域１１及びドレイン領域１２より深い位置に設けられている。 <Second modification of the first embodiment>
As shown in FIG. 16, the semiconductor device according to the second modification of the first embodiment is an n-type semiconductor device provided between the p-type semiconductor substrate 1 and the n-type well (backgate region) 7. It differs from the semiconductor device according to the first embodiment shown in FIG. 14 in that it further includes an n-type well 8 which is a semiconductor layer and a p-type well 9 which is a p-type semiconductor layer. The joint surface between the n-type well 7 and the p-type well 9 is provided at a position shallower than the STI region 4 and deeper than the source region 11 and the drain region 12.
　一般的なＣＭＯＳプロセスでは、半導体基板１上に形成された回路の間で信号の干渉が起こらないように、ノイズを出す回路をウェルで囲み、電気的分離を強固に行う場合がある。ここでは、ｎ型ウェル８が、半導体基板１とｎ型ウェル７とを電気的に分離する。更に、ｐ型ウェル９が、ｎ型ウェル８とｎ型ウェル７とを電気的に分離する。第１実施形態の第２変形例に係る半導体装置の他の構成は、図１４に示した第１実施形態に係る半導体装置と同様であるので、重複した説明を省略する。 In a general CMOS process, a circuit that produces noise may be surrounded by wells to ensure strong electrical separation so that signal interference does not occur between the circuits formed on the semiconductor substrate 1. Here, the n-type well 8 electrically separates the semiconductor substrate 1 and the n-type well 7. Further, the p-type well 9 electrically separates the n-type well 8 and the n-type well 7. Since other configurations of the semiconductor device according to the second modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
　第１実施形態の第２変形例に係る半導体装置によれば、ｎ型ウェル８及びｐ型ウェル９を更に備える場合でも、第１実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。 According to the semiconductor device according to the second modification of the first embodiment, even when the n-type well 8 and the p-type well 9 are further provided, noise reduction and circuit miniaturization are realized as in the first embodiment. It will be possible.
　なお、ｐ型の半導体基板１の代わりに、ｎ型の半導体基板を使用してもよい。この場合、例えばｎ型の半導体基板上に、ｐ型ウェル、ｎ型ウェル及びｐ型ウェル（バックゲート領域）を設け、ｐ型ウェル（バックゲート領域）に、ｎ＋型のソース領域、ｎ＋型のドレイン領域及びｐ＋型のバックゲート端子を設けてよい。或いは、ｎ型の半導体基板上に、ｐ型ウェル、ｎ型ウェル（バックゲート領域）を設け、ｎ型ウェル（バックゲート領域）に、ｐ＋型のソース領域、ｐ＋型のドレイン領域及びｎ＋型のバックゲート端子を設けてよい。 An n-type semiconductor substrate may be used instead of the p-type semiconductor substrate 1. In this case, for example, a p-type well, an n-type well, and a p-type well (back gate region) are provided on an n-type semiconductor substrate, and an n + type source region and n + are provided in the p-type well (back gate region). A mold drain region and a p + type backgate terminal may be provided. Alternatively, a p-type well and an n-type well (back gate region) are provided on the n-type semiconductor substrate, and the p + type source region, p + type drain region, and n are provided in the n-type well (back gate region). A + type back gate terminal may be provided.
　＜第１実施形態の第３変形例＞
　第１実施形態の第３変形例に係る半導体装置は、図１７に示すように、バックゲート端子１３ａを構成する高不純物濃度のウェルタップ領域（拡散層）が無い点が、図１４に示した第１実施形態に係る半導体装置と異なる。 <Third variant of the first embodiment>
As shown in FIG. 17, the semiconductor device according to the third modification of the first embodiment does not have a well-tap region (diffusion layer) having a high impurity concentration constituting the back gate terminal 13a, as shown in FIG. It is different from the semiconductor device according to the first embodiment.
　第１実施形態の第３変形例では、図１７に破線で模式的に示すように、バックゲート端子１３ａは、分離膜６直下のｐ型ウェル３をソース領域１１と共に挟む、ｐ型ウェル３の一部で構成されている。第１実施形態の第３変形例に係る半導体装置の他の構成は、図１４に示した第１実施形態に係る半導体装置と同様であるので、重複した説明を省略する。 In the third modification of the first embodiment, as schematically shown by a broken line in FIG. 17, the back gate terminal 13a sandwiches the p-type well 3 directly under the separation membrane 6 together with the source region 11. It is composed of a part. Since other configurations of the semiconductor device according to the third modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
　第１実施形態の第３変形例に係る半導体装置によれば、バックゲート端子１３ａを、低抵抗化のための高不純物濃度のウェルタップ領域（拡散層）で構成する代わりに、ｐ型ウェル３の一部で構成する場合でも、第１実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。更に、ソース領域１１の近傍に、ソース領域１１と逆極性の高不純物濃度のウェルタップ領域（拡散層）が無いため、ソース領域１１の接合容量を低減することができる。 According to the semiconductor device according to the third modification of the first embodiment, instead of forming the back gate terminal 13a with a well tap region (diffusion layer) having a high impurity concentration for lowering the resistance, the p-type well 3 Even when it is composed of a part of the above, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment. Further, since there is no well-tapped region (diffusion layer) having a high impurity concentration opposite to that of the source region 11 in the vicinity of the source region 11, the bonding capacitance of the source region 11 can be reduced.
　＜第１実施形態の第４変形例＞
　第１実施形態の第４変形例に係る半導体装置は、図１８に示すように、バックゲート端子４３ａを構成する高不純物濃度のウェルタップ領域（拡散層）が無い点が、図１５に示した第１実施形態の第１変形例に係る半導体装置と異なる。また、第１実施形態の第４変形例に係る半導体装置は、半導体装置がｐＭＯＳで構成されている点が、図１７に示した第１実施形態の第３変形例に係る半導体装置と異なる。 <Fourth modification of the first embodiment>
As shown in FIG. 18, the semiconductor device according to the fourth modification of the first embodiment does not have a well-tap region (diffusion layer) having a high impurity concentration constituting the back gate terminal 43a, as shown in FIG. It is different from the semiconductor device according to the first modification of the first embodiment. Further, the semiconductor device according to the fourth modification of the first embodiment is different from the semiconductor device according to the third modification of the first embodiment shown in FIG. 17 in that the semiconductor device is composed of pMOS.
　第１実施形態の第４変形例では、図１８に破線で模式的に示すように、バックゲート端子４３ａは、分離膜６直下のｎ型ウェル７をソース領域４１と共に挟む、ｎ型ウェル７の一部で構成されている。第１実施形態の第４変形例に係る半導体装置の他の構成は、図１５に示した第１実施形態の第１変形例に係る半導体装置と同様であるので、重複した説明を省略する。 In the fourth modification of the first embodiment, as schematically shown by a broken line in FIG. 18, the back gate terminal 43a sandwiches the n-type well 7 directly under the separation membrane 6 together with the source region 41, and the n-type well 7 It is composed of a part. Since other configurations of the semiconductor device according to the fourth modification of the first embodiment are the same as those of the semiconductor device according to the first modification of the first embodiment shown in FIG. 15, duplicated description will be omitted.
　第１実施形態の第４変形例に係る半導体装置によれば、半導体装置がｐＭＯＳで構成されており、バックゲート端子４３ａを、低抵抗化のための高不純物濃度のウェルタップ領域（拡散層）で構成する代わりに、ｎ型ウェル７の一部で構成する場合でも、第１実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。更に、ソース領域４１の近傍に、ソース領域４１と逆極性の高不純物濃度のウェルタップ領域（拡散層）が無いため、ソース領域４１の接合容量を低減することができる。 According to the semiconductor device according to the fourth modification of the first embodiment, the semiconductor device is composed of pMOS, and the back gate terminal 43a is provided with a well-tap region (diffusion layer) having a high impurity concentration for lowering the resistance. Even when it is configured by a part of the n-type well 7 instead of being configured by, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment. Further, since there is no well-tapped region (diffusion layer) having a high impurity concentration opposite to that of the source region 41 in the vicinity of the source region 41, the bonding capacitance of the source region 41 can be reduced.
　＜第１実施形態の第５変形例＞
　第１実施形態の第５変形例に係る半導体装置は、図１９に示すように、ＳＴＩ領域４が、平面パターン上、バックゲート端子１３とＭＯＳＦＥＴのソース領域１１の間に延在する凸部４ａ，４ｂを有する点が、図１４に示した第１実施形態に係る半導体装置と異なる。 <Fifth variant of the first embodiment>
In the semiconductor device according to the fifth modification of the first embodiment, as shown in FIG. 19, the convex portion 4a in which the STI region 4 extends between the back gate terminal 13 and the source region 11 of the MOSFET on a plane pattern. , 4b is different from the semiconductor device according to the first embodiment shown in FIG.
　図１９では、分離膜６直下の凸部４ａ，４ｂの平面パターンを破線で模式的に示している。図１９の凸部４ａ上を通過するＡ－Ａ方向から見た断面を図２０に示す。また、図２０の凸部４ａ，４ｂの間を通過するＢ－Ｂ方向から見た断面を図２１に示す。凸部４ａ，４ｂの深さは、周辺のＳＴＩ領域４の深さと同等である。第１実施形態の第５変形例に係る半導体装置の他の構成は、図１３及び図１４に示した第１実施形態に係る半導体装置と同様であるので、重複した説明を省略する。 In FIG. 19, the planar patterns of the convex portions 4a and 4b directly below the separation membrane 6 are schematically shown by broken lines. FIG. 20 shows a cross section seen from the direction of AA passing over the convex portion 4a of FIG. Further, FIG. 21 shows a cross section seen from the BB direction passing between the convex portions 4a and 4b of FIG. 20. The depths of the convex portions 4a and 4b are equivalent to the depths of the surrounding STI regions 4. Since other configurations of the semiconductor device according to the fifth modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIGS. 13 and 14, duplicate description will be omitted.
　第１実施形態の第５変形例に係る半導体装置によれば、第１実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。更に、ＳＴＩ領域４が、平面パターン上、バックゲート端子１３とＭＯＳＦＥＴのソース領域１１の間に延在する凸部４ａ，４ｂを有することにより、ソース領域１１とバックゲート端子１３に挟まれるｐ型ウェル３が狭くなるので、ソース領域１１の接合容量を低減することができる。なお、第１実施形態の第５変形例では、半導体装置がｎＭＯＳで構成された場合を例示したが、半導体装置をｐＭＯＳで構成してもよい。 According to the semiconductor device according to the fifth modification of the first embodiment, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment. Further, the STI region 4 has convex portions 4a and 4b extending between the back gate terminal 13 and the source region 11 of the MOSFET on a plane pattern, so that the p-type is sandwiched between the source region 11 and the back gate terminal 13. Since the well 3 is narrowed, the junction capacity of the source region 11 can be reduced. In the fifth modification of the first embodiment, the case where the semiconductor device is composed of nMOS is illustrated, but the semiconductor device may be configured by pMOS.
　＜第１実施形態の第６変形例＞
　第１実施形態の第６変形例に係る半導体装置は、図２２に示すように、バックゲート端子１３とＭＯＳＦＥＴのソース領域１１の間のｐ型ウェル３上に分離膜が無い点が、図１４に示した第１実施形態に係る半導体装置と異なる。 <Sixth modification of the first embodiment>
As shown in FIG. 22, the semiconductor device according to the sixth modification of the first embodiment has no separation membrane on the p-type well 3 between the back gate terminal 13 and the source region 11 of the MOSFET. It is different from the semiconductor device according to the first embodiment shown in.
　また、バックゲート端子１３、ソース領域１１及びドレイン領域１２の上部にシリサイド層は設けられていない。第１実施形態の第６変形例に係る半導体装置の他の構成は、図１４に示した第１実施形態に係る半導体装置と同様であるので、重複した説明を省略する。 Further, the silicide layer is not provided above the back gate terminal 13, the source region 11, and the drain region 12. Since other configurations of the semiconductor device according to the sixth modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
　第１実施形態の第６変形例に係る半導体装置によれば、半導体基板１の表面をシリサイド化しないＣＭＯＳプロセスを使用する場合には、バックゲート端子１３とＭＯＳＦＥＴのソース領域１１とを電気的に分離するための分離膜を設けなくてもよい。この場合でも、第１実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。 According to the semiconductor device according to the sixth modification of the first embodiment, when the CMOS process that does not silicide the surface of the semiconductor substrate 1 is used, the back gate terminal 13 and the source region 11 of the MOSFET are electrically connected. It is not necessary to provide a separation membrane for separation. Even in this case, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment.
　＜第１実施形態の第７変形例＞
　第１実施形態の第７変形例に係る半導体装置は、図２３に示すように、バックゲート端子４３とＭＯＳＦＥＴのソース領域４１の間のｎ型ウェル７上に分離膜が無い点が、図１５に示した第１実施形態の第１変形例に係る半導体装置と異なる。また、第１実施形態の第７変形例に係る半導体装置は、半導体装置がｐＭＯＳで構成されている点が、図２２に示した第１実施形態の第６変形例に係る半導体装置と異なる。 <7th modification of the 1st embodiment>
As shown in FIG. 23, the semiconductor device according to the seventh modification of the first embodiment has no separation film on the n-type well 7 between the back gate terminal 43 and the source region 41 of the MOSFET. It is different from the semiconductor device according to the first modification of the first embodiment shown in. Further, the semiconductor device according to the seventh modification of the first embodiment is different from the semiconductor device according to the sixth modification of the first embodiment shown in FIG. 22 in that the semiconductor device is composed of pMOS.
　また、バックゲート端子４３、ソース領域４１及びドレイン領域４２の上部にシリサイド層は設けられていない。第１実施形態の第７変形例に係る半導体装置の他の構成は、図１５に示した第１実施形態の第１変形例に係る半導体装置と同様であるので、重複した説明を省略する。 Further, the silicide layer is not provided above the back gate terminal 43, the source region 41, and the drain region 42. Since other configurations of the semiconductor device according to the seventh modification of the first embodiment are the same as those of the semiconductor device according to the first modification of the first embodiment shown in FIG. 15, duplicated description will be omitted.
　第１実施形態の第７変形例に係る半導体装置によれば、半導体基板１の表面をシリサイド化しないＣＭＯＳプロセスを使用する場合には、バックゲート端子４３とＭＯＳＦＥＴのソース領域４１とを電気的に分離するための分離膜を設けなくてもよい。この場合でも、第１実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。 According to the semiconductor device according to the seventh modification of the first embodiment, when a CMOS process that does not silicide the surface of the semiconductor substrate 1 is used, the back gate terminal 43 and the source region 41 of the MOSFET are electrically connected. It is not necessary to provide a separation membrane for separation. Even in this case, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment.
　（第２実施形態）
　第１実施形態では、半導体装置がプレーナ型ＭＯＳＦＥＴを構成する場合を例示したが、本技術に係る半導体装置はプレーナ型ＭＯＳＦＥＴに限定されない。第２実施形態では半導体装置がフィン型のＭＯＳＦＥＴ（以下、「ＦｉｎＦＥＴ」ともいう）である場合を例示する。ここでは、ｎチャネル型のＦｉｎＦＥＴを例示する。 (Second Embodiment)
In the first embodiment, the case where the semiconductor device constitutes a planar MOSFET is illustrated, but the semiconductor device according to the present technology is not limited to the planar MOSFET. In the second embodiment, a case where the semiconductor device is a fin-type MOSFET (hereinafter, also referred to as “FinFET”) will be illustrated. Here, an n-channel FinFET will be illustrated.
　図２４は、第２実施形態に係る半導体装置の平面パターンであり、図２４のＡ－Ａ方向から見た断面が図２５に対応し、図２４のＢ－Ｂ方向から見た断面が図２６に対応する。図２４～図２６に示すように、第２実施形態に係る半導体装置は、ｐ型の半導体基板１と、半導体基板１上に設けられたｎ型ウェル２と、ｎ型ウェル２上に設けられたｐ型ウェル３とを備える。図２５に示すように、ｐ型ウェル３の上面が、ＳＴＩ領域４の上面よりも上方に位置する場合を例示する。ｎ型ウェル２と、ｐ型ウェル３との接合面は、ＳＴＩ領域４よりも浅く、ソース領域１１及びドレイン領域１２より深い位置になるように設けられている。 FIG. 24 is a planar pattern of the semiconductor device according to the second embodiment, the cross section of FIG. 24 seen from the AA direction corresponds to FIG. 25, and the cross section of FIG. 24 seen from the BB direction is FIG. 26. Corresponds to. As shown in FIGS. 24 to 26, the semiconductor device according to the second embodiment is provided on the p-type semiconductor substrate 1, the n-type well 2 provided on the semiconductor substrate 1, and the n-type well 2. It is provided with a p-type well 3. As shown in FIG. 25, a case where the upper surface of the p-type well 3 is located above the upper surface of the STI region 4 is illustrated. The joint surface between the n-type well 2 and the p-type well 3 is provided so as to be shallower than the STI region 4 and deeper than the source region 11 and the drain region 12.
　ｐ型ウェル３には、ｎ＋型のソース領域１１及びｎ＋型のドレイン領域１２が互いに離間して設けられている。ソース領域１１及びドレイン領域１２で挟まれるチャネル領域を囲むように、ゲート絶縁膜（不図示）を介してゲート電極５が設けられている。ゲート電極５の断面形状は、チャネル領域の上面及び両側面の３方を囲む逆Ｕ字状であってもよい。ゲート電極５に囲まれたチャネル領域はフィン形状を有する。なお、ゲート電極５の形状はこれに限定されない。例えば、ゲート電極５が、複数本のフィン形状のチャネル領域を区画するＭ字状、π字状等の断面形状であってもよい。 The p-type well 3 is provided with an n + type source region 11 and an n + type drain region 12 separated from each other. A gate electrode 5 is provided via a gate insulating film (not shown) so as to surround the channel region sandwiched between the source region 11 and the drain region 12. The cross-sectional shape of the gate electrode 5 may be an inverted U shape that surrounds the upper surface and both side surfaces of the channel region. The channel region surrounded by the gate electrode 5 has a fin shape. The shape of the gate electrode 5 is not limited to this. For example, the gate electrode 5 may have a cross-sectional shape such as an M-shape or a π-shape that divides a plurality of fin-shaped channel regions.
　ｐ型ウェル３には、ソース領域１１及びドレイン領域１２と離間してｐ＋型のバックゲート端子１３が設けられている。バックゲート端子１３は、ｐ型ウェル３よりも高不純物濃度のウェルタップ領域（拡散層）で構成されている。なお、バックゲート端子１３を構成するウェルタップ領域（拡散層）が無く、ｐ型ウェル３の一部でバックゲート端子を構成してもよい。ソース領域１１、ドレイン領域１２及びバックゲート端子１３の上部には、シリサイド層２１，２２，２３がそれぞれ設けられている。なお、シリサイド層２１，２２，２３が設けられていなくてもよい。 The p-type well 3 is provided with a p + type back gate terminal 13 separated from the source region 11 and the drain region 12. The back gate terminal 13 is composed of a well tap region (diffusion layer) having a higher impurity concentration than the p-type well 3. The back gate terminal may be formed by a part of the p-type well 3 without the well tap region (diffusion layer) constituting the back gate terminal 13. Silicide layers 21, 22, and 23 are provided above the source region 11, the drain region 12, and the back gate terminal 13, respectively. It should be noted that the silicide layers 21, 22, and 23 may not be provided.
　ソース領域１１及びドレイン領域１２と、バックゲート端子１３との間に挟まれたｐ型ウェル３上には、分離膜６が設けられている。分離膜６の形状は、例えばゲート電極５の形状と同様であってよい。例えば、図２６に示すように、分離膜６の断面形状は、フィン状のｐ型ウェル３の上面及び両側面の３方を囲む逆Ｕ字状であってもよい。なお、分離膜６は、ゲート電極５とは異なる材料で構成してもよく、例えば絶縁材料で構成してもよい。また、シリサイド層２１，２２，２３が設けられていない場合には、分離膜６が無くてもよい。 A separation membrane 6 is provided on the p-type well 3 sandwiched between the source region 11 and the drain region 12 and the back gate terminal 13. The shape of the separation membrane 6 may be the same as the shape of the gate electrode 5, for example. For example, as shown in FIG. 26, the cross-sectional shape of the separation membrane 6 may be an inverted U shape surrounding the upper surface and both side surfaces of the fin-shaped p-shaped well 3. The separation membrane 6 may be made of a material different from that of the gate electrode 5, and may be made of, for example, an insulating material. Further, when the silicide layers 21, 22, and 23 are not provided, the separation membrane 6 may be omitted.
　バックゲート端子１３とソース領域１１との間にはフィン状のｐ型ウェル３が介在し、ＳＴＩ領域４により電気的に分離されていない。即ち、バックゲート端子１３、ソース領域１１及びドレイン領域１２は、ＳＴＩ領域４で囲まれた同一の活性領域Ａ０内に設けられている。バックゲート端子１３は、図示しないメタルコンタクトと多層配線を介してゲート電極５と電気的に接続され、ゲート電極５と同電位である。 A fin-shaped p-type well 3 is interposed between the back gate terminal 13 and the source region 11, and is not electrically separated by the STI region 4. That is, the back gate terminal 13, the source region 11, and the drain region 12 are provided in the same active region A0 surrounded by the STI region 4. The back gate terminal 13 is electrically connected to the gate electrode 5 via a metal contact (not shown) and multi-layer wiring, and has the same potential as the gate electrode 5.
　第２実施形態に係る半導体装置によれば、半導体装置がＦｉｎＦＥＴで構成される場合でも、第１実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。 According to the semiconductor device according to the second embodiment, even when the semiconductor device is composed of FinFETs, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment.
　＜第２実施形態の変形例＞
　第２実施形態の変形例に係る半導体装置は、図２７及び図２８に示すように、半導体装置がｐチャネル型のＦｉｎＦＥＴで構成されている点が、図２４～図２６に示した第２実施形態に係る半導体装置と異なる。 <Modified example of the second embodiment>
As shown in FIGS. 27 and 28, the semiconductor device according to the modified example of the second embodiment is the second embodiment shown in FIGS. 24 to 26 in that the semiconductor device is composed of a p-channel type FinFET. It is different from the semiconductor device according to the form.
　第２実施形態では、ｐ型の半導体基板１にｎ型ウェル７が設けられている。ｎ型ウェル７と半導体基板１との接合面は、ＳＴＩ領域４よりも浅く、ソース領域４１及びドレイン領域４２よりも深い。ｎ型ウェル７の上部には、ｐ＋型のソース領域４１及びｐ＋型のドレイン領域４２が設けられている。ソース領域４１及びドレイン領域４２に挟まれたチャネル領域を囲むように、ゲート絶縁膜（不図示）を介してゲート電極５が設けられている。 In the second embodiment, the p-type semiconductor substrate 1 is provided with the n-type well 7. The joint surface between the n-type well 7 and the semiconductor substrate 1 is shallower than the STI region 4 and deeper than the source region 41 and the drain region 42. A p + type source region 41 and a p + type drain region 42 are provided above the n-type well 7. A gate electrode 5 is provided via a gate insulating film (not shown) so as to surround the channel region sandwiched between the source region 41 and the drain region 42.
　ｎ型ウェル７の上部には、ソース領域４１及びドレイン領域４２から離間して、ｎ＋型のウェルタップ領域で構成されるバックゲート端子４３が設けられている。バックゲート端子４３は、ゲート電極５に電気的に接続されて同電位となる。バックゲート端子４３とソース領域４１との間には、フィン状のｎ型ウェル７が介在する。即ち、バックゲート端子４３と、ソース領域４１及びドレイン領域４２は、ＳＴＩ領域４に囲まれた同一の活性領域Ａ０内に設けられている。 A back gate terminal 43 composed of an n + type well tap region is provided above the n-type well 7 so as to be separated from the source region 41 and the drain region 42. The back gate terminal 43 is electrically connected to the gate electrode 5 and has the same potential. A fin-shaped n-shaped well 7 is interposed between the back gate terminal 43 and the source region 41. That is, the back gate terminal 43, the source region 41, and the drain region 42 are provided in the same active region A0 surrounded by the STI region 4.
　バックゲート端子４３と、ソース領域４１及びドレイン領域４２の間のｎ型ウェル７上には分離膜６が設けられている。バックゲート端子４３、ソース領域４１及びドレイン領域４２の上部には、シリサイド層２１，２２，２３がそれぞれ設けられている。第２実施形態の変形例に係る半導体装置の他の構成は、図２４～図２６に示した第２実施形態に係る半導体装置と同様であるので、重複した説明を省略する。 A separation membrane 6 is provided on the n-type well 7 between the back gate terminal 43 and the source region 41 and the drain region 42. Silicide layers 21, 22, and 23 are provided above the back gate terminal 43, the source region 41, and the drain region 42, respectively. Since other configurations of the semiconductor device according to the modified example of the second embodiment are the same as those of the semiconductor device according to the second embodiment shown in FIGS. 24 to 26, duplicate description will be omitted.
　第２実施形態の変形例に係る半導体装置によれば、半導体装置がｐチャネル型のＦｉｎＦＥＴで構成されている場合でも、第２実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。 According to the semiconductor device according to the modified example of the second embodiment, even when the semiconductor device is composed of a p-channel type FinFET, it is possible to realize low noise and miniaturization of the circuit as in the second embodiment. It becomes.
　（第３実施形態）
　第１及び第２実施形態では、半導体装置がバルク型ＭＯＳＦＥＴで構成される場合を例示したが、これに限定されない。第３実施形態では、半導体装置がＳＯＩ型ＭＯＳＦＥＴで構成される場合を例示する。 (Third Embodiment)
In the first and second embodiments, the case where the semiconductor device is composed of a bulk MOSFET is illustrated, but the present invention is not limited to this. In the third embodiment, a case where the semiconductor device is composed of an SOI type MOSFET is illustrated.
　第３実施形態に係る半導体装置は、図２９に示すように、ｎＭＯＳで構成されている。ｐ型の半導体基板１上にｎ型ウェル２及びｐ型ウェル（バックゲート領域）３が設けられている。ｐ型ウェル３の一部の上面に、埋込絶縁膜（ＢＯＸ層）１４が設けられている。ｎ型ウェル２と、ｐ型ウェル３との接合面は、ＳＴＩ領域４よりも浅く、ソース領域１１及びドレイン領域１２より深い位置になるように設けられている。 As shown in FIG. 29, the semiconductor device according to the third embodiment is composed of nMOS. An n-type well 2 and a p-type well (back gate region) 3 are provided on the p-type semiconductor substrate 1. An embedded insulating film (BOX layer) 14 is provided on the upper surface of a part of the p-type well 3. The joint surface between the n-type well 2 and the p-type well 3 is provided so as to be shallower than the STI region 4 and deeper than the source region 11 and the drain region 12.
　埋込絶縁膜１４上には、Ｓｉからなる薄いｐ型の半導体層（ＳＯＩ層）１５が設けられている。埋込絶縁膜１４は、バックゲート領域を構成するｐ型ウェル３とＳＯＩ層１５と電気的に分離する。ＳＯＩ層１５に、ｎ＋型のソース領域１１及びｎ＋型のドレイン領域１２が互いに離間して設けられている。ソース領域１１及びドレイン領域１２で挟まれるチャネル領域上に、ゲート絶縁膜（不図示）を介してゲート電極５が設けられている。 A thin p-type semiconductor layer (SOI layer) 15 made of Si is provided on the embedded insulating film 14. The embedded insulating film 14 is electrically separated from the p-type well 3 and the SOI layer 15 constituting the back gate region. The SOI layer 15 is provided with an n + type source region 11 and an n + type drain region 12 separated from each other. A gate electrode 5 is provided on a channel region sandwiched between a source region 11 and a drain region 12 via a gate insulating film (not shown).
　埋込絶縁膜１４に被覆されていないｐ型ウェル３の上部には、ｐ＋型のバックゲート端子１３が設けられている。ソース領域１１、ドレイン領域１２、バックゲート端子１３の上面には、シリサイド層２１，２２，２３がそれぞれ設けられている。なお、ソース領域１１及び埋込絶縁膜１４の側壁にはサイドウォール（不図示）が形成されており、このサイドウォールによりソース領域１１とバックゲート端子１３とは電気的に分離されている。 A p + type back gate terminal 13 is provided on the upper portion of the p-type well 3 which is not covered with the embedded insulating film 14. Silicide layers 21, 22, and 23 are provided on the upper surfaces of the source region 11, the drain region 12, and the back gate terminal 13, respectively. A sidewall (not shown) is formed on the side wall of the source region 11 and the embedded insulating film 14, and the source region 11 and the back gate terminal 13 are electrically separated by this sidewall.
　バックゲート端子１３は、ｐ型ウェル３よりも高不純物濃度のウェルタップ領域（拡散層）で構成されている。バックゲート端子１３を構成するウェルタップ領域（拡散層）は、埋込絶縁膜１４の一部を除去し、ｐ型ウェル３の露出した上面にイオン注入を行った後、熱処理を行うことにより形成可能である。なお、バックゲート端子１３を構成するウェルタップ領域（拡散層）が無く、ｐ型ウェル３の一部でバックゲート端子を構成してもよい。 The back gate terminal 13 is composed of a well tap region (diffusion layer) having a higher impurity concentration than the p-type well 3. The well tap region (diffusion layer) constituting the back gate terminal 13 is formed by removing a part of the embedded insulating film 14, implanting ions into the exposed upper surface of the p-type well 3, and then performing heat treatment. It is possible. The back gate terminal may be formed by a part of the p-type well 3 without the well tap region (diffusion layer) constituting the back gate terminal 13.
　バックゲート端子１３とソース領域１１との間にはＳＴＩ領域４が介在しない。即ち、バックゲート端子１３、ソース領域１１及びドレイン領域１２は、ＳＴＩ領域４で囲まれた同一の活性領域Ａ０内に設けられている。バックゲート端子１３は、図示しないメタルコンタクトと多層配線を介してゲート電極５と電気的に接続され、ゲート電極５と同電位である。 The STI region 4 does not intervene between the back gate terminal 13 and the source region 11. That is, the back gate terminal 13, the source region 11, and the drain region 12 are provided in the same active region A0 surrounded by the STI region 4. The back gate terminal 13 is electrically connected to the gate electrode 5 via a metal contact (not shown) and multi-layer wiring, and has the same potential as the gate electrode 5.
　第３実施形態に係る半導体装置によれば、半導体装置がＳＯＩ型ＭＯＳＦＥＴで構成されている場合でも、第１及び第２実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。 According to the semiconductor device according to the third embodiment, even when the semiconductor device is composed of the SOI type MOSFET, it is possible to realize low noise and miniaturization of the circuit as in the first and second embodiments. ..
　＜第３実施形態の第１変形例＞
　第３実施形態の第１変形例に係る半導体装置は、図３０に示すように、半導体装置がｎＭＯＳで構成されている点は、図２９に示した第３実施形態に係る半導体装置と共通する。しかし、第３実施形態の第１変形例に係る半導体装置は、ｎ型ウェル７がバックゲート領域を構成する点が、図２９に示した第３実施形態に係る半導体装置と異なる。 <First modification of the third embodiment>
As shown in FIG. 30, the semiconductor device according to the first modification of the third embodiment is common to the semiconductor device according to the third embodiment shown in FIG. 29 in that the semiconductor device is composed of nMOS. .. However, the semiconductor device according to the first modification of the third embodiment is different from the semiconductor device according to the third embodiment shown in FIG. 29 in that the n-type well 7 constitutes a back gate region.
　埋込絶縁膜１４は、バックゲート領域を構成するｎ型ウェル７とＳＯＩ層１５と電気的に分離する。このため、バックゲート領域の極性は、ＳＯＩ層１５の極性に依存しない。バックゲート端子４３は、ｎ型ウェル７よりも高不純物濃度のｎ＋型のウェルタップ領域（拡散層）で構成されている。第３実施形態の第１変形例に係る半導体装置の他の構成は、図２９に示した第３実施形態に係る半導体装置と同様であるので、重複した説明を省略する。 The embedded insulating film 14 is electrically separated from the n-type well 7 and the SOI layer 15 constituting the back gate region. Therefore, the polarity of the back gate region does not depend on the polarity of the SOI layer 15. The back gate terminal 43 is composed of an n + type well tap region (diffusion layer) having a higher impurity concentration than the n type well 7. Since other configurations of the semiconductor device according to the first modification of the third embodiment are the same as those of the semiconductor device according to the third embodiment shown in FIG. 29, duplicate description will be omitted.
　第３実施形態の第１変形例に係る半導体装置によれば、ｎ型ウェル７がバックゲート領域を構成する場合でも、第３実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。 According to the semiconductor device according to the first modification of the third embodiment, even when the n-type well 7 constitutes the back gate region, it is possible to realize low noise and miniaturization of the circuit as in the third embodiment. It becomes.
　＜第３実施形態の第２変形例＞
　第３実施形態の第２変形例に係る半導体装置は、図３１に示すように、半導体装置がｐＭＯＳで構成されている点が、図２９に示した第３実施形態に係る半導体装置と異なる。 <Second modification of the third embodiment>
As shown in FIG. 31, the semiconductor device according to the second modification of the third embodiment is different from the semiconductor device according to the third embodiment shown in FIG. 29 in that the semiconductor device is composed of pMOS.
　埋込絶縁膜１４は、バックゲート領域を構成するｐ型ウェル３とｎ型のＳＯＩ層１６と電気的に分離する。このため、ＳＯＩ層１６の極性は、バックゲート領域の極性に依存しない。ＳＯＩ層１６には、ｐ＋型のソース領域４１及びｐ＋型のドレイン領域４２が設けられている。第３実施形態の第２変形例に係る半導体装置の他の構成は、図２９に示した第３実施形態に係る半導体装置と同様であるので、重複した説明を省略する。 The embedded insulating film 14 is electrically separated from the p-type well 3 and the n-type SOI layer 16 constituting the back gate region. Therefore, the polarity of the SOI layer 16 does not depend on the polarity of the back gate region. The SOI layer 16 is provided with a p + type source region 41 and a p + type drain region 42. Since other configurations of the semiconductor device according to the second modification of the third embodiment are the same as those of the semiconductor device according to the third embodiment shown in FIG. 29, duplicate description will be omitted.
　第３実施形態の第２変形例に係る半導体装置によれば、半導体装置がｐＭＯＳで構成されている場合でも、第３実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。 According to the semiconductor device according to the second modification of the third embodiment, even when the semiconductor device is composed of pMOS, it is possible to realize low noise and miniaturization of the circuit as in the third embodiment. ..
　＜第３実施形態の第３変形例＞
　第３実施形態の第３変形例に係る半導体装置は、図３２に示すように、半導体装置がｐＭＯＳで構成されている点と、ｎ型ウェル７がバックゲート領域を構成する点が、図２９に示した第３実施形態に係る半導体装置と異なる。 <Third variant of the third embodiment>
As shown in FIG. 32, the semiconductor device according to the third modification of the third embodiment has a point that the semiconductor device is composed of pMOS and a point that the n-type well 7 constitutes a back gate region. It is different from the semiconductor device according to the third embodiment shown in.
　埋込絶縁膜１４は、バックゲート領域を構成するｎ型ウェル７とｎ型のＳＯＩ層１６と電気的に分離する。ＳＯＩ層１６には、ｐ＋型のソース領域４１及びｐ＋型のドレイン領域４２が設けられている。バックゲート端子４３は、ｎ型ウェル７よりも高不純物濃度のｎ＋型のウェルタップ領域（拡散層）で構成されている。第３実施形態の第３変形例に係る半導体装置の他の構成は、図２９に示した第３実施形態に係る半導体装置と同様であるので、重複した説明を省略する。 The embedded insulating film 14 is electrically separated from the n-type well 7 and the n-type SOI layer 16 constituting the back gate region. The SOI layer 16 is provided with a p + type source region 41 and a p + type drain region 42. The back gate terminal 43 is composed of an n + type well tap region (diffusion layer) having a higher impurity concentration than the n type well 7. Since other configurations of the semiconductor device according to the third modification of the third embodiment are the same as those of the semiconductor device according to the third embodiment shown in FIG. 29, duplicate description will be omitted.
　第３実施形態の第３変形例に係る半導体装置によれば、半導体装置がｐＭＯＳで構成され、且つｎ型ウェル７がバックゲート領域を構成する場合でも、第３実施形態と同様に、低ノイズ化と回路の小型化を実現可能となる。 According to the semiconductor device according to the third modification of the third embodiment, even when the semiconductor device is composed of pMOS and the n-type well 7 constitutes the back gate region, the noise is low as in the third embodiment. It is possible to realize miniaturization and miniaturization of circuits.
　（第４実施形態）
　第４実施形態として、本技術に係る半導体装置を、単位画素毎にＡＤ変換機を有する固体撮像装置に適用した場合を説明する。ここでは、監視カメラ等で使用されるローカルバイナリーパターン（ＬＢＰ）方式を用いた固体撮像装置を例示する。 (Fourth Embodiment)
As a fourth embodiment, a case where the semiconductor device according to the present technology is applied to a solid-state image sensor having an AD converter for each unit pixel will be described. Here, a solid-state image sensor using a local binary pattern (LBP) method used in a surveillance camera or the like will be illustrated.
　第４実施形態に係る固体撮像装置は、図３３に示すように、半導体として例えばシリコン（Ｓｉ）を用いた半導体基板３１１に、画素３２１が２次元アレイ状に配列された画素アレイ部３２２を備える。画素アレイ部３２２は、時刻コード発生部３２６で生成された時刻コードを各画素３２１に転送する時刻コード転送部３２３を有する。半導体基板３１１上の画素アレイ部３２２の周辺には、画素駆動回路３２４、ＤＡＣ（D/A Converter）３２５、時刻コード発生部３２６、垂直駆動回路３２７、出力部３２８及びタイミング生成回路３２９が配置されている。 As shown in FIG. 33, the solid-state image sensor according to the fourth embodiment includes a pixel array unit 322 in which pixels 321 are arranged in a two-dimensional array on a semiconductor substrate 311 using, for example, silicon (Si) as a semiconductor. .. The pixel array unit 322 has a time code transfer unit 323 that transfers the time code generated by the time code generation unit 326 to each pixel 321. A pixel drive circuit 324, a DAC (D / A Converter) 325, a time code generator 326, a vertical drive circuit 327, an output unit 328, and a timing generation circuit 329 are arranged around the pixel array unit 322 on the semiconductor substrate 311. ing.
　２次元アレイ状に配列された画素３２１のそれぞれには、図３４に示すように、画素回路３４１とＡＤＣ３４２が設けられている。画素３２１は、画素内の受光素子（例えば、フォトダイオード）で受光した光量に応じた電荷信号を生成し、デジタルの画素信号ＳＩＧに変換して出力する。 As shown in FIG. 34, each of the pixels 321 arranged in a two-dimensional array is provided with a pixel circuit 341 and an ADC 342. The pixel 321 generates a charge signal according to the amount of light received by a light receiving element (for example, a photodiode) in the pixel, converts it into a digital pixel signal SIG, and outputs it.
　画素駆動回路３２４は、画素３２１内の画素回路３４１を駆動する。ＤＡＣ３２５は、時間経過に応じてレベル（電圧）が単調減少するスロープ信号である参照信号（基準電圧信号）ＲＥＦを生成し、各画素３２１に供給する。時刻コード発生部３２６は、各画素３２１が、アナログの画素信号ＳＩＧをデジタルの信号に変換（ＡＤ変換）する際に使用される時刻コードを生成し、対応する時刻コード転送部３２３に供給する。時刻コード発生部３２６は、画素アレイ部３２２に対して複数個設けられている。画素アレイ部３２２内には、時刻コード発生部３２６に対応する数だけ、時刻コード転送部３２３が設けられている。即ち、時刻コード発生部３２６と、時刻コード発生部３２６により生成された時刻コードを転送する時刻コード転送部３２３は、１対１に対応する。 The pixel drive circuit 324 drives the pixel circuit 341 in the pixel 321. The DAC 325 generates a reference signal (reference voltage signal) REF, which is a slope signal whose level (voltage) monotonically decreases with the passage of time, and supplies it to each pixel 321. The time code generation unit 326 generates a time code used when each pixel 321 converts an analog pixel signal SIG into a digital signal (AD conversion), and supplies the time code to the corresponding time code transfer unit 323. A plurality of time code generation units 326 are provided for the pixel array unit 322. In the pixel array unit 322, as many time code transfer units 323 as the number corresponding to the time code generation unit 326 are provided. That is, the time code generation unit 326 and the time code transfer unit 323 that transfers the time code generated by the time code generation unit 326 have a one-to-one correspondence.
　垂直駆動回路３２７は、画素３２１内で生成されたデジタルの画素信号ＳＩＧを、タイミング生成回路３２９から供給されるタイミング信号に基づいて、所定の順番で出力部３２８に出力させる制御を行う。画素３２１から出力されたデジタルの画素信号ＳＩＧは、出力部３２８から固体撮像装置の外部へ出力される。出力部３２８は、黒レベルを補正する黒レベル補正処理や相関２重サンプリング（ＣＤＳ）処理等、所定のデジタル信号処理を必要に応じて行い、その後、外部へ出力する。 The vertical drive circuit 327 controls the output unit 328 to output the digital pixel signal SIG generated in the pixel 321 to the output unit 328 in a predetermined order based on the timing signal supplied from the timing generation circuit 329. The digital pixel signal SIG output from the pixel 321 is output from the output unit 328 to the outside of the solid-state image sensor. The output unit 328 performs predetermined digital signal processing such as black level correction processing for correcting the black level and correlation double sampling (CDS) processing as necessary, and then outputs the digital signal to the outside.
　タイミング生成回路３２９は、各種のタイミング信号を生成するタイミングジェネレータ等によって構成され、生成した各種のタイミング信号を、画素駆動回路３２４、ＤＡＣ３２５、垂直駆動回路３２７等に供給する。 The timing generation circuit 329 is configured by a timing generator or the like that generates various timing signals, and supplies the generated various timing signals to the pixel drive circuit 324, the DAC 325, the vertical drive circuit 327, or the like.
　図３４に示すように、画素回路３４１は、受光した光量に応じた電荷信号をアナログの画素信号ＳＩＧとしてＡＤＣ３４２に出力する。ＡＤＣ３４２は、画素回路３４１から供給されたアナログの画素信号ＳＩＧをデジタル信号に変換する。 As shown in FIG. 34, the pixel circuit 341 outputs a charge signal corresponding to the amount of received light to the ADC 342 as an analog pixel signal SIG. The ADC 342 converts the analog pixel signal SIG supplied from the pixel circuit 341 into a digital signal.
　ＡＤＣ３４２は、比較回路３５１とデータ記憶部３５２で構成される。比較回路３５１は、ＤＡＣ３２５から供給される参照信号ＲＥＦと画素信号ＳＩＧを比較し、比較結果を表す比較結果信号として、出力信号ＶＣＯを出力する。比較回路３５１は、参照信号ＲＥＦと画素信号ＳＩＧが同一の電圧になったとき、出力信号ＶＣＯを反転させる。 The ADC 342 is composed of a comparison circuit 351 and a data storage unit 352. The comparison circuit 351 compares the reference signal REF supplied from the DAC 325 with the pixel signal SIG, and outputs an output signal VCO as a comparison result signal representing the comparison result. The comparison circuit 351 inverts the output signal VCO when the reference signal REF and the pixel signal SIG have the same voltage.
　比較回路３５１は、差動入力回路３６１、電圧変換回路３６２、及び正帰還回路（ＰＦＢ）３６３により構成される。データ記憶部３５２には、比較回路３５１から出力信号ＶＣＯが入力される他、垂直駆動回路３２７から、画素信号の書き込み動作であることを表すＷＲ信号、画素信号の読み出し動作であることを表すＲＤ信号、及び、画素信号の読み出し動作中における画素３２１の読み出しタイミングを制御するＷＯＲＤ信号が、垂直駆動回路３２７から供給される。また、時刻コード転送部３２３を介して、時刻コード発生部３２６で生成された時刻コードも供給される。 The comparison circuit 351 is composed of a differential input circuit 361, a voltage conversion circuit 362, and a positive feedback circuit (PFB) 363. In addition to inputting the output signal VCO from the comparison circuit 351 to the data storage unit 352, the vertical drive circuit 327 indicates that the operation is a pixel signal writing operation and that the pixel signal reading operation is RD. The signal and the WORD signal that controls the read timing of the pixel 321 during the read operation of the pixel signal are supplied from the vertical drive circuit 327. Further, the time code generated by the time code generation unit 326 is also supplied via the time code transfer unit 323.
　データ記憶部３５２は、ＷＲ信号及びＲＤ信号に基づいて、時刻コードの書き込み動作と読み出し動作を制御するラッチ制御回路３７１と、時刻コードを記憶するラッチ記憶部３７２で構成される。 The data storage unit 352 is composed of a latch control circuit 371 that controls a time code writing operation and a reading operation based on a WR signal and an RD signal, and a latch storage unit 372 that stores the time code.
　ラッチ制御回路３７１は、時刻コードの書き込み動作においては、比較回路３５１からハイ（Ｈ）の出力信号ＶＣＯが入力されている間、時刻コード転送部３２３から供給される、単位時間ごとに更新される時刻コードをラッチ記憶部３７２に記憶させる。そして、参照信号ＲＥＦと画素信号ＳＩＧが同一の電圧になり、比較回路３５１から供給される出力信号ＶＣＯがロー（Ｌ）に反転されたとき、供給される時刻コードの書き込み（更新）を中止し、最後にラッチ記憶部３７２に記憶された時刻コードをラッチ記憶部３７２に保持させる。ラッチ記憶部３７２に記憶された時刻コードは、画素信号ＳＩＧと参照信号ＲＥＦが等しくなった時刻を表しており、画素信号ＳＩＧがその時刻の基準電圧であったことを示すデータ、即ち、デジタル化された光量値を表す。 In the time code writing operation, the latch control circuit 371 is updated every unit time supplied from the time code transfer unit 323 while the high (H) output signal VCO is input from the comparison circuit 351. The time code is stored in the latch storage unit 372. Then, when the reference signal REF and the pixel signal SIG have the same voltage and the output signal VCO supplied from the comparison circuit 351 is inverted to low (L), the writing (update) of the supplied time code is stopped. Finally, the latch storage unit 372 holds the time code stored in the latch storage unit 372. The time code stored in the latch storage unit 372 represents the time when the pixel signal SIG and the reference signal REF become equal, and data indicating that the pixel signal SIG was the reference voltage at that time, that is, digitization. Represents the light intensity value.
　参照信号ＲＥＦの掃引が終了し、画素アレイ部３２２内の全ての画素３２１のラッチ記憶部３７２に時刻コードが記憶された後、画素３２１の動作が、書き込み動作から読み出し動作に変更される。 After the sweep of the reference signal REF is completed and the time code is stored in the latch storage unit 372 of all the pixels 321 in the pixel array unit 322, the operation of the pixel 321 is changed from the writing operation to the reading operation.
　ラッチ制御回路３７１は、時刻コードの読み出し動作においては、読み出しタイミングを制御するＷＯＲＤ信号に基づいて、画素３２１が自分の読み出しタイミングとなったときに、ラッチ記憶部３７２に記憶されている時刻コード（デジタルの画素信号ＳＩＧ）を、時刻コード転送部３２３に出力する。時刻コード転送部３２３は、供給された時刻コードを、列方向（垂直方向）に順次転送し、出力部３２８に供給する。 In the time code reading operation, the latch control circuit 371 is based on the WORD signal that controls the reading timing, and when the pixel 321 reaches its own reading timing, the time code stored in the latch storage unit 372 ( The digital pixel signal SIG) is output to the time code transfer unit 323. The time code transfer unit 323 sequentially transfers the supplied time code in the column direction (vertical direction) and supplies it to the output unit 328.
　差動入力回路３６１は、画素３２１内の画素回路３４１から出力された画素信号ＳＩＧと、ＤＡＣ３２５から出力された参照信号ＲＥＦとを比較し、画素信号ＳＩＧが参照信号ＲＥＦよりも高いときに所定の信号（電流）を出力する。 The differential input circuit 361 compares the pixel signal SIG output from the pixel circuit 341 in the pixel 321 with the reference signal REF output from the DAC 325, and determines when the pixel signal SIG is higher than the reference signal REF. Output a signal (current).
　図３５に示すように、差動入力回路３６１は、差動対となるトランジスタ３８１，３８２、カレントミラーを構成するトランジスタ３８３，３８４、入力バイアス電流Ｖｂに応じた電流ＩＢを供給する定電流源としてのトランジスタ３８５、並びに、差動入力回路３６１の出力信号ＨＶＯを出力するトランジスタ３８６により構成されている。 As shown in FIG. 35, the differential input circuit 361 serves as a constant current source for supplying transistors 381 and 382 as differential pairs, transistors 383 and 384 constituting the current mirror, and a current IB corresponding to the input bias current Vb. The transistor 385 and the transistor 386 that outputs the output signal HVO of the differential input circuit 361 are configured.
　トランジスタ３８１，３８２，３８５は、ｎＭＯＳトランジスタで構成され、トランジスタ３８３，３８４，３８６は、ｐＭＯＳトランジスタで構成される。 The transistors 381, 382, 385 are composed of nMOS transistors, and the transistors 383, 384, 386 are composed of pMOS transistors.
　差動対となるトランジスタ３８１，３８２のうち、トランジスタ３８１のゲートには、ＤＡＣ３２５から出力された参照信号ＲＥＦが入力され、トランジスタ３８２のゲートには、画素３２１内の画素回路３４１から出力された画素信号ＳＩＧが入力される。トランジスタ３８１，３８２のソースは、トランジスタ３８５のドレインと接続され、トランジスタ３８５のソースは、所定の電圧ＶＳＳに接続されている。 Of the transistors 381 and 382 that form a differential pair, the reference signal REF output from the DAC 325 is input to the gate of the transistor 381, and the pixel output from the pixel circuit 341 in the pixel 321 is input to the gate of the transistor 382. The signal SIG is input. The source of the transistors 381 and 382 is connected to the drain of the transistor 385, and the source of the transistor 385 is connected to a predetermined voltage VSS.
　トランジスタ３８１のドレインは、カレントミラー回路を構成するトランジスタ３８３，３８４のゲート及びトランジスタ３８３のドレインと接続され、トランジスタ３８２のドレインは、トランジスタ３８４のドレイン及びトランジスタ３８６のゲートと接続されている。トランジスタ３８３，３８４，３８６のソースは、第１電源電圧ＶＤＤ１に接続されている。 The drain of the transistor 381 is connected to the gate of the transistors 383 and 384 and the drain of the transistor 383 constituting the current mirror circuit, and the drain of the transistor 382 is connected to the drain of the transistor 384 and the gate of the transistor 386. The source of the transistors 383,384,386 is connected to the first power supply voltage VDD1.
　電圧変換回路３６２は、例えば、ｎＭＯＳ型のトランジスタ３９１で構成される。トランジスタ３９１のドレインは、差動入力回路３６１のトランジスタ３８６のドレインと接続され、トランジスタ３９１のソースは、正帰還回路３６３内の所定の接続点に接続され、トランジスタ３８６のゲートは、バイアス電圧ＶＢＩＡＳに接続されている。 The voltage conversion circuit 362 is composed of, for example, an nMOS type transistor 391. The drain of the transistor 391 is connected to the drain of the transistor 386 of the differential input circuit 361, the source of the transistor 391 is connected to a predetermined connection point in the positive feedback circuit 363, and the gate of the transistor 386 is connected to the bias voltage VBIAS. It is connected.
　差動入力回路３６１を構成するトランジスタ３８１～３８６は、第１電源電圧ＶＤＤ１までの高電圧で動作する回路であり、正帰還回路３６３は、第１電源電圧ＶＤＤ１よりも低い第２電源電圧ＶＤＤ２で動作する回路である。電圧変換回路３６２は、差動入力回路３６１から入力される出力信号ＨＶＯを、正帰還回路３６３が動作可能な低電圧の信号（変換信号）ＬＶＩに変換して、正帰還回路３６３に供給する。 The transistors 381 to 386 constituting the differential input circuit 361 are circuits that operate at a high voltage up to the first power supply voltage VDD1, and the positive feedback circuit 363 has a second power supply voltage VDD2 lower than the first power supply voltage VDD1. It is a working circuit. The voltage conversion circuit 362 converts the output signal HVO input from the differential input circuit 361 into a low voltage signal (conversion signal) LVI in which the positive feedback circuit 363 can operate, and supplies the output signal HVO to the positive feedback circuit 363.
　バイアス電圧ＶＢＩＡＳは、定電圧で動作する正帰還回路３６３の各トランジスタ４０１～４０５を破壊しない電圧に変換する電圧であればよい。例えば、バイアス電圧ＶＢＩＡＳは、正帰還回路３６３の第２電源電圧ＶＤＤ２と同じ電圧とすることができる。 The bias voltage VBIAS may be any voltage that converts the transistors 401 to 405 of the positive feedback circuit 363 that operates at a constant voltage into a voltage that does not destroy them. For example, the bias voltage VBIAS can be the same voltage as the second power supply voltage VDD2 of the positive feedback circuit 363.
　正帰還回路３６３は、差動入力回路３６１からの出力信号ＨＶＯが第２電源電圧ＶＤＤ２に対応する信号に変換された変換信号ＬＶＩに基づいて、画素信号ＳＩＧが参照信号ＲＥＦよりも高いときに反転する比較結果信号を出力する。また、正帰還回路３６３は、比較結果信号として出力する出力信号ＶＣＯが反転するときの遷移速度を高速化する。 The positive feedback circuit 363 reverses when the pixel signal SIG is higher than the reference signal REF based on the conversion signal LVI in which the output signal HVO from the differential input circuit 361 is converted into a signal corresponding to the second power supply voltage VDD2. Outputs the comparison result signal. Further, the positive feedback circuit 363 speeds up the transition speed when the output signal VCO output as the comparison result signal is inverted.
　正帰還回路３６３は、５つのトランジスタ４０１～４０５で構成される。ここで、トランジスタ４０１，４０２，４０４は、ｐＭＯＳトランジスタで構成され、トランジスタ４０３，４０５は、ｎＭＯＳトランジスタで構成される。 The positive feedback circuit 363 is composed of five transistors 401 to 405. Here, the transistors 401, 402, and 404 are composed of pMOS transistors, and the transistors 403 and 405 are composed of nMOS transistors.
　電圧変換回路３６２の出力端であるトランジスタ３９１のソースは、トランジスタ４０２，４０３のドレインと、トランジスタ４０４，４０５のゲートに接続されている。トランジスタ４０１，４０４のソースは、第２電源電圧ＶＤＤ２に接続され、トランジスタ４０１のドレインは、トランジスタ４０２のソースと接続され、トランジスタ４０２のゲートは、正帰還回路３６３の出力端でもあるトランジスタ４０４，４０５のドレインと接続されている。トランジスタ４０３，４０５のソースは、所定の電圧ＶＳＳに接続されている。トランジスタ４０１，４０３のゲートには、初期化信号ＩＮＩが供給される。トランジスタ４０４，４０５はインバータ回路を構成し、それらのドレイン同士の接続点は、比較回路３５１が出力信号ＶＣＯを出力する出力端となっている。 The source of the transistor 391, which is the output end of the voltage conversion circuit 362, is connected to the drain of the transistors 402 and 403 and the gate of the transistors 404 and 405. The source of the transistors 401 and 404 is connected to the second power supply voltage VDD2, the drain of the transistor 401 is connected to the source of the transistor 402, and the gate of the transistor 402 is the output end of the positive feedback circuit 363. It is connected to the drain of. The sources of transistors 403,405 are connected to a predetermined voltage VSS. The initialization signal INI is supplied to the gates of the transistors 401 and 403. The transistors 404 and 405 form an inverter circuit, and the connection point between the drains thereof is an output end at which the comparison circuit 351 outputs an output signal VCO.
　画素回路３４１は、光電変換素子としてのフォトダイオード（ＰＤ）４２１、排出トランジスタ４２２、転送トランジスタ４２３、リセットトランジスタ４２４、及び、浮遊拡散層（ＦＤ）４２５で構成されている。 The pixel circuit 341 is composed of a photodiode (PD) 421 as a photoelectric conversion element, an emission transistor 422, a transfer transistor 423, a reset transistor 424, and a floating diffusion layer (FD) 425.
　排出トランジスタ４２２は、露光期間を調整する場合に使用される。具体的には、露光期間を任意のタイミングで開始したいときに排出トランジスタ４２２をオンさせると、それまでの間にフォトダイオード４２１に蓄積されていた電荷が排出されるので、排出トランジスタ４２２がオフされた以降から、露光期間が開始されることになる。 The discharge transistor 422 is used when adjusting the exposure period. Specifically, when the emission transistor 422 is turned on when the exposure period is desired to be started at an arbitrary timing, the electric charge accumulated in the photodiode 421 up to that point is discharged, so that the emission transistor 422 is turned off. After that, the exposure period will start.
　転送トランジスタ４２３は、フォトダイオード４２１で生成された電荷をＦＤ４２５に転送する。リセットトランジスタ４２４は、ＦＤ４２５に保持されている電荷をリセットする。ＦＤ４２５は、差動入力回路３６１のトランジスタ３８２のゲートに接続されている。これにより、差動入力回路３６１のトランジスタ３８２は、画素回路３４１の増幅トランジスタとしても機能する。 The transfer transistor 423 transfers the electric charge generated by the photodiode 421 to the FD425. The reset transistor 424 resets the charge held in the FD425. The FD425 is connected to the gate of the transistor 382 of the differential input circuit 361. As a result, the transistor 382 of the differential input circuit 361 also functions as an amplification transistor of the pixel circuit 341.
　リセットトランジスタ４２４のソースは、差動入力回路３６１のトランジスタ３８２のゲート、及び、ＦＤ４２５に接続されており、リセットトランジスタ４２４のドレインは、トランジスタ３８２のドレインと接続されている。したがって、ＦＤ４２５の電荷をリセットするための固定のリセット電圧がない。これは、差動入力回路３６１の回路状態を制御することで、ＦＤ４２５をリセットするリセット電圧を、参照信号ＲＥＦを用いて任意に設定可能であるためである。 The source of the reset transistor 424 is connected to the gate of the transistor 382 of the differential input circuit 361 and the drain of the FD425, and the drain of the reset transistor 424 is connected to the drain of the transistor 382. Therefore, there is no fixed reset voltage to reset the charge on the FD425. This is because the reset voltage for resetting the FD425 can be arbitrarily set by using the reference signal REF by controlling the circuit state of the differential input circuit 361.
　第４実施形態に係る固体撮像装置は、図３６に示すように、上側基板３０１と下側基板３０２の２枚の半導体チップを重ねて、ＴＳＶ（through-silicon via）によって上下チップの配線の一部が電気的に接続された積層型イメージセンサで構成される。この場合、上側基板３０１に画素回路３０３が搭載されて、画素回路３０３以外の周辺回路３０４が下側基板３０２に搭載される。図３５に示した等価回路図において、破線の領域３００はＴＳＶ接続箇所を示している。即ち、リセットトランジスタ４２４のソースと、差動入力回路３６１のトランジスタ３８２のゲートがＴＳＶ接続される。リセットトランジスタ４２４のドレインは、トランジスタ３８２のドレインとＴＳＶ接続される。 In the solid-state image sensor according to the fourth embodiment, as shown in FIG. 36, two semiconductor chips of the upper substrate 301 and the lower substrate 302 are overlapped, and one of the wirings of the upper and lower chips is provided by TSV (through-silicon via). It is composed of a laminated image sensor whose parts are electrically connected. In this case, the pixel circuit 303 is mounted on the upper substrate 301, and peripheral circuits 304 other than the pixel circuit 303 are mounted on the lower substrate 302. In the equivalent circuit diagram shown in FIG. 35, the broken line region 300 indicates the TSV connection location. That is, the source of the reset transistor 424 and the gate of the transistor 382 of the differential input circuit 361 are TSV-connected. The drain of the reset transistor 424 is TSV-connected to the drain of the transistor 382.
　このような回路構成の場合、図３５に示した差動入力回路３６１がランダムノイズのノイズ源となる。具体的には、ｎＭＯＳからなる差動入力トランジスタ３８１，３８２とＰＭＯＳからなる能動負荷トランジスタ３８３，３８４である。これらのノイズ源のＭＯＳＦＥＴに、本技術に係るＭＯＳＦＥＴで構成すれば、ランダムノイズを大きく低減できる。 In the case of such a circuit configuration, the differential input circuit 361 shown in FIG. 35 becomes a noise source of random noise. Specifically, there are differential input transistors 381 and 382 made of nMOS and active load transistors 383 and 384 made of MOSFET. Random noise can be greatly reduced by configuring the MOSFETs of these noise sources with MOSFETs according to the present technology.
　図３７及び図３８は、ｎＭＯＳで構成された差動入力トランジスタ３８１，３８２の適用例を示す。差動入力トランジスタ３８１，３８２の活性領域Ａ３，Ａ４は、ＳＴＩ領域４で区画されて、互いに電気的に分離されている。ｐ型の半導体基板１上にｎ型ウェル２及びｐ型ウェル３が設けられている。 37 and 38 show application examples of differential input transistors 381 and 382 composed of nMOS. The active regions A3 and A4 of the differential input transistors 381 and 382 are partitioned by the STI region 4 and electrically separated from each other. An n-type well 2 and a p-type well 3 are provided on the p-type semiconductor substrate 1.
　差動入力トランジスタ３８１は、複数のソース領域１１ａ，１１ｂが配列されたマルチフィンガー構造を有する。差動入力トランジスタ３８１は、ｐ型ウェル３の上部に設けられたｎ＋型のソース領域１１ａ，１１ｂ、ｎ＋型のドレイン領域１２ａ、ｐ＋型のバックゲート端子１３ａを有する。ソース領域１１ａとドレイン領域１２ａに挟まれたチャネル領域上には、ゲート絶縁膜（不図示）を介してゲート電極５ａが設けられている。ソース領域１１ｂとドレイン領域１２ａに挟まれたチャネル領域上には、ゲート絶縁膜（不図示）を介してゲート電極５ｂが設けられている。ソース領域１１ｂとバックゲート端子１３ａに挟まれたｐ型ウェル３上には分離膜６ａが設けられている。ソース領域１１ａ，１１ｂ、ドレイン領域１２ａ、バックゲート端子１３ａの上部にはシリサイド層２１ａ，２１ｂ，２２ａ，２３ａがそれぞれ設けられている。 The differential input transistor 381 has a multi-finger structure in which a plurality of source regions 11a and 11b are arranged. The differential input transistor 381 has n + type source regions 11a and 11b, n + type drain regions 12a, and p + type back gate terminals 13a provided above the p-type well 3. A gate electrode 5a is provided on the channel region sandwiched between the source region 11a and the drain region 12a via a gate insulating film (not shown). A gate electrode 5b is provided on the channel region sandwiched between the source region 11b and the drain region 12a via a gate insulating film (not shown). A separation membrane 6a is provided on the p-type well 3 sandwiched between the source region 11b and the back gate terminal 13a. Silicide layers 21a, 21b, 22a, and 23a are provided above the source regions 11a and 11b, the drain region 12a, and the back gate terminal 13a, respectively.
　差動入力トランジスタ３８２は、複数のソース領域１１ｃ，１１ｄが配列されたマルチフィンガー構造を有する。差動入力トランジスタ３８２は、ｐ型ウェル３の上部に設けられたｎ＋型のソース領域１１ｃ，１１ｄ、ｎ＋型のドレイン領域１２ｂ、ｐ＋型のバックゲート端子１３ｂを有する。ソース領域１１ｃとドレイン領域１２ｂに挟まれたチャネル領域上には、ゲート絶縁膜（不図示）を介してゲート電極５ｃが設けられている。ソース領域１１ｄとドレイン領域１２ｂに挟まれたチャネル領域上には、ゲート絶縁膜（不図示）を介してゲート電極５ｄが設けられている。ソース領域１１ｄとバックゲート端子１３ｂに挟まれたｐ型ウェル３上には分離膜６ｂが設けられている。ソース領域１１ｃ，１１ｄ、ドレイン領域１２ｂ、バックゲート端子１３ｂの上部にはシリサイド層２１ｄ，２１ｄ，２２ｂ，２３ｂがそれぞれ設けられている。 The differential input transistor 382 has a multi-finger structure in which a plurality of source regions 11c and 11d are arranged. The differential input transistor 382 has n + type source regions 11c and 11d, n + type drain regions 12b, and p + type back gate terminals 13b provided above the p-type well 3. A gate electrode 5c is provided on the channel region sandwiched between the source region 11c and the drain region 12b via a gate insulating film (not shown). A gate electrode 5d is provided on the channel region sandwiched between the source region 11d and the drain region 12b via a gate insulating film (not shown). A separation membrane 6b is provided on the p-type well 3 sandwiched between the source region 11d and the back gate terminal 13b. Silicide layers 21d, 21d, 22b, and 23b are provided above the source regions 11c and 11d, the drain region 12b, and the back gate terminal 13b, respectively.
　図３９及び図４０は、ｐＭＯＳで構成された能動負荷トランジスタ３８３，３８４の適用例を示す。能動負荷トランジスタ３８３，３８４の活性領域Ａ５，Ａ６は、ＳＴＩ領域４で区画されて、互いに電気的に分離されている。ｐ型の半導体基板１上にｎ型ウェル７が設けられている。ｎ型ウェル７は、図３８に示したｎ型ウェル２に対応する。 39 and 40 show application examples of active load transistors 383 and 384 composed of pMOS. The active regions A5 and A6 of the active load transistors 383 and 384 are partitioned by the STI region 4 and electrically separated from each other. An n-type well 7 is provided on the p-type semiconductor substrate 1. The n-type well 7 corresponds to the n-type well 2 shown in FIG. 38.
　能動負荷トランジスタ３８３は、複数のソース領域４１ａ，４１ｂが配列されたマルチフィンガー構造を有する。能動負荷トランジスタ３８３は、ｎ型ウェル７の上部に設けられたｐ＋型のソース領域４１ａ，４１ｂ、ｐ＋型のドレイン領域４２ａ、ｎ＋型のバックゲート端子４３ａを有する。ソース領域４１ａとドレイン領域４２ａに挟まれたチャネル領域上には、ゲート絶縁膜（不図示）を介してゲート電極５ａが設けられている。ソース領域４１ｂとドレイン領域４２ａに挟まれたチャネル領域上には、ゲート絶縁膜（不図示）を介してゲート電極５ｂが設けられている。ソース領域４１ｂとバックゲート端子４３ａに挟まれたｎ型ウェル７上には分離膜６ａが設けられている。ソース領域４１ａ，４１ｂ、ドレイン領域４２ａ、バックゲート端子４３ａの上部にはシリサイド層２１ａ，２１ｂ，２２ａ，２３ａがそれぞれ設けられている。 The active load transistor 383 has a multi-finger structure in which a plurality of source regions 41a and 41b are arranged. The active load transistor 383 has p + type source regions 41a and 41b, p + type drain regions 42a, and n + type backgate terminals 43a provided above the n-type well 7. A gate electrode 5a is provided on the channel region sandwiched between the source region 41a and the drain region 42a via a gate insulating film (not shown). A gate electrode 5b is provided on the channel region sandwiched between the source region 41b and the drain region 42a via a gate insulating film (not shown). A separation membrane 6a is provided on the n-type well 7 sandwiched between the source region 41b and the back gate terminal 43a. Silicide layers 21a, 21b, 22a, and 23a are provided above the source regions 41a and 41b, the drain region 42a, and the back gate terminal 43a, respectively.
　能動負荷トランジスタ３８４は、複数のソース領域４１ｃ，４１ｄが配列されたマルチフィンガー構造を有する。能動負荷トランジスタ３８４は、ｎ型ウェル７の上部に設けられたｐ＋型のソース領域４１ｃ，４１ｄ、ｐ＋型のドレイン領域４２ｂ、ｎ＋型のバックゲート端子４３ｂを有する。ソース領域４１ｃとドレイン領域４２ｂに挟まれたチャネル領域上には、ゲート絶縁膜（不図示）を介してゲート電極５ｃが設けられている。ソース領域４１ｄとドレイン領域４２ｂに挟まれたチャネル領域上には、ゲート絶縁膜（不図示）を介してゲート電極５ｄが設けられている。ソース領域４１ｄとバックゲート端子４３ｂに挟まれたｎ型ウェル７上には分離膜６ｂが設けられている。ソース領域４１ｃ，４１ｄ、ドレイン領域４２ｂ、バックゲート端子４３ｂの上部にはシリサイド層２１ｄ，２１ｄ，２２ｂ，２３ｂがそれぞれ設けられている。 The active load transistor 384 has a multi-finger structure in which a plurality of source regions 41c and 41d are arranged. The active load transistor 384 has p + type source regions 41c and 41d, p + type drain regions 42b, and n + type backgate terminals 43b provided above the n-type well 7. A gate electrode 5c is provided on the channel region sandwiched between the source region 41c and the drain region 42b via a gate insulating film (not shown). A gate electrode 5d is provided on the channel region sandwiched between the source region 41d and the drain region 42b via a gate insulating film (not shown). A separation membrane 6b is provided on the n-type well 7 sandwiched between the source region 41d and the back gate terminal 43b. Silicide layers 21d, 21d, 22b, and 23b are provided above the source regions 41c and 41d, the drain region 42b, and the back gate terminal 43b, respectively.
　図４１に示すように、差動入力トランジスタ３８１，３８２と、定電流源としてのトランジスタ３８５が上側基板３０１に配置されていてもよい。この場合、図４１に破線で囲んだ領域３００がＴＳＶ接続箇所となる。差動入力トランジスタ３８１，３８２と、定電流源としてのトランジスタ３８５が上側基板３０１に配置された構成の場合でも、上側基板３０１に配置された差動入力トランジスタ３８１，３８２において、図３７及び図３８に示した構造を適用し、回路を低ノイズ化することができる。 As shown in FIG. 41, the differential input transistors 381 and 382 and the transistor 385 as a constant current source may be arranged on the upper substrate 301. In this case, the area 300 surrounded by the broken line in FIG. 41 is the TSV connection point. Even in the case where the differential input transistors 381 and 382 and the transistor 385 as a constant current source are arranged on the upper substrate 301, the differential input transistors 381 and 382 arranged on the upper substrate 301 are shown in FIGS. 37 and 38. The structure shown in the above can be applied to reduce the noise of the circuit.
　（第５実施形態）
　第１～第４実施形態では、本技術に係る半導体装置を電子機器の一例である固体撮像装置に適用した場合を例示した。第５実施形態では、本技術に係る半導体装置をその他の電子機器に適用した場合を例示する。 (Fifth Embodiment)
In the first to fourth embodiments, a case where the semiconductor device according to the present technology is applied to a solid-state image sensor which is an example of an electronic device is illustrated. In the fifth embodiment, a case where the semiconductor device according to the present technology is applied to other electronic devices will be illustrated.
　例えば、本技術に係る半導体装置は、一般的な比較器を構成するＭＯＳＦＥＴへ適用可能である。一般的な比較器は、例えば図４２に示すように、能動負荷トランジスタＴ３１，Ｔ３２と、差動入力トランジスタＴ４１，Ｔ４２を備え、能動負荷トランジスタＴ３１，Ｔ３２及び差動入力トランジスタＴ４１，Ｔ４２の構成として本技術に係る半導体装置を適用可能である。比較器を構成するＭＯＳＦＥＴに本技術に係る半導体装置を適用することで、比較器を低ノイズ化できる。このような比較器は、光、温度、匂い等の各種センサ回路で用いられるアナログスイッチに適用される。例えば、比較器が光検出器に適用される場合には、図４４及び図４５に示すように、フォトダイオードを使って検出した検出信号Ｖｄと基準電圧Ｖｒｅｆとを比較器４０１が比較し、その比較結果に応じた電圧Ｖｏｕｔを出力することで、光の検出有無を判定する。本技術に係る半導体装置は、検出信号Ｖｄが微弱で、高Ｓ／Ｎ比が要求されるような比較器を構成するＭＯＳＦＥＴに好適である。 For example, the semiconductor device according to the present technology can be applied to MOSFETs constituting a general comparator. As shown in FIG. 42, for example, a general comparator includes active load transistors T31 and T32 and differential input transistors T41 and T42, and has a configuration of active load transistors T31 and T32 and differential input transistors T41 and T42. The semiconductor device according to this technology can be applied. By applying the semiconductor device according to the present technology to the MOSFETs that make up the comparator, the comparator can be made less noisy. Such a comparator is applied to an analog switch used in various sensor circuits such as light, temperature, and odor. For example, when the comparator is applied to a photodetector, as shown in FIGS. 44 and 45, the comparator 401 compares the detection signal Vd detected using the photodiode with the reference voltage Vref, and the comparator 401 compares the detection signal Vd and the reference voltage Vref. By outputting the voltage Vout according to the comparison result, it is determined whether or not light is detected. The semiconductor device according to the present technology is suitable for a MOSFET that constitutes a comparator in which a detection signal Vd is weak and a high S / N ratio is required.
　また、本技術に係る半導体装置は、ＤＡコンバータに適用できる。例えば、本技術に係る半導体装置は、ＤＡコンバータの一例である、図４６に示すような重み抵抗型ＤＡコンバータを示す。重み抵抗型ＤＡコンバータは、比較器４０２と抵抗素子Ｒｆからなる加算回路を用いて、抵抗の比例で、各ビットに比例して出力電圧の重みを作り、アナログ信号に変換する。この比較器４０２を構成するＭＯＳＦＥＴに、本技術に係る半導体装置を適用可能である。 Further, the semiconductor device according to this technology can be applied to a DA converter. For example, the semiconductor device according to the present technology shows a weight resistance type DA converter as shown in FIG. 46, which is an example of a DA converter. The weighted resistance type DA converter uses an adder circuit including a comparator 402 and a resistance element Rf to create a weight of an output voltage in proportion to each bit in proportion to resistance and convert it into an analog signal. The semiconductor device according to the present technology can be applied to the MOSFETs constituting the comparator 402.
　また、本技術に係る半導体装置は、上述したもの他にも、各種計測器、ＡＶ機器、家電製品等の種々の電子機器で使用されるＭＯＳＦＥＴに適用可能である。 In addition to the above-mentioned semiconductor devices, the semiconductor devices according to this technology can be applied to MOSFETs used in various electronic devices such as various measuring instruments, AV devices, and home appliances.
　なお、本技術は、以下のような構成を取ることができる。
（１）
　第１半導体層と、
　前記第１半導体層に互いに設けられ、前記第１半導体層と反対導電型の第１及び第２主電極領域と、
　前記第１及び第２主電極領域に挟まれたチャネル領域上に設けられたゲート電極と、
　前記ゲート電極と電気的に接続されたバックゲート端子と、
　を備え、
　前記第１及び第２主電極領域並びに前記バックゲート端子が、素子分離領域で区画された同一の活性領域内にある、
　半導体装置。
（２）
　前記第１半導体層の下に設けられ、前記第１半導体層に接し、前記第１半導体層と反対導電型の第２半導体層又は半導体基板を更に備え、
　前記第１半導体層と前記第２半導体層又は前記半導体基板との接合面が、前記素子分離領域よりも浅く、前記第１及び第２主電極領域よりも深い、
　前記（１）に記載の半導体装置。
（３）
　前記バックゲート端子が、前記第１半導体層に設けられ、前記第１半導体層と同一導電型で、前記第１半導体層よりも高不純物濃度のウェルタップ領域からなる、
　前記（１）又は（２）に記載の半導体装置。
（４）
　前記バックゲート端子が、前記第１及び第２主電極領域から離間した前記第１半導体層の一部からなる、
　前記（１）又は（２）に記載の半導体装置。
（５）
　前記第１及び第２主電極領の一方と前記バックゲート端子とに挟まれた前記第１半導体層上に設けられた分離膜を更に備える、
　前記（１）～（４）のいずれかに記載の半導体装置。
（６）
　前記第１及び第２主電極領域並びに前記バックゲート端子の上部にシリサイド層がそれぞれ設けられている、
　前記（５）に記載の半導体装置。
（７）
　前記分離膜が、前記ゲート電極と同一の材料からなる、
　前記（５）又は（６）に記載の半導体装置。
（８）
　前記分離膜が、絶縁材料からなる、
　前記（５）又は（６）に記載の半導体装置。
（９）
　前記素子分離領域が、平面パターン上、前記第１及び第２主電極領域の一方と前記バックゲート端子との間に延在する凸部を有する、
　前記（１）～（８）のいずれかに記載の半導体装置。
（１０）
　前記チャネル領域がフィン形状を有し、
　前記第１及び第２主電極領域の一方と、前記バックゲート端子との間に挟まれた前記第１半導体層の一部がフィン形状を有する、
　前記（１）～（８）のいずれかに記載の半導体装置。
（１１）
　前記活性領域内に設けられた第２半導体層と、
　前記第２半導体層の一部の上に選択的に設けられた埋込絶縁膜と、
　を更に備え、
　前記第１半導体層、前記第１及び第２主電極領域が前記埋込絶縁膜上に設けられ、
　前記バックゲート端子が、前記第２半導体層の他の一部に設けられている、
　前記（１）又は（２）に記載の半導体装置。
（１２）
　前記第２半導体層が、前記第１半導体層と同一導電型であり、
　前記バックゲート端子が、前記第２半導体層と同一導電型で、前記第２半導体層よりも高不純物濃度のウェルタップ領域からなる、
　前記（１１）に記載の半導体装置。
（１３）
　前記第２半導体層が、前記第１半導体層と反対導電型であり、
　前記バックゲート端子が、前記第２半導体層と同一導電型で、前記第２半導体層よりも高不純物濃度のウェルタップ領域からなる、
　前記（１１）に記載の半導体装置。
（１４）
　前記第２半導体層の下に設けられ、前記第２半導体層に接し、前記第２半導体層と反対導電型の第３半導体層又は半導体基板を更に備え、
　前記第２半導体層と前記第３半導体層又は前記半導体基板との接合面が、前記素子分離領域よりも浅く、前記第１及び第２主電極領域よりも深い、
　前記（１１）～（１３）のいずれかに記載の半導体装置。
（１５）
　第１半導体層と、
　前記第１半導体層に互いに設けられ、前記第１半導体層と反対導電型の第１及び第２主電極領域と、
　前記第１及び第２主電極領域に挟まれたチャネル領域上に設けられたゲート電極と、
　前記ゲート電極と電気的に接続されたバックゲート端子と、
　を有する半導体装置を備え、
　前記第１及び第２主電極領域並びに前記バックゲート端子が、素子分離領域で区画された同一の活性領域内にある、
　電子機器。 The present technology can have the following configurations.
(1)
The first semiconductor layer and
The first and second main electrode regions, which are provided on the first semiconductor layer and are opposite to the first semiconductor layer,
A gate electrode provided on the channel region sandwiched between the first and second main electrode regions, and
A back gate terminal electrically connected to the gate electrode and
With
The first and second main electrode regions and the back gate terminal are in the same active region partitioned by the device separation region.
Semiconductor device.
(2)
A second semiconductor layer or a semiconductor substrate which is provided below the first semiconductor layer, is in contact with the first semiconductor layer, and is opposite to the first semiconductor layer, is further provided.
The bonding surface between the first semiconductor layer and the second semiconductor layer or the semiconductor substrate is shallower than the element separation region and deeper than the first and second main electrode regions.
The semiconductor device according to (1) above.
(3)
The back gate terminal is provided in the first semiconductor layer, has the same conductive type as the first semiconductor layer, and has a well-tapped region having a higher impurity concentration than the first semiconductor layer.
The semiconductor device according to (1) or (2) above.
(4)
The back gate terminal comprises a part of the first semiconductor layer separated from the first and second main electrode regions.
The semiconductor device according to (1) or (2) above.
(5)
A separation film provided on the first semiconductor layer sandwiched between one of the first and second main electrode areas and the back gate terminal is further provided.
The semiconductor device according to any one of (1) to (4) above.
(6)
Silicide layers are provided above the first and second main electrode regions and the back gate terminal, respectively.
The semiconductor device according to (5) above.
(7)
The separation membrane is made of the same material as the gate electrode.
The semiconductor device according to (5) or (6) above.
(8)
The separation membrane is made of an insulating material.
The semiconductor device according to (5) or (6) above.
(9)
The element separation region has a convex portion extending between one of the first and second main electrode regions and the back gate terminal on a plane pattern.
The semiconductor device according to any one of (1) to (8) above.
(10)
The channel region has a fin shape
A part of the first semiconductor layer sandwiched between one of the first and second main electrode regions and the back gate terminal has a fin shape.
The semiconductor device according to any one of (1) to (8) above.
(11)
The second semiconductor layer provided in the active region and
An embedded insulating film selectively provided on a part of the second semiconductor layer,
With more
The first semiconductor layer and the first and second main electrode regions are provided on the embedded insulating film.
The back gate terminal is provided in another part of the second semiconductor layer.
The semiconductor device according to (1) or (2) above.
(12)
The second semiconductor layer is the same conductive type as the first semiconductor layer.
The back gate terminal is of the same conductive type as the second semiconductor layer, and is composed of a well-tap region having a higher impurity concentration than the second semiconductor layer.
The semiconductor device according to (11) above.
(13)
The second semiconductor layer is an opposite conductive type to the first semiconductor layer.
The back gate terminal is of the same conductive type as the second semiconductor layer, and is composed of a well-tap region having a higher impurity concentration than the second semiconductor layer.
The semiconductor device according to (11) above.
(14)
It is provided below the second semiconductor layer, is in contact with the second semiconductor layer, and further includes a third semiconductor layer or a semiconductor substrate that is opposite to the second semiconductor layer.
The bonding surface between the second semiconductor layer and the third semiconductor layer or the semiconductor substrate is shallower than the element separation region and deeper than the first and second main electrode regions.
The semiconductor device according to any one of (11) to (13).
(15)
The first semiconductor layer and
The first and second main electrode regions, which are provided on the first semiconductor layer and are opposite to the first semiconductor layer,
A gate electrode provided on the channel region sandwiched between the first and second main electrode regions, and
A back gate terminal electrically connected to the gate electrode and
Equipped with a semiconductor device that has
The first and second main electrode regions and the back gate terminal are in the same active region partitioned by the device separation region.
Electronics.
　１…半導体基板、２，７，８…ｎ型ウェル、３，９…ｐ型ウェル、４，４ｘ…素子分離領域（ＳＴＩ領域）、４ａ，４ｂ…凸部、５…ゲート電極、６…分離膜、１１，４１…ソース領域、１２，４２…ドレイン領域、１３，１３ａ，４３，４３ａ…バックゲート端子、１４…埋込絶縁膜（ＢＯＸ層）、１５，１６…半導体層（ＳＯＩ層）、２１，２２，２３…シリサイド層、３０…画素、３１，２０５…定電流源負荷、１００…固体撮像装置（ＣＭＯＳイメージセンサ）、１１０，２０１…画素アレイ部、１２０，２０２…行選択回路、１３０，２０８…水平転送走査回路、１４０，２０４…タイミング制御回路、１５０…ＡＤＣ群、１５１，２０６…比較器（コンパレータ）、１５２…カウンタ、１５３ラッチ、１６０…デジタル－アナログ変換装置、１７０…アンプ回路、１８０，２１０…信号処理回路、１９０…水平転送線、２０７…カウンタ／ラッチ回路、２０９…ＤＣ供給回路、３０１…上側基板、３０２…下側基板、３０３…画素回路、３０４…周辺回路、３１１…半導体基板、３２１…画素、３２２…画素アレイ部、３２３…時刻コード転送部、３２４…画素駆動回路、３２５…画素駆動回路、３２６…時刻コード発生部、３２７…垂直駆動回路、３２８…出力部、３２９…タイミング生成回路、３４１…画素回路、３５１…比較回路、３５２…データ記憶部、３６１…差動入力回路、３６２…電圧変換回路、３６３…正帰還回路、３７０…アンプ回路、３７１…ラッチ制御回路、３７２…ラッチ記憶部、３８１～３８６，３９１，４０１～４０５…トランジスタ、４２１…フォトダイオード、４２２…排出トランジスタ、４２３…転送トランジスタ、４２４…リセットトランジスタ、５０１，５０２…比較器、Ａ０～Ａ６…活性領域、Ｃ１，Ｃ２…サンプリング容量、Ｄ１…光電変換素子、ＦＤ…フローティングディフュージョン、ＩＳ…定電流源、ＬＲＳＴ…リセット制御線、ＬＳＥＬ…選択制御線、ＬＳＧＮ…信号線、ＬＳＧＮ…垂直信号線、ＬＴＲＧ…転送制御線、ＬＶＤＤ…電源ライン、Ｒｆ…抵抗素子、Ｔ１～Ｔ４，Ｔ１１，Ｔ１２，Ｔ２１，Ｔ２２，Ｔ３１，Ｔ３２，Ｔ４１，Ｔ４２…トランジスタ 1 ... semiconductor substrate, 2,7,8 ... n-type well, 3,9 ... p-type well, 4,4x ... element separation region (STI region), 4a, 4b ... convex portion, 5 ... gate electrode, 6 ... separation Membrane, 11, 41 ... Source region, 12, 42 ... Drain region, 13, 13a, 43, 43a ... Back gate terminal, 14 ... Embedded insulating film (BOX layer), 15, 16 ... Semiconductor layer (SOI layer), 21,22,23 ... VDD layer, 30 ... Pixels, 31,205 ... Constant current source load, 100 ... Solid image pickup device (CMOS image sensor), 110, 201 ... Pixel array unit, 120, 202 ... Row selection circuit, 130 , 208 ... Horizontal transfer scanning circuit, 140, 204 ... Timing control circuit, 150 ... ADC group, 151,206 ... Comparer (comparator), 152 ... Counter, 153 latch, 160 ... Digital-analog converter, 170 ... Amplifier circuit , 180, 210 ... Signal processing circuit, 190 ... Horizontal transfer line, 207 ... Counter / latch circuit, 209 ... DC supply circuit, 301 ... Upper board, 302 ... Lower board, 303 ... Pixel circuit, 304 ... Peripheral circuit, 311 ... Semiconductor substrate, 321 ... Pixels, 322 ... Pixel array unit, 323 ... Time code transfer unit, 324 ... Pixel drive circuit, 325 ... Pixel drive circuit, 326 ... Time code generator, 327 ... Vertical drive circuit, 328 ... Output unit , 329 ... Timing generation circuit, 341 ... Pixel circuit, 351 ... Comparison circuit, 352 ... Data storage unit, 361 ... Differential input circuit, 362 ... Voltage conversion circuit, 363 ... Positive feedback circuit, 370 ... Amplifier circuit, 371 ... Latch Control circuit, 372 ... Latch storage, 381 to 386, 391, 401 to 405 ... Transistor, 421 ... Photo diode, 422 ... Ejection transistor, 423 ... Transfer transistor, 424 ... Reset transistor, 501, 502 ... Comparer, A0 to A6 ... active region, C1, C2 ... sampling capacitance, D1 ... photoelectric conversion element, FD ... floating diffusion, IS ... constant current source, LRST ... reset control line, LSEL ... selection control line, LSGN ... signal line, LSGN ... vertical signal Line, LTRG ... Transfer control line, L VDD ... Power supply line, Rf ... Resistance element, T1 to T4, T11, T12, T21, T22, T31, T32, T41, T42 ... Transistor

Claims (15)

  1. 　第１半導体層と、
    　前記第１半導体層に互いに設けられ、前記第１半導体層と反対導電型の第１及び第２主電極領域と、
    　前記第１及び第２主電極領域に挟まれたチャネル領域上に設けられたゲート電極と、
    　前記ゲート電極と電気的に接続されたバックゲート端子と、
    　を備え、
    　前記第１及び第２主電極領域並びに前記バックゲート端子が、素子分離領域で区画された同一の活性領域内にある、
    　半導体装置。     The first semiconductor layer and
    The first and second main electrode regions, which are provided on the first semiconductor layer and are opposite to the first semiconductor layer,
    A gate electrode provided on the channel region sandwiched between the first and second main electrode regions, and
    A back gate terminal electrically connected to the gate electrode and
    With
    The first and second main electrode regions and the back gate terminal are in the same active region partitioned by the device separation region.
    Semiconductor device.
  2. 　前記第１半導体層の下に設けられ、前記第１半導体層に接し、前記第１半導体層と反対導電型の第２半導体層又は半導体基板を更に備え、
    　前記第１半導体層と前記第２半導体層又は前記半導体基板との接合面が、前記素子分離領域よりも浅く、前記第１及び第２主電極領域よりも深い、
    　請求項１に記載の半導体装置。     A second semiconductor layer or a semiconductor substrate which is provided below the first semiconductor layer, is in contact with the first semiconductor layer, and is opposite to the first semiconductor layer, is further provided.
    The bonding surface between the first semiconductor layer and the second semiconductor layer or the semiconductor substrate is shallower than the element separation region and deeper than the first and second main electrode regions.
    The semiconductor device according to claim 1.
  3. 　前記バックゲート端子が、前記第１半導体層に設けられ、前記第１半導体層と同一導電型で、前記第１半導体層よりも高不純物濃度のウェルタップ領域からなる、
    　請求項１に記載の半導体装置。     The back gate terminal is provided in the first semiconductor layer, has the same conductive type as the first semiconductor layer, and has a well-tapped region having a higher impurity concentration than the first semiconductor layer.
    The semiconductor device according to claim 1.
  4. 　前記バックゲート端子が、前記第１及び第２主電極領域から離間した前記第１半導体層の一部からなる、
    　請求項１に記載の半導体装置。     The back gate terminal comprises a part of the first semiconductor layer separated from the first and second main electrode regions.
    The semiconductor device according to claim 1.
  5. 　前記第１及び第２主電極領の一方と前記バックゲート端子とに挟まれた前記第１半導体層上に設けられた分離膜を更に備える、
    　請求項１に記載の半導体装置。     A separation film provided on the first semiconductor layer sandwiched between one of the first and second main electrode areas and the back gate terminal is further provided.
    The semiconductor device according to claim 1.
  6. 　前記第１及び第２主電極領域並びに前記バックゲート端子の上部にシリサイド層がそれぞれ設けられている、
    　請求項５に記載の半導体装置。     Silicide layers are provided above the first and second main electrode regions and the back gate terminal, respectively.
    The semiconductor device according to claim 5.
  7. 　前記分離膜が、前記ゲート電極と同一の材料からなる、
    　請求項５に記載の半導体装置。     The separation membrane is made of the same material as the gate electrode.
    The semiconductor device according to claim 5.
  8. 　前記分離膜が、絶縁材料からなる、
    　請求項５に記載の半導体装置。     The separation membrane is made of an insulating material.
    The semiconductor device according to claim 5.
  9. 　前記素子分離領域が、平面パターン上、前記第１及び第２主電極領域の一方と前記バックゲート端子との間に延在する凸部を有する、
    　請求項１に記載の半導体装置。     The element separation region has a convex portion extending between one of the first and second main electrode regions and the back gate terminal on a plane pattern.
    The semiconductor device according to claim 1.
  10. 　前記チャネル領域がフィン形状を有し、
    　前記第１及び第２主電極領域の一方と、前記バックゲート端子との間に挟まれた前記第１半導体層の一部がフィン形状を有する、
    　請求項１に記載の半導体装置。     The channel region has a fin shape
    A part of the first semiconductor layer sandwiched between one of the first and second main electrode regions and the back gate terminal has a fin shape.
    The semiconductor device according to claim 1.
  11. 　前記活性領域内に設けられた第２半導体層と、
    　前記第２半導体層の一部の上に選択的に設けられた埋込絶縁膜と、
    　を更に備え、
    　前記第１半導体層、前記第１及び第２主電極領域が前記埋込絶縁膜上に設けられ、
    　前記バックゲート端子が、前記第２半導体層の他の一部に設けられている、
    　請求項１に記載の半導体装置。     The second semiconductor layer provided in the active region and
    An embedded insulating film selectively provided on a part of the second semiconductor layer,
    With more
    The first semiconductor layer and the first and second main electrode regions are provided on the embedded insulating film.
    The back gate terminal is provided in another part of the second semiconductor layer.
    The semiconductor device according to claim 1.
  12. 　前記第２半導体層が、前記第１半導体層と同一導電型であり、
    　前記バックゲート端子が、前記第２半導体層と同一導電型で、前記第２半導体層よりも高不純物濃度のウェルタップ領域からなる、
    　請求項１１に記載の半導体装置。     The second semiconductor layer is the same conductive type as the first semiconductor layer.
    The back gate terminal is of the same conductive type as the second semiconductor layer, and is composed of a well-tap region having a higher impurity concentration than the second semiconductor layer.
    The semiconductor device according to claim 11.
  13. 　前記第２半導体層が、前記第１半導体層と反対導電型であり、
    　前記バックゲート端子が、前記第２半導体層と同一導電型で、前記第２半導体層よりも高不純物濃度のウェルタップ領域からなる、
    　請求項１１に記載の半導体装置。     The second semiconductor layer is an opposite conductive type to the first semiconductor layer.
    The back gate terminal is of the same conductive type as the second semiconductor layer, and is composed of a well-tap region having a higher impurity concentration than the second semiconductor layer.
    The semiconductor device according to claim 11.
  14. 　前記第２半導体層の下に設けられ、前記第２半導体層に接し、前記第２半導体層と反対導電型の第３半導体層又は半導体基板を更に備え、
    　前記第２半導体層と前記第３半導体層又は前記半導体基板との接合面が、前記素子分離領域よりも浅く、前記第１及び第２主電極領域よりも深い、
    　請求項１１に記載の半導体装置。     It is provided below the second semiconductor layer, is in contact with the second semiconductor layer, and further includes a third semiconductor layer or a semiconductor substrate that is opposite to the second semiconductor layer.
    The bonding surface between the second semiconductor layer and the third semiconductor layer or the semiconductor substrate is shallower than the element separation region and deeper than the first and second main electrode regions.
    The semiconductor device according to claim 11.
  15. 　第１半導体層と、
    　前記第１半導体層に互いに設けられ、前記第１半導体層と反対導電型の第１及び第２主電極領域と、
    　前記第１及び第２主電極領域に挟まれたチャネル領域上に設けられたゲート電極と、
    　前記ゲート電極と電気的に接続されたバックゲート端子と、
    　を有する半導体装置を備え、
    　前記第１及び第２主電極領域並びに前記バックゲート端子が、素子分離領域で区画された同一の活性領域内にある、
    　電子機器。     The first semiconductor layer and
    The first and second main electrode regions, which are provided on the first semiconductor layer and are opposite to the first semiconductor layer,
    A gate electrode provided on the channel region sandwiched between the first and second main electrode regions, and
    A back gate terminal electrically connected to the gate electrode and
    Equipped with a semiconductor device that has
    The first and second main electrode regions and the back gate terminal are in the same active region partitioned by the device separation region.
    Electronics.
PCT/JP2020/026908 2019-08-22 2020-07-09 Semiconductor device and electronic apparatus WO2021033454A1 (en)

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