WO2021033454A1 - Dispositif à semi-conducteur et appareil électronique - Google Patents

Dispositif à semi-conducteur et appareil électronique Download PDF

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WO2021033454A1
WO2021033454A1 PCT/JP2020/026908 JP2020026908W WO2021033454A1 WO 2021033454 A1 WO2021033454 A1 WO 2021033454A1 JP 2020026908 W JP2020026908 W JP 2020026908W WO 2021033454 A1 WO2021033454 A1 WO 2021033454A1
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semiconductor layer
semiconductor device
region
back gate
gate terminal
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PCT/JP2020/026908
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English (en)
Japanese (ja)
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場色　正昭
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2021033454A1 publication Critical patent/WO2021033454A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the technology according to the present disclosure (the present technology) relates to a technology for reducing random noise such as a MOS field effect transistor (MOSFET) suitable for a solid-state image sensor represented by a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
  • MOSFET MOS field effect transistor
  • CMOS Complementary Metal Oxide Semiconductor
  • Examples of the solid-state image sensor that captures an image include a CCD (Charge Coupled Device) image sensor and a CMOS image sensor.
  • CCD Charge Coupled Device
  • CMOS image sensors that can be manufactured by existing CMOS processes without requiring special capital investment have attracted attention, and are rapidly being adopted in camera systems and surveillance systems built into mobile phones. It is progressing.
  • the CMOS image sensor has an AD conversion unit that AD (Analog to Digital) converts an analog electrical signal output by a pixel that performs photoelectric conversion.
  • the AD conversion unit of the CMOS image sensor can perform AD conversion in parallel to electrical signals output by two or more pixels, such as all of a plurality of pixels lined up in a row, in response to a request for high-speed processing.
  • a type AD conversion unit (hereinafter, also referred to as “column parallel AD conversion unit”) is adopted.
  • the column-parallel AD converter is configured by, for example, arranging a plurality of analog-to-digital converters (ADCs) having the same number of pixels as the number of columns arranged side by side in the row direction.
  • the ADC in each row performs AD conversion of the electrical signal output by the pixels in that row.
  • the ADC constituting the column-parallel AD conversion unit includes, for example, a comparator and a counter, and AD conversion of an electric signal is performed by comparing a predetermined reference signal with an electric signal output by a pixel. There is a so-called reference signal comparison type ADC that is performed.
  • a reference signal comparison type ADC for example, there is a single slope type ADC (see Patent Document 1).
  • a single-slope ADC a differential input transistor composed of MOSFETs and a comparator consisting of an active load compare a reference signal whose level changes with a constant inclination such as a lamp signal and a pixel signal output by a pixel. By counting the time required for the level of the reference signal to change until the levels of the reference signal and the electric signal match in the counter, the electric signal output by the pixel is AD-converted.
  • the lander noise of the MOSFET is almost determined by flicker noise (1 / f noise), random telegraph noise (RTN), and thermal noise (see Non-Patent Document 1). Of these, the flicker noise and RTN noise levels are known to be inversely proportional to the gate electrode area of the MOSFET.
  • the MOSFET that is the noise source has a multi-finger structure in which multiple MOSFETs are connected in parallel, and the gate electrode area of the entire MOSFET is increased to increase flicker noise and RTN. It is possible to reduce the temporal variation of the sensed image data (see Patent Document 2).
  • CMOS image sensors As the application of CMOS image sensors to various fields progresses, miniaturization and higher performance are required.
  • One of the requirements is to reduce the noise of the CMOS image sensor, but the means of increasing the gate electrode area of the MOSFET, which is the noise source, also increases the circuit area, making it difficult to achieve both miniaturization of the sensor. .. against this background, there is a demand for a technique for reducing noise without increasing the circuit area. In response to such a requirement, a structure in which the gate electrode and the back gate are electrically shared is disclosed (see Patent Document 3).
  • the purpose of this technology is to provide semiconductor devices and electronic devices that achieve both low noise and miniaturization without complicating the manufacturing process.
  • the semiconductor device is provided on the first semiconductor layer and the first semiconductor layer, and is opposite to the first semiconductor layer and has first and second main electrode regions, and first and second.
  • a gate electrode provided on a channel region sandwiched between the main electrode regions and a back gate terminal electrically connected to the gate electrode are provided, and the first and second main electrode regions and the back gate terminal are separated from each other.
  • the gist is that they are in the same active region partitioned by regions.
  • the electronic devices according to one aspect of the present technology are provided on the first semiconductor layer and the first semiconductor layer, and are opposite to the first semiconductor layer and have first and second main electrode regions, and first and second main electrode regions. It has a semiconductor device including a gate electrode provided on a channel region sandwiched between main electrode regions and a back gate terminal electrically connected to the gate electrode, and has first and second main electrode regions and a back gate.
  • the gist is that the terminals are in the same active region partitioned by the element separation region.
  • the "first main electrode region" of the semiconductor device constituting the semiconductor device including the solid-state imaging device is an insulated gate type field effect transistor (MISFET) such as a MOSFET or an insulated gate type electrostatic induction transistor (MISSIT). ) Or a semiconductor region that is either a source region or a drain region such as a high electron mobility transistor (HEMT).
  • the “second main electrode region” means a semiconductor region such as a MISFET that is either a source region or a drain region that does not become the first main electrode region. As described above, when the "first main electrode region” is the source region, the "second main electrode region” means the drain region.
  • first conductive type means one of the p-type or the n-type
  • second conductive type means one of the p-type or the n-type different from the “first conductive type”.
  • third conductive type means one of the p-type or the n-type different from the “first conductive type”.
  • the definition of the vertical direction in the following description is merely a definition for convenience of explanation, and does not limit the technical idea of the present technology. For example, if the object is rotated by 90 ° and observed, the top and bottom are converted to left and right and read, and if the object is rotated by 180 ° and observed, the top and bottom are reversed and read.
  • the solid-state image sensor 100 includes a pixel array unit 110 and peripheral circuits for reading an electric signal from the pixel array unit 110 and performing predetermined signal processing.
  • the solid-state image sensor 100 generates a row selection circuit 120 for controlling row addresses and row scans, a horizontal transfer scanning circuit 130 for controlling column addresses and column scans, and an internal clock as control circuits.
  • the timing control circuit 140 is provided.
  • the solid-state imaging device 100 according to the first embodiment includes an ADC group 150 as peripheral circuits, a digital-to-analog converter (DAC) 160 as a lamp signal generator, an amplifier circuit 170, a signal processing circuit 180, and horizontal transfer. It has a line 190.
  • the solid-state image sensor 100 according to the first embodiment has a DC power supply circuit (not shown) as a peripheral circuit.
  • the pixel array unit 110 is configured by arranging a large number of pixels 30 in an array shape (matrix shape).
  • the pixel 30 has, for example, a photoelectric conversion element D1 made of, for example, a photodiode (PD), as shown in FIG.
  • the pixel 30 has four transistors, a transfer transistor T1, a reset transistor T2, an amplification transistor T3, and a selection transistor T4, as active elements with respect to the photoelectric conversion element D1.
  • the constant current source load 31 is connected to the vertical signal line (LSGN) in which the pixel 30 is shared in the column direction.
  • LSGN vertical signal line
  • the photoelectric conversion element D1 photoelectrically converts the incident light into an electric charge (electrons in this case) in an amount corresponding to the amount of the light.
  • the transfer transistor T1 as a transfer element is connected between the photoelectric conversion element D1 and the floating diffusion FD as an input node, and a transfer signal TRG which is a control signal is given to the gate (transfer gate) through the transfer control line LTRG. .. As a result, the transfer transistor T1 transfers the electrons photoelectrically converted by the photoelectric conversion element D1 to the floating diffusion FD.
  • the reset transistor T2 is connected between the power supply line L VDD to which the power supply voltage VDD is supplied and the floating diffusion FD, and the reset signal RST, which is a control signal, is given to the gate through the reset control line LRST.
  • the reset transistor T2 as the reset element resets the potential of the floating diffusion FD to the potential of the power supply line L VDD.
  • the gate of the amplification transistor T3 as an amplification element is connected to the floating diffusion FD. That is, the floating diffusion FD functions as an input node of the amplification transistor T3 as an amplification element.
  • the amplification transistor T3 and the selection transistor T4 are connected in series between the power supply line L VDD to which the power supply voltage VDD is supplied and the signal line LSGN. In this way, the amplification transistor T3 is connected to the signal line LSGN via the selection transistor T4, and constitutes a constant current source IS outside the pixel portion and a source follower.
  • the selection signal SEL which is a control signal corresponding to the address signal
  • the selection transistor T4 is turned on.
  • the amplification transistor T3 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the signal line LSGN.
  • the voltage output from each pixel through the signal line LSGN is output to the ADC group 150. Since, for example, the gates of the transfer transistor T1, the reset transistor T2, and the selection transistor T4 are connected in row units, these operations are performed simultaneously for each pixel for one row.
  • the reset control line LRST, the transfer control line LTRG, and the selection control line LSEL wired to the pixel array unit 110 are wired as a set for each row of the pixel array.
  • the reset control line LRST, the transfer control line LTRG, and the selection control line LSEL are each provided with M lines. These reset control line LRST, transfer control line LTRG, and selection control line LSEL are driven by the row selection circuit 120.
  • the comparator 151 has a differential amplifier circuit including differential input transistors T21 and T22 forming a differential pair and active load transistors T11 and T12 including a current mirror circuit.
  • the differential input transistors T21 and T22 are composed of n-type MOSFETs (hereinafter, also referred to as “nMOS”), and the active load transistors T11 and T12 are composed of p-type MOSFETs (hereinafter, also referred to as “pMOS”).
  • nMOS n-type MOSFETs
  • pMOS p-type MOSFETs
  • the active load transistors T11 and T12 and the differential input transistors T21 and T22 serve as noise sources.
  • the comparator 151 includes a reference voltage (DAC side input) Vslop, which is a ramp waveform obtained by changing the reference voltage generated by the DAC 160 in a stepwise manner, and an analog signal obtained from a pixel via the vertical signal line LSGN for each line. (VSL (Vertical Signal Line) side input) is compared.
  • VSL Very Signal Line
  • the counter 152 shown in FIG. 1 counts the comparison time of the comparator 151.
  • the ADC group 150 has an n-bit digital signal conversion function and is arranged for each vertical signal line (row line) to form a row-parallel ADC block.
  • the output of each latch 153 is connected to, for example, a horizontal transfer line 190 having a width of 2 n bits. Then, 2n amplifier circuits 170 and signal processing circuits 180 corresponding to the horizontal transfer lines 190 are arranged.
  • FIG. 5 shows a layout diagram of each circuit constituting the solid-state image sensor according to the first embodiment on the semiconductor chip.
  • the pixel array unit 201, the constant current source load 205, the comparator 206, the counter / latch circuit 207, and the horizontal transfer scanning circuit 208 are arranged from the upper side to the lower side.
  • a row selection circuit 202 is arranged adjacent to the pixel array unit 201.
  • the DAC 203 is arranged adjacent to the constant current source load 205 and the comparator 206.
  • a timing control circuit 204 is arranged adjacent to the counter / latch circuit 207 and the horizontal transfer scanning circuit 208.
  • a DC supply circuit 209 is arranged adjacent to the pixel array unit 201. Further, a signal processing circuit 210 is arranged adjacent to the pixel array unit 201, the constant current source load 205, the comparator 206, the counter / latch circuit 207, and the horizontal transfer scanning circuit 208.
  • Each circuit constituting the solid-state imaging device according to the first embodiment is configured by connecting semiconductor devices such as photodiodes, MOSFETs, bipolar transistors, resistance elements, and capacitive elements formed on a semiconductor substrate with multilayer wiring.
  • semiconductor devices such as photodiodes, MOSFETs, bipolar transistors, resistance elements, and capacitive elements formed on a semiconductor substrate with multilayer wiring.
  • a general CMOS process can be adopted as a method for forming each circuit constituting the solid-state image sensor according to the first embodiment on the semiconductor substrate.
  • an n-type well 2 and a p-type well 3 are provided on the p-type semiconductor substrate 1.
  • An STI region 4 is provided in a part of the upper part of the p-type well 3, and the active regions A1 and A2 are respectively partitioned by the STI region 4.
  • an n + type source region 11 and an n + type drain region 12 of the MOSFET are provided above the p-type well 3.
  • a p + type back gate terminal 13 is provided above the p type well 3.
  • Svg gate input conversion noise
  • the applied structure is shown in FIGS. 9 and 10.
  • the column-parallel AD conversion circuit one AD conversion circuit (column circuit) is arranged for each column of the pixel array unit 110. Therefore, as shown in FIG. 1, the column circuits are arranged at arbitrary intervals (column circuits) in the horizontal direction. It is repeatedly arranged at the column pitch).
  • the differential input transistors constituting the comparator are also repeatedly arranged at equal intervals.
  • the p-type well 3 needs to be electrically separated between the columns.
  • N-type well 2 is provided in order to electrically separate the p-type well 3 between columns.
  • an n-type well 17 is provided directly below the STI region 4 between the p-type wells 3 between the columns.
  • the n-type well 17 can usually be formed by ion-implanting n-type impurities into the semiconductor substrate 1 and then performing heat treatment to activate the impurities, but the width W1 of the n-type well 17 is reduced to a certain width or less. If this happens, the pressure resistance between the p-type wells 3 adjacent to the n-type well 17 will drop sharply. When the withstand voltage characteristic deteriorates, a leak current flows between the column circuits, which causes a defective operation. In order to keep the withstand voltage above a certain level, it is necessary to increase the impurity concentration of the n-type well 17. However, since high-temperature heat treatment is performed after ion implantation, it is difficult to form an n-type well 17 that is deep from the Si substrate surface, has a high impurity concentration, and has a narrow width W1.
  • Patent Document 3 discloses a technique for improving the withstand voltage between wells between adjacent MOSFETs in a layout in which MOSFETs are repeatedly arranged at narrow intervals.
  • this technique as shown in FIG. 11, with respect to the n-type well 2 that separates the p-type semiconductor substrate 1 and the p-type well (back gate) 3, the joint surface between the p-type well 3 and the n-type well 2 is formed. It is formed so as to be shallower than the bottom surface of the STI region 4.
  • the distance between the adjacent p-type wells 3 (shown by the broken line arrow) can be increased, so that the element separation withstand voltage can be improved as compared with the structures shown in FIGS. 9 and 10. Can be done.
  • the STI region 4 becomes a wall, and it becomes impossible to secure a path for pulling out the p-type well 3 constituting the back gate to the upper surface of the semiconductor substrate 1.
  • the depth of the STI region 4x that is a wall is formed to be shallower than that of the surrounding STI region 4, so that the shallow STI region 4x A structure is adopted in which the back gate is taken out on the upper surface of the semiconductor substrate 1 by passing under the bottom.
  • the semiconductor device according to the first embodiment includes a semiconductor substrate 1 made of a p-type Si substrate and an n-type well which is an n-type semiconductor layer provided on the semiconductor substrate 1. 2 and a p-type well 3 which is a p-type semiconductor layer provided on the n-type well 2 are provided.
  • the n-type well 2 has a function of separating the semiconductor substrate 1 and the p-type well 3.
  • the p-type well 3 functions as a back gate region.
  • the p-type well 3 is provided with an n + type source region 11 and an n + type drain region 12 separated from each other.
  • a gate electrode 5 is provided on the channel region sandwiched between the source region 11 and the drain region 12 via a gate insulating film (not shown).
  • a gate insulating film not shown.
  • the material of the gate electrode 5 polysilicon having a high impurity concentration can be used, and a metal material other than polysilicon can also be used.
  • the p-type well 3 is provided with a p + type back gate terminal 13 separated from the source region 11 and the drain region 12.
  • the back gate terminal 13 is composed of a well tap region having a higher impurity concentration than the p-type well 3.
  • the STI region 4 is not interposed between the back gate terminal 13 and the source region 11 and the drain region 12. That is, the back gate terminal 13, the source region 11, and the drain region 12 are provided in the same active region A0 surrounded by the STI region 4.
  • the joint surface between the n-type well 2 and the p-type well 3 is provided so as to be shallower than the STI region 4 and deeper than the source region 11 and the drain region 12. Therefore, the electrical withstand voltage between the MOSFETs constituting the adjacent comparator 151 is secured.
  • metal contacts 31 and 32 are arranged on the source region 11.
  • Metal contacts 33 and 34 are arranged on the drain region 12.
  • a metal contact 35 is arranged on the gate electrode 5.
  • Metal contacts 36 and 37 are arranged on the back gate terminal 13.
  • the back gate terminal 13 is electrically common (same potential) as the gate electrode 5. Although not shown, the back gate terminal 13 is electrically connected to the gate electrode 5 via metal contacts such as metal contacts 35, 36, 37 and multi-layer wiring. As shown in FIG. 14, the source region 11, the drain region 12, and the upper portions of the back gate terminal 13 are provided with the VDD layers 21, 22, and 23, respectively.
  • the material of the silicide layers 21, 22, and 23 is, for example, cobalt (Co) silicide or nickel (Ni) silicide. In the plane layout of FIG. 13, the silicide layers 21, 22, 23 and the multilayer wiring shown in FIG. 14 are omitted.
  • a separation film (0045 block layer) 6 is provided on the p-type well 3 sandwiched between the source region 11 and the back gate terminal 13.
  • the separation membrane 6 has a function of preventing the formation of a silicide layer directly under the separation membrane 6 and preventing a short circuit between the source region 11 and the drain region 12 and the back gate terminal 13 via the silicide layer.
  • a silicide process for reducing the contact resistance between the semiconductor substrate 1 made of Si and the metal contacts 31 to 36 is generally used, but when this process is used, it is made of Si not covered by the STI region 4. With respect to the surface of the semiconductor substrate 1, all the regions where the separation layer 6 for preventing the formation of VDD is not arranged are silicidized.
  • the separation membrane 6 is made of the same material as the gate electrode 5, for example, and can be formed at the same time as the gate electrode 5.
  • the gate electrode 5 is often a conductor such as polycrystalline Si, and the separation membrane 6 is made of a metal contact, wiring, etc. (not shown) so that the potential does not fluctuate. It is preferable to electrically connect to the semiconductor substrate 1 or the like to fix the potential.
  • the separation membrane 6 may have a laminated structure of a layer of the same material as the gate electrode 5 and a gate insulating film (not shown).
  • the separation membrane 6 can also use an insulating material such as a nitride or a silicon (Si) -based oxide such as silicon dioxide (SiO 2).
  • an insulating material such as a nitride or a silicon (Si) -based oxide such as silicon dioxide (SiO 2).
  • the source region 11 and drain region 12 of the MOSFET and the back gate terminal 13 are provided in the same active region A0 surrounded by the STI region 4. Therefore, as compared with the structure shown in FIG. 12, the back gate terminal 13 can be provided without partially changing the depth of the STI region 4, which facilitates the manufacturing process. Further, the semiconductor device according to the first embodiment has a structure suitable for miniaturization of a circuit because a withstand voltage between wells between adjacent MOSFETs can be secured. Therefore, it is possible to achieve both low noise and miniaturization of the circuit without increasing the manufacturing cost.
  • the semiconductor device according to the first embodiment is suitable for a MOSFET as a noise source among the MOSFETs constituting the solid-state image sensor.
  • the semiconductor device according to the first embodiment by applying the semiconductor device according to the first embodiment to the differential input transistors T21 and T22 of the comparator 151 shown in FIG. 4, the random noise of the peripheral circuit is reduced by about 13% with respect to the conventional structure. I confirmed that I could do it.
  • the semiconductor device according to the first modification of the first embodiment is different from the semiconductor device according to the first embodiment shown in FIG. 14 in that the semiconductor device is composed of pMOS.
  • the semiconductor device according to the first modification of the first embodiment includes a p-type semiconductor substrate 1 and an n-type well 7 which is an n-type semiconductor layer provided on the semiconductor substrate 1.
  • a p + type source region 41 and a p + type drain region 42 are provided above the n-type well 7.
  • a gate electrode 5 is provided on the channel region sandwiched between the source region 41 and the drain region 42 via a gate insulating film (not shown).
  • the joint surface between the n-type well 7 and the semiconductor substrate 1 is shallower than the STI region 4 and deeper than the source region 41 and the drain region 42.
  • n + type back gate terminal 43 is provided above the n-type well 7 so as to be separated from the source region 41 and the drain region 42.
  • the back gate terminal 43 is composed of a well tap region having a higher impurity concentration than the n-type well 7.
  • the back gate terminal 43 is electrically connected to the gate electrode 5 and has the same potential.
  • the STI region 4 does not intervene between the back gate terminal 43 and the source region 41 and the drain region 42. That is, the back gate terminal 43, the source region 41, and the drain region 42 are provided in the same active region A0 surrounded by the STI region 4.
  • a separation membrane 6 is provided on the n-type well 7 between the back gate terminal 43 and the source region 41 and the drain region 42.
  • Silicide layers 21, 22, and 23 are provided above the back gate terminal 43, the source region 41, and the drain region 42, respectively. When the salicide step is not carried out in the CMOS process, the silicide layers 21, 22, and 23 may not be provided. Since other configurations of the semiconductor device according to the first modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
  • the semiconductor device even when the semiconductor device is composed of pMOS, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment. ..
  • the semiconductor device according to the second modification of the first embodiment is an n-type semiconductor device provided between the p-type semiconductor substrate 1 and the n-type well (backgate region) 7. It differs from the semiconductor device according to the first embodiment shown in FIG. 14 in that it further includes an n-type well 8 which is a semiconductor layer and a p-type well 9 which is a p-type semiconductor layer.
  • the joint surface between the n-type well 7 and the p-type well 9 is provided at a position shallower than the STI region 4 and deeper than the source region 11 and the drain region 12.
  • a circuit that produces noise may be surrounded by wells to ensure strong electrical separation so that signal interference does not occur between the circuits formed on the semiconductor substrate 1.
  • the n-type well 8 electrically separates the semiconductor substrate 1 and the n-type well 7.
  • the p-type well 9 electrically separates the n-type well 8 and the n-type well 7. Since other configurations of the semiconductor device according to the second modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
  • An n-type semiconductor substrate may be used instead of the p-type semiconductor substrate 1.
  • a p-type well, an n-type well, and a p-type well are provided on an n-type semiconductor substrate, and an n + type source region and n + are provided in the p-type well (back gate region).
  • a mold drain region and a p + type backgate terminal may be provided.
  • a p-type well and an n-type well (back gate region) are provided on the n-type semiconductor substrate, and the p + type source region, p + type drain region, and n are provided in the n-type well (back gate region).
  • a + type back gate terminal may be provided.
  • the semiconductor device according to the third modification of the first embodiment does not have a well-tap region (diffusion layer) having a high impurity concentration constituting the back gate terminal 13a, as shown in FIG. It is different from the semiconductor device according to the first embodiment.
  • the back gate terminal 13a sandwiches the p-type well 3 directly under the separation membrane 6 together with the source region 11. It is composed of a part. Since other configurations of the semiconductor device according to the third modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
  • the semiconductor device instead of forming the back gate terminal 13a with a well tap region (diffusion layer) having a high impurity concentration for lowering the resistance, the p-type well 3 Even when it is composed of a part of the above, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment. Further, since there is no well-tapped region (diffusion layer) having a high impurity concentration opposite to that of the source region 11 in the vicinity of the source region 11, the bonding capacitance of the source region 11 can be reduced.
  • the semiconductor device according to the fourth modification of the first embodiment does not have a well-tap region (diffusion layer) having a high impurity concentration constituting the back gate terminal 43a, as shown in FIG. It is different from the semiconductor device according to the first modification of the first embodiment. Further, the semiconductor device according to the fourth modification of the first embodiment is different from the semiconductor device according to the third modification of the first embodiment shown in FIG. 17 in that the semiconductor device is composed of pMOS.
  • the back gate terminal 43a sandwiches the n-type well 7 directly under the separation membrane 6 together with the source region 41, and the n-type well 7 It is composed of a part. Since other configurations of the semiconductor device according to the fourth modification of the first embodiment are the same as those of the semiconductor device according to the first modification of the first embodiment shown in FIG. 15, duplicated description will be omitted.
  • the semiconductor device is composed of pMOS, and the back gate terminal 43a is provided with a well-tap region (diffusion layer) having a high impurity concentration for lowering the resistance.
  • a well-tap region diffusion layer
  • the semiconductor device is composed of pMOS, and the back gate terminal 43a is provided with a well-tap region (diffusion layer) having a high impurity concentration for lowering the resistance.
  • FIG. 19 the planar patterns of the convex portions 4a and 4b directly below the separation membrane 6 are schematically shown by broken lines.
  • FIG. 20 shows a cross section seen from the direction of AA passing over the convex portion 4a of FIG.
  • FIG. 21 shows a cross section seen from the BB direction passing between the convex portions 4a and 4b of FIG. 20.
  • the depths of the convex portions 4a and 4b are equivalent to the depths of the surrounding STI regions 4. Since other configurations of the semiconductor device according to the fifth modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIGS. 13 and 14, duplicate description will be omitted.
  • the semiconductor device According to the semiconductor device according to the fifth modification of the first embodiment, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment. Further, the STI region 4 has convex portions 4a and 4b extending between the back gate terminal 13 and the source region 11 of the MOSFET on a plane pattern, so that the p-type is sandwiched between the source region 11 and the back gate terminal 13. Since the well 3 is narrowed, the junction capacity of the source region 11 can be reduced.
  • the semiconductor device is composed of nMOS is illustrated, but the semiconductor device may be configured by pMOS.
  • the semiconductor device according to the sixth modification of the first embodiment has no separation membrane on the p-type well 3 between the back gate terminal 13 and the source region 11 of the MOSFET. It is different from the semiconductor device according to the first embodiment shown in.
  • the silicide layer is not provided above the back gate terminal 13, the source region 11, and the drain region 12. Since other configurations of the semiconductor device according to the sixth modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIG. 14, duplicate description will be omitted.
  • the back gate terminal 13 and the source region 11 of the MOSFET are electrically connected. It is not necessary to provide a separation membrane for separation. Even in this case, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment.
  • the semiconductor device according to the seventh modification of the first embodiment has no separation film on the n-type well 7 between the back gate terminal 43 and the source region 41 of the MOSFET. It is different from the semiconductor device according to the first modification of the first embodiment shown in. Further, the semiconductor device according to the seventh modification of the first embodiment is different from the semiconductor device according to the sixth modification of the first embodiment shown in FIG. 22 in that the semiconductor device is composed of pMOS.
  • the silicide layer is not provided above the back gate terminal 43, the source region 41, and the drain region 42. Since other configurations of the semiconductor device according to the seventh modification of the first embodiment are the same as those of the semiconductor device according to the first modification of the first embodiment shown in FIG. 15, duplicated description will be omitted.
  • the back gate terminal 43 and the source region 41 of the MOSFET are electrically connected. It is not necessary to provide a separation membrane for separation. Even in this case, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment.
  • the semiconductor device constitutes a planar MOSFET
  • the semiconductor device according to the present technology is not limited to the planar MOSFET.
  • the semiconductor device is a fin-type MOSFET (hereinafter, also referred to as “FinFET”)
  • FinFET fin-type MOSFET
  • an n-channel FinFET will be illustrated.
  • FIG. 24 is a planar pattern of the semiconductor device according to the second embodiment, the cross section of FIG. 24 seen from the AA direction corresponds to FIG. 25, and the cross section of FIG. 24 seen from the BB direction is FIG. 26.
  • the semiconductor device according to the second embodiment is provided on the p-type semiconductor substrate 1, the n-type well 2 provided on the semiconductor substrate 1, and the n-type well 2. It is provided with a p-type well 3.
  • FIG. 25 a case where the upper surface of the p-type well 3 is located above the upper surface of the STI region 4 is illustrated.
  • the joint surface between the n-type well 2 and the p-type well 3 is provided so as to be shallower than the STI region 4 and deeper than the source region 11 and the drain region 12.
  • the p-type well 3 is provided with an n + type source region 11 and an n + type drain region 12 separated from each other.
  • a gate electrode 5 is provided via a gate insulating film (not shown) so as to surround the channel region sandwiched between the source region 11 and the drain region 12.
  • the cross-sectional shape of the gate electrode 5 may be an inverted U shape that surrounds the upper surface and both side surfaces of the channel region.
  • the channel region surrounded by the gate electrode 5 has a fin shape.
  • the shape of the gate electrode 5 is not limited to this.
  • the gate electrode 5 may have a cross-sectional shape such as an M-shape or a ⁇ -shape that divides a plurality of fin-shaped channel regions.
  • the p-type well 3 is provided with a p + type back gate terminal 13 separated from the source region 11 and the drain region 12.
  • the back gate terminal 13 is composed of a well tap region (diffusion layer) having a higher impurity concentration than the p-type well 3.
  • the back gate terminal may be formed by a part of the p-type well 3 without the well tap region (diffusion layer) constituting the back gate terminal 13.
  • Silicide layers 21, 22, and 23 are provided above the source region 11, the drain region 12, and the back gate terminal 13, respectively. It should be noted that the silicide layers 21, 22, and 23 may not be provided.
  • a separation membrane 6 is provided on the p-type well 3 sandwiched between the source region 11 and the drain region 12 and the back gate terminal 13.
  • the shape of the separation membrane 6 may be the same as the shape of the gate electrode 5, for example.
  • the cross-sectional shape of the separation membrane 6 may be an inverted U shape surrounding the upper surface and both side surfaces of the fin-shaped p-shaped well 3.
  • the separation membrane 6 may be made of a material different from that of the gate electrode 5, and may be made of, for example, an insulating material. Further, when the silicide layers 21, 22, and 23 are not provided, the separation membrane 6 may be omitted.
  • a fin-shaped p-type well 3 is interposed between the back gate terminal 13 and the source region 11, and is not electrically separated by the STI region 4. That is, the back gate terminal 13, the source region 11, and the drain region 12 are provided in the same active region A0 surrounded by the STI region 4.
  • the back gate terminal 13 is electrically connected to the gate electrode 5 via a metal contact (not shown) and multi-layer wiring, and has the same potential as the gate electrode 5.
  • the semiconductor device even when the semiconductor device is composed of FinFETs, it is possible to realize low noise and miniaturization of the circuit as in the first embodiment.
  • the semiconductor device according to the modified example of the second embodiment is the second embodiment shown in FIGS. 24 to 26 in that the semiconductor device is composed of a p-channel type FinFET. It is different from the semiconductor device according to the form.
  • the p-type semiconductor substrate 1 is provided with the n-type well 7.
  • the joint surface between the n-type well 7 and the semiconductor substrate 1 is shallower than the STI region 4 and deeper than the source region 41 and the drain region 42.
  • a p + type source region 41 and a p + type drain region 42 are provided above the n-type well 7.
  • a gate electrode 5 is provided via a gate insulating film (not shown) so as to surround the channel region sandwiched between the source region 41 and the drain region 42.
  • a back gate terminal 43 composed of an n + type well tap region is provided above the n-type well 7 so as to be separated from the source region 41 and the drain region 42.
  • the back gate terminal 43 is electrically connected to the gate electrode 5 and has the same potential.
  • a fin-shaped n-shaped well 7 is interposed between the back gate terminal 43 and the source region 41. That is, the back gate terminal 43, the source region 41, and the drain region 42 are provided in the same active region A0 surrounded by the STI region 4.
  • a separation membrane 6 is provided on the n-type well 7 between the back gate terminal 43 and the source region 41 and the drain region 42.
  • Silicide layers 21, 22, and 23 are provided above the back gate terminal 43, the source region 41, and the drain region 42, respectively. Since other configurations of the semiconductor device according to the modified example of the second embodiment are the same as those of the semiconductor device according to the second embodiment shown in FIGS. 24 to 26, duplicate description will be omitted.
  • the semiconductor device even when the semiconductor device is composed of a p-channel type FinFET, it is possible to realize low noise and miniaturization of the circuit as in the second embodiment. It becomes.
  • the semiconductor device according to the third embodiment is composed of nMOS.
  • An n-type well 2 and a p-type well (back gate region) 3 are provided on the p-type semiconductor substrate 1.
  • An embedded insulating film (BOX layer) 14 is provided on the upper surface of a part of the p-type well 3.
  • the joint surface between the n-type well 2 and the p-type well 3 is provided so as to be shallower than the STI region 4 and deeper than the source region 11 and the drain region 12.
  • a thin p-type semiconductor layer (SOI layer) 15 made of Si is provided on the embedded insulating film 14.
  • the embedded insulating film 14 is electrically separated from the p-type well 3 and the SOI layer 15 constituting the back gate region.
  • the SOI layer 15 is provided with an n + type source region 11 and an n + type drain region 12 separated from each other.
  • a gate electrode 5 is provided on a channel region sandwiched between a source region 11 and a drain region 12 via a gate insulating film (not shown).
  • a p + type back gate terminal 13 is provided on the upper portion of the p-type well 3 which is not covered with the embedded insulating film 14.
  • Silicide layers 21, 22, and 23 are provided on the upper surfaces of the source region 11, the drain region 12, and the back gate terminal 13, respectively.
  • a sidewall (not shown) is formed on the side wall of the source region 11 and the embedded insulating film 14, and the source region 11 and the back gate terminal 13 are electrically separated by this sidewall.
  • the back gate terminal 13 is composed of a well tap region (diffusion layer) having a higher impurity concentration than the p-type well 3.
  • the well tap region (diffusion layer) constituting the back gate terminal 13 is formed by removing a part of the embedded insulating film 14, implanting ions into the exposed upper surface of the p-type well 3, and then performing heat treatment. It is possible.
  • the back gate terminal may be formed by a part of the p-type well 3 without the well tap region (diffusion layer) constituting the back gate terminal 13.
  • the STI region 4 does not intervene between the back gate terminal 13 and the source region 11. That is, the back gate terminal 13, the source region 11, and the drain region 12 are provided in the same active region A0 surrounded by the STI region 4.
  • the back gate terminal 13 is electrically connected to the gate electrode 5 via a metal contact (not shown) and multi-layer wiring, and has the same potential as the gate electrode 5.
  • the semiconductor device even when the semiconductor device is composed of the SOI type MOSFET, it is possible to realize low noise and miniaturization of the circuit as in the first and second embodiments. ..
  • the semiconductor device according to the first modification of the third embodiment is common to the semiconductor device according to the third embodiment shown in FIG. 29 in that the semiconductor device is composed of nMOS. ..
  • the semiconductor device according to the first modification of the third embodiment is different from the semiconductor device according to the third embodiment shown in FIG. 29 in that the n-type well 7 constitutes a back gate region.
  • the embedded insulating film 14 is electrically separated from the n-type well 7 and the SOI layer 15 constituting the back gate region. Therefore, the polarity of the back gate region does not depend on the polarity of the SOI layer 15.
  • the back gate terminal 43 is composed of an n + type well tap region (diffusion layer) having a higher impurity concentration than the n type well 7. Since other configurations of the semiconductor device according to the first modification of the third embodiment are the same as those of the semiconductor device according to the third embodiment shown in FIG. 29, duplicate description will be omitted.
  • the semiconductor device even when the n-type well 7 constitutes the back gate region, it is possible to realize low noise and miniaturization of the circuit as in the third embodiment. It becomes.
  • the semiconductor device according to the second modification of the third embodiment is different from the semiconductor device according to the third embodiment shown in FIG. 29 in that the semiconductor device is composed of pMOS.
  • the embedded insulating film 14 is electrically separated from the p-type well 3 and the n-type SOI layer 16 constituting the back gate region. Therefore, the polarity of the SOI layer 16 does not depend on the polarity of the back gate region.
  • the SOI layer 16 is provided with a p + type source region 41 and a p + type drain region 42. Since other configurations of the semiconductor device according to the second modification of the third embodiment are the same as those of the semiconductor device according to the third embodiment shown in FIG. 29, duplicate description will be omitted.
  • the semiconductor device even when the semiconductor device is composed of pMOS, it is possible to realize low noise and miniaturization of the circuit as in the third embodiment. ..
  • the semiconductor device according to the third modification of the third embodiment has a point that the semiconductor device is composed of pMOS and a point that the n-type well 7 constitutes a back gate region. It is different from the semiconductor device according to the third embodiment shown in.
  • the embedded insulating film 14 is electrically separated from the n-type well 7 and the n-type SOI layer 16 constituting the back gate region.
  • the SOI layer 16 is provided with a p + type source region 41 and a p + type drain region 42.
  • the back gate terminal 43 is composed of an n + type well tap region (diffusion layer) having a higher impurity concentration than the n type well 7. Since other configurations of the semiconductor device according to the third modification of the third embodiment are the same as those of the semiconductor device according to the third embodiment shown in FIG. 29, duplicate description will be omitted.
  • the semiconductor device even when the semiconductor device is composed of pMOS and the n-type well 7 constitutes the back gate region, the noise is low as in the third embodiment. It is possible to realize miniaturization and miniaturization of circuits.
  • the solid-state image sensor according to the fourth embodiment includes a pixel array unit 322 in which pixels 321 are arranged in a two-dimensional array on a semiconductor substrate 311 using, for example, silicon (Si) as a semiconductor. ..
  • the pixel array unit 322 has a time code transfer unit 323 that transfers the time code generated by the time code generation unit 326 to each pixel 321.
  • a pixel drive circuit 324, a DAC (D / A Converter) 325, a time code generator 326, a vertical drive circuit 327, an output unit 328, and a timing generation circuit 329 are arranged around the pixel array unit 322 on the semiconductor substrate 311. ing.
  • each of the pixels 321 arranged in a two-dimensional array is provided with a pixel circuit 341 and an ADC 342.
  • the pixel 321 generates a charge signal according to the amount of light received by a light receiving element (for example, a photodiode) in the pixel, converts it into a digital pixel signal SIG, and outputs it.
  • a light receiving element for example, a photodiode
  • the pixel drive circuit 324 drives the pixel circuit 341 in the pixel 321.
  • the DAC 325 generates a reference signal (reference voltage signal) REF, which is a slope signal whose level (voltage) monotonically decreases with the passage of time, and supplies it to each pixel 321.
  • the time code generation unit 326 generates a time code used when each pixel 321 converts an analog pixel signal SIG into a digital signal (AD conversion), and supplies the time code to the corresponding time code transfer unit 323.
  • a plurality of time code generation units 326 are provided for the pixel array unit 322. In the pixel array unit 322, as many time code transfer units 323 as the number corresponding to the time code generation unit 326 are provided. That is, the time code generation unit 326 and the time code transfer unit 323 that transfers the time code generated by the time code generation unit 326 have a one-to-one correspondence.
  • the vertical drive circuit 327 controls the output unit 328 to output the digital pixel signal SIG generated in the pixel 321 to the output unit 328 in a predetermined order based on the timing signal supplied from the timing generation circuit 329.
  • the digital pixel signal SIG output from the pixel 321 is output from the output unit 328 to the outside of the solid-state image sensor.
  • the output unit 328 performs predetermined digital signal processing such as black level correction processing for correcting the black level and correlation double sampling (CDS) processing as necessary, and then outputs the digital signal to the outside.
  • the timing generation circuit 329 is configured by a timing generator or the like that generates various timing signals, and supplies the generated various timing signals to the pixel drive circuit 324, the DAC 325, the vertical drive circuit 327, or the like.
  • the pixel circuit 341 outputs a charge signal corresponding to the amount of received light to the ADC 342 as an analog pixel signal SIG.
  • the ADC 342 converts the analog pixel signal SIG supplied from the pixel circuit 341 into a digital signal.
  • the ADC 342 is composed of a comparison circuit 351 and a data storage unit 352.
  • the comparison circuit 351 compares the reference signal REF supplied from the DAC 325 with the pixel signal SIG, and outputs an output signal VCO as a comparison result signal representing the comparison result.
  • the comparison circuit 351 inverts the output signal VCO when the reference signal REF and the pixel signal SIG have the same voltage.
  • the comparison circuit 351 is composed of a differential input circuit 361, a voltage conversion circuit 362, and a positive feedback circuit (PFB) 363.
  • the vertical drive circuit 327 indicates that the operation is a pixel signal writing operation and that the pixel signal reading operation is RD.
  • the signal and the WORD signal that controls the read timing of the pixel 321 during the read operation of the pixel signal are supplied from the vertical drive circuit 327.
  • the time code generated by the time code generation unit 326 is also supplied via the time code transfer unit 323.
  • the data storage unit 352 is composed of a latch control circuit 371 that controls a time code writing operation and a reading operation based on a WR signal and an RD signal, and a latch storage unit 372 that stores the time code.
  • the latch control circuit 371 is updated every unit time supplied from the time code transfer unit 323 while the high (H) output signal VCO is input from the comparison circuit 351.
  • the time code is stored in the latch storage unit 372.
  • the latch storage unit 372 holds the time code stored in the latch storage unit 372.
  • the time code stored in the latch storage unit 372 represents the time when the pixel signal SIG and the reference signal REF become equal, and data indicating that the pixel signal SIG was the reference voltage at that time, that is, digitization. Represents the light intensity value.
  • the operation of the pixel 321 is changed from the writing operation to the reading operation.
  • the latch control circuit 371 is based on the WORD signal that controls the reading timing, and when the pixel 321 reaches its own reading timing, the time code stored in the latch storage unit 372 ( The digital pixel signal SIG) is output to the time code transfer unit 323.
  • the time code transfer unit 323 sequentially transfers the supplied time code in the column direction (vertical direction) and supplies it to the output unit 328.
  • the differential input circuit 361 compares the pixel signal SIG output from the pixel circuit 341 in the pixel 321 with the reference signal REF output from the DAC 325, and determines when the pixel signal SIG is higher than the reference signal REF. Output a signal (current).
  • the differential input circuit 361 serves as a constant current source for supplying transistors 381 and 382 as differential pairs, transistors 383 and 384 constituting the current mirror, and a current IB corresponding to the input bias current Vb.
  • the transistor 385 and the transistor 386 that outputs the output signal HVO of the differential input circuit 361 are configured.
  • the transistors 381, 382, 385 are composed of nMOS transistors, and the transistors 383, 384, 386 are composed of pMOS transistors.
  • the reference signal REF output from the DAC 325 is input to the gate of the transistor 381, and the pixel output from the pixel circuit 341 in the pixel 321 is input to the gate of the transistor 382.
  • the signal SIG is input.
  • the source of the transistors 381 and 382 is connected to the drain of the transistor 385, and the source of the transistor 385 is connected to a predetermined voltage VSS.
  • the drain of the transistor 381 is connected to the gate of the transistors 383 and 384 and the drain of the transistor 383 constituting the current mirror circuit, and the drain of the transistor 382 is connected to the drain of the transistor 384 and the gate of the transistor 386.
  • the source of the transistors 383,384,386 is connected to the first power supply voltage VDD1.
  • the voltage conversion circuit 362 is composed of, for example, an nMOS type transistor 391.
  • the drain of the transistor 391 is connected to the drain of the transistor 386 of the differential input circuit 361, the source of the transistor 391 is connected to a predetermined connection point in the positive feedback circuit 363, and the gate of the transistor 386 is connected to the bias voltage VBIAS. It is connected.
  • the transistors 381 to 386 constituting the differential input circuit 361 are circuits that operate at a high voltage up to the first power supply voltage VDD1, and the positive feedback circuit 363 has a second power supply voltage VDD2 lower than the first power supply voltage VDD1. It is a working circuit.
  • the voltage conversion circuit 362 converts the output signal HVO input from the differential input circuit 361 into a low voltage signal (conversion signal) LVI in which the positive feedback circuit 363 can operate, and supplies the output signal HVO to the positive feedback circuit 363.
  • the bias voltage VBIAS may be any voltage that converts the transistors 401 to 405 of the positive feedback circuit 363 that operates at a constant voltage into a voltage that does not destroy them.
  • the bias voltage VBIAS can be the same voltage as the second power supply voltage VDD2 of the positive feedback circuit 363.
  • the positive feedback circuit 363 reverses when the pixel signal SIG is higher than the reference signal REF based on the conversion signal LVI in which the output signal HVO from the differential input circuit 361 is converted into a signal corresponding to the second power supply voltage VDD2. Outputs the comparison result signal. Further, the positive feedback circuit 363 speeds up the transition speed when the output signal VCO output as the comparison result signal is inverted.
  • the positive feedback circuit 363 is composed of five transistors 401 to 405.
  • the transistors 401, 402, and 404 are composed of pMOS transistors
  • the transistors 403 and 405 are composed of nMOS transistors.
  • the source of the transistor 391, which is the output end of the voltage conversion circuit 362, is connected to the drain of the transistors 402 and 403 and the gate of the transistors 404 and 405.
  • the source of the transistors 401 and 404 is connected to the second power supply voltage VDD2, the drain of the transistor 401 is connected to the source of the transistor 402, and the gate of the transistor 402 is the output end of the positive feedback circuit 363. It is connected to the drain of.
  • the sources of transistors 403,405 are connected to a predetermined voltage VSS.
  • the initialization signal INI is supplied to the gates of the transistors 401 and 403.
  • the transistors 404 and 405 form an inverter circuit, and the connection point between the drains thereof is an output end at which the comparison circuit 351 outputs an output signal VCO.
  • the pixel circuit 341 is composed of a photodiode (PD) 421 as a photoelectric conversion element, an emission transistor 422, a transfer transistor 423, a reset transistor 424, and a floating diffusion layer (FD) 425.
  • PD photodiode
  • FD floating diffusion layer
  • the discharge transistor 422 is used when adjusting the exposure period. Specifically, when the emission transistor 422 is turned on when the exposure period is desired to be started at an arbitrary timing, the electric charge accumulated in the photodiode 421 up to that point is discharged, so that the emission transistor 422 is turned off. After that, the exposure period will start.
  • the transfer transistor 423 transfers the electric charge generated by the photodiode 421 to the FD425.
  • the reset transistor 424 resets the charge held in the FD425.
  • the FD425 is connected to the gate of the transistor 382 of the differential input circuit 361.
  • the transistor 382 of the differential input circuit 361 also functions as an amplification transistor of the pixel circuit 341.
  • the source of the reset transistor 424 is connected to the gate of the transistor 382 of the differential input circuit 361 and the drain of the FD425, and the drain of the reset transistor 424 is connected to the drain of the transistor 382. Therefore, there is no fixed reset voltage to reset the charge on the FD425. This is because the reset voltage for resetting the FD425 can be arbitrarily set by using the reference signal REF by controlling the circuit state of the differential input circuit 361.
  • the solid-state image sensor according to the fourth embodiment as shown in FIG. 36, two semiconductor chips of the upper substrate 301 and the lower substrate 302 are overlapped, and one of the wirings of the upper and lower chips is provided by TSV (through-silicon via). It is composed of a laminated image sensor whose parts are electrically connected.
  • the pixel circuit 303 is mounted on the upper substrate 301, and peripheral circuits 304 other than the pixel circuit 303 are mounted on the lower substrate 302.
  • the broken line region 300 indicates the TSV connection location. That is, the source of the reset transistor 424 and the gate of the transistor 382 of the differential input circuit 361 are TSV-connected. The drain of the reset transistor 424 is TSV-connected to the drain of the transistor 382.
  • the differential input circuit 361 shown in FIG. 35 becomes a noise source of random noise.
  • differential input transistors 381 and 382 composed of nMOS.
  • the active regions A3 and A4 of the differential input transistors 381 and 382 are partitioned by the STI region 4 and electrically separated from each other.
  • An n-type well 2 and a p-type well 3 are provided on the p-type semiconductor substrate 1.
  • the differential input transistor 381 has a multi-finger structure in which a plurality of source regions 11a and 11b are arranged.
  • the differential input transistor 381 has n + type source regions 11a and 11b, n + type drain regions 12a, and p + type back gate terminals 13a provided above the p-type well 3.
  • a gate electrode 5a is provided on the channel region sandwiched between the source region 11a and the drain region 12a via a gate insulating film (not shown).
  • a gate electrode 5b is provided on the channel region sandwiched between the source region 11b and the drain region 12a via a gate insulating film (not shown).
  • a separation membrane 6a is provided on the p-type well 3 sandwiched between the source region 11b and the back gate terminal 13a.
  • Silicide layers 21a, 21b, 22a, and 23a are provided above the source regions 11a and 11b, the drain region 12a, and the back gate terminal 13a, respectively.
  • the differential input transistor 382 has a multi-finger structure in which a plurality of source regions 11c and 11d are arranged.
  • the differential input transistor 382 has n + type source regions 11c and 11d, n + type drain regions 12b, and p + type back gate terminals 13b provided above the p-type well 3.
  • a gate electrode 5c is provided on the channel region sandwiched between the source region 11c and the drain region 12b via a gate insulating film (not shown).
  • a gate electrode 5d is provided on the channel region sandwiched between the source region 11d and the drain region 12b via a gate insulating film (not shown).
  • a separation membrane 6b is provided on the p-type well 3 sandwiched between the source region 11d and the back gate terminal 13b.
  • Silicide layers 21d, 21d, 22b, and 23b are provided above the source regions 11c and 11d, the drain region 12b, and the back gate terminal 13b, respectively.
  • n-type well 7 is provided on the p-type semiconductor substrate 1.
  • the n-type well 7 corresponds to the n-type well 2 shown in FIG. 38.
  • the active load transistor 383 has a multi-finger structure in which a plurality of source regions 41a and 41b are arranged.
  • the active load transistor 383 has p + type source regions 41a and 41b, p + type drain regions 42a, and n + type backgate terminals 43a provided above the n-type well 7.
  • a gate electrode 5a is provided on the channel region sandwiched between the source region 41a and the drain region 42a via a gate insulating film (not shown).
  • a gate electrode 5b is provided on the channel region sandwiched between the source region 41b and the drain region 42a via a gate insulating film (not shown).
  • a separation membrane 6a is provided on the n-type well 7 sandwiched between the source region 41b and the back gate terminal 43a.
  • Silicide layers 21a, 21b, 22a, and 23a are provided above the source regions 41a and 41b, the drain region 42a, and the back gate terminal 43a, respectively.
  • the active load transistor 384 has a multi-finger structure in which a plurality of source regions 41c and 41d are arranged.
  • the active load transistor 384 has p + type source regions 41c and 41d, p + type drain regions 42b, and n + type backgate terminals 43b provided above the n-type well 7.
  • a gate electrode 5c is provided on the channel region sandwiched between the source region 41c and the drain region 42b via a gate insulating film (not shown).
  • a gate electrode 5d is provided on the channel region sandwiched between the source region 41d and the drain region 42b via a gate insulating film (not shown).
  • a separation membrane 6b is provided on the n-type well 7 sandwiched between the source region 41d and the back gate terminal 43b.
  • Silicide layers 21d, 21d, 22b, and 23b are provided above the source regions 41c and 41d, the drain region 42b, and the back gate terminal 43b, respectively.
  • the differential input transistors 381 and 382 and the transistor 385 as a constant current source may be arranged on the upper substrate 301.
  • the area 300 surrounded by the broken line in FIG. 41 is the TSV connection point.
  • the differential input transistors 381 and 382 and the transistor 385 as a constant current source are arranged on the upper substrate 301, the differential input transistors 381 and 382 arranged on the upper substrate 301 are shown in FIGS. 37 and 38.
  • the structure shown in the above can be applied to reduce the noise of the circuit.
  • the semiconductor device according to the present technology can be applied to MOSFETs constituting a general comparator.
  • a general comparator includes active load transistors T31 and T32 and differential input transistors T41 and T42, and has a configuration of active load transistors T31 and T32 and differential input transistors T41 and T42.
  • the semiconductor device according to this technology can be applied.
  • the comparator can be made less noisy.
  • Such a comparator is applied to an analog switch used in various sensor circuits such as light, temperature, and odor. For example, when the comparator is applied to a photodetector, as shown in FIGS.
  • the comparator 401 compares the detection signal Vd detected using the photodiode with the reference voltage Vref, and the comparator 401 compares the detection signal Vd and the reference voltage Vref. By outputting the voltage Vout according to the comparison result, it is determined whether or not light is detected.
  • the semiconductor device according to the present technology is suitable for a MOSFET that constitutes a comparator in which a detection signal Vd is weak and a high S / N ratio is required.
  • the semiconductor device according to this technology can be applied to a DA converter.
  • the semiconductor device according to the present technology shows a weight resistance type DA converter as shown in FIG. 46, which is an example of a DA converter.
  • the weighted resistance type DA converter uses an adder circuit including a comparator 402 and a resistance element Rf to create a weight of an output voltage in proportion to each bit in proportion to resistance and convert it into an analog signal.
  • the semiconductor device according to the present technology can be applied to the MOSFETs constituting the comparator 402.
  • the semiconductor devices according to this technology can be applied to MOSFETs used in various electronic devices such as various measuring instruments, AV devices, and home appliances.
  • the present technology can have the following configurations.
  • the bonding surface between the first semiconductor layer and the second semiconductor layer or the semiconductor substrate is shallower than the element separation region and deeper than the first and second main electrode regions.
  • the separation membrane is made of the same material as the gate electrode.
  • the separation membrane is made of an insulating material.
  • the element separation region has a convex portion extending between one of the first and second main electrode regions and the back gate terminal on a plane pattern.
  • the channel region has a fin shape A part of the first semiconductor layer sandwiched between one of the first and second main electrode regions and the back gate terminal has a fin shape.
  • the second semiconductor layer provided in the active region and An embedded insulating film selectively provided on a part of the second semiconductor layer, With more The first semiconductor layer and the first and second main electrode regions are provided on the embedded insulating film.
  • the back gate terminal is provided in another part of the second semiconductor layer.
  • the second semiconductor layer is the same conductive type as the first semiconductor layer.
  • the back gate terminal is of the same conductive type as the second semiconductor layer, and is composed of a well-tap region having a higher impurity concentration than the second semiconductor layer.
  • the second semiconductor layer is an opposite conductive type to the first semiconductor layer.
  • the back gate terminal is of the same conductive type as the second semiconductor layer, and is composed of a well-tap region having a higher impurity concentration than the second semiconductor layer.
  • the semiconductor device according to (11) above. (14) It is provided below the second semiconductor layer, is in contact with the second semiconductor layer, and further includes a third semiconductor layer or a semiconductor substrate that is opposite to the second semiconductor layer. The bonding surface between the second semiconductor layer and the third semiconductor layer or the semiconductor substrate is shallower than the element separation region and deeper than the first and second main electrode regions.
  • Horizontal transfer scanning circuit 140, 204 ... Timing control circuit, 150 ... ADC group, 151,206 ... Comparer (comparator), 152 ... Counter, 153 latch, 160 ... Digital-analog converter, 170 ... Amplifier circuit , 180, 210 ... Signal processing circuit, 190 ... Horizontal transfer line, 207 ... Counter / latch circuit, 209 ... DC supply circuit, 301 ... Upper board, 302 ... Lower board, 303 ... Pixel circuit, 304 ... Peripheral circuit, 311 ... Semiconductor substrate, 321 ... Pixels, 322 ... Pixel array unit, 323 ... Time code transfer unit, 324 ... Pixel drive circuit, 325 ... Pixel drive circuit, 326 ...
  • Time code generator 327 ... Vertical drive circuit, 328 ... Output unit , 329 ... Timing generation circuit, 341 ... Pixel circuit, 351 ... Comparison circuit, 352 ... Data storage unit, 361 ... Differential input circuit, 362 ... Voltage conversion circuit, 363 ... Positive feedback circuit, 370 ... Amplifier circuit, 371 ... Latch Control circuit, 372 ... Latch storage, 381 to 386, 391, 401 to 405 ... Transistor, 421 ... Photo diode, 422 ... Ejection transistor, 423 ... Transfer transistor, 424 ... Reset transistor, 501, 502 ... Comparer, A0 to A6 ... active region, C1, C2 ... sampling capacitance, D1 ...
  • photoelectric conversion element FD ... floating diffusion, IS ... constant current source, LRST ... reset control line, LSEL ... selection control line, LSGN ... signal line, LSGN ... vertical signal Line, LTRG ... Transfer control line, L VDD ... Power supply line, Rf ... Resistance element, T1 to T4, T11, T12, T21, T22, T31, T32, T41, T42 ... Transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur capable d'obtenir simultanément une réduction de bruit et une réduction de la taille sans compliquer un procédé de fabrication de celui-ci. Ce dispositif à semi-conducteur comporte : une première couche semi-conductrice ; des première et seconde régions d'électrode principale d'un type de conductivité opposé à celui de la première couche semi-conductrice ; une électrode de grille disposée sur une région de canal interposée entre les première et seconde régions d'électrode principale ; et une borne de grille arrière électriquement connectée à l'électrode de grille, les première et seconde régions d'électrode principale et la borne de grille arrière étant situées dans la même région active divisée par des régions de séparation d'éléments.
PCT/JP2020/026908 2019-08-22 2020-07-09 Dispositif à semi-conducteur et appareil électronique WO2021033454A1 (fr)

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JP2019151654A JP2021034493A (ja) 2019-08-22 2019-08-22 半導体装置及び電子機器

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WO2023181653A1 (fr) * 2022-03-24 2023-09-28 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie à semi-conducteurs et procédé de fabrication de dispositif à semi-conducteurs

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JP2002164441A (ja) * 2000-11-27 2002-06-07 Matsushita Electric Ind Co Ltd 高周波スイッチ回路装置
JP2009164364A (ja) * 2008-01-08 2009-07-23 Renesas Technology Corp 半導体装置およびその製造方法
JP2010522986A (ja) * 2007-03-28 2010-07-08 アドバンスト・アナロジック・テクノロジーズ・インコーポレイテッド 絶縁分離された集積回路装置
JP2011060876A (ja) * 2009-09-08 2011-03-24 Renesas Electronics Corp 半導体装置及びその耐圧制御方法
JP2011211213A (ja) * 2011-05-20 2011-10-20 Renesas Electronics Corp 半導体装置およびそれを用いた半導体集積回路
US20150228649A1 (en) * 2014-02-10 2015-08-13 Globalfoundries Inc. Transistor with well tap implant
JP2018014395A (ja) * 2016-07-20 2018-01-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

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Publication number Priority date Publication date Assignee Title
JP2002164441A (ja) * 2000-11-27 2002-06-07 Matsushita Electric Ind Co Ltd 高周波スイッチ回路装置
JP2010522986A (ja) * 2007-03-28 2010-07-08 アドバンスト・アナロジック・テクノロジーズ・インコーポレイテッド 絶縁分離された集積回路装置
JP2009164364A (ja) * 2008-01-08 2009-07-23 Renesas Technology Corp 半導体装置およびその製造方法
JP2011060876A (ja) * 2009-09-08 2011-03-24 Renesas Electronics Corp 半導体装置及びその耐圧制御方法
JP2011211213A (ja) * 2011-05-20 2011-10-20 Renesas Electronics Corp 半導体装置およびそれを用いた半導体集積回路
US20150228649A1 (en) * 2014-02-10 2015-08-13 Globalfoundries Inc. Transistor with well tap implant
JP2018014395A (ja) * 2016-07-20 2018-01-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023181653A1 (fr) * 2022-03-24 2023-09-28 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie à semi-conducteurs et procédé de fabrication de dispositif à semi-conducteurs

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