JP4720434B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device, and more particularly to a configuration of a solid-state imaging device including an amplifying element having a ring-shaped gate electrode in a pixel.

  Solid-state imaging devices can be roughly classified into two types: CCD (Charge Coupled Device) and CMOS (Complementary MOS) sensors.

  The CCD has a structure in which charges obtained by photoelectric conversion by a photodiode in a pixel are transferred to a reading unit through a vertical charge transfer path and a horizontal charge transfer path, and converted into a voltage there to obtain an output signal. Since the charge photoelectrically converted in all pixels is converted into a voltage by a single readout unit, the CCD has the feature that there is little signal variation between pixels and low noise. In addition, since the charges photoelectrically converted by the photodiodes can be transferred to the vertical charge transfer path simultaneously in all pixels and then sequentially transferred to read the signals, a so-called global shutter (collective shutter) operation can be easily realized. On the other hand, the CCD requires several kinds of high voltages for charge transfer and consumes a large amount of power. When the number of pixels increases, the charge transfer, particularly horizontal charge transfer, takes time and cannot operate at high speed.

  On the other hand, a CMOS sensor converts a charge obtained by photoelectric conversion with a photodiode into a voltage or current signal in the pixel, amplifies the signal with an amplifying transistor provided in the pixel, and then out of the pixel. Take the structure to output. Since the pixel units arranged in a matrix are switched and switched to read out signals, the CMOS sensor operates at a high speed, and the pixel unit and the peripheral drive circuit are composed of CMOS, so the CMOS sensor can be driven at a low voltage and is low. The power consumption is reduced, and further, signal processing circuits such as AD converters can be mounted on the same chip.

  On the other hand, a CMOS sensor amplifies a signal with an individual amplifying transistor provided in a pixel, so that signal variation between pixels is large, and noise characteristics are disadvantageous compared to a CCD. In addition, when trying to perform a global shutter operation that can be easily realized with a CCD, it is necessary to increase the number of transistors per pixel to 4 to 5 in the CMOS sensor, which increases the chip area and the cost. For this reason, a general-purpose CMOS sensor is based on a so-called line shutter (rolling shirt) operation in which a signal is read out for each line of a screen scanning line.

  Here, the relationship between the image captured by the solid-state imaging device and the shutter operation will be described. When a fast-moving subject is taken with an imaging device (CMOS sensor) that operates with a line shutter, the image is distorted. For example, when taking a circular ball 100 that moves up and down as shown in FIG. 10A with a CMOS sensor that reads out one line from the upper end of the screen, if the ball 100 moves up, the captured image is When the ball 100 moves downward as indicated by 101 in FIG. 5B and the ball 100 moves downward, the captured image extends in a vertically long ellipse as indicated by 102 in FIG. . This phenomenon is a particularly noticeable defect when a captured image is read as a still image.

  For this reason, when applying a line shutter sensor to a video / still image camera, it is possible to use a mechanical shutter together to make the light receiving time of the photodiodes the same for all pixels. There is a problem that the system becomes larger and costs increase.

  Thus, a solid-state imaging device that improves the distortion of moving images by increasing the speed of the line shutter operation of the CMOS sensor is conventionally known (see, for example, Patent Document 1). In this conventional solid-state imaging device, a unit pixel is composed of a photoelectric conversion element, a pixel signal amplification amplifier, a transistor that transfers the charge of the photoelectric conversion element to the pixel signal amplification amplifier, and a transistor that resets the photoelectric conversion element. In addition, the same number of signal holding means as the number of pixels are provided outside the imaging area in which a plurality of unit pixels are two-dimensionally arranged.

  In the signal readout operation of this conventional solid-state imaging device, signal readout and photoelectric conversion device reset are performed for each line of the screen scanning line as in a normal CMOS sensor, but these readouts are performed within the vertical blanking period. This is performed for the entire screen, and the pixel signals are accumulated in the signal holding means outside the imaging area, and then the accumulated pixel signals are read over one field (one frame) time.

  Accordingly, in the line shutter operation of a normal CMOS sensor, the reset time of the photoelectric conversion element after signal reading differs by one field (one frame) time between the uppermost one line and the lowermost one line. In the conventional solid-state imaging device described in Document 1, this time difference is about one-hundred of one field (frame) time, and the video distortion is at a level where there is no problem.

  On the other hand, as an attempt to improve the pixel structure of the CMOS sensor itself, reduce the number of transistors per pixel, and realize the global shutter function, the pixel is formed by a photoelectric conversion region, a transfer gate, and a ring-shaped gate readout transistor. A solid-state imaging device configured and realizing a global shutter function is disclosed (for example, see Patent Document 2).

JP-A-1-243675 JP 10-41493 A

  However, since the conventional solid-state imaging device described in Patent Document 1 requires the same number of signal holding means as the number of pixels outside the imaging area, it is disadvantageous for improving the pixel density and reducing the chip area.

  On the other hand, in the conventional solid-state imaging device described in Patent Document 2, since the photoelectrically converted charge is transferred to the p-well that is installed entirely under the ring-shaped gate electrode, the charge-voltage conversion efficiency is poor and the output voltage is low. There is a small bug. Further, this conventional solid-state imaging device is a CMOS sensor with a global shutter function, and since one pixel can be composed of two transistors, it is easy to narrow the pixel pitch, and a solid-state imaging device with a high pixel count can be obtained using the same optical system. Easy to realize. However, as the pixel pitch is reduced to 2 μm or less, the area ratio occupied by the wiring increases, the area ratio of the photoelectric conversion region relatively decreases, and the signal output voltage decreases.

  In order to suppress this bad influence, it is necessary to reduce the wiring width. However, if the wiring width is reduced, the wiring resistance increases and the voltage drop cannot be ignored. In particular, in the vertical output line, the size of the wiring resistance is extremely different between the center pixel and the end pixel of the screen, and output voltage nonuniformity (shading) occurs due to the wiring resistance. Further, from the relationship of arranging one pixel column of the peripheral driving circuit within the width of one pixel pitch, when the pixel pitch is narrowed, the arrangement area of the peripheral driving circuit for one pixel column becomes long, and as a result, the pixel area area However, there is a problem that it is difficult to reduce the chip size even if the pixel area is reduced.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a solid-state imaging device capable of reducing the chip size without causing nonuniform signal voltage even when the wiring width in the pixel region is narrowed. To do.

In order to achieve the above object, the solid-state imaging device of the present invention drives a plurality of unit pixels, a pixel region in which a plurality of unit pixels that photoelectrically convert incident light from a subject are regularly arranged, and In a solid-state imaging device having a drive circuit that processes a signal output from each unit pixel, the pixel region and the drive circuit are created in different substrates, and the pixel region is separated from the pixel region by wiring that passes through the substrate in which the pixel region is created. The drive circuit is formed on a different substrate, and the pixel region and the drive circuit are connected by a wiring penetrating the substrate on which the pixel region is formed, and connected to electrodes of a plurality of unit pixels in the pixel region. ,
The pixel region includes a plurality of rows of photoelectric conversion regions arranged at regular intervals at a first pitch in the horizontal direction and at a second pitch in the vertical direction on the substrate, and both in the horizontal and vertical directions on the substrate. A row of a plurality of signal output means arranged at different intervals and a wiring penetrating the substrate arranged in an empty space of the row of the plurality of signal output means are arranged .

  Here, each of the plurality of unit pixels arranged in the pixel region has a ring-shaped gate electrode, and outputs a signal output means for outputting the amount of input charge as a change in threshold voltage, and light. It is characterized by having a photoelectric conversion region that converts and accumulates charges and a charge transfer means that transfers the charges accumulated in the photoelectric conversion region to a signal output means.

In order to achieve the above object, the solid-state imaging device of the present invention drives a plurality of unit pixels and a pixel region in which a plurality of unit pixels that photoelectrically convert incident light from a subject are regularly arranged, In addition, in a solid-state imaging device having a drive circuit that processes a signal output from each unit pixel, the pixel region and the drive circuit are created in different substrates, and the pixel is formed by wiring that penetrates the substrate in which the pixel region is created. Connecting the region and the drive circuit, and connecting to the electrodes of a plurality of unit pixels in the pixel region,
The pixel region has a ring-shaped gate electrode, and a signal output unit that outputs the amount of input charge as a change in threshold voltage; a plurality of photoelectric conversion regions that convert light into charge and store; It comprises a plurality of charge transfer means for separately transferring charges accumulated in a plurality of photoelectric conversion regions to a common signal output means, and the plurality of photoelectric conversion regions and the plurality of charge transfer means are a common one A plurality of blocks are arranged two-dimensionally with blocks having a structure arranged symmetrically with respect to the signal output means, and a substrate on which a pixel region is created is provided at each boundary of the plurality of blocks. The connecting means that penetrates is arranged.

In order to achieve the above object, according to the present invention, the signal output means is a ring-shaped device provided on the second conductivity type well region formed on the first conductivity type substrate portion via an insulating film. Surrounding the gate electrode, the second conductivity type source region provided in the second conductivity type well region corresponding to the central opening of the ring-shaped gate electrode, and the second conductivity type source region, and in a ring shape A signal output transistor comprising a first conductivity type source vicinity region provided in a second conductivity type well region so as not to reach the outer periphery of the gate electrode;
The charge transfer means transfers the charges accumulated in the first conductivity type photoelectric conversion region provided in the second conductivity type well region to the corresponding first conductivity type source vicinity region in the same pixel in all pixels. It is a means for transferring all at once.

  According to the present invention, each electrode of a plurality of pixels (photoelectric conversion regions) shares a through-wiring that is a connecting means that penetrates a substrate that is a connecting means, thereby reducing the area in which the through-electrodes are arranged in the pixel region. For example, even when the diameter of the through wiring is 1 μm or more, the entire pixel pitch can be kept small.

  In addition, according to the present invention, even if the wiring from the through wiring to the predetermined electrode of the peripheral pixel in the pixel region is wired with the minimum line width permitted by the design rule, the wiring length is short, so that the voltage drop due to the wiring resistance is reduced. It can be suppressed. Further, in the present invention, even if the through wiring is provided in the pixel region, the regularity of the arrangement of the photoelectric conversion regions is not disturbed, so that unnaturalness in viewing the image does not occur.

  Furthermore, according to the present invention, since the substrate on which the peripheral drive circuit is mounted is formed on a substrate different from the substrate on which the pixel region is formed, the peripheral drive circuit can be arranged in an area corresponding to the pixel region. In addition, since a signal processing circuit such as an AD converter can be included, a solid-state imaging device (CMOS sensor) can be realized with a chip corresponding to the pixel area when viewed in plan, and the solid-state imaging device can be downsized.

  Next, embodiments of the present invention will be described with reference to the drawings. First, the configuration of each embodiment of the solid-state imaging device provided with the through wiring according to the present invention will be described, and then the manufacturing process of the through wiring will be described. FIG. 1 is a schematic plan view of a first embodiment of a solid-state imaging device according to the present invention. In the figure, a double circle indicates a ring-shaped gate readout transistor 31, and a circle indicates a photoelectric conversion region 33. There is a charge transfer gate 32 between the photoelectric conversion region 33 and the ring-shaped gate readout transistor 31. These one ring-shaped gate readout transistor 31, one photoelectric conversion region 33, and one charge transfer gate 32 between them constitute a unit pixel.

The configuration of this unit pixel is the same as the configuration of the unit pixel of the solid-state imaging device proposed by the present applicant in Japanese Patent Application No. 2004-021895. Therefore, the solid-state imaging device proposed by the applicant will be described. 2 is a schematic plan view of a unit pixel of the solid-state imaging device proposed by the applicant, and FIG. 3 is a cross-sectional view taken along line XX ′ of FIG. In FIG. 2, the ring-shaped gate electrode 12 corresponds to the gate electrode of the ring-shaped gate read transistor 31, the p ⁻ type region 6 corresponds to the photoelectric conversion region 33, and the transfer gate electrode 16 corresponds to the charge transfer described above. This corresponds to the gate 32.

In this solid-state imaging device (CMOS sensor), as shown in FIG. 3, a substrate in which a p ⁻ type epitaxial layer 2 is grown on p ⁺ silicon 1 is used. An n well 4 is provided in the p ⁻ type epitaxial layer 2, and a ring-shaped gate electrode 12 is formed on the n well 4 with a gate oxide film 11 interposed therebetween. An n ⁺ -type source region 15 is present on the surface of the n-well 4 at the central opening of the ring-shaped gate electrode 12, and a p-type source vicinity region 9 is adjacent to the source region 15. A p ⁺ region 3 is provided in the p ⁻ type epitaxial layer 2 below the p type region 9 near the source.

On the surface of the n-well 4 that is separated from the source region 15 and the p-type region 9 near the source, there is an n ⁺ -type drain region 10. A p ⁻ type region 6 is formed in the n-well 4 outside the ring-shaped gate electrode 12, and a buried photodiode is formed together with the n-well 4. There is an n ⁺ layer 7 on the surface of the embedded photodiode, and this n ⁺ layer 7 is connected to the n ⁺ drain region 10 on the outer periphery of the unit pixel area. There is a transfer gate electrode 16 between the embedded photodiode and the ring-shaped gate electrode 12.

FIG. 4 shows an equivalent circuit diagram of a unit pixel of this solid-state imaging device. The pixels are arranged in m rows and n columns in the pixel spread area, but only one of them is represented by an equivalent circuit. The pixel equivalent circuit shown in FIG. 4 includes a MOSFET 18 having a ring-shaped gate electrode 12, a drain 23 (corresponding to the drain region 10 and n ⁺ layer 7 in FIG. 3), a transfer gate MOSFET 20 having a transfer gate electrode 16, It consists of a diode 19, the drain of the ring-shaped gate MOSFET 18 is connected to the n-type of the photodiode 19, the source of the transfer gate MOSFET 20 is connected to the p-type of the photodiode 19, and the drain of the transfer gate MOSFET 20 is the ring-shaped gate MOSFET 18. Are connected to the back gate (the source vicinity p-type region 9 in FIG. 3).

  The ring-shaped gate electrode of the MOSFET 18 in the pixel is connected to the vertical scanning circuit 25, the transfer gate electrode of the MOSFET 20 is connected to the transfer gate drive circuit 26, and the drain electrode of the MOSFET 18 is connected to the drain voltage control circuit 27. Since the ring-shaped gate electrode is controlled for each row, wiring is performed in the horizontal direction. However, since the transfer gate electrode is controlled at the same time for all pixels, wiring in the vertical direction may be used, but here it is expressed in the horizontal direction. The drain voltage control circuit 27 may control all the pixels at the same time, or may control it for each row. Here, the drain voltage control circuit 27 is expressed by the composition direction. A wiring 24 connected to the source electrode of the MOSFET 18 is wired in the vertical direction. One of the wirings 24 is connected to the source potential control circuit 28 and the other is connected to the signal output circuit 29.

  The signal output circuit 29 has a so-called CDS (correlated double sampling) function of reading a difference between the signal voltage and the reset voltage by a clamp circuit, a sample hold circuit, and a differential amplifier (not shown). The signal output from the signal output circuit 29 is output via a switch controlled by the horizontal scanning circuit 30.

The operation of this equivalent circuit will be described with reference to the timing chart of FIG. In the period up to time t1 in FIG. 5, light enters the embedded photodiode 19, electron hole pairs are generated by the photoelectric effect, and holes are accumulated in the p ⁻ type region (6 in FIG. 3) of the photodiode 19. . At time t1, as shown in FIG. 5B, the potential VTG of the transfer gate electrode becomes low level (Low), and hole charges are transferred from the photodiode 19 to the back gate of the ring-shaped gate MOSFET 18 all at once in all pixels. . The source potential VS of the MOSFET 18 is set to S1 by the source potential control circuit 28 as shown in FIG. S1> Low, which keeps the ring-shaped gate MOSFET 18 off and prevents current from flowing.

  At time t2, the transfer gate electrode potential VTG becomes high level (Vdd) again as shown in FIG. 5B, and the transfer gate MOSFET 20 is turned off. In the photodiode 19, the accumulation of hole charges starts again, and this continues until the next transfer. Since the pixel signal reading is performed in order for each row, the time t2 to t3 is in a standby state until the signal is read. The gate potential VR of the ring-shaped gate MOSFET 18 in the standby state is low level (Low) as shown in FIG. 5C, and the source potential VS is S1 as shown in FIG.

  The source potential VS can take various values depending on the value of the signal from the pixel while the signal is read from another row. At time t3, reading of the illustrated pixel starts. First, at time t3, as shown in FIG. 5C, the ring-shaped gate electrode potential VR becomes Vg1. This Vg1 is a potential between Low and Vdd.

  On the other hand, a source follower circuit is connected to the output line 24 by a switch in the signal output circuit 29, and the source potential VS of the ring-shaped gate MOSFET 18 becomes S2 (= Vg1-Vth1) as shown in FIG. Here, Vth1 is a threshold voltage of the ring-shaped gate MOSFET 18 in a state where there is a hole in the back gate (p-type region near the source) of the ring-shaped gate MOSFET 18. This source potential S 2 is stored in the first capacitor C 1 in the signal output circuit 29.

Next, at time t4, the ring-shaped gate electrode potential VR becomes Vg2 as shown in FIG. 5C, and the source electrode potential VS becomes S3 as shown in FIG. 5D. Here, Vg2, S3> Low, and it is desirable to set the potential so that the ring-shaped gate MOSFET 18 is turned on and no current flows. Further, Vg2 and S3 ≦ Vdd are desirable. In a simple setting, Vg2 = S3 = Vdd. At this time, the potential of the p-type region 9 near the source shown in FIG. 3 is raised, and holes are discharged to the p-type epitaxial layer 2 beyond the barrier of the n-well 4 (reset). The p ⁺ layer 3 under the p-type region 9 near the source in FIG. 3 is provided to adjust the reset voltage to an appropriate value.

  Next, at time t5, as shown in FIG. 5C, the ring-shaped gate electrode potential VR becomes Vg1 again. On the other hand, a source follower circuit is connected to the output line 24 by the signal output circuit 29, and the source potential VS of the ring-shaped gate MOSFET 18 becomes S0 (= Vg1−Vth0) as shown in FIG. Here, Vth0 is the threshold voltage of the ring-shaped gate MOSFET 18 in the state where there is no hole in the back gate (p-type region 9 near the source) of the ring-shaped gate MOSFET 18. This source potential S0 is stored in the second capacitor C2 in the signal output circuit 29, and the potential difference between C1 and C2, that is, (Vth0−Vth1) is output by the differential amplifier. This output value is a change in threshold value due to hole charges. This signal is output outside the sensor through a switch in the horizontal scanning circuit 30. Note that, after time t1, the drain voltage VD output from the drain voltage control circuit 27 is Vdd as shown in FIG.

  In the above description, the source potential S3 at the time of resetting from time t4 to t5 is supplied from the source potential control circuit 28. However, there is a method in which the potential is made floating. In this case, when the ring-shaped gate electrode potential is Vg2, the ring-shaped gate MOSFET 18 is turned on, current is supplied from the drain to the source, and the source electrode potential rises. Therefore, the potential of the p-type region 9 near the source in FIG. 3 is raised, and holes are discharged to the p-type epitaxial layer 2 beyond the barrier of the n-well 4 (reset). The source electrode potential when the holes are completely discharged becomes (Vg2-Vth0). This method can reduce the number of transistors that supply S3 in the source potential control circuit 28, and can reduce the chip area.

  As is apparent from the above description, in this solid-state imaging device, a CMOS sensor is formed by two transistors per pixel, but all the pixels all at once are ring-shaped gate MOSFETs 18 that are signal readout transistors from the photodiodes 19. Since the charge is transferred to the global shutter function, a global shutter function can be realized. Further, since the photoelectrically converted charge is transferred to the p-type region 9 near the source having a small area, the charge-voltage conversion efficiency is high and the output can be increased.

  Further, since the number of transistors per pixel is small, increasing the area ratio of the photodiode within the pixel area also contributes to an increase in signal output. Further, when the ring-shaped gate MOSFET 18 is reset, the p-type region 9 in the vicinity of the source is completely depleted, so that there is an excellent feature that no reset noise is generated due to variations in the residual charge amount at the time of reset.

  Returning again to FIG. In the first embodiment shown in FIG. 1, the adjacent photoelectric conversion regions 33 are arranged at equal intervals, but the intervals are slightly different in the vertical and horizontal directions of the adjacent read transistors 31. The unit pixels are rotated little by little and arranged in the pixel area. The plurality of photoelectric conversion regions 33 are arranged at equal intervals in the vertical direction at the first pitch, and are arranged at equal intervals in the horizontal direction at the second pitch. The pitch may be the same or different.

  With this arrangement method, an empty space is created in the column of the read transistors 31 while the pitch of the photoelectric conversion regions 33 is kept constant, and transfer gate through wires 35 and 40 and source output through wires 36 and 38 are formed there. 41, 43 and drain through-wirings 37, 42 are arranged.

Each through wiring is connected to each electrode of a plurality of pixels by a normal metal wiring. FIG. 1 illustrates the source output line 39. The drain of the ring-shaped gate readout transistor 31 (the drain 23 of the ring-shaped gate MOSFET 18 in FIG. 4, n ⁺ regions 7 and 10 in FIG. 3) is common to all pixels and is connected by a well (n-well 4 in FIG. 3). Therefore, it is not necessary to provide metal wiring for each pixel. The wiring of the charge transfer gate 32 is wired with a metal of a different layer from the source output line 39. Note that the ring-shaped gate electrode (12 in FIG. 3) of the ring-shaped gate readout transistor 31 is connected in the lateral direction by a polysilicon wiring 34 and connected to the through wiring at the outer periphery of the pixel area.

  As is clear from the above description, in the CMOS sensor of the first embodiment, since the through wiring is shared by a plurality of pixels, the area for arranging the through wiring can be reduced. Even when the diameter is 1 μm or more, the pixel pitch can be kept small. Even if the wiring from the through wiring to the peripheral pixels is wired with the minimum line width permitted by the design rule, the voltage drop due to the wiring resistance can be suppressed because the wiring length is short. Further, in this embodiment, the arrangement of unit pixels is irregular and the regularity of the arrangement of the photoelectric conversion regions is not disturbed even though the through wiring is provided in the pixel region (pixel area) ( Since the photoelectric conversion regions are arranged at equal intervals), there is no problem in visual observation.

  Further, as shown in FIG. 9 to be described later, the peripheral drive circuit is arranged on a separate substrate, apart from the substrate on which the pixel region having the plurality of unit pixels of the present embodiment arranged as shown in FIG. 1 is created. Since the electrodes and the drive circuits of the plurality of unit pixels in the pixel region are connected to each other by the wiring that passes through the substrate on which the pixel region is created, the peripheral drive circuit is formed within the area corresponding to the pixel area. Further, a signal processing circuit such as an AD converter can be included. As a result, when viewed in plan, a CMOS sensor can be realized with a chip corresponding to the pixel area, and the solid-state imaging device can be downsized.

  Next, a second embodiment of the solid-state imaging device of the present invention will be described. FIG. 6 is a schematic plan view of one readout transistor of the second embodiment of the solid-state imaging device according to the present invention. This embodiment is an example in which charges accumulated in four photoelectric conversion regions are output as a change in threshold voltage from one common readout transistor. This is an effective method for reducing the pixel pitch.

  In FIG. 6, four photodiodes 52a, 52b, 52c, and 52d and four transfer gate electrodes 53a, 53b, 53c, and 53d are arranged symmetrically with the ring-shaped gate electrode 50 and the source region 51 as the center. . FIG. 7 is a plan view when a large number of units of four pixels in FIG. 6 are arranged and through wirings are provided at the intersections.

  In FIG. 7, the four transfer gate electrodes 53a, 53b, 53c, and 53d in FIG. 6 are denoted by T1, T2, T3, and T4, and through-wires respectively connected to these transfer gate electrodes are denoted by T11, T12, and T13. , T14, and the through wiring arrangement shown in FIG. 7 is from the top left to the right, the first row is T12, T11, T12, T11, the second row is T14, (S1), T14, T13, the third row Is the order of T12, T11, T12, (VD), and the fourth row is arranged in the order of T14, T13, T14, T13. The portion is replaced with the source output through wiring S1 and the drain through wiring VD.

  This is to shorten the wiring length of the transfer gate by using the penetrating wiring at the intersection of the arrangement of the common readout transistor units of one unit of four pixels as a principle of the wiring of the transfer gate, while reading common to the four pixels. For the common source for each vertical column of transistors and the common drain for all pixels, replace the necessary number of through-wirings for the transfer gate electrode to reduce the series resistance of those wirings. Wiring is placed. For example, with respect to the through wiring T11, the transfer gate electrode 53a (T1) of the common readout transistor unit of one unit of four pixels is arranged so as to face each other, so that the wiring length of the transfer gate electrode and the through wiring is reduced. The same applies to the other through wirings T12 to T14.

  S1 indicates a source output through wiring 54, and a source output line 55 is connected. Even if the width of the source output line 55 is narrowed, the wiring line resistance of the source output line can be lowered because it is connected to the source output through-wiring 54 for every certain number of pixels. The transfer gate through wiring 56 (T14) is connected to transfer gate electrodes 57a (T4), 57b (T4), 57c (T4), and 57d (T4) around the transfer gate electrode 57a (T4). A transfer gate electrode in a place where there is no through wiring (for example, around the drain through wiring 59 (VD)) is connected to a normal metal wiring 61 from a through wiring 60 of a transfer gate electrode of the same phase nearby. The ring-shaped gate electrode 50 of the readout transistor is connected to each other in the horizontal direction by a polysilicon wiring 58 and is connected to a through wiring around the pixel area.

  In the CMOS sensor according to the second embodiment of the present invention described above, since the through wiring is formed at the intersection of the arrangement of the common readout transistor unit of 4 pixels per unit, for example, the diameter of the through wiring is 1 μm or more. Even in this case, the entire pixel pitch can be kept small. Further, even if the wiring from the through wiring to the peripheral pixels is the minimum line width allowed by the design rule, the wiring length is short, so that a voltage drop due to the wiring resistance can be prevented. Also in this configuration example, the regularity of the arrangement of the photoelectric conversion regions is not disturbed even though the through wiring is provided in the pixel area, so that there is no problem in viewing the image.

  Next, the process of through wiring will be described. The through wiring described in the first and second embodiments is described in, for example, a known document (Kang Wook Lee, et al., “Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip”, Japanese Journal). Applied Physics Vol. 39 (2000), pp. 2473-2477). This process will be described with reference to FIGS.

  First, as shown in FIG. 8A, a groove 72 is formed by etching or the like in a substrate 71 that has completed the LSI creation process of the pixel area, an insulating film 73 is formed inside the groove 72, and then tungsten 74 is embedded. The surface is flattened by CMP (Chemical Mechanical Polish) and then connected to the element in the pixel area with metal 75. The metal 75 is formed by sputtering a film of aluminum or the like and using a photo process and etching.

  Next, as shown in FIG. 8B, after a glass plate 76 is bonded to the surface of the substrate 71 provided with the metal 75, the back surface of the substrate 71 is polished to expose the tungsten 74 on the back surface. Subsequently, as shown in FIG. 8C, an insulating film 77 is coated on the entire back surface of the substrate 71, a portion of tungsten 74 of the insulating film 77 is opened, and a metal electrode 78 is formed. Micro bumps 79 are formed on the metal electrodes 78 for connection to the electrodes.

  On the other hand, as shown in FIG. 9A, a metal electrode 81 for connection to an upper substrate having a pixel area is formed on the surface of an LSI substrate 80 in which a CMOS sensor drive circuit and a signal processing circuit are formed. Thereafter, by using a double-sided alignment device, the micro bumps 79 of the substrate 71 shown in FIG. 8C and the metal electrodes 81 of the substrate 80 shown in FIG. By removing the glass plate 76 attached to the upper substrate 71, the solid-state imaging device shown in FIG. 9B is manufactured. The minimum diameter of tungsten 74 that becomes a through wiring that can be formed in this step is 1 to 2 μm.

  With the configuration of the CMOS sensor and the through electrode creation process described in the above description, it is possible to realize a solid-state imaging device that has high pixel density and small output voltage variation due to wiring resistance.

  Note that the present invention is not limited to the above-described embodiment. For example, in the second embodiment of FIG. 7, the common readout transistor unit is one unit of four pixels shown in FIG. It is good also as multiple pixel 1 unit other than. 8 and 9, a known wiring material other than tungsten 74 can also be used. Furthermore, the present invention can be applied in principle to a CMOS sensor having an amplifying transistor (readout transistor) that does not have a ring-shaped gate electrode in a pixel.

1 is a schematic plan view of a first embodiment of a solid-state imaging device of the present invention. It is a schematic plan view of an example of a solid-state imaging device having a ring-shaped gate electrode. FIG. 3 is a longitudinal sectional view taken along line X-X ′ in FIG. 2. FIG. 4 is an equivalent circuit diagram per pixel of the solid-state imaging device of FIGS. 2 and 3. 5 is a timing chart for explaining the operation of the equivalent circuit of FIG. 4. It is a top view of the unit pixel group in 2nd Embodiment of the solid-state imaging device of this invention. It is a pixel area top view of 2nd Embodiment of the solid-state imaging device of this invention. It is apparatus sectional drawing for the process description of the penetration wiring preparation of 2nd Embodiment of the solid-state imaging device of this invention (the 1). It is apparatus sectional drawing (the 2) for process description of the penetration wiring preparation of 2nd Embodiment of the solid-state imaging device of this invention. It is explanatory drawing of the image distortion of a line shutter operation | movement.

Explanation of symbols

18 Ring-shaped gate MOSFET
19, 52a to 52d Photodiode 20 Transfer gate MOSFET
24, 39, 55 Source output wiring 31 Ring-shaped gate readout transistor 32 Charge transfer gate 33 Photoelectric conversion region 34, 58 Polysilicon wiring 35-38, 40-43 Through wiring 50 Reading transistor ring-shaped gate electrode 51 Source region 53a ˜53d Transfer gate electrode 54 Source output through wiring (S1)
56 Transfer gate through wiring 57a to 57d Transfer gate electrode (T4)
59 Drain through wiring (VD)
61 Metal wiring

Claims (4)

A pixel region in which a plurality of unit pixels that photoelectrically convert incident light from a subject are regularly arranged, and a drive circuit that drives the plurality of unit pixels and processes a signal output from each unit pixel; In a solid-state imaging device having
The pixel region and the driving circuit are formed in different substrates, the pixel region and the driving circuit are connected by a wiring penetrating the substrate in which the pixel region is formed, and the plurality of pixels in the pixel region are connected Connected to the electrode of the unit pixel of
In the pixel region,
A plurality of rows of the photoelectric conversion regions arranged at regular intervals on the substrate at a first pitch in the horizontal direction and at a second pitch in the vertical direction;
A plurality of rows of the signal output means arranged at different intervals in the horizontal direction and the vertical direction on the substrate;
A solid-state imaging device comprising: a plurality of the signal output means arranged in an empty space in a row and a wiring penetrating the substrate . Each of the plurality of unit pixels arranged in the pixel region is
A signal output means having a ring-shaped gate electrode and outputting the amount of input charge as a change in threshold voltage;
A photoelectric conversion region for converting light into electric charge and storing it;
The solid-state imaging device according to claim 1, further comprising: charge transfer means for transferring the charge accumulated in the photoelectric conversion region to the signal output means. A pixel region in which a plurality of unit pixels that photoelectrically convert incident light from a subject are regularly arranged, and a drive circuit that drives the plurality of unit pixels and processes a signal output from each unit pixel; In a solid-state imaging device having
The pixel region and the driving circuit are formed in different substrates, the pixel region and the driving circuit are connected by a wiring penetrating the substrate in which the pixel region is formed, and the plurality of pixels in the pixel region are connected Connected to the electrode of the unit pixel of
In the pixel region,
A signal output means having a ring-shaped gate electrode and outputting the amount of input charge as a change in threshold voltage;
A plurality of photoelectric conversion regions for storing light by converting it into electric charges;
A plurality of charge transfer means for separately transferring the charges accumulated in the plurality of photoelectric conversion areas to one common signal output means, wherein the plurality of photoelectric conversion areas and the plurality of charge transfer means include A plurality of blocks are arranged two-dimensionally with a block having a structure arranged symmetrically around a common signal output means, and at each boundary of the plurality of blocks, solid-state image sensor you characterized in that a connecting means passing through the substrate on which the pixel region is created. The signal output means includes the ring-shaped gate electrode provided on the second-conductivity-type well region formed on the first-conductivity-type substrate portion via an insulating film, and a central opening of the ring-shaped gate electrode. The second conductivity type source region provided in the second conductivity type well region corresponding to the portion and the second conductivity type source region are surrounded and do not reach the outer periphery of the ring-shaped gate electrode. And a signal output transistor comprising a first conductivity type source vicinity region provided in the second conductivity type well region,
The charge transfer means converts the charge accumulated in the photoelectric conversion region of the first conductivity type provided in the well region of the second conductivity type into the corresponding source of the first conductivity type in the same pixel. 4. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is a means for transferring all pixels simultaneously to a neighboring area.

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