JP2009026984A - Solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the sensitivity deviation between pixels, while maintaining a high aperture ratio by sharing an amplifier transistor, and the like, with a plurality of pixels. <P>SOLUTION: Each pixel 1 contains a photodiode PD1 or PD2 for generating and storing a signal charge that corresponds to an incident light and further, contains various transistors. Color filters, arrayed according to a Bayer array, are provided to the light-incident side of the photodiode PD1 or PD2 of each pixel 1. Each unit cell 10 contains two pixels 1, in which the photodiodes PD1 or PD2 are laid side by side, in a column direction. In each unit cell 10, the two pixels 1 share a predetermined transistor, and so on Adjacent unit cells 10 in the row direction are displaced from each other by one pitch, in the column direction of the photodiodes PD1 and PD2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  Video cameras, electronic still cameras, and the like have a CCD solid-state image sensor and an amplification solid-state image sensor. In these solid-state imaging devices, a plurality of pixels having photoelectric conversion units are arranged in a matrix, and signal charges are generated in the photoelectric conversion units of the respective pixels. In the amplification type solid-state imaging device, the signal charge generated and accumulated in the photoelectric conversion unit of the pixel is led to a charge-voltage conversion unit such as a floating diffusion, and the signal charge is converted into a voltage by the charge-voltage conversion unit, and according to the voltage The signal is output from the pixel by an amplifying transistor provided in the pixel.

  In an amplification type solid-state imaging device, generally, each pixel has a charge such as a photoelectric conversion unit that generates and accumulates a signal charge according to incident light, and a floating diffusion that receives the signal charge and converts the signal charge into a voltage. A voltage conversion unit, an amplification transistor that outputs a signal corresponding to the potential of the charge voltage conversion unit, a transfer transistor that transfers charge from the photoelectric conversion unit to the charge voltage conversion unit, and a reset that resets the potential of the charge voltage conversion unit A transistor and a selection transistor for selecting the pixel are included. Further, the amplification type solid-state imaging device has a vertical signal line to which the output of the pixel for each column is supplied.

  In such an amplification type solid-state imaging device, in general, not only a photoelectric conversion unit and a transfer transistor but also a set of a charge voltage conversion unit, an amplification transistor, a reset transistor, and a selection transistor are provided for each pixel. . Therefore, in such an amplification type solid-state imaging device, since the number of transistors is large, the area for the photoelectric conversion unit is narrowed and the aperture ratio is lowered.

  Therefore, in the solid-state imaging device disclosed in Patent Document 1 below, a unit cell is formed for each predetermined number of pixels sequentially arranged in the column direction, and the predetermined number of pixels belonging to the unit cell is 1 for each unit cell. A set of charge-voltage conversion unit, amplification transistor, reset transistor, and selection transistor are shared. For this reason, the number of transistors per pixel can be reduced, and the aperture ratio can be increased. When the aperture ratio is large, a lot of charges are handled, and the SN ratio is improved.

  In the solid-state imaging device disclosed in Patent Document 1, the photoelectric conversion unit and the photoelectric conversion unit in a unit cell including a plurality of pixels sharing one set of charge-voltage conversion unit, amplification transistor, reset transistor, and selection transistor. Each set composed of transfer transistors provided corresponding to the conversion units is translationally symmetric with respect to each other. Here, parallel symmetry means that when a pair of photoelectric conversion units and a transfer transistor are moved in parallel in the same direction at a constant interval (pixel pitch; photoelectric conversion region pitch), the pair of photoelectric conversion units and transfer This means that a transistor overlaps with another set of photoelectric conversion units and transfer transistors. By adopting such a translationally symmetrical arrangement, it is possible to prevent the occurrence of a sensitivity shift between pixels in the unit cell. As a result, it is possible to obtain a good image free from fixed pattern noise caused by sensitivity shift.

  In the solid-state imaging device disclosed in Patent Document 1, the unit cells adjacent to each other in the row direction are not displaced in the column direction and are arranged at exactly the same column direction position.

In the solid-state imaging device disclosed in Patent Document 1, each pixel is provided with a color filter arranged according to a Bayer array, and one R pixel (a pixel provided with a red color filter), 1 2 × 2 pixels, one B pixel (a pixel provided with a blue color filter) and two G pixels (a pixel provided with a green color filter) (one of which is called a Gr pixel and the other is called a Gb pixel) These basic units are arranged in a matrix.
JP 2006-73733 A

  However, the conventional solid-state imaging device disclosed in Patent Document 1 cannot always sufficiently reduce the sensitivity shift between pixels. This point will be described below.

  In a solid-state imaging device in which a plurality of pixels share an amplification transistor or the like for each unit cell, it is assumed that unit cells adjacent to each other in the row direction are arranged at exactly the same column direction position. These pixels share an amplification transistor and the like. Therefore, the positional relationship (optical positional relationship regarding sensitivity) of other elements such as surrounding transistors with respect to the photoelectric conversion unit in each pixel cannot be made the same for all the pixels, and the Gr pixel and Gb In principle, a sensitivity deviation occurs between the pixels. Although the sensitivity is originally different between the R pixel, the B pixel, and the G pixel, the sensitivity should be the same between the Gr pixel and the Gb pixel, and the image quality is greatly deteriorated even if the sensitivity difference therebetween is slight. Near the center of the solid-state image sensor, light is condensed by the microlens so as to focus on the center of the photoelectric conversion unit. Therefore, for the pixels near the center of the solid-state image sensor, other elements around the photoelectric conversion unit The fact that the positional relationship is close to that of other pixels is not a problem. On the other hand, when oblique light is incident on the area around the solid-state image sensor, the condensing position of the incident light is shifted from the center of the photoelectric conversion unit. It is particularly important that the positional relationship between these elements is close to that of other pixels.

  In the conventional solid-state imaging device disclosed in Patent Document 1, since the above-described translational symmetry arrangement is adopted, the positional relationship of the transfer transistor with respect to the photoelectric conversion unit is the same for all pixels, but the photoelectric conversion unit The positional relationship of other transistors and wiring elements is not the same. Therefore, in the conventional solid-state imaging device disclosed in Patent Document 1, it is not always possible to sufficiently reduce the sensitivity shift between pixels, such as the sensitivity shift between the Gr pixel and the Gb pixel.

  The present invention has been made in view of such circumstances, and a solid-state imaging capable of further reducing sensitivity deviation between pixels while maintaining a high aperture ratio by sharing an amplification transistor or the like among a plurality of pixels. An object is to provide an element.

  In order to solve the above problems, the solid-state imaging device according to the first aspect of the present invention includes a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and receives the signal charges and converts the signal charges into a voltage. A plurality of pixels having a charge-voltage conversion unit, an amplification transistor that outputs a signal corresponding to the potential of the charge-voltage conversion unit, and a transfer transistor that transfers charge from the photoelectric conversion unit to the charge-voltage conversion unit, A solid-state imaging device having a plurality of pixels arranged in a two-dimensional manner and having a vertical signal line to which the output of the pixel for each column is supplied, wherein the photoelectric conversion units are sequentially arranged in the column direction. A unit cell is formed for each of N pixels (N is an integer of 2 or more) arranged, and for each unit cell, the N pixels belonging to the unit cell are a set of the charge-voltage conversion unit and the amplification transistor. The unit cells that share the data and are adjacent to each other in the row direction are shifted in the column direction by a predetermined number from 1 to N−1 in the column direction pitch of the photoelectric conversion units. It is a thing.

  A solid-state imaging device according to a second aspect of the present invention is the solid-state imaging device according to the first aspect, wherein the plurality of pixels are provided with color filters arranged according to a Bayer array.

  In the solid-state imaging device according to the third aspect of the present invention, in the first or second aspect, the N is an even number and the predetermined number is an odd number.

  In the solid-state imaging device according to the fourth aspect of the present invention, in any one of the first to third aspects, the gates of the transfer transistors of the plurality of pixels are electrically connected to each pixel row in common. Is.

  A solid-state imaging device according to a fifth aspect of the present invention is the solid-state imaging device according to any one of the first to fourth aspects, wherein the pixel selects a reset transistor that resets the potential of the charge-voltage converter and the pixel. Each of the unit cells has a selection transistor, and the N pixels belonging to the unit cell share a set of the reset transistor and the selection transistor.

  A solid-state imaging device according to a sixth aspect of the present invention is the solid-state imaging device according to the fifth aspect, wherein the drain of the amplification transistor and the drain of the reset transistor are shared for each unit cell.

  The solid-state imaging device according to a seventh aspect of the present invention is the solid-state imaging device according to the fifth or sixth aspect, wherein the gates of the reset transistors of the unit cells in different columns shifted from each other in the column direction are electrically independent from each other. The gates of the selection transistors of the unit cells in different columns shifted from each other in the column direction are electrically wired separately from each other.

  The solid-state imaging device according to an eighth aspect of the present invention, in any one of the fifth to seventh aspects, includes, for each unit cell, the amplification transistor shared by the N pixels belonging to the unit cell, The reset transistor and the selection transistor are arranged in a straight line.

  The solid-state imaging device according to a ninth aspect of the present invention is the solid-state imaging device according to any one of the first to eighth aspects, wherein the transistor shared by the N pixels in each unit cell is the photoelectric conversion of the unit cell. It is formed in a region that protrudes in the row direction from the region in the column in which the parts are arranged.

  In the solid-state imaging device according to the tenth aspect of the present invention, in any one of the first to eighth aspects, the transistor shared by the N pixels in each unit cell is the photoelectric conversion of the unit cell. It is almost formed in the region in the row where the parts are lined up.

  According to an eleventh aspect of the present invention, in any one of the first to tenth aspects, in each of the unit cells, between the photoelectric conversion units of the pixels adjacent in the column direction, between the two. A crosstalk reducing portion for reducing charge crosstalk is formed.

  A solid-state imaging device according to a twelfth aspect of the present invention includes, in the eleventh aspect, a first conductivity type first semiconductor layer, and the photoelectric conversion units of the plurality of pixels include the first semiconductor layer. The cross-conduction reducing portion includes the second conductivity type semiconductor region formed in the first semiconductor layer and applied with a predetermined potential. .

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state image sensor which can reduce the sensitivity shift between pixels can be provided, maintaining a high aperture ratio by sharing an amplification transistor etc. by several pixels.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a circuit diagram showing a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention. The solid-state imaging device according to the present embodiment is formed as a CMOS type solid-state imaging device on a silicon substrate using a CMOS process, and is mounted on an electronic camera such as a digital still camera or a video camera.

  The solid-state imaging device according to the present embodiment includes a plurality of pixels 1 arranged in a two-dimensional shape (only 4 × 3 pixels 1 are shown in FIG. 1), a vertical scanning circuit 2, and a horizontal scanning circuit 3. And a vertical signal line 5 provided for each column of the pixels 1 to which an output of the pixel 1 for each column is supplied, a constant current source 6 connected to each vertical signal line 5, and photoelectric conversion by the pixels 1. A first horizontal signal line 7S for transmitting an optical signal including the optical information and a second horizontal signal line 7N for transmitting a so-called dark signal as a differential signal including a noise component to be subtracted from the optical signal, And a dynamic output amplifier 8. Needless to say, the number of pixels 1 is not limited.

  Further, the solid-state imaging device according to the present embodiment corresponds to each column of the pixels 1, the optical signal storage capacitor CS that stores the optical signal, the dark signal storage capacitor CN that stores the dark signal, and the optical signal vertical transfer. The transistor TS, the dark signal vertical transfer transistor TN, the optical signal horizontal transfer transistor HS, and the dark signal horizontal transfer transistor HN are included. Actually, each transistor for resetting the horizontal signal lines 7S and 7N at a predetermined timing is provided, but the illustration of these transistors is omitted.

  In the present embodiment, each pixel 1 includes a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and charge-voltage conversion that receives the signal charges and converts the signal charges into a voltage. The floating diffusion FD as a part, the amplification transistor AMP that outputs a signal corresponding to the potential of the floating diffusion FD, the transfer transistor TX that transfers charges from the photodiode PD to the floating diffusion FD, and the potential of the floating diffusion FD are reset. The reset transistor RES and a selection transistor SEL for selecting the pixel 1 are connected as shown in FIG. In the present embodiment, the transistors AMP, TX, RES, and SEL of the pixel 1 are all nMOS transistors. In FIG. 1, Vdd is a power supply voltage.

  In the drawing, in the unit cell 10 described later, the photodiode of the upper pixel 1 in the figure is denoted by PD1, and the photodiode of the lower pixel 1 in the figure is denoted by PD2. When the description is made without distinguishing between the two, there is a case in which the reference numeral PD is attached to both. Similarly, in the unit cell 10 which will be described later, the transfer transistor of the upper pixel 1 in the figure is denoted by TX1, and the transfer transistor of the lower pixel 1 in the figure is denoted by TX2, and they are distinguished from each other. When the description is made without distinction, the description may be given with the symbol TX.

  In the present embodiment, the plurality of pixels 1 form a unit cell 10 for every two pixels 1 in which photodiodes PD are sequentially arranged in the column direction. FIG. 2 is a schematic plan view schematically showing an arrangement state of the unit cells 10 of the solid-state imaging device shown in FIG. FIG. 2 shows 5 × 3 pixels 1.

  In the present embodiment, for each unit cell 10, two pixels 1 belonging to the unit cell 10 share one set of floating diffusion FD, amplification transistor AMP, reset transistor RES, and selection transistor SEL. The photodiode PD and the transfer transistor TX are provided for each pixel 1 without being shared by the two pixels 1. In the present embodiment, as shown in FIG. 2, the unit cells 10 that are adjacent to each other in the row direction are shifted in the column direction by one pitch of the photodiode PD in the column direction.

  A color filter (not shown) is provided on the light incident side of the photodiode PD of each pixel 1. In the present embodiment, a system using R, G, and B is employed as a combination of color filters, and a Bayer array is employed. However, the present invention is not limited to this. For example, a stripe arrangement may be adopted. In FIG. 1 and FIG. 2, a photodiode PD provided with a red color filter that mainly transmits red light may be denoted by R and the pixel 1 may be referred to as an R pixel, and mainly transmits green light. A photodiode PD provided with a green color filter is given Gr and Gb, and its pixel 1 may be called a Gr pixel or Gb pixel. The photodiode PD provided with a blue color filter that mainly transmits blue light may be used. In some cases, B is attached and the pixel is referred to as a B pixel. The Gr photodiode PD is a photodiode adjacent to the R photodiode PD in the row direction, and the Gb photodiode PD is a photodiode adjacent to the B photodiode PD in the row direction. Although they are distinguished, the optical characteristics are the same.

  In this embodiment, the Bayer arrangement is adopted as described above, and the unit cells 10 adjacent to each other in the row direction are shifted in the column direction by one column pitch of the photodiode PD. ing. As a result, as shown in FIG. 2, the unit cell 10 composed of Gr pixel and B pixel is shifted by one pixel in the column direction with respect to the unit cell 10 composed of Gb pixel and R pixel.

  Refer to FIG. 1 again. In the following description, the row of pixels 1 is referred to as a pixel row, and the simple row means a row (cell row) in which the unit cell 10 is a unit. That is, paying attention to the unit cell 10 extending over two pixel rows, the two pixel rows are defined as one cell row. In the following description, this one cell row is simply referred to as a “row”. However, in view of the fact that the unit cells 10 adjacent to each other in the row direction are shifted in the column direction, the cell row based on the unit cell 10 in the m-th column is simply referred to as “row”. Therefore, each row includes an upper pixel row and a lower pixel row in the figure. For example, the upper row n means the pixel row to which the upper pixel 1 of the n-th unit cell 10 belongs, and the lower row n belongs to the lower pixel 1 of the n-th unit cell 10 in the drawing. It shall mean a pixel row.

  As shown in FIG. 1, the gate of the transfer transistor TX is connected to a control line that supplies a control signal φTX for controlling the transfer transistor TX from the vertical scanning circuit 2 to the transfer transistor TX for each pixel row. However, the control signal φTX includes a control signal φTXA supplied to the upper transfer transistor TX in each row and a control signal φTXB supplied to the lower transfer transistor TX in each row.

  The reset transistor RES receives a control signal φRES for controlling the reset transistor RES from the vertical scanning circuit 2 for each unit cell 10 arranged in the exact same column direction position without being displaced in the column direction. Connected to the control line that supplies However, the control signal φRES includes the control signal φRESA supplied to the reset transistor RES of the unit cell 10 (such as the unit cell 10 in the m-th column) that is just fit in one cell row, and the unit cell 10 ( and a control signal φRESB supplied to the reset transistor RES of the unit cell 10 in the (m + 1) th column. Note that φRESA (n) means a control signal supplied to the reset transistor RES of the unit cell 10 in the nth row, but φRESB (n) is the same pixel row as the lower pixel 1 in the nth row. This means a control signal supplied to the reset transistor RES of the unit cell 10 having the pixel 1 as the upper pixel 1. As can be seen from the above description, in the present embodiment, the gates of the reset transistors RES of the unit cells 10 in different columns shifted from each other in the column direction are wired separately and electrically independent from each other. However, the present invention is not necessarily limited thereto. For example, a control line that supplies φRESA (n) and a control line that supplies φRESB (n) may be connected in common so that the same control signal is given to both. Is possible. However, it is preferable to wire the two separately as in this embodiment because the wiring can be formed linearly. Refer to FIG. 3 to be described later.

  The gate of the selection transistor SEL is supplied with a control signal φSEL for controlling the selection transistor SEL from the vertical scanning circuit 2 for each unit cell 10 arranged at exactly the same column direction position without being displaced in the column direction. Connected to the control line that supplies However, in this control signal φSEL, the control signal φSELA supplied to the selection transistor SEL of the unit cell 10 (such as the unit cell 10 in the m-th column) that just fits in one cell row and the unit cell 10 ( and a control signal φSELB supplied to the selection transistor SEL of the unit cell 10 in the (m + 1) th column. Note that φSELA (n) means a control signal supplied to the selection transistor SEL of the unit cell 10 in the n-th row, but φSELB (n) is the same pixel row as the lower pixel 1 in the n-th row. This means a control signal supplied to the selection transistor SEL of the unit cell 10 in which the pixel 1 is the upper pixel 1. As can be seen from the above description, in the present embodiment, the gates of the select transistors SEL of the unit cells 10 in different columns shifted from each other in the column direction are separately wired independently from each other. However, the present invention is not necessarily limited to this. For example, a control line for supplying φSELA (n) and a control line for supplying φSELB (n) may be connected in common so that the same control signal is given to both. Is possible. However, it is preferable to wire the two separately as in this embodiment because the wiring can be formed linearly. Refer to FIG. 3 to be described later.

  The photodiode PD generates a signal charge according to the amount of incident light (subject light). The transfer transistor TX is turned on during a high level period of the transfer pulse (control signal) φTX, and transfers the signal charge accumulated in the photodiode PD to the floating diffusion FD. The reset transistor RES is turned on during a high level period of the reset pulse (control signal) φRES to reset the floating diffusion FD.

  The amplification transistor AMP has a drain connected to the power supply voltage Vdd, a gate connected to the floating diffusion FD, a source connected to the drain of the selection transistor SEL, and a source follower circuit having the constant current source 6 as a load. is doing. The amplification transistor AMP outputs a read current to the vertical signal line 5 via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during a high level period of the selection pulse (control signal) φSEL, and connects the source of the amplification transistor AMP to the vertical signal line 5.

  The vertical scanning circuit 2 outputs the selection pulse φSEL (φSELA, φSELB), the reset pulse φRES (φRESA, φRESB) and the transfer pulse φTX (φTXA, φTXB), respectively.

  By the correlated double sampling, the noise component is removed from the pixel signal on which the noise signal is superimposed. In correlated double sampling, the selection transistor SEL is turned on to perform a source follower operation, and then the dark signal vertical transfer transistor TN is turned on to accumulate a noise signal in the storage capacitor CN. Next, the dark signal vertical transfer transistor TN is turned off, the optical signal vertical transfer transistor TS is turned on, and the transfer transistor TX is turned on, thereby accumulating signals in the storage capacitor CS. Further, both signals accumulated in the storage capacitors CN and CS are read out to the horizontal signal lines 7N and 7S, respectively, by the control signal φH from the horizontal scanning circuit 3, and the difference between the two signals is obtained by the differential output amplifier 8. Thus, correlated double sampling is performed.

  Here, the structure of each unit cell 10 of the solid-state imaging device shown in FIG. 1 will be described with reference to FIGS. FIG. 3 is a schematic plan view showing the 3 × 5 pixels 1 of the solid-state imaging device shown in FIG. 1 in more detail than FIG. In FIG. 3, control lines for supplying the control signals φSELA, φSELB, φRESA, φRESB, φTXA, and φTXB are shown, but a predetermined potential is applied to the vertical signal line 5, the power supply Vdd line, and the P-type impurity diffusion region 28. Wiring for supplying is omitted. FIG. 4 is a diagram illustrating a part (two unit cells 10) in FIG. FIG. 5 is a schematic cross-sectional view along the line A-A ′ in FIGS. 3 and 4. FIG. 6 is a schematic cross-sectional view along the line B-B ′ in FIGS. 3 and 4. In practice, a color filter and a microlens are arranged above the photodiode PD, but are omitted here.

  In the present embodiment, a P-type well 22 is provided on an N-type silicon substrate 21, and each element in the pixel portion such as a photodiode PD is disposed in the P-type well 22. Each pixel 1 is separated by a thick silicon oxide film 23 formed by LOCOS and an isolation diffusion (not shown) arranged therebelow if necessary. A region where the thick silicon oxide film 23 is not formed becomes an active region.

  4 to 6, reference numerals 30 to 35 denote N-type impurity diffusion regions which are part of the above-described transistors. Reference numerals 36a, 36b, 38 to 40 are gate electrodes of the respective transistors made of polysilicon. Reference numeral 33 denotes a power supply diffusion unit to which the power supply voltage Vdd is applied. The diffusion regions 30, 31, and 32 are connected by the wiring 41 and constitute one floating diffusion FD as a whole. This floating diffusion FD is shared by the two pixels 1 of one unit cell 10. A control wiring for applying a control signal φTXA or φTXB from the vertical scanning circuit 2 is connected to the gate electrodes 36a and 36b. A control wiring for applying a control signal φRESA or φRESB from the vertical scanning circuit 2 is connected to the gate electrode 38. A control wiring for applying a control signal φSELA or φSELB from the vertical scanning circuit 2 is connected to the gate electrode 40.

  As shown in FIG. 5, the photodiodes PD1 and PD2 are embedded with an N-type charge storage layer 25 provided in a P-type well 22 and a P-type depletion prevention layer 26 disposed on the surface side thereof. Type photodiode. However, the photodiodes PD1 and PD2 may be photodiodes without a depletion prevention layer. The photodiodes PD1 and PD2 photoelectrically convert incident light and store the generated charges in the charge storage layer 25. The charges accumulated in the charge accumulation layer 25 of the photodiodes PD1 and PD2 are transferred to the floating diffusion FD when the corresponding transfer transistors TX1 and TX2 are turned on.

  The transfer transistors TX1 and TX2 are MOS transistors having the charge storage layer 25 of the corresponding photodiodes PD1 and PD2 as a source and the N-type impurity diffusion region 30 or 31 constituting a part of the floating diffusion FD as a drain. The transfer transistors TX1 and TX2 are driven by a control signal φTXA or φTXB applied to the gate 36 thereof.

  The amplification transistor AMP is a MOS transistor having the power supply diffusion portion 33 as a drain and the diffusion region 34 as a source. The gate electrode 39 of the amplification transistor AMP is electrically connected to the floating diffusion FD by a wiring 41. The charges transferred from the photodiodes PD1 and PD2 to the floating diffusion FD via the transfer transistors TX1 and TX2 are converted into a voltage by the floating diffusion FD, and this voltage is applied to the gate electrode 39 of the amplification transistor AMP. The amplification transistor AMP outputs an electrical signal corresponding to the voltage of the gate electrode 39. Therefore, the amplification transistor AMP outputs an electrical signal (pixel signal) corresponding to the amount of charges generated and accumulated by the photodiodes PD1 and PD2.

  The selection transistor SEL is a MOS transistor having the diffusion region 34 as a drain and the diffusion region 35 as a source. Although not shown in FIGS. 3 and 4, the diffusion region 35 is connected to the vertical signal line 5 for each column. When the selection transistor SEL is turned on, the output of the amplification transistor AMP is output to the vertical signal line 5. That is, reading by the source follower is possible by the amplification transistor AMP and the selection transistor SEL.

  The reset transistor RES is a MOS transistor having the power supply diffusion portion 33 as a drain and the floating diffusion 32 as a source. The reset transistor RES resets the electric charge accumulated in the floating diffusion FD by being turned on.

  As can be seen from the above description, in the present embodiment, in each unit cell 10, the upper pixel 1 is provided with the photodiode PD1 and the transfer transistor TX1, and the lower pixel 1 is provided with the photodiode PD2 and the transfer. A transistor TX2 is provided, which is not shared by the two pixels 1. On the other hand, for each unit cell 10, two pixels 1 belonging to the unit cell 10 share a set of floating diffusion FD, amplification transistor AMP, reset transistor RES, and selection transistor SEL.

  As described above with reference to FIG. 2, as can be seen from FIG. 3, the unit cells 10 adjacent to each other in the row direction can be arranged in the column direction by one column pitch of the photodiode PD. It is shifted. As a result, as shown in FIG. 3, the positional relationship of the other elements such as the transistors SEL, AMP, and RES around the photodiode PD (optical positional relationship related to sensitivity) is set between Gb pixels and Gr pixels. In other words, the Gb pixel and the Gr pixel can be made exactly the same. Therefore, according to the present embodiment, the sensitivity shift between the Gb pixel and the Gr pixel can be greatly reduced.

  In the present embodiment, as shown in FIGS. 3 and 4, for each unit cell 10, the reset transistor RES, the amplification transistor AMP, and the selection transistor SEL are arranged in a straight line in the row direction. Both the drain and the drain of the reset transistor RES serve as a power supply diffusion unit 33, and both are made common. On the other hand, in the conventional solid-state imaging device disclosed in Patent Document 1, in order to realize the above-described translational symmetrical arrangement, the amplification transistor and the selection transistor are arranged adjacent to each other, but the reset transistor is located at a separate location. Is arranged. Therefore, in this conventional solid-state imaging device, the drain of the amplification transistor AMP and the drain of the reset transistor RES are inevitably shared, and these drains are provided separately. On the other hand, in the present embodiment, since the drain of the amplification transistor AMP and the drain of the reset transistor RES are shared as described above, the area for one drain is not required, and the conventional solid-state imaging device is not necessary. As compared with the above, the aperture ratio of the photodiode PD can be increased. However, in the present invention, the drain of the amplification transistor and the drain of the reset transistor are not necessarily shared. For example, the transistors RES, AMP, and SEL may be arranged in a straight line in the column direction.

  In the present embodiment, as shown in FIG. 3, the transistors RES, AMP, and SEL shared by the two pixels 1 in each unit cell 10 are arranged in a column in which the photodiodes PD of the unit cells 10 are arranged. It is formed in a region protruding from the region in the row direction.

  In the present embodiment, in each of the transistors TX1, TX2, RES, AMP, SEL, and AMP, the diffusion layers (source and drain) adjacent to the gate electrodes 36a, 36b, and 38 to 40 alleviate the electric field in the vicinity of the drain. In addition, it has a so-called LDD (Lightly Doped Drain) structure. 5 and 6, reference numerals 30a, 31a, 32a, 33a, 34a, and 35a denote low impurity concentration N-type diffusion regions that constitute the LDD structure. Note that the scope of application of the present invention is not limited to a transistor structure having an LDD structure. For example, the present invention may be applied to a solid-state imaging device in which a transistor having a single drain structure and a double drain structure is formed.

  3 and 6, reference numeral 28 denotes a high impurity concentration P-type impurity diffusion region for supplying a predetermined potential to the P-type well 22. Although not shown in the drawing, the P-type impurity diffusion region 28 is connected to a wiring for supplying a predetermined potential. Although not shown in the drawing, a dummy pixel having the same structure as that of the pixel 1 is provided around the effective pixel region as necessary.

  FIG. 7 is a timing chart showing an example of the reading operation of the solid-state imaging device according to the present embodiment.

  In this embodiment, after a mechanical shutter (not shown) is opened for a predetermined exposure period and charges are accumulated in the charge accumulation layer of the photodiode PD of each pixel 1, the readout operation of each pixel row is the same in order. Will be done. FIG. 7 shows operations after reading out the pixels 1 on the lower side of the n-th row in FIGS. 1 and 3. In FIG. 7, periods T1 and T2 are readout periods for the pixels 1 on the lower side of the nth row, periods T3 and T4 are readout periods for the pixels 1 on the upper side of the nth row, and periods T5 and T6 are readouts of the pixels 1 on the lower side of the (n + 1) th row. The periods T7 and T8 indicate the readout period of the pixel 1 on the upper side of the (n + 1) th row.

  In the period T1, the reset pulses φRESA (n) and φRESB (n) in the nth row change to a low level, and the corresponding reset transistor RES is turned off. In the period T1, the vertical scanning circuit 2 changes the selection pulses φSELA (n) and φSELB (n) of the n-th row to a high level, and the corresponding selection transistor SEL is turned on. When the selection transistor SEL is turned on, the source of the corresponding amplification transistor AMP is connected to the vertical output line 5. The amplification transistor AMP operates as a source follower circuit by the constant current source 6.

  After the period T1 starts, in the period T11, the noise transfer pulse φTN changes to a high level, the dark signal vertical transfer transistor TN is turned on, and a noise signal (dark signal) corresponding to the reset state is input to the dark signal storage capacitor CN. Accumulated. This operation is executed simultaneously in parallel for all the pixels 1 on the lower side of the nth row. Thereafter, in the period T12, the transfer pulse φTXB (n) on the lower side of the nth row changes to a high level, and the lower transfer transistor TX on the nth row is turned on. When the transfer transistor TX on the lower side of the n-th row is turned on, the signal charge photoelectrically converted and accumulated by the photodiode PD on the lower side of the n-th row is transferred to the corresponding floating diffusion FD. As a result, the voltage of the floating diffusion FD becomes a voltage corresponding to the transferred charge amount, and this voltage is applied to the gate electrode 39 of the amplification transistor AMP.

  Next, in the period T13 within the period T1, the optical signal transfer pulse φTS changes to a high level, the optical signal vertical transfer transistor TS is turned on, and the optical signal is stored in the optical signal storage capacitor CS. This operation is executed simultaneously in parallel for all the pixels 1 on the lower side of the nth row.

  In the period T2 after the period T1, the horizontal transfer transistors HS and HN are sequentially turned on for each column by the horizontal scanning by the control signal φH from the horizontal scanning circuit 3, and the optical signal and the dark signal stored in the storage capacitors CS and CN are stored. Are sequentially read out to the horizontal signal lines 7S and 7N for each column, and the difference between these signals is taken by the differential output amplifier 8 and outputted to the outside. By taking the difference in this way, correlated double sampling is realized, and the noise component is removed from the pixel signal on which the noise signal is superimposed.

  Next, readout of the pixel 1 on the upper side of the n-th row starts from the period T3 after the period T2.

  In the period T3, the reset pulse φRESA (n) in the nth row and the reset pulse φRESB (n + 1) in the n + 1th row are changed to a low level, and the corresponding reset transistor RES is turned off. In the period T3, the vertical scanning circuit 2 changes the selection pulse φSELA (n) in the nth row and the selection pulse φSELB (n + 1) in the n + 1th row to high level, and the corresponding selection transistor SEL is turned on. When the selection transistor SEL is turned on, the source of the corresponding amplification transistor AMP is connected to the vertical output line 5. The amplification transistor AMP operates as a source follower circuit by the constant current source 6.

  After the period T3 starts, in the period T14, the noise transfer pulse φTN changes to a high level, the dark signal vertical transfer transistor TN is turned on, and the noise signal (dark signal) corresponding to the reset state is input to the dark signal storage capacitor CN. Accumulated. This operation is executed simultaneously in parallel for all the pixels 1 on the upper side of the nth row. Thereafter, in the period T15, the transfer pulse φTXA (n) on the upper side of the nth row changes to a high level, and the transfer transistor TX on the upper side of the nth row is turned on. When the transfer transistor TX on the upper side of the n-th row is turned on, the signal charge photoelectrically converted and accumulated by the photodiode PD on the upper side of the n-th row is transferred to the corresponding floating diffusion FD. As a result, the voltage of the floating diffusion FD becomes a voltage corresponding to the transferred charge amount, and this voltage is applied to the gate electrode 39 of the amplification transistor AMP.

  Next, in a period T16 within the period T3, the optical signal transfer pulse φTS changes to a high level, the optical signal vertical transfer transistor TS is turned on, and the optical signal is stored in the optical signal storage capacitor CS. This operation is executed simultaneously in parallel for all the pixels 1 on the upper side of the nth row.

  In the period T4 after the period T3, the horizontal transfer transistors HS and HN are sequentially turned on for each column by the horizontal scanning by the control signal φH from the horizontal scanning circuit 3, and the optical signal and the dark signal stored in the storage capacitors CS and CN are turned on. Are sequentially read out to the horizontal signal lines 7S and 7N for each column, and the difference between these signals is taken by the differential output amplifier 8 and outputted to the outside. By taking the difference in this way, correlated double sampling is realized, and the noise component is removed from the pixel signal on which the noise signal is superimposed.

  The same operation as described above is repeated after the period T4 and after the period T5.

  According to the present embodiment, since the two pixels 1 share the transistors SEL, AMP, and RES in each unit cell 10, a high aperture ratio can be maintained. According to the present embodiment, as described above, the unit cells 10 that are adjacent to each other in the row direction are shifted in the column direction by one pitch of the photodiode PD in the column direction. As shown in FIG. 3, the positional relationship (optical positional relationship related to sensitivity) of other elements such as the peripheral transistors SEL, AMP, and RES with respect to the photodiode PD is not only between Gb pixels and Gr pixels. The Gb pixel and the Gr pixel can be made exactly the same, and this can greatly reduce the sensitivity shift between the Gb pixel and the Gr pixel.

  FIG. 8 is a schematic plan view schematically showing an arrangement state of the unit cells 10 of the solid-state imaging device according to the comparative example compared with the present embodiment, and corresponds to FIG. In FIG. 8, the same or corresponding elements as those in FIG. 2 are denoted by the same reference numerals, and redundant description thereof is omitted. In this comparative example, unlike the above-described conventional solid-state imaging device, the unit cells 10 adjacent to each other in the row direction are not displaced in the column direction and are arranged at exactly the same column direction positions, unlike the present embodiment. ing. Therefore, in this comparative example, the positional relationship (optical positional relationship regarding sensitivity) of other elements such as the peripheral transistors SEL, AMP, and RES with respect to the photodiode PD is exactly the same between the Gb pixel and the Gr pixel. Therefore, the sensitivity shift between the Gb pixel and the Gr pixel becomes large.

  According to the present embodiment, as described above, by sharing transistors and the like among the plurality of pixels 1, the sensitivity deviation between the Gb pixel and the Gr pixel can be greatly reduced while maintaining a high aperture ratio. Therefore, a solid-state imaging device with high sensitivity and good color reproducibility can be realized.

  [Second Embodiment]

  FIG. 9 is a schematic plan view schematically showing 3 × 5 pixels 1 of the solid-state imaging device according to the second embodiment of the present invention, and corresponds to FIG. 10 is a schematic cross-sectional view taken along the line C-C ′ in FIG. 9 and corresponds to FIG. 6. 9 and 10, elements that are the same as or correspond to those in FIGS. 3 and 6 are given the same reference numerals, and redundant descriptions thereof are omitted.

  This embodiment is different from the first embodiment in that the P-type impurity diffusion region 28 is narrowed, and in each unit cell 10, between the photodiodes PD1 and PD2 adjacent in the column direction, between the two. The only difference is that an N-type impurity diffusion region 50 is formed in the P-type well 22 as a crosstalk reducing portion that reduces charge crosstalk. The N-type impurity diffusion region 50 is connected to the power supply voltage Vdd by a wiring (not shown), and serves as an absorption layer for charges generated inside the silicon. The crosstalk reducing unit is not limited to such a diffusion region 50.

  According to the present embodiment, the same advantages as those of the first embodiment can be obtained, and the N-type impurity diffusion region 50 is disposed between the photodiodes PD1 and PD2, and therefore, between the photodiodes PD1 and PD2. The crosstalk can be reduced and color mixing can be prevented.

  [Third Embodiment]

  FIG. 11 is a schematic plan view schematically showing an arrangement state of the unit cells 10 of the solid-state imaging device according to the third embodiment of the present invention, and corresponds to FIG. FIG. 12 is a schematic plan view showing 3 × 5 pixels 1 of the solid-state imaging device shown in FIG. 11 in more detail than FIG. 11, and corresponds to FIG. FIG. 13 is a diagram illustrating a part (two unit cells 10) in FIG. 12, and corresponds to FIG. 11 to 13, elements that are the same as or correspond to those in FIGS. 2 to 4 are given the same reference numerals, and redundant descriptions thereof are omitted.

  This embodiment is different from the first embodiment in that the transistors RES, AMP, and SEL shared by the two pixels 1 in each unit cell 10 are arranged in a column in which the photodiodes PD of the unit cells 10 are arranged. The only difference is that the arrangement of each part is changed so as to be substantially formed in the inner region.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained. A modification similar to that obtained by modifying the first embodiment to obtain the second embodiment may be applied to the present embodiment.

  [Fourth Embodiment]

  FIG. 14 is a schematic plan view schematically showing an arrangement state of the unit cells 110 of the solid-state imaging device according to the fourth embodiment of the present invention, and corresponds to FIG.

  In the present invention, a plurality of pixels are formed for each of N pixels (N is an integer of 2 or more) in which photoelectric conversion units are sequentially arranged in the column direction, and the N belonging to the unit cell is included in each unit cell. Each pixel shares one set of charge-voltage conversion unit and amplification transistor, and the unit cells adjacent to each other in the row direction have a pitch in the column direction of the photoelectric conversion unit from 1 to N−1. It is only necessary to shift in the column direction by a predetermined number. The first to third embodiments are examples in which the N pieces are two, whereas the present embodiment is an example in which the N pieces are four.

  In the present embodiment, each unit cell 110 includes four pixels 101 in which photodiodes PD1 to PD4 are sequentially arranged in the column direction. Each pixel 101 has the same configuration as that of the pixel 1 described above, but in each unit cell 110, the four pixels 101 include a set of floating diffusion FD, amplification transistor AMP, reset transistor RES, and selection transistor SEL. Share. The photodiode PD and the transfer transistor TX are provided for each pixel 1 without being shared by the four pixels 101. Also in the present embodiment, a color filter arranged according to a Bayer array is provided on the light incident side of the photodiode PD of each pixel 101.

  In this embodiment, the unit cells 110 adjacent to each other in the row direction are shifted in the column direction by one column pitch of the photodiode PD. Thus, as in the first embodiment, the positional relationship (optical positional relationship related to sensitivity) of other elements such as the peripheral transistors SEL, AMP, and RES with respect to the photodiode PD is changed to the Gb pixel. The Gb pixel and the Gr pixel can be exactly the same or close to each other as well as between the Gr pixel and the Gr pixel. This can reduce the sensitivity shift between the Gb pixel and the Gr pixel.

  FIG. 15 is a schematic plan view schematically showing an arrangement state of the unit cells 110 of the solid-state imaging device according to the comparative example compared with the present embodiment, and corresponds to FIG. 15, elements that are the same as or correspond to those in FIG. 14 are given the same reference numerals, and redundant descriptions thereof are omitted. In this comparative example, unlike the above-described conventional solid-state imaging device, the unit cells 110 adjacent to each other in the row direction are not displaced in the column direction and are arranged at exactly the same column direction position, unlike this embodiment. ing. Therefore, in this comparative example, the positional relationship (optical positional relationship regarding sensitivity) of other elements such as the peripheral transistors SEL, AMP, and RES with respect to the photodiode PD is the same between the Gb pixel and the Gr pixel. It cannot be brought closer, and the sensitivity shift between the Gb pixel and the Gr pixel becomes large.

  As can be understood from the comparison of FIG. 14 with FIG. 15, in the present embodiment, at least the Gb pixel having the photodiode PD1 and the Gr pixel having the photodiode PD1 and the Gb pixel having the photodiode PD3. And the Gr pixel having the photodiode PD3 can have the same positional relationship (optical positional relationship with respect to sensitivity) of the peripheral transistors and the like with respect to the photodiode PD. Therefore, according to the present embodiment, it is possible to reduce the sensitivity shift between the Gb pixel and the Gr pixel as compared with the comparative example shown in FIG.

  When the Bayer arrangement is adopted as in the present embodiment, an odd number (for example, 1) of the pitch in the column direction of the photodiodes PD between the unit cells 110 adjacent to each other in the row direction. It is only necessary to shift in the column direction.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

1 is a circuit diagram illustrating a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a schematic plan view schematically showing an abstracted arrangement state of unit cells of the solid-state imaging device shown in FIG. 1. FIG. 2 is a schematic plan view schematically showing 3 × 5 pixels of the solid-state imaging device shown in FIG. 1. It is a figure which extracts and shows a part in FIG. FIG. 5 is a schematic cross-sectional view along the line A-A ′ in FIGS. 3 and 4. FIG. 5 is a schematic cross-sectional view taken along line B-B ′ in FIGS. 3 and 4. 2 is a timing chart illustrating an example of a reading operation of the solid-state imaging device illustrated in FIG. 1. It is a schematic plan view which abstracts and shows typically the arrangement | positioning condition of the unit cell of the solid-state image sensor by the comparative example compared with the 1st Embodiment of this invention. It is a schematic plan view which shows typically 3 * 5 pixel of the solid-state image sensor by the 2nd Embodiment of this invention. FIG. 10 is a schematic cross-sectional view taken along line C-C ′ in FIG. 9. It is a schematic plan view which abstracts and shows typically the arrangement | positioning condition of the unit cell of the solid-state image sensor by the 3rd Embodiment of this invention. FIG. 12 is a schematic plan view schematically showing 3 × 5 pixels 1 of the solid-state imaging device shown in FIG. 11. It is a figure which extracts and shows a part in FIG. It is a schematic plan view which abstracts and shows typically the arrangement state of the unit cell of the solid-state image sensor by the 4th Embodiment of this invention. It is a schematic plan view which abstracts and shows typically the arrangement | positioning condition of the unit cell of the solid-state image sensor by the comparative example compared with the 4th Embodiment of this invention.

Explanation of symbols

PD1, PD2 Photodiode AMP Amplifying transistor RES Reset transistor TX1, TX2 Transfer transistor SEL Select transistor FD Floating diffusion 10,110 Unit cell

Claims (12)

A photoelectric conversion unit that generates and accumulates signal charge according to incident light, a charge-voltage conversion unit that receives the signal charge and converts the signal charge into voltage, and an amplifier that outputs a signal according to the potential of the charge-voltage conversion unit A plurality of pixels having a transistor and a transfer transistor that transfers charges from the photoelectric conversion unit to the charge-voltage conversion unit,
The plurality of pixels are two-dimensionally arranged;
A solid-state imaging device having a vertical signal line to which the output of the pixel for each column is supplied,
The plurality of pixels form a unit cell for each of N pixels (N is an integer of 2 or more) in which the photoelectric conversion units are sequentially arranged in a column direction,
For each unit cell, the N pixels belonging to the unit cell share a set of the charge-voltage converter and the amplification transistor,
The unit cells adjacent to each other in the row direction are shifted in the column direction by a predetermined number of 1 to N−1 pitches in the column direction of the photoelectric conversion units. A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the plurality of pixels are provided with color filters arranged according to a Bayer arrangement.   The solid-state imaging device according to claim 1, wherein the N is an even number, and the predetermined number is an odd number.   4. The solid-state imaging device according to claim 1, wherein gates of the transfer transistors of the plurality of pixels are electrically connected to each pixel row in common. 5. The pixel includes a reset transistor that resets the potential of the charge-voltage converter and a selection transistor for selecting the pixel.
5. The solid-state imaging device according to claim 1, wherein for each unit cell, the N pixels belonging to the unit cell share a set of the reset transistor and the selection transistor.   6. The solid-state imaging device according to claim 5, wherein a drain of the amplification transistor and a drain of the reset transistor are made common for each unit cell. The gates of the reset transistors of the unit cells in different columns shifted from each other in the column direction are separately wired independently of each other electrically,
7. The solid-state imaging device according to claim 5, wherein the gates of the selection transistors of the unit cells in different columns shifted from each other in the column direction are separately wired independently from each other.   The amplification transistor, the reset transistor, and the selection transistor shared by the N pixels belonging to the unit cell are arranged in a straight line for each unit cell. The solid-state imaging device described.   The transistor shared by the N pixels in each unit cell is formed in a region protruding in a row direction from a region in a column in which the photoelectric conversion units of the unit cell are arranged. The solid-state imaging device according to claim 1.   9. The transistor according to claim 1, wherein the transistor shared by the N pixels in each unit cell is substantially formed in a region in a column in which the photoelectric conversion units of the unit cell are arranged. The solid-state image sensor in any one.   11. The crosstalk reducing unit for reducing crosstalk of electric charges between the photoelectric conversion units of the pixels adjacent in the column direction is formed in each unit cell. The solid-state image sensor in any one. Comprising a first semiconductor layer of a first conductivity type;
The photoelectric conversion units of the plurality of pixels have a second conductivity type charge storage layer provided in the first semiconductor layer,
The solid-state imaging device according to claim 11, wherein the crosstalk reducing unit includes the second conductivity type semiconductor region formed in the first semiconductor layer and applied with a predetermined potential.

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