JP2008305983A - Solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To adjust a signal level at a high SN ratio. <P>SOLUTION: The solid-state imaging element is provided with a plurality of pixels. The pixel is provided with a photodiode PD for generating and storing signal charges corresponding to incident light, a floating capacitance part FC for receiving the signal charges and converting the signal charges to a voltage, an amplifier transistor AMP for outputting signals corresponding to the potential of the floating capacitance part FC, a transfer transistor TX for transferring the charges from the photodiode PD to the floating capacitance part FC, and a reset transistor for resetting the potential of the floating capacitance part. The floating capacitance part FC is a variable capacitance part where a capacitance value is changed corresponding to supplied control signals ϕVg. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  Video cameras, electronic still cameras, and the like have a CCD solid-state image sensor and an amplification solid-state image sensor. In these solid-state imaging devices, a plurality of pixels having photoelectric conversion units are arranged in a matrix, and signal charges are generated in the photoelectric conversion units of the respective pixels. In the amplification type solid-state imaging device, the signal charge generated and accumulated in the photoelectric conversion unit of the pixel is guided to the floating diffusion, the signal charge is converted into a voltage by the floating diffusion, and a signal corresponding to the voltage is provided in the pixel. Output from the pixel by the amplification transistor.

  In an amplification type solid-state imaging device, each pixel generally includes a photoelectric conversion unit that generates and accumulates signal charges according to incident light, a floating diffusion that receives the signal charges and converts the signal charges into voltage, and the floating An amplification transistor that outputs a signal corresponding to the potential of the diffusion, a transfer transistor that transfers charges from the photoelectric conversion unit to the floating diffusion, and a reset transistor that resets the potential of the floating diffusion (for example, The following patent documents 1, 2).

  In the amplification type solid-state imaging device disclosed in Patent Document 1, not only a photoelectric conversion unit and a transfer transistor but also a set of a floating diffusion, an amplification transistor, and a reset transistor are provided for each pixel. Therefore, since the amplification type solid-state imaging device disclosed in Patent Document 1 has a large number of transistors, the area for the photoelectric conversion unit is narrowed and the aperture ratio is reduced.

  Therefore, in the amplification type solid-state imaging device disclosed in Patent Document 2, a plurality of pixels share one set of floating diffusion, amplification transistor, and reset transistor. For this reason, the number of transistors per pixel can be reduced, and the aperture ratio can be increased. When the aperture ratio is large, a lot of charges are handled, and the SN ratio is improved.

In these conventional amplifying solid-state imaging devices, the capacitance value of the floating diffusion is fixed to a constant value regardless of whether or not the transistors and the floating diffusion are shared by a plurality of pixels. The amplification transistor of the pixel is not a variable gain amplifier but a fixed gain amplifier.
JP-A-11-122532 JP 2006-73733 A

  As described above, in the conventional solid-state imaging device, since the capacitance value of the floating diffusion is fixed to a constant value and the amplification transistor of the pixel is a gain fixing amplifier, the conversion gain of each pixel (elementary charge received by the floating diffusion) The ratio of the output value of the amplification transistor to the fixed value) is a fixed value, and the conversion gain cannot be adjusted.

  Therefore, in the conventional solid-state imaging device described above, when adjusting the level of the signal to be obtained, the pixel output is amplified by the signal processing circuit at the subsequent stage. In this case, since noise components such as noise of the pixel amplification transistor and reset noise are also amplified by the signal processing circuit, the SN ratio of the obtained signal is lowered.

  For example, in the above-described conventional solid-state imaging device, when the difference in RGB sensitivity is compensated and the signal levels are made uniform, the signal-to-noise ratio of the signal obtained with respect to any one of RGB pixels with low sensitivity has been lowered. That is, in the solid-state imaging device, the RGB sensitivities are different. Therefore, even if the incident light amounts of the corresponding colors for the pixels of each color are the same, the amount of signal charge generated and accumulated in the photoelectric conversion unit of each color pixel is the same. Different. Therefore, in order to prevent the signal of a specific pixel from being saturated by the signal processing circuit, the conversion gain of any pixel is set in accordance with a pixel having a high sensitivity, that is, a pixel having a large number of generated charges for the same incident light amount. They are set the same. Therefore, for the same incident light quantity, the output level of a pixel with a low sensitivity is lower than the output of a pixel with a high sensitivity. In order to compensate for this and make the signal level uniform, the output of the pixel of low sensitivity is amplified by the signal processing circuit. As a result, for a pixel with low sensitivity, noise components such as noise of the amplification transistor and reset noise of the pixel are also amplified by the signal processing circuit, so the signal-to-noise ratio of the obtained signal was reduced. is there.

  Further, for example, in the conventional solid-state imaging device described above, when performing high-sensitivity shooting without using a strobe in a room or at night, the pixel output of each pixel is amplified with a large gain by a signal processing circuit in the subsequent stage. Therefore, noise components such as pixel amplification transistor noise and reset noise are also amplified by the signal processing circuit, so that the signal-to-noise ratio of the obtained signal is reduced, and high-sensitivity imaging with less noise can be performed. There wasn't.

  Furthermore, for example, in the conventional solid-state imaging device described above, when performing auto, preset, and manual white balance, the pixel output of each color pixel is amplified by each gain necessary for white balance in the signal processing circuit in the subsequent stage. To do. In this case, since noise components such as noise of the amplification transistor and reset noise of each pixel are also amplified by the signal processing circuit, the S / N ratio of the obtained signal is lowered.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a solid-state imaging device capable of adjusting a signal level with a high SN ratio.

  In order to solve the above problems, the solid-state imaging device according to the first aspect of the present invention includes a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and receives the signal charges and converts the signal charges into a voltage. A floating capacitor, an amplifying transistor that outputs a signal corresponding to the potential of the floating capacitor, a transfer transistor that transfers charge from the photoelectric converter to the floating capacitor, and a reset transistor that resets the potential of the floating capacitor The floating capacitance unit is a variable capacitance unit whose capacitance value changes according to a supplied control signal.

  In the solid-state imaging device according to the second aspect of the present invention, in the first aspect, the floating capacitor includes a MOS capacitor having a gate electrode that receives the control signal.

  The solid-state imaging device according to a third aspect of the present invention is the solid-state imaging device according to the second aspect, wherein the pixel has a selection transistor for selecting the pixel, and the gate electrode of the selection transistor is commonly used for each row. The gate electrodes of the MOS capacitors are electrically connected in common for each column.

  In the solid-state imaging device according to the fourth aspect of the present invention, in the second or third aspect, the floating capacitor portion is adjacent to a semiconductor region constituting the MOS capacitor below the gate electrode of the MOS capacitor. And a diffusion capacitor constituted by diffusion regions arranged in a row.

  A solid-state imaging device according to a fifth aspect of the present invention is the solid-state imaging device according to the fourth aspect, wherein the floating capacitor section has an MIM capacitor (Metal-Insulator-) having an electrode electrically connected to the diffusion region of the diffusion capacitor. Metal).

  In the solid-state imaging device according to a sixth aspect of the present invention, in any one of the second to fifth aspects, the floating capacitor portion is a semiconductor region constituting the MOS capacitor below the gate electrode of the MOS capacitor. And a floating diffusion that is disposed adjacent to and electrically connected to the gate electrode of the amplification transistor.

  The solid-state imaging device according to a seventh aspect of the present invention is the solid-state imaging device according to the sixth aspect, wherein the impurity concentration of the semiconductor region constituting the MOS capacitor is the floating region from the floating diffusion side to the opposite side of the semiconductor region. It is changed stepwise or continuously so that the diffusion side is relatively low.

  In the solid-state imaging device according to the eighth aspect of the present invention, in any one of the first to seventh aspects, the predetermined number of pixels is 1 for every two or more predetermined numbers of the plurality of pixels. A set of the floating capacitor, the amplification transistor, and the reset transistor are shared.

  The solid-state imaging device according to a ninth aspect of the present invention is the solid-state imaging device according to any one of the second to seventh aspects, wherein (i) the pixel has a selection transistor for selecting the pixel, and (ii) the For every two pixels of the plurality of pixels, the two pixels share one set of the floating capacitor, the amplification transistor, the reset transistor, and the selection transistor, and (iii) of the two pixels The positional relationship between the gate electrodes of the selection transistor and the amplification transistor shared by the two pixels with respect to the photoelectric conversion unit of one pixel, and the photoelectric conversion unit of the other pixel of the two pixels The positional relationship between the gate electrodes of the reset transistor and the MOS capacitor shared by the two pixels is substantially the same. A.

  A solid-state imaging device according to a ninth aspect of the present invention is the solid-state imaging device according to any one of the first to ninth aspects, wherein the plurality of pixels are divided into a plurality of groups, and color filters having different colors are provided for each group. A control unit that supplies the control signal to the floating capacitance units of the plurality of pixels, and the control unit has a capacitance value of a floating capacitance unit of a pixel provided with a color filter of the same color from the pixel. The control signal is supplied so that the capacitance values are substantially the same when the signal is read out.

  The solid-state imaging device according to an eleventh aspect of the present invention is the solid-state imaging device according to the tenth aspect, wherein the control unit has the same amount of incident light of the corresponding color with respect to the pixel provided with the color filter of each color. The control signal is supplied so that the outputs of the pixels provided with the color filters are substantially the same.

  It is possible to provide a solid-state imaging device capable of performing signal level adjustment with a high S / N ratio.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a circuit diagram showing a schematic configuration of a solid-state imaging device according to the first embodiment of the present invention. The solid-state imaging device according to the present embodiment is formed as a CMOS type solid-state imaging device on a silicon substrate using a CMOS process, and is mounted on, for example, a digital still camera or a video camera.

  The solid-state imaging device according to the present embodiment includes a plurality of unit pixels 1 (only 3 × 3 pixels 1 are shown in FIG. 1) arranged in a two-dimensional manner, a vertical scanning circuit 2, and a horizontal scanning circuit. 3, floating capacitance control circuit 4, vertical signal line 5 provided for each column of pixel 1, constant current source 6 connected to each vertical signal line 5, and optical information photoelectrically converted by pixel 1 A first horizontal signal line 7S for transmitting an optical signal including a second horizontal signal line 7N for transmitting a so-called dark signal as a differential signal including a noise component to be subtracted from the optical signal, and a differential output amplifier 8 and. Needless to say, the number of pixels 1 is not limited.

  Further, the solid-state imaging device according to the present embodiment corresponds to each column of the pixels 1, the optical signal storage capacitor CS that stores the optical signal, the dark signal storage capacitor CN that stores the dark signal, and the optical signal vertical transfer. The transistor TS, the dark signal vertical transfer transistor TN, the optical signal horizontal transfer transistor HS, and the dark signal horizontal transfer transistor HN are included. Actually, each transistor for resetting the horizontal signal lines 7S and 7N at a predetermined timing is provided, but the illustration of these transistors is omitted.

  In the present embodiment, each pixel 1 includes a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and a floating capacitance unit that receives the signal charges and converts the signal charges into a voltage. FC, an amplification transistor AMP that outputs a signal corresponding to the potential of the floating capacitor portion FC, a transfer transistor TX that transfers charges from the photodiode PD to the floating capacitor portion FC, and a reset transistor that resets the potential of the floating capacitor portion FC RES and a selection transistor SEL for selecting the pixel 1 are connected as shown in FIG. In the present embodiment, the transistors AMP, TX, RES, and SEL of the pixel 1 are all nMOS transistors.

  The gate of the transfer transistor TX is connected to a control line for supplying the control signal φTX for controlling the transfer transistor TX from the vertical scanning circuit 2 to the transfer transistor TX for each row. The gate of the reset transistor RES is connected to a control line for supplying a control signal φRES for controlling the reset transistor RES from the vertical scanning circuit 2 to the reset transistor RES for each row. The gate of the selection transistor SEL is connected to a control line for supplying the control signal φSEL for controlling the selection transistor SEL from the vertical scanning circuit 2 to the selection transistor SEL for each row. In FIG. 1, Vdd is a power supply voltage.

  The floating capacitor portion FC has a gate electrode 37 (a gate electrode 37 of a MOS capacitor MC described later, see FIGS. 2 and 3), and is supplied from the floating capacitor control circuit 4 to the gate electrode 37. This is a variable capacitance section whose capacitance value changes according to the control signal φVg. A specific structure of the floating capacitor unit FC will be described in detail later. In the present embodiment, the gate electrode 37 of the floating capacitor unit FC is connected to the control line 9 that supplies the control signal φVg from the floating capacitor control circuit 4 to the gate electrode 37 for each column. In the present embodiment, the control signal φVg is output as a voltage pulse from the floating capacitance control circuit 4, and the control signal φVg is applied to the gate electrode 37 of the floating capacitance section FC. By this control signal φVg, the capacitance value of the floating capacitor portion FC is adjusted, and consequently, the conversion gain of the pixel 1 (ratio of the output value of the amplification transistor AMP to the elementary charge received by the floating capacitor portion FC) is adjusted. When the capacitance value of the floating capacitor portion FC is C, the elementary charge is q, and the source follower gain by the amplification transistor AMP is Gsf, the conversion gain G of the pixel 1 is represented by G = Gfs · q / C. The conversion gain G of each pixel 1 can be freely adjusted by selecting the pixel 1 by a combination of the selection transistor pulse φSEL and the control signal φVg.

  The photodiode PD generates a signal charge according to the amount of incident light (subject light). The transfer transistor TX is turned on during a high level period of the transfer pulse (control signal) φTX, and transfers the signal charge accumulated in the photodiode PD to the floating capacitor unit FC. The reset transistor RES is turned on during a high level period of the reset pulse (control signal) φRES to reset the floating capacitor unit FC.

  The amplification transistor AMP has a drain that is connected to the power supply voltage Vdd, a gate that is connected to the floating capacitor FC, a source that is connected to the drain of the selection transistor SEL, and a force follower circuit that uses the constant current source 6 as a load. It is composed. The amplification transistor AMP outputs a read current to the vertical signal line 5 via the selection transistor SEL according to the voltage value of the floating capacitor unit FC. The selection transistor SEL is turned on during a high level period of the selection pulse (control signal) φSEL, and connects the source of the amplification transistor AMP to the vertical signal line 5.

  The vertical scanning circuit 3 outputs a selection pulse φSEL, a reset pulse φRES, and a transfer pulse φTX for each row of the pixels 1.

  By the correlated double sampling, the noise component is removed from the pixel signal on which the noise signal is superimposed. In correlated double sampling, the selection transistor SEL is turned on to perform a source follower operation, and then the dark signal vertical transfer transistor TN is turned on to accumulate a noise signal in the storage capacitor CN. Next, the dark signal vertical transfer transistor TN is turned off, the optical signal vertical transfer transistor TS is turned on, and the transfer transistor TX is turned on, thereby accumulating signals in the storage capacitor CS. Further, both signals accumulated in the storage capacitors CN and CS are read out to the horizontal signal lines 7N and 7S, respectively, by the control signal φH from the horizontal scanning circuit 3, and the difference between the two signals is obtained by the differential output amplifier 8. Thus, correlated double sampling is performed.

  Here, the structure of each pixel 1 of the solid-state imaging device shown in FIG. 1 will be described with reference to FIGS. FIG. 2 is a schematic plan view schematically showing 2 × 2 pixels 1 of the solid-state imaging device shown in FIG. In FIG. 2, the control wiring for supplying the control signals φSEL, φRES, and φTX and the wiring for the power supply Vdd are omitted. FIG. 3 is a schematic cross-sectional view along the line A-A ′ in FIG. 2. In practice, a color filter and a microlens are arranged above the photodiode FD, but are omitted here. However, the present invention can also be applied to a so-called black and white solid-state imaging device, and in that case, no color filter is provided. In FIG. 3, in order to facilitate understanding of the connection relationship, a photodiode PD or the like that does not appear in the cross section along the line A-A ′ in FIG. 2 is also shown as a circuit diagram. This also applies to FIGS. 6, 7, 9, 11, 14, and 15 described later.

  In the present embodiment, a system using R, G, and B is employed as a combination of color filters, and a Bayer array is employed. However, a stripe arrangement or the like may be employed, or a complementary color system (for example, a system using magenta, green, cyan, and yellow) may be employed.

  In the present embodiment, a P-type well 22 is provided on an N-type silicon substrate 21, and each element in the pixel portion such as a photodiode PD is disposed in the P-type well 22. Each pixel 1 is separated by a thick silicon oxide film 23 formed by LOCOS and an isolation diffusion (not shown) arranged therebelow if necessary. A region where the thick silicon oxide film 23 is not formed becomes an active region.

  2 and 3, reference numerals 31 to 35 denote N-type impurity diffusion regions which are part of the above-described transistors. Reference numerals 36 and 38 to 40 denote gate electrodes of the respective transistors made of polysilicon. Reference numeral 37 denotes a gate electrode of a MOS capacitor MC made of polysilicon. Reference numeral 33 denotes a power supply diffusion unit to which the power supply voltage Vdd is applied, and reference numerals 31 and 32 denote floating diffusions constituting a part of the floating capacitor unit FC. The gate electrodes 36, 38 and 40 are respectively connected to a control wiring (not shown), and control signals φTX, φRES and φSEL output from the vertical scanning circuit 2 are applied thereto. The gate electrode 37 of the MOS capacitor MC is connected to the control wiring 9, and the control signal φVg is applied from the floating capacitor control circuit 4.

  Although not shown in the drawing, the photodiode PD is an embedded photodiode composed of an N-type charge storage layer provided in the P-type well 22 and a P-type depletion prevention layer disposed on the surface side thereof. is there. However, the photodiode PD may be a photodiode without a depletion prevention layer. The photodiode PD photoelectrically converts incident light and accumulates the generated charges in the charge accumulation layer. The charges accumulated in the charge accumulation layer of the photodiode PD are transferred to the floating capacitor unit FC when the transfer transistor TX is turned on.

  The transfer transistor TX is a MOS transistor having the charge storage layer of the photodiode PD as a source and the floating diffusion 31 constituting a part of the floating capacitor portion FC as a drain. The transfer transistor TX is driven by a control signal φTX applied to its gate 36.

  The floating capacitor unit FC includes floating diffusions 31 and 32 and a MOS capacitor MC. More specifically, the floating capacitance portion FC includes the capacitance of the wiring 41 and the gate electrode 39 of the amplification transistor AMP. The floating diffusion 31 and the floating diffusion 32 are electrically connected by a wiring 41. The floating diffusions 31 and 32 are electrically connected to the gate electrode 39 of the amplification transistor AMP by the wiring 41. The MOS capacitor MC includes a P-type well region (P-type semiconductor region) adjacent to the floating diffusion 32 and a gate electrode 37 formed on the P-type semiconductor region via a relatively thin oxide film (insulating film) 24. And is configured as an NMOS transistor. For example, when the gate electrode 37 receives a control voltage Vg of +5 V, the MOS capacitor MC functions as a capacitor due to the inversion layer 50 formed in the semiconductor region under the gate electrode 37. On the other hand, when the control voltage Vg of 0 V is received by the gate electrode 37, since the inversion layer 50 cannot be formed, the capacitance value of the MOS capacitor MC becomes small. As described above, the capacitance value of the MOS capacitor MC changes according to the control signal φVg supplied to the gate electrode 37. Since the MOS capacitor MC is a variable capacitor in this way, the capacitance values of the floating diffusions 31 and 32 are fixed values, but the floating capacitor unit FC as a whole responds to the control signal φVg supplied to the gate electrode 37. It is a variable capacitance section in which the capacitance value changes. Therefore, the conversion gain G = Gfs · q / C of the pixel 1 can be changed by changing the control signal φVg. The charges transferred from the photodiode PD via the transfer transistor TX are stored in the entire floating capacitance unit FC.

  In the present embodiment, the impurity concentration of the semiconductor region (P-type well region) under the gate electrode 37 in the MOS capacitor MC is substantially constant from the floating diffusion 32 side to the opposite side of the semiconductor region.

  The amplification transistor AMP is a MOS transistor having the power supply diffusion portion 33 as a drain and the diffusion region 34 as a source. As described above, the gate electrode 39 of the amplification transistor AMP is connected to the floating diffusions 32 and 33. The charges transferred from the photodiode PD to the floating capacitor unit FC via the transfer transistor TX are converted into a voltage by the floating capacitor unit FC, and this voltage is applied to the gate electrode 39 of the amplification transistor AMP. The amplification transistor AMP outputs an electrical signal corresponding to the voltage of the gate electrode 39. Therefore, the amplification transistor AMP outputs an electrical signal (pixel signal) corresponding to the amount of charge generated and accumulated by the photodiode PD. If the number of charges transferred to the floating capacitor unit FC is N, the output of the amplification transistor AMP changes by G · N.

  The selection transistor SEL is a MOS transistor having the drain of the diffusion region 34 and the source of the diffusion region 35. When the selection transistor SEL is turned on, the output of the amplification transistor AMP is output to the vertical signal line 5. That is, reading by the source follower is possible by the amplification transistor AMP and the selection transistor SEL.

  The reset transistor RES is a MOS transistor having the power supply diffusion portion 33 as a drain and the floating diffusion 32 as a source. The reset transistor RES resets the electric charge accumulated in the floating capacitor unit FC by being turned on.

  In the present embodiment, as shown in FIG. 2, the photodiode PD, the transfer transistor TX, and the floating diffusion 31 are arranged in a row in the horizontal direction (row direction) in FIG. Further, as shown in FIGS. 2 and 3, the selection transistor SEL, the amplification transistor AMP, the reset transistor RES, and the MOS capacitor MC are arranged in a line in parallel with the line in which the photodiode PD, the transfer transistor TX, and the floating diffusion 31 are arranged. ing. In the selection transistor SEL, the amplification transistor AMP, the reset transistor RES, and the MOS capacitor MC, the gate electrodes 40 to 37 are arranged at a predetermined interval with respect to one active region extending in the horizontal direction (row direction) in FIG. It is formed by doing.

  In the present embodiment, in each transistor SEL, AMP, RES and MOS capacitor MC, the diffusion layers (source and drain) adjacent to the gate electrodes 40 to 37 are so-called LDD (Lightly) in order to relax the electric field in the vicinity of the drain. Doped Drain) structure. In FIG. 3, reference numerals 35a, 34a, 33a, and 32a denote low impurity concentration N-type diffusion regions constituting the LDD structure. Note that the scope of application of the present invention is not limited to a transistor structure having an LDD structure. For example, the present invention may be applied to a solid-state imaging device in which a transistor having a single drain structure and a double drain structure is formed.

  FIG. 4 is a timing chart showing an example of the reading operation of the solid-state imaging device according to the present embodiment. As shown in FIG. 1, a Bayer array is adopted, and the pixel 1 in the n-th row and the m-th column is a G pixel, the pixel 1 in the n + 1-th row and the m-th column is an R pixel, the n-th row and the In the following description, the pixel 1 in the (m + 1) th column is a B pixel, and the pixel 1 in the (n + 1) th row and the (m + 1) th column is a G pixel. In addition, here, for the sake of simplicity of explanation, it is assumed that the B pixel and the G pixel have the same sensitivity and only the R pixel has a low sensitivity.

  In this embodiment, after a mechanical shutter (not shown) is opened for a predetermined exposure period and charges are accumulated in the charge accumulation layer of the photodiode PD of each pixel 1, each row is sequentially selected, and each row is sequentially selected. The same operation is performed. FIG. 4 shows an operation when the pixel 1 in the nth row is selected and the pixel 1 in the (n + 1) th row is subsequently selected. FIG. 4 shows only the m-th column and the (m + 1) -th column for the control signal φVg.

  In the period T1, the pixel 1 in the n-th row is selected by the vertical scanning circuit 2, the reset pulse φRES (n) in the n-th row is changed to a low level, and the reset transistor RES in the n-th row is turned off. Further, in the period T1, the selection pulse φSEL (n) in the nth row changes to a high level, and the selection transistor SEL in the nth row is turned on. When the n-th row selection transistor SEL is turned on, the source of the n-th row amplification transistor AMP is connected to the vertical output line 5. The amplification transistor AMP in the n-th row operates as a source follower circuit by the constant current source 6. Furthermore, in the period T1, the control signal φVg (mth column φVg (m)) of the G pixel and B pixel columns (all columns in this example because of the Bayer array) among the pixels in the nth row. , M + 1-th column φVg (m + 1)) is set to the high level. As a result, in the period T1, the capacitance of the floating capacitor portion FC of the pixel in the column (m-th column, m + 1-th column, etc.) to which the high-level control signal φVg is applied increases, and the conversion gain G of the pixel in the column increases. Get smaller.

  After the period T1 starts, in the period T5, the noise transfer pulse φTN changes to a high level, the dark signal vertical transfer transistor TN is turned on, and a noise signal (dark signal) corresponding to the reset state is applied to the dark signal storage capacitor CN. Accumulated. This operation is executed simultaneously in parallel for all the pixels 1 in the nth row. Thereafter, in the period T6, the transfer pulse φTX (n) in the nth row changes to a high level, and the transfer transistor TX in the nth row is turned on. When the transfer transistor TX in the n-th row is turned on, the signal charge photoelectrically converted and accumulated by the photodiode PD in the n-th row is transferred to the corresponding floating capacitance unit FC. As a result, the voltage of the floating capacitor portion FC becomes a voltage corresponding to the transferred charge amount, and this voltage is applied to the gate electrode 39 of the amplification transistor AMP.

  Next, in the period T7 in the period T1, the optical signal transfer pulse φTS changes to a high level, the optical signal vertical transfer transistor TS is turned on, and the optical signal is stored in the optical signal storage capacitor CS. At this time, the control signal φVg (φVg (m) in the mth column, φVg (m + 1) in the m + 1th column, etc.) of the G pixel and B pixel columns having high sensitivity among the pixels in the nth row is set to the high level. Since the conversion gain G of the pixel is small, a low gain G signal or B signal is accumulated in the optical signal storage capacitor CS as a pixel signal in each column of the nth row. This operation is executed simultaneously in parallel for all the pixels 1 in the nth row.

  In the period T2 after the period T1, the horizontal transfer transistors HS and HN are sequentially turned on for each column by the horizontal scanning by the control signal φH from the horizontal scanning circuit 3, and the optical signal and the dark signal stored in the storage capacitors CS and CN are stored. Are sequentially read out to the horizontal signal lines 7S and 7N for each column, and the difference between these signals is taken by the differential output amplifier 8 and outputted to the outside. By taking the difference in this way, correlated double sampling is realized, and the noise component is removed from the pixel signal on which the noise signal is superimposed.

  Next, in the periods T3 and T4, operations similar to those performed in the periods T1 and T2 with respect to the nth row are performed for the (n + 1) th row. However, in the period T3, the control signal φVg (such as φVg (m) in the m-th column) of the low-sensitivity R pixel among the pixels in the n + 1-th row is set to the low level, while the pixel in the n + 1-th row A control signal φVg (such as φVg (m + 1) in the (m + 1) th column) of the G pixel column having a high sensitivity is set to the high level. As a result, in the period T3, the capacitance of the floating capacitor portion FC of the pixel in the column (m-th column or the like) to which the low-level control signal φVg is applied decreases, and the conversion gain G of the pixel in the column increases. The capacity of the floating capacitor portion FC of the pixel in the column (such as the (m + 1) th column) to which the high-level control signal φVg is applied increases, and the conversion gain G of the pixel in the column decreases. Therefore, a low gain G signal and a high gain R signal are obtained from the pixel.

  In this embodiment, in this way, a low gain pixel signal can be obtained from the high sensitivity G pixel and B pixel, while a high gain pixel signal can be obtained from the low sensitivity R pixel. . Therefore, by appropriately setting the high level and the low level of the control signal φVg, when the incident light amounts of the corresponding colors with respect to the pixels of the respective colors are the same, the levels of the pixel outputs obtained from the pixels of the respective colors are made substantially the same. It is possible to make the signal level uniform by compensating for the difference in sensitivity of RGB.

  In the present embodiment, the conversion gain G of the pixel 1 can be adjusted by adjusting the capacitance value of the floating capacitor unit FC using the control signal φVg, and thereby the signal level can be adjusted. Therefore, such signal level adjustment does not involve amplification of noise components such as noise of the amplification transistor AMP and reset noise, and therefore, signal level adjustment can be performed with a high SN ratio. Therefore, when applied to compensation for differences in RGB sensitivity as in the present embodiment, the compensation can be performed with a high S / N ratio. In the present embodiment, the difference in RGB sensitivity can be compensated without amplifying the output of the low-sensitivity R pixel in the subsequent signal processing circuit, so the difference in RGB sensitivity is compensated with a high S / N ratio. can do.

  FIG. 5 is a graph showing an example of the relationship between the conversion gain G and the control signal φVg of the solid-state imaging device according to the present embodiment. In this example, for example, the low level control signal φVg given to the low-sensitivity R pixel is set to 0V, and the high level control signal φVg given to the high-sensitivity G pixel and B pixel is set to 5V. it can. In this case, a high conversion gain G of 37 μV / e− is obtained for the R pixel, and a low conversion gain G of 23 μV / e− is obtained for the G pixel and the B pixel. FIG. 5 shows that the conversion gain G can be adjusted by freely selecting the voltage of φVg.

  In the above, the example which uses the solid-state image sensor of this invention for compensation of the difference in RGB sensitivity was demonstrated. However, the solid-state imaging device of the present invention is not limited to such applications, and can be used for various signal level adjustments.

  In the present embodiment, the floating capacitance control circuit 4 gives the same value of the control signal φVg to the pixel 1 of the same color at the time of reading, so that the capacitance value of the floating capacitance portion FC of the pixel 1 of the same color is The control signal φVg is supplied to the gate electrode 37 of the floating capacitor portion FC of each pixel 1 so as to have substantially the same value when reading the signal from the pixel 1, and the capacitance value of the floating capacitor portion FC is controlled for each color. ing. In this embodiment, the floating capacitance control circuit 4 supplies a binary signal of high level and low level as the control signal φVg, and the capacitance value of the floating capacitance unit FC is adjusted to one of the binary values. Yes. However, the present invention is not limited to such an example.

  For example, the floating capacity control circuit 4 may be configured to output a multi-value control signal φVg of three or more values or an analog control signal φVg in accordance with an external command signal. In this case, for example, the floating capacitance control circuit 4 receives a white balance adjustment command signal from outside the solid-state imaging device in the camera, supplies a control signal φVg corresponding to the command signal to each pixel 1, and sets each color. By controlling the capacitance value of the floating capacitance unit FC for each, white balance can be achieved with a high SN ratio. In addition, for example, when performing high-sensitivity shooting without using a strobe in a room or at night, the conversion gain of each pixel is compared to that during normal shooting in response to a command signal to that effect from outside the solid-state image sensor in the camera. By controlling the control signal φVg so that G increases, high-sensitivity imaging can be performed with a high SN ratio. At this time, the capacitance values of the floating diffusions 31 and 32, the capacitance value variable range of the MOS capacitor MC, and the like may be set as appropriate so that the dynamic range of the conversion gain G becomes a desired range. These points are the same for each embodiment described later.

  [Second Embodiment]

  FIG. 6 is a schematic cross-sectional view showing a solid-state imaging device according to the second embodiment of the present invention, and corresponds to FIG. 6, elements that are the same as or correspond to those in FIG. 3 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The present embodiment differs from the first embodiment in that the gate length of the MOS capacitor MC (the left and right sides of the gate electrode 37 in FIG. 3) is different from the first embodiment. This is only the point where the length in the direction is long.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained. Further, according to the present embodiment, the variable width of the capacitance value of the MOS capacitor MC becomes larger than that of the first embodiment, and as a result, the variable width of the capacitance value of the floating capacitor portion FC becomes larger.

  [Third Embodiment]

  FIG. 7 is a schematic cross-sectional view showing a solid-state imaging device according to the third embodiment of the present invention, and corresponds to FIG. 7, elements that are the same as or correspond to those in FIG. 3 are given the same reference numerals, and redundant descriptions thereof are omitted.

This embodiment is different from the first embodiment only in the points described below. In the first embodiment, as described above, the impurity concentration of the semiconductor region (P-type well region) under the gate electrode 37 in the MOS capacitor MC is from the floating diffusion 32 side to the opposite side of the semiconductor region. It is almost constant. On the other hand, in the present embodiment, as shown in FIG. 7, the impurity concentration in the region 60a on the floating diffusion 32 side in the semiconductor region (P-type well region) under the gate electrode 37 in the MOS capacitor MC is increased. Is set lower than the impurity concentration of the region 60b on the opposite side of the semiconductor region. For example, the impurity concentration of the region 60a is 1 × 10 ¹⁶ / cm ³ for the p-type, and the impurity concentration of the region 60b is 8 × 10 ¹⁶ / cm ³ for the p-type.

  When the impurity concentration of the semiconductor region under the gate electrode 37 is set in this way, the voltage that can be generated in the inversion layer 50 differs between the region 60a and the region 60b. Therefore, when the applied voltage (control signal) φVg is increased, first, the region The inversion layer 50 is formed in 60a, and when the applied voltage φVg is further increased, the inversion layer is also formed in the region 60b. Therefore, according to the present embodiment, as shown in FIG. 8, the conversion gain G can be gradually changed with respect to the applied voltage φVg as compared with the first embodiment, and the MOS capacitor MC (and eventually , The capacitance value of the floating capacitor portion FC) can be easily adjusted. FIG. 8 is a graph showing an example of the relationship between the conversion gain G and the control signal φVg of the solid-state imaging device according to the present embodiment. FIG. 8 also shows an example of the relationship between the conversion gain G of the solid-state imaging device according to the first embodiment and the control signal φVg (the same as that shown in FIG. 5).

  Except for the above points, the present embodiment can provide the same advantages as those of the first embodiment.

  In the present embodiment, the impurity concentration of the semiconductor region under the gate electrode 37 is changed in two steps, but the step is performed in three or more steps so that the impurity concentration on the floating diffusion 32 side is relatively low. May be changed continuously or continuously.

  [Fourth Embodiment]

  FIG. 9 is a schematic cross-sectional view showing a solid-state imaging device according to the fourth embodiment of the present invention, and corresponds to FIG. 9, elements that are the same as or correspond to those in FIG. 3 are given the same reference numerals, and redundant descriptions thereof are omitted.

  This embodiment differs from the first embodiment in this embodiment in that the N-type diffusion disposed adjacent to the semiconductor region (P-type well region) under the gate electrode 37 of the MOS capacitor MC. The region 70 is added, and the floating capacitor portion FC only includes a diffusion capacitor formed by the N-type diffusion region 70 in addition to the floating diffusions 31 and 32 and the MOS capacitor MC. The N-type diffusion region 70 has a low impurity concentration N-type diffusion region 70a constituting an LDD structure at the end on the gate electrode 37 side, but such an LDD structure is not necessarily required.

  According to the present embodiment, the same advantages as those of the first embodiment can be obtained. In the present embodiment, if the control signal φVg is small, the inversion layer 50 cannot be formed under the gate electrode 37 of the MOS capacitor MC. Therefore, the capacitance value of the diffusion capacitance by the diffusion region 70 is the capacitance value of the floating capacitance portion FC. Don't join. On the other hand, when the control signal φVg is increased, the diffusion region 70 is connected to the floating diffusion 32 via the inversion layer 50, so that the capacitance value of the diffusion region due to the diffusion region 70 is added to the capacitance value of the floating capacitor portion FC. Therefore, according to the present embodiment, the variable width of the capacitance value of the floating capacitor unit FC becomes larger than that in the first embodiment.

  By the way, once the control signal φVg is increased and charges are accumulated in the diffusion region 70, the control signal φVg is decreased and the inversion layer 50 cannot be formed in the semiconductor region under the gate electrode 37 of the MOS capacitor MC. The charges accumulated in 70 remain in the diffusion region 70 as they are. Therefore, if the residual charge is left as it is, the new signal charge is superimposed on the residual charge when the signal charge is newly accumulated in the diffusion region 70 next time, so that the appropriate charge voltage is set. Conversion will not be performed. For this reason, when the operation is performed according to the timing chart shown in FIG. 4 described above, appropriate charge-voltage conversion is not performed.

  Therefore, the solid-state imaging device according to the present embodiment performs, for example, an operation according to the timing chart shown in FIG. 10 instead of the operation according to the timing chart shown in FIG. The operation shown in FIG. 10 differs from the operation shown in FIG. 4 in that the control signals φVg of all the columns are set in each period Tres immediately before the row selection period (reading period of each row) such as periods T1 and T3. It is only a point to make it a high level. In the period Tres, the reset pulse φRES is at a high level and the reset transistor RES is on. Therefore, by setting the control signal φVg to a high level in the period Tres, the transistor formed by the MOS capacitor MC is turned on, so that the residual charge accumulated in the diffusion region 70 passes through the MOS capacitor MC and the reset transistor RES. The residual charge is reset. Therefore, the solid-state imaging device according to the present embodiment performs appropriate charge-voltage conversion by performing the operation according to the timing chart shown in FIG.

  [Fifth Embodiment]

  FIG. 11 is a schematic cross-sectional view showing a solid-state imaging device according to the fifth embodiment of the present invention, and corresponds to FIG. 11, elements that are the same as or correspond to those in FIG. 9 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The solid-state imaging device according to the present embodiment is different from the solid-state imaging device according to the fourth embodiment only in that an MIM capacitor 80 is added. The MIM capacitor 80 includes metal electrodes 81 and 82 and an insulating layer 83 such as a silicon oxide layer therebetween. One electrode 81 of the MIM capacitor 80 is electrically connected to the diffusion region 70. Therefore, according to the present embodiment, the floating capacitor portion FC includes the MIM capacitor 80 in addition to the diffusion capacitors formed by the floating diffusions 31 and 32, the MOS capacitor MC, and the N-type diffusion region 70.

  This embodiment can provide the same advantages as those of the fourth embodiment. Moreover, according to the present embodiment, the variable width of the capacitance value of the floating capacitor portion FC is further increased by the amount of the MIM capacitor 80.

  Note that the solid-state imaging device according to the present embodiment also operates according to the timing chart shown in FIG. 10, for example, instead of the operation according to the timing chart shown in FIG. 4, similarly to the solid-state imaging device according to the fourth embodiment. Done.

  [Sixth Embodiment]

  FIG. 12 is a circuit diagram showing a schematic configuration of a solid-state imaging device according to the sixth embodiment of the present invention, and corresponds to FIG. FIG. 1 shows 3 × 3 pixels 1, whereas FIG. 12 shows 6 × 3 pixels 1 (3 × 3 pixel blocks 101). FIG. 13 is a schematic plan view schematically showing 2 × 2 pixels 1 (1 × 2 pixel blocks 101) of the solid-state imaging device shown in FIG. 12, and corresponds to FIG. FIG. 14 is a schematic cross-sectional view along the line B-B ′ in FIG. 13. FIG. 15 is a schematic sectional view taken along line C-C ′ in FIG. 13. 12 to 15, the same or corresponding elements as those in FIGS. 1 to 3 are denoted by the same reference numerals, and redundant description thereof is omitted.

  This embodiment is different from the first embodiment in that, for each of two pixels 1 adjacent in the column direction, the two pixels 1 are a set of a floating capacitance unit FC, an amplification transistor AMP, and a reset transistor RES. The only difference is that the selection transistor SEL is shared and the arrangement of each element is changed accordingly. In FIG. 12 and FIG. 13, two pixels 1 sharing one set of the floating capacitance unit FC, the amplification transistor AMP, the reset transistor RES, and the selection transistor SEL are shown as a pixel block 101. 12 and 13, the photodiode PD and the transfer transistor TX of the upper pixel 1 in the pixel block 101 are denoted by reference symbols PDA and TXA, respectively, and the photodiode PD and the lower pixel 1 of the pixel block 101 in FIG. The transfer transistors TX are indicated by symbols PDB and TXB, respectively, to distinguish them. Further, the control signal supplied to the gate electrode 36 of the transfer transistor TXA is φTXA, and the control signal supplied to the gate electrode 36 of the transfer transistor TXB is φTXB to distinguish them. In FIG. 1, n indicates a pixel row, but in FIG. 12, n indicates a row of the pixel block 101.

  FIG. 16 is a timing chart showing an example of the reading operation of the solid-state imaging device according to the present embodiment, and corresponds to FIG. It is assumed that a Bayer arrangement is adopted and the color filter color of each pixel is set as shown in FIG. Here, as in the case of the first embodiment, in order to simplify the description, it is assumed that the B pixel and the G pixel have the same sensitivity and only the R pixel has a low sensitivity.

  In the present embodiment, after a mechanical shutter (not shown) is opened for a predetermined exposure period and charges are accumulated in the charge accumulation layers of the photodiodes PDA and PDB of each pixel 1 of each pixel block 101, the pixel block Each row 101 is sequentially selected, and the same operation is sequentially performed for each row. FIG. 16 shows the operation when the pixel block 101 in the nth row is selected and the pixel block 101 in the (n + 1) th row is selected subsequently. In FIG. 16, only the m-th column and the (m + 1) -th column are shown for the control signal φVg.

  As can be understood by comparing FIG. 16 with FIG. 4, in periods T11 and T12, operations similar to those in periods T1 and T2 in FIG. . Next, in periods T13 and T14, operations similar to those in periods T3 and T4 in FIG. 4 are performed on the pixel 1 on the upper side of the pixel block 101 in the n-th row. Thereafter, in the periods T15, T16, T17, and T18, operations similar to those in the periods T11, T12, T13, and T14 are performed on the pixel block 101 in the (n + 1) th row.

  Therefore, according to the present embodiment, although the two pixels 1 share one set of the floating capacitance unit FC, the amplification transistor AMP, the reset transistor RES, and the selection transistor SEL, Similarly to the embodiment, when the incident light amounts of the corresponding colors for the pixels of each color are the same, the pixel output levels obtained from the pixels of each color can be made substantially the same, and the signal level is compensated by compensating for the difference in RGB sensitivity. The same advantages as in the first embodiment can be obtained.

  In this embodiment, since the two pixels 1 share one set of the floating capacitor portion FC, the amplification transistor AMP, the reset transistor RES, and the selection transistor SEL, the number of transistors per pixel can be reduced. The aperture ratio can be increased.

  In the present embodiment, as shown in FIG. 13, the selection transistor SEL and the amplification transistor AMP shared by the two pixels 1 of the pixel block 101 with respect to the photodiode PDA of the upper pixel 1 of the pixel block 101. The reset transistor RES and the MOS capacitor MC shared by the two pixels 1 of the pixel block 101 with respect to the positional relationship between the gate electrodes 40 and 39 of the pixel block 101 and the photodiode PDB of the lower pixel 1 of the pixel block 101. The positional relationship between the gate electrodes 38 and 37 is substantially the same. Therefore, in this embodiment, the optical conditions for the photodiodes PDA and PDB are almost the same. If there is no MOS capacitor MC (and therefore its gate electrode 37), two gate electrodes 40 and 39 are arranged for the photodiode PDA, whereas one gate electrode for the photodiode PDB. Only 38 will be arranged. In this case, the light deviating from the photodiodes PDA and PDB has a difference in reflection or the like due to the difference in the arrangement state of the gate electrodes arranged in the vicinity between the photodiode PDA and the photodiode PDB. This difference appears as an output difference, and the image quality deteriorates. On the other hand, in the present embodiment, since the arrangement state of the gate electrodes arranged in the vicinity of the photodiode PDA and the photodiode PDB is substantially the same, it is possible to suppress deterioration in image quality.

In the present embodiment, for every two pixels 1 adjacent in the column direction, the two pixels 1 share one set of the floating capacitance unit FC, the amplification transistor AMP, the reset transistor RES, and the selection transistor SEL. In the present invention, for example, for each of a predetermined number of three or more pixels 1 adjacent in the column direction, the predetermined number of pixels 1 includes a set of the floating capacitor FC, the amplification transistor AMP, the reset transistor RES, and the selection transistor SEL. You may make it share.
The present embodiment may be modified in the same manner as the second to fifth embodiments obtained by modifying the first embodiment.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

  For example, the above embodiments may be arbitrarily combined as appropriate. For example, the third embodiment may be combined with the fourth or fifth embodiment.

1 is a circuit diagram illustrating a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a schematic plan view schematically showing 2 × 2 pixels of the solid-state imaging device shown in FIG. 1. FIG. 3 is a schematic cross-sectional view along the line A-A ′ in FIG. 2. 2 is a timing chart illustrating an example of a reading operation of the solid-state imaging device illustrated in FIG. 1. 3 is a graph showing an example of a relationship between a conversion gain of the solid-state imaging device shown in FIG. 1 and a control signal φVg. It is a schematic sectional drawing which shows the solid-state image sensor by the 2nd Embodiment of this invention. It is a schematic sectional drawing which shows the solid-state image sensor by the 3rd Embodiment of this invention. It is a graph which shows an example of the relationship between the conversion gain of the solid-state image sensor shown in FIG. 7, and control signal (phi) Vg. It is a schematic sectional drawing which shows the solid-state image sensor by the 4th Embodiment of this invention. 10 is a timing chart illustrating an example of a reading operation of the solid-state imaging device illustrated in FIG. 9. It is a schematic sectional drawing which shows the solid-state image sensor by the 5th Embodiment of this invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor by the 6th Embodiment of this invention. FIG. 13 is a schematic plan view schematically showing 2 × 2 pixels 1 of the solid-state imaging device shown in FIG. 12. FIG. 14 is a schematic sectional view taken along line B-B ′ in FIG. 13. FIG. 14 is a schematic cross-sectional view taken along line C-C ′ in FIG. 13. 13 is a timing chart illustrating an example of a reading operation of the solid-state imaging device illustrated in FIG. 12.

Explanation of symbols

4 Floating capacitance control circuit PD Photodiode AMP Amplifying transistor RES Reset transistor TX Transfer transistor SEL Select transistor FC Floating capacitance section MC MOS capacitance

Claims (11)

A photoelectric conversion unit that generates and accumulates signal charges according to incident light, a floating capacitance unit that receives the signal charges and converts the signal charges into a voltage, an amplification transistor that outputs a signal according to the potential of the floating capacitance unit, A solid-state imaging device including a plurality of pixels each having a transfer transistor that transfers charges from the photoelectric conversion unit to the floating capacitance unit, and a reset transistor that resets the potential of the floating capacitance unit,
The solid-state imaging device, wherein the floating capacitance portion is a variable capacitance portion whose capacitance value changes according to a supplied control signal.   The solid-state imaging device according to claim 1, wherein the floating capacitor includes a MOS capacitor having a gate electrode that receives the control signal. The pixel has a selection transistor for selecting the pixel,
The gate electrode of the selection transistor is electrically connected in common for each row,
3. The solid-state imaging device according to claim 2, wherein the gate electrode of the MOS capacitor is electrically connected in common for each column.   3. The floating capacitor section includes a diffusion capacitor formed by a diffusion region disposed adjacent to a semiconductor region that forms the MOS capacitor below the gate electrode of the MOS capacitor. Or the solid-state image sensor of 3.   5. The solid-state imaging device according to claim 4, wherein the floating capacitor portion includes an MIM capacitor having an electrode electrically connected to the diffusion region of the diffusion capacitor.   The floating capacitor portion includes a floating diffusion disposed adjacent to a semiconductor region constituting the MOS capacitor below the gate electrode of the MOS capacitor and electrically connected to the gate electrode of the amplification transistor. The solid-state image sensor according to any one of claims 2 to 5.   The impurity concentration of the semiconductor region constituting the MOS capacitor is changed stepwise or continuously from the floating diffusion side to the opposite side of the semiconductor region so that the floating diffusion side is relatively low. The solid-state imaging device according to claim 6, wherein   The predetermined number of pixels share one set of the floating capacitance section, the amplification transistor, and the reset transistor for every two or more predetermined number of pixels among the plurality of pixels. 8. The solid-state image sensor according to any one of 7 above. The pixel has a selection transistor for selecting the pixel,
For every two pixels of the plurality of pixels, the two pixels share a set of the floating capacitor, the amplification transistor, the reset transistor, and the selection transistor,
The positional relationship between the gate electrodes of the selection transistor and the amplification transistor shared by the two pixels with respect to the photoelectric conversion unit of one of the two pixels, and the other of the two pixels The positional relationship between the gate electrode of each of the reset transistor and the MOS capacitor shared by the two pixels with respect to the photoelectric conversion unit of the pixel is substantially the same.
The solid-state imaging device according to claim 2, wherein the solid-state imaging device is provided. The plurality of pixels are divided into a plurality of groups, and color filters of different colors are provided for each group,
A control unit that supplies the control signal to the floating capacitance units of the plurality of pixels;
The control unit supplies the control signal so that a capacitance value of a floating capacitance unit of a pixel provided with a color filter of the same color is substantially the same when reading a signal from the pixel. The solid-state imaging device according to claim 1.   The control unit controls the control signal so that the output of the pixel provided with the color filter of each color is substantially the same when the incident light amount of the corresponding color for the pixel provided with the color filter of each color is the same. The solid-state imaging device according to claim 10, wherein the solid-state imaging device is supplied.

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