JP2017139498A - Solid-state image pickup device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of improving random noises.SOLUTION: At a longer edge side (right side in Figure) of one PD group which is constituted of photodiodes of 2×4 pixels, pixels Tr. which includes at least a selection Tr., an amplification Tr., and a reset Tr. is disposed as one Tr. group. Each of the pixels Tr. in the one Tr. group is symmetrically disposed relative to the PD group, respectively. A dummy Tr. is a dummy of the reset Tr.118, and symmetric property is enhanced by having the dummy. The disclosure is applicable to, for example, a CMOS solid-state image pickup device which is used for an imaging apparatus such as a camera.SELECTED DRAWING: Figure 5

Description

  The present disclosure relates to a solid-state imaging device and an electronic device, and more particularly to a solid-state imaging device and an electronic device that can improve random noise.

  In a backside illuminated CMOS image sensor with a pixel sharing layout for PRNU (Photo Response Non Uniformity) countermeasures described in Patent Document 1, pixel transistors (hereinafter referred to as Tr.) Are divided into two groups. Tr. Is arranged symmetrically.

  This is because amplification Tr. (Hereinafter referred to as AMP), selection Tr. (Hereinafter referred to as SEL) and reset Tr. (Hereinafter referred to as RST) are applied to a photodiode (hereinafter referred to as PD). By arranging them symmetrically, the amount of light incident from the back side is reflected and absorbed by Tr. Poly-Si, and the amount absorbed by the source and drain is the same in the two groups. Yes.

JP 2013-62789 A

  However, in the technique described in Patent Document 1, since the pixel Tr. Is divided into two groups, the L length of each transistor cannot be extended, and RN (random noise) sometimes deteriorates.

  More specifically, when AMP / SEL is arranged in group 1 and two Tr. 2 are arranged in group 2, a total of six source / drains are required, three in group 1 and three in group 2. At this time, there was a limit to the extension of the Tr.L length due to the litho line width limit, the processing limit between poly-Si and contacts, and the isolation breakdown voltage. In particular, this effect is significant when miniaturized, and RN deteriorates because the L length of AMP is short.

  This indication is made in view of such a situation, and can improve random noise.

  The solid-state imaging device according to one aspect of the present technology includes a photoelectric conversion element group in which one shared shape is a rectangle, eight photoelectric conversion elements are included in one shared unit, and 1 in the long side direction of the photoelectric conversion element group. A pixel transistor group including a reset transistor, an amplifying transistor, and a selection transistor, and the eight photoelectric conversion elements share one floating fusion with each of the four photoelectric conversion elements, and The arrangement direction of the two floating fusions shared by the conversion element group is the same as the long side direction of the photoelectric conversion element group.

  The pixel transistor group includes a dummy transistor.

  The pixel transistor group is arranged so as to be shifted with respect to one shared rectangle of the photoelectric conversion element group.

  The L length of the amplification transistor included in the pixel transistor group is longer than the L length of the other transistors included in the pixel transistor group.

  The L length of the amplification transistor included in the pixel transistor group is 0.6 to 1.4 times the pitch of the photoelectric conversion element group.

  The L length of the selection transistor included in the pixel transistor group is longer than the L length of the other transistors included in the pixel transistor group.

  A well contact is further provided between the photoelectric conversion element group and another photoelectric conversion element group located next to the photoelectric conversion element group.

  A well contact is further provided between the pixel transistor group and another pixel transistor group located next to the pixel transistor group.

  Back-illuminated type.

  According to an electronic device of one aspect of the present invention, one shared shape is a rectangle, one photoelectric conversion element group including eight photoelectric conversion elements in one shared unit, and one photoelectric conversion element group in the long side direction of the photoelectric conversion element group. And a pixel transistor group including a reset transistor, an amplifying transistor, and a selection transistor, and the eight photoelectric conversion elements share one floating fusion with each of the four photoelectric conversion elements, and the photoelectric conversion An arrangement direction of two floating fusions shared by the element group is the same as a long side direction of the photoelectric conversion element group, and a signal processing circuit that processes an output signal output from the solid-state imaging apparatus And an optical system that makes incident light incident on the solid-state imaging device.

  The pixel transistor group includes a dummy transistor.

  The pixel transistor group is arranged so as to be shifted with respect to one shared rectangle of the photoelectric conversion element group.

  The L length of the amplification transistor included in the pixel transistor group is longer than the L length of the other transistors included in the pixel transistor group.

  The L length of the amplification transistor included in the pixel transistor is 0.6 to 1.4 times the pitch of the photoelectric conversion element group.

  A well contact is further provided between the photoelectric conversion element group and another photoelectric conversion element group located next to the photoelectric conversion element group.

  A well contact is further provided between the pixel transistor group and another pixel transistor group located next to the pixel transistor group.

  The solid-state imaging device is a backside illumination type.

  In one aspect of the present technology, in the photoelectric conversion element group, one shared shape is a rectangle, and eight photoelectric conversion elements are included in one shared unit. A pixel transistor group including a reset transistor, an amplifying transistor, and a selection transistor is arranged as one group in the long side direction of the photoelectric conversion element group. The eight photoelectric conversion elements share one floating fusion with each of the four photoelectric conversion elements, and the arrangement direction of the two floating fusions shared with the photoelectric conversion element group is the length of the photoelectric conversion element group. Same as side direction.

  According to the present technology, the poly-Si of the transistor can be arranged with approximately symmetry with respect to the photodiode. Further, according to the present technology, random noise can be improved.

  In addition, the effect described in this specification is an illustration to the last, and the effect of this technique is not limited to the effect described in this specification, and there may be an additional effect.

It is a block diagram which shows the schematic structural example of the solid-state imaging device to which this technique is applied. It is a circuit diagram showing a configuration example of a pixel of 3Tr. Configuration. It is a circuit diagram showing a configuration example of a pixel of 4Tr. It is a circuit diagram which shows the structural example of the pixel of a pixel sharing structure. It is a figure showing the 1st example of composition of the solid imaging device to which this art is applied. It is a figure which shows the other example of arrangement | positioning of a transistor. It is a figure which shows the other example of arrangement | positioning of a transistor. It is a figure which shows the other example of arrangement | positioning of a transistor. It is a figure which shows the 2nd structural example of the solid-state imaging device to which this technique is applied. It is a figure which shows the 3rd structural example of the solid-state imaging device to which this technique is applied. It is a figure which shows the 4th structural example of the solid-state imaging device to which this technique is applied. It is a figure which shows the other example of arrangement | positioning of a transistor. It is a block diagram which shows the structural example of the electronic device to which this technique is applied.

Hereinafter, modes for carrying out the present disclosure (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
0. Schematic configuration example of solid-state imaging device First Embodiment (Example of 4Tr. Type 8-pixel sharing)
2. Second Embodiment (Example of 4Tr. Type 2-pixel sharing)
3. Third Embodiment (Example of 4Tr. Type 16 pixel sharing)
4). Fourth embodiment (example of 3Tr. Type 8-pixel sharing)
5. Fifth embodiment (example of electronic device)

<0. Schematic configuration example of solid-state imaging device>
<Schematic configuration example of solid-state imaging device>
FIG. 1 illustrates a schematic configuration example of an example of a complementary metal oxide semiconductor (CMOS) solid-state imaging device applied to each embodiment of the present technology.

  As shown in FIG. 1, a solid-state imaging device (element chip) 1 includes a pixel region (a pixel region in which pixels 2 including a plurality of photoelectric conversion elements are regularly arranged two-dimensionally on a semiconductor substrate 11 (for example, a silicon substrate). A so-called imaging region) 3 and a peripheral circuit section.

  The pixel 2 includes a photoelectric conversion element (for example, a photodiode) and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplifying transistor, and can further be constituted by four transistors by adding a selection transistor. Since the equivalent circuit of each pixel 2 (unit pixel) is the same as a general one, detailed description thereof is omitted here.

  Further, the pixel 2 may have a pixel sharing structure. The pixel sharing structure includes a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other pixel transistor that is shared. The photodiode is a photoelectric conversion element.

  The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.

  The control circuit 8 receives data for instructing an input clock, an operation mode, and the like, and outputs data such as internal information of the solid-state imaging device 1. Specifically, the control circuit 8 is based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, and the clock signal or the reference signal for the operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 Generate a control signal. The control circuit 8 inputs these signals to the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6.

  The vertical drive circuit 4 is configured by, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel 2 to the selected pixel drive wiring, and drives the pixels 2 in units of rows. Specifically, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 sequentially in the vertical direction in units of rows, and generates the signal according to the amount of light received by the photoelectric conversion element of each pixel 2 through the vertical signal line 9. A pixel signal based on the signal charge is supplied to the column signal processing circuit 5.

  The column signal processing circuit 5 is disposed, for example, for each column of the pixels 2, and performs signal processing such as noise removal on the signal output from the pixels 2 for one row for each pixel column. Specifically, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling), signal amplification, and A / D (Analog / Digital) conversion for removing fixed pattern noise specific to the pixel 2. . At the output stage of the column signal processing circuit 5, a horizontal selection switch (not shown) is provided connected to the horizontal signal line 10.

  The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

  The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10. For example, the output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like.

  The input / output terminal 12 is provided for exchanging signals with the outside.

<Pixel configuration example>
FIG. 2 is a diagram illustrating a pixel configuration in a global shutter type CMOS sensor. In the example of FIG. 2, an example of a three-transistor (hereinafter referred to as Tr.) Configuration (hereinafter also referred to as a 3Tr. Type) is shown.

  2 has one shared floating diffusion (hereinafter referred to as FD) 21, photodiode 22, and three Tr. In a unit pixel. Each of the three Tr. Is a reset Tr. 23, a transfer Tr. 24, and an amplification Tr.

  The photodiode 22 has an anode electrode connected to a negative power source (for example, ground), and photoelectrically converts the received light into photocharge (here, photoelectrons) having a charge amount corresponding to the light amount. The cathode electrode of the photodiode 22 is electrically connected to the gate electrode of the amplification Tr. 25 via the transfer Tr. The node where the gate electrode of the amplification Tr.25 and the transfer Tr.24 are electrically connected is the FD21.

  The transfer Tr. 24 is connected between the cathode electrode of the photodiode 22 and the FD 21. A transfer pulse φTRF having a high level (for example, VDD level) active (hereinafter referred to as “High active”) is applied to the gate electrode of the transfer Tr. 24 via a transfer line (not shown). When the transfer pulse φTRF is applied, the transfer Tr. 24 is turned on and the photoelectric charge photoelectrically converted by the photodiode 22 is transferred to the FD 21.

  The reset Tr. 23 has a drain electrode connected to the pixel power supply VDD and a source electrode connected to the FD 21. Prior to the transfer of the signal charge from the photodiode 22 to the FD 21, a high active reset pulse φRST is given to the gate electrode of the reset Tr. 23 via a reset line (not shown). When the reset pulse φRST is given, the reset Tr. 23 is turned on, and the FD 21 is reset by discarding the charge of the FD 21 to the pixel power supply VDD.

  In the amplification Tr. 25, the gate electrode is connected to the FD 21, the drain electrode is connected to the pixel power supply VDD, and the source electrode is connected to the vertical signal line. And amplification Tr.25 outputs the electric potential of FD21 after reset by reset Tr.23 as a reset signal (reset level) Vreset. Further, the amplification Tr.25 outputs the potential of the FD 21 after the signal charge is transferred by the transfer transistor Tr.24 as the optical accumulation signal (signal level) Vsig.

  FIG. 3 is a diagram showing another configuration of the pixel in the global shutter type CMOS sensor. In the example of FIG. 3, an example of a 4Tr. Configuration (hereinafter also referred to as a 4Tr. Type) is shown.

  The pixel 2 in FIG. 3 is common to the pixel 2 in FIG. 2 in that the FD 21, the photodiode 22, the reset Tr. 23, the transfer Tr. 24, and the amplification Tr. 25 are provided. 3 is different from the pixel 2 of FIG. 2 in that a selection Tr. 31 is added.

  In the selection Tr. 31, for example, the drain electrode is connected to the source electrode of the amplification Tr. 25, and the source electrode is connected to the vertical signal line. A high active selection pulse φSEL is applied to the gate electrode of the selection Tr. 31 via a selection line (not shown). When the selection pulse φSEL is given, the selection Tr.31 is turned on, the unit pixel is selected, and the signal output from the amplification Tr.25 is relayed to the vertical signal line.

  As for the selection Tr. 31, it is possible to adopt a circuit configuration connected between the pixel power supply VDD and the drain of the amplification Tr.

<Pixel sharing configuration example>
FIG. 4 is a diagram showing a configuration in which one Tr. Set is shared by two pixels, four pixels, and eight pixels. Tr. Set refers to reset Tr. 23 and amplification Tr. 25 described above with reference to FIG. 2 or reset Tr. 23, amplification Tr. 25, and selection Tr. 31 described above with reference to FIG. That is. In either case, the transfer Tr. Is necessary for each photodiode and is directly connected to each photodiode.

  That is, in the case of sharing two pixels, a set of transfer Tr. 41 and photodiode 42 is added via the FD 21 to the configuration of the pixel 2 in FIG. That is, in this case, the two pixels (the photodiode 22 and the photodiode 42) share one Tr. Set.

  In the case of 4-pixel sharing, two sets of transfer Tr. 51-1 and 51-2 and photodiodes 52-1 and 52-2 are added to the 2-pixel sharing configuration via the FD 21. That is, in this case, the four pixels (photodiode 22, photodiode 42, photodiodes 52-1 and 52-2) share one Tr. Set.

  In the case of 8-pixel sharing, four sets of transfer Tr. 61-1 to 61-4 and photodiodes 62-1 to 62-4 are further added to the 4-pixel sharing configuration via the FD 21. That is, in this case, a configuration in which eight pixels (photodiode 22, photodiode 42, photodiodes 52-1 and 52-2, and photodiodes 62-1 to 62-4) share one Tr. Set. It becomes.

<1. First Example>
<Configuration example of solid-state imaging device of the present technology>
FIG. 5 is a diagram illustrating a configuration example of a solid-state imaging device to which the present technology is applied. In the example of FIG. 5, an example in which the solid-state imaging device is configured by a back-illuminated CMOS sensor sharing 4Tr. Type 8 pixels (2 × 4 pixels) is shown.

  In general, in the 4Tr. Type, in addition to the photodiode region where the photodiode is arranged, the above-described three transistors of reset Tr. (RST), amplification Tr. (AMP), and selection Tr. (SEL) are arranged. 1 region. Since the transfer Tr. Is directly connected to the photodiode, it is assumed that the transfer Tr. Is arranged in the photodiode region.

  In the solid-state imaging device 101 of FIG. 5, the photodiode 111 for 2 × 4 pixels, which is a pixel sharing unit, and the corresponding transfer Tr. 112 for 2 × 4 pixels are placed in the photodiode region on the left side in the drawing. Arranged as a group 121.

  In the PD group 121, the photodiodes 111 and the transfer Tr. 112 for 2 × 4 pixels are arranged so as to be vertically long in a row of two upper and lower stages in the drawing for every four pixels.

  On the other hand, in the solid-state imaging device 101, a selection Tr. 115, an amplification Tr. 116, a dummy Tr. 117, and a reset Tr. 118 is arranged as one Tr. Group 122.

  That is, on the long side of one PD group 121 composed of photodiodes 111 of 2 × 4 pixels, a pixel Tr comprising a selection Tr. 115, an amplification Tr. 116, a dummy Tr. 117, and a reset Tr. Are arranged as one Tr. Group 122.

  By arranging in this way, the L length of the amplified Tr. 116 can be increased (at least longer than other Tr.), And therefore RN (random noise) can be improved. Note that the amplification Tr. Is often long in the L length direction from the viewpoint of RN and has a long side in this embodiment, but the long side is not necessarily L length. That is, the L length represents the length in the direction connecting the source and drain.

  Not only the amplified Tr. 116 but also the L length of the selected Tr. 117 may be extended. When the L length of the selected Tr. Is extended, it is difficult to receive the short channel effect and a robust characteristic can be obtained.

  Further, each pixel Tr. Of the Tr. Group 122 is arranged so as to be symmetrical with respect to each photodiode 111 of the PD group 121 in a positional manner (that is, optically of the photodiode). Yes.

  That is, as indicated by the dotted circle, there is an amplification Tr. 116 on the side of the lower right photodiode 111 in the upper four pixels, but the lower right photodiode 111 in the lower four pixels. Since there is no Tr. On the side, the same color (for example, Green), but the density of poly-Si is different, and the optical characteristics may change.

  Therefore, in the solid-state imaging device 101, the dummy Tr. 117 that is a dummy of the reset Tr. 118 is arranged in the Tr. Group 122, and two reset Tr. That is, the selection Tr. 115 and the amplification Tr. 116 are arranged in the vicinity of the transfer Tr. 112 in the upper four pixels, and the dummy Tr. 117 and the reset are in the vicinity of the transfer Tr. 112 in the lower four pixels. Tr. 118 is arranged. The dummy Tr. 117 is not necessarily driven as a Tr. That is, the dummy Tr. 117 may be driven or may be disposed and not driven.

  As described above, in the Tr. Group 122, the layout (gate / source and drain size) substantially the same as the selection Tr. 115 and the amplification Tr. Since it can be ensured by Tr. 118, symmetry can be improved. Thereby, in the solid-state imaging device 101, it is possible to reduce the influence caused by the difference in the density of the poly-Si of Tr. And improve PRNU (Photo Response Non Uniformity).

  The dummy Tr. 117 is not limited to the reset Tr. 118 dummy and may be a dummy of another Tr.

  Further, in the solid-state imaging device 101, the well contact 113 is arranged between the PD group 121 and another PD group 121 (not shown) arranged up and down in the drawing. As a result, an area for additional Tr. Is efficiently secured. The interval at which the PD group 121 is arranged is hereinafter referred to as the PD group 121 pitch.

  Furthermore, since the well contact 113 affects various pixel characteristics (particularly dark current), the difference between the pixels is reduced by arranging the well contact 113 between the PD group 121 and the other PD groups 121 arranged above and below in the figure. Can be suppressed. That is, by disposing the well contact 113 in this manner, any PD is present at an equal distance, so that a difference between pixels hardly occurs.

  Further, as a countermeasure against PRNU, if the symmetry of Tr. Poly-Si is high, an additional dummy Tr. Is not necessarily required as shown in FIG.

<Other arrangement examples of Tr.>
6 is a diagram illustrating an arrangement example of photodiodes and Tr. In a solid-state imaging device to which the present technology is applied.

  In the solid-state imaging device 151 of FIG. 6, the Tr. Group 122 is arranged on the long side of one PD group 121 composed of the photodiodes 111 for 2 × 4 pixels, similarly to the solid-state imaging device 101 of FIG. 5. Has been. Therefore, as indicated by the L length of the amplified Tr. 116, the L length of the existing Tr. Can be increased, so that RN (random noise) can be improved.

  On the other hand, the solid-state imaging device 151 of FIG. 6 differs from the solid-state imaging device 101 of FIG. 5 in that the dummy Tr. 117 is removed from the Tr. Group 122 and the arrangement position of the Tr. Yes.

  That is, in the Tr. Group 122, the amplification Tr. 116 is arranged in the vicinity of the right side of the transfer Tr. 112 for the upper four pixels in the figure, and the selection Tr. 115 and the reset Tr. As indicated by P2, the photodiodes 111 for the upper four pixels in the figure are arranged at the corners on the side where there is no transfer Tr. 112. As indicated by the arrow P3, the selection Tr. 115 of the Tr. Group 122 corresponding to the other PD group 121 arranged under the PD group 121 is also the photodiode 111 for the lower four pixels in the figure. Is arranged at the corner on the side where there is no transfer Tr.

  For this reason, the Tr. Group 122 is disposed so as to be shifted upward in the drawing with respect to the position of the PD group 121. In the example of FIG. 5, the positions of the PD group 121 and the Tr. Group 122 are aligned. On the other hand, for example, in the example of FIG. 6, the Tr. Group 122 is shifted upward by the length of the long side of one photodiode 111 with respect to one shared rectangle of the PD group 121 ( Is shifting). The shift amount is not limited to the length of the long side of one photodiode 111. The same applies to the following.

  Further, in the solid-state imaging device 151 of FIG. 6, a well contact 113 is provided in the vicinity of the right side of the transfer Tr. 112 for the lower four pixels in the drawing in order to increase the symmetry of the photodiodes 111 for the upper and lower four pixels. Is arranged. Note that the amplification Tr. 116 and the well contact 113 do not necessarily need to be directly beside the transfer Tr. 112 for four pixels, and the above-described symmetry effect can be desired as long as it is near the beside.

  As described above, in the solid-state imaging device 151 of FIG. 6, even if no dummy Tr. Is provided, the reset Tr., Amplification Tr., And selection Tr. Therefore, PRNU can be improved.

  In the solid-state imaging device 151 in FIG. 6, unlike the solid-state imaging device 101 in FIG. 5, the well contact 113 is not arranged between the PD groups 121. In that case, it is also possible to arrange the well contacts 113 between the PD groups 121 as in the example of FIG.

  Furthermore, as shown in FIG. 7, it is also possible to arrange the location of each Tr. In the Tr. Group 122 in a layout that allows both PRNU countermeasures and RN countermeasures to be compatible.

  7 is different from the solid-state imaging device 151 of FIG. 6 in that the amplified Tr. 116 is replaced with the amplified Tr. 211 whose L length is maximized in the Tr. Group 122. The solid-state imaging device 201 of FIG. .

  That is, in the solid-state imaging device 201 of FIG. 7, the L length of the amplified Tr. 211 in the Tr. Group 122 is maximally longer than the L length of the amplified Tr.

  Thus, in the solid-state imaging device 201 of FIG. 7, the Tr. Group 122 is arranged on the long side of the PD group 121 composed of the photodiodes 111 for 2 × 8 pixels, as in the solid-state imaging device 101 of FIG. Is arranged. Therefore, as indicated by the L length of the amplified Tr. 211, the L length of the existing Tr. Can be increased, so that RN (random noise) can be improved.

  More specifically, in the Tr. Group 122, the amplified Tr. 211 is arranged near the right side of the transfer Tr. 112 for the upper four pixels in the figure, and the selected Tr. 115 and the reset Tr. As shown by arrows P11 and P12, the photodiodes 111 for the upper four pixels in the drawing are arranged at the corners on the side where there is no transfer Tr. 112. As indicated by the arrow P13, the selected Tr. 115 of the Tr. Group 122 corresponding to the other PD group 121 arranged under the PD group 121 is also the photodiode 111 for the lower four pixels in the figure. Is arranged at the corner on the side where there is no transfer Tr.

  In this case as well, the Tr. Group 122 is entirely displaced from the position of the PD group 121 on the upper side in the drawing.

  As described above, in the solid-state imaging device 201 of FIG. 7, the dummy Tr. Is not disposed and the L length of the amplified Tr. Is extended to the maximum, so that RN can be improved. Since the selection Tr. 115 and the reset Tr. 118 are arranged so as to have symmetry with respect to the photodiode, PRNU can be improved.

  Further, in the solid-state imaging device 201 in FIG. 7, the well contact 113 is formed between the PD group 121 and another PD group 121 (not shown) arranged at the bottom in the figure, as in the solid-state imaging device 101 in FIG. Arranged between.

  Therefore, in the solid-state imaging device 201 of FIG. 7, the difference between pixels can be suppressed to be small as in the solid-state imaging device 101 of FIG. If the element isolation width between the PDs can be reduced and the well contact 113 cannot be arranged between the PDs, it can be arranged in the Tr. Group 122 as in the example of FIG. .

  Furthermore, as shown in FIG. 8, the most symmetric layout is that the arrangement of Tr. Poly-Si is almost equal to the arrangement of the photodiodes 111 of the PD group 121, so that the PRNU is further increased. Can improve.

  That is, in the solid-state imaging device 251 of FIG. 8, in the Tr. Group 122, the selected Tr. 115 is disposed in the vicinity of the side of the well contact 113 disposed in the upper part of the PD group 121 in the drawing. In addition, an amplification Tr. 116 is arranged near the right side of the transfer Tr. 112 for the upper four pixels of the PD group 121 in the figure, and a reset Tr. 118 includes a photodiode 111 for the four pixels of the PD group 121, It is arranged in the vicinity of the photodiode 111 for four pixels.

  Further, a dummy Tr. 117 is arranged in the vicinity of the right side of the transfer Tr. 112 for four pixels on the lower side of the PD group 121 in the figure.

  As described above, in the solid-state imaging device 251 of FIG. 8, Tr. Poly-Si is arranged more evenly with respect to the arrangement of the photodiodes of the PD group 121. In this case, since the L length of the amplification Tr. 116 cannot be extended as compared with the solid-state imaging device 101 of FIG. 5, RN cannot be improved much, but it is the best PRNU countermeasure. Further, since the well contact 113 is also arranged between the PD group as in the solid-state imaging device 101 of FIG. 5, the difference in pixel characteristics between pixels can be reduced. The dummy Tr. 117 is not always necessary. That is, since the Poly-Si density is already high in the vicinity of the transfer Tr. 112, the Poly-Si beside the transfer Tr. 112 may not affect the PRNU. In that case, a layout without dummy Tr. 117 is also an option.

<2. Second Embodiment>
<Configuration example of solid-state imaging device of the present technology>
FIG. 9 is a diagram illustrating another configuration example of the solid-state imaging device to which the present technology is applied. In the example of FIG. 9, an example in which the solid-state imaging device is configured by a back-illuminated CMOS sensor of 4Tr. Type 2 pixel sharing (1 × 2 pixels) is shown. The example in FIG. 9 is an example in the case where the layout shown in FIG. 5 is applied to two-pixel sharing.

  In the solid-state imaging device 301 in FIG. 9, the photodiode 111 for 1 × 2 pixels sharing pixels and the corresponding transfer Tr. 112 for 1 × 2 pixels are located in the photodiode region on the left side in the drawing. The PD group 121 is arranged so as to be a vertically long rectangle.

  Further, on the long side of the PD group 121, a pixel Tr. Including a selection Tr. 115, an amplification Tr. 116, a dummy Tr. 117, and a reset Tr. 118 is arranged in the Tr. Each pixel Tr. Of the Tr. Group 122 is arranged so as to have symmetry with respect to each photodiode 111 of the PD group 121.

  That is, in the Tr. Group 122 of FIG. 9, the selected Tr. 115 is arranged near the center of the upper photodiode 111 in the PD group 121, and the reset Tr. It is arranged near the center of the lower photodiode 111 in the PD group 121.

  Similarly, in the Tr. Group 122 of FIG. 9, the amplified Tr. 116 is arranged in the vicinity of the upper transfer Tr. 112 in the PD group 121, and the dummy Tr. , Arranged in the vicinity of the lower transfer Tr. 112 in the PD group 121.

  As described above, also in the case of sharing two pixels, the same effect as in the case of sharing eight pixels described above with reference to FIG. 5 can be obtained. That is, by arranging the Tr. Group 122 on the long side of the PD group 121, the L length of the amplified Tr. Can be increased, so that RN (random noise) can be improved. In addition, since the symmetry of Tr. Poly-Si with respect to the photodiode is high, PRNU can be improved.

  In the case of the solid-state imaging device 301 in FIG. 9, the well contact 113 is disposed between the Tr. Group 122 and the other Tr. Group 122 positioned above, but as in the example of FIG. It is also possible to place it between PD and PD.

<3. Third Example>
<Configuration example of solid-state imaging device of the present technology>
FIG. 10 is a diagram illustrating another configuration example of the solid-state imaging device to which the present technology is applied. In the example of FIG. 10, an example in which the solid-state imaging device is configured by a back-illuminated CMOS sensor sharing 4Tr. Type 16 pixels (2 × 8 pixels) is shown. The example of FIG. 10 is an example in the case where the layout shown in FIG. 5 is applied to 16 pixel sharing.

  In the solid-state imaging device 351 in FIG. 10, the photodiode 111 for 2 × 8 pixels sharing pixels and the corresponding transfer Tr. 112 for 2 × 8 pixels are located in the photodiode region on the left side of the drawing. 1 PD group 121 is arranged.

  In the PD group 121, the photodiodes 111 and the transfer Tr. 112 for 2 × 8 pixels are arranged so as to be vertically long and arranged in four vertical rows in the drawing for every four pixels.

  Further, on the long side (right side in the drawing) of the PD group 121, the Tr. Group 122 having one pixel Tr. Consisting of the selection Tr. 115, the amplification Tr. 116, the dummy Tr. 117, and the reset Tr. Has been. A well contact 113 is arranged on the upper side of the Tr. Group 122 in the figure. The well contact 113 and each pixel Tr. Of the Tr. Group 122 are arranged so as to have symmetry with respect to each photodiode 111 of the PD group 121.

  That is, in the example of FIG. 10, the well contact 113 is disposed in the vicinity of the right side of the transfer Tr. 112 for four pixels in the first stage from the top in the drawing. In the Tr. Group 122, the selected Tr. 115 is arranged in the vicinity of the position opposite to the transfer Tr. 112 of the photodiode 111 for the four pixels in the second stage from the top in the PD group 121 in the drawing.

  In the Tr. Group 122, the amplified Tr. 116 is arranged in the vicinity of the position of the transfer Tr. 112 of the photodiode 111 for the four pixels in the second stage from the top in the drawing in the PD group 121. In the Tr. Group 122, the dummy Tr. 117 is arranged in the vicinity of the position of the transfer Tr. 112 of the photodiode 111 corresponding to the fourth pixel in the third stage from the top in the drawing in the PD group 121. The reset Tr. 118 is arranged in the PD group 121 in the vicinity of the position opposite to the transfer Tr. 112 of the photodiode 111 in the fourth stage from the top in the drawing.

  As described above, also in the case of 16 pixel sharing, the same effect as in the case of 8 pixel sharing described above with reference to FIG. 5 can be obtained. That is, in the solid-state imaging device 351 in FIG. 10, as in the solid-state imaging device 101 in FIG. 5, the Tr. Group is arranged on the long side of one PD group 121 composed of the photodiodes 111 for 2 × 8 pixels. Since 122 is arranged, the L length of the existing Tr. Can be increased as shown in the L length of the amplified Tr. Thereby, RN (random noise) can be improved. In addition, since the symmetry of Tr. Poly-Si with respect to the photodiode is high, PRNU can be improved.

  However, also in the case of the solid-state imaging device 351 in FIG. 10, the well contact 113 is disposed between the Tr. Group 122 and the other Tr. Group 122 positioned above, and the well contact 113 is disposed between the PD group 121. Since they are not arranged, the influence of the difference between pixels may remain. In that case, it is possible to arrange the well contact 113 between the PDs as in the example of FIG. When arranged between four pixels in each stage, there is a possibility that the inter-pixel difference in characteristics can be reduced.

  As described above, the present technology can be applied when one share is rectangular, such as 4Tr. Type 2-pixel sharing, 8-pixel sharing, and 16-pixel sharing. That is, the number of shared pixels is not limited, and the arrangement of the solid-state imaging devices is not limited as long as the arrangement of photodiodes in one share is rectangular.

  Further, regarding the arrangement of the Tr., The variation of the arrangement of the 4Tr. Type 8-pixel sharing (2 × 4 pixels) described in the first embodiment can also be applied to 2-pixel sharing and 16-pixel sharing.

<4. Fourth embodiment>
<Configuration example of solid-state imaging device of the present technology>
FIG. 11 is a diagram illustrating a configuration example of a solid-state imaging device to which the present technology is applied. In the example of FIG. 11, an example in which the solid-state imaging device is configured with a 3Tr. Type 8-pixel shared (2 × 4 pixel) back-illuminated CMOS sensor is illustrated.

  In general, the 3Tr. Type has two transistors, the reset Tr. (RST) and amplification Tr. (AMP) described above, in addition to the photodiode region where the photodiode is arranged. There is no. Since the transfer Tr. Is directly connected to the photodiode, it is assumed that the transfer Tr. Is arranged in the photodiode region.

  11 is different from the solid-state imaging device 101 of FIG. 5 in that the selected Tr. 115 and the dummy Tr. 117 are removed from the Tr. Group 122. The solid-state imaging device 401 of FIG. It is common to the solid-state imaging device 101 of FIG. 5 that the arrangement fits in the rectangle shared by the solid-state imaging device 4011 of FIG. 11 (the PD group and the Tr. Group are directly beside).

  That is, in the Tr. Group 122, the amplification Tr. 116 is arranged near the right side of the transfer Tr. 112 for the upper four pixels in the figure, and the reset Tr. 118 is equivalent to the lower four pixels in the figure. It is arranged near the side of the transfer Tr. In the example of FIG. 11, the amplification Tr. 116 and the reset Tr. 118 are configured with substantially the same size.

  In the solid-state imaging device 451 in FIG. 12, the arrangement position of the Tr. Group 122 in FIG. 11 is shifted upward in the drawing by, for example, the length of the long side of one photodiode 111. That is, in the Tr. Group 122, the amplification Tr. 116 is arranged in the vicinity of the position not on the transfer Tr. 112 side of the photodiode 111 for the upper four pixels in the figure, and the reset Tr. The photodiode 111 for the middle and lower four pixels is arranged near the side of the transfer Tr. 112 that is not on the side. Also in the example of FIG. 12, the amplification Tr. 116 and the reset Tr. 118 are configured to have substantially the same size.

  That is, also in the solid-state imaging device 401 in FIG. 11 and the solid-state imaging device 451 in FIG. 12, the Tr. Group 122 is arranged on the long side of the PD group 121, so that the L length of the amplified Tr. Thus, the L length of the existing Tr. Can be increased. Thereby, RN (random noise) can be improved. Also, in the solid-state imaging device 401 in FIG. 11 and the solid-state imaging device 451 in FIG. 12, Tr. Poly-Si has symmetry with respect to the photodiode, so PRNU can be improved.

  As described above, the present technology can be applied to all 3Tr. Types when one share is arranged in a rectangle. That is, the number of shared pixels is not limited, and the arrangement of the solid-state imaging devices is not limited as long as the arrangement of photodiodes in one share is rectangular.

  In the above description, an example (vertical example) in which the short side of 1 pixel sharing is arranged on the upper side in the figure and the long side of 1 pixel sharing is on the right side of the figure has been described. Rotating it 90 degrees and laying out the solid-state imaging device so that the long side of 1 pixel sharing is on the upper side in the drawing and the short side of 1 pixel sharing is on the left side of the drawing is the same. .

  As described above, according to the present technology, the L length of Tr. (Particularly amplified Tr.) Can be increased, so that RN (random noise) can be improved.

  That is, in the case of a solid-state imaging device in which AMP / SEL is arranged in group 1 and two Tr. 2 are arranged in group 2, six sources, three in group 1 and three in group 2, are required. At this time, there was a limit to the extension of the Tr.L length due to the litho line width limit, the processing limit between poly-Si and contacts, and the isolation breakdown voltage. In particular, this effect is significant when miniaturized, and there is a risk that RN may deteriorate due to the short L length of AMP.

  On the other hand, according to the present technology, since the L length of the amplified Tr. Can be extended, RN is improved. In the above example, the L length of the amplified Tr. Is preferably 0.6 to 1.4 times the pitch of the PD group. Further, according to the present technology, since it is possible to extend the L length of the selected Tr., When the L length of the selected Tr. Is extended, it is difficult to receive the short channel effect and a robust characteristic can be obtained.

  The above effects can be obtained more particularly when the pixel size is about 1.0 mm or less.

  In addition, according to the present technology, PRNU can be improved because it is arranged so as to have Tr. Poly-Si symmetry.

  In the above, the configuration in which the present technology is applied to the CMOS solid-state imaging device has been described. However, the present technology may be applied to a solid-state imaging device such as a CCD (Charge Coupled Device) solid-state imaging device.

  The solid-state imaging device may be a backside illumination type or a frontside illumination type.

  Furthermore, the solid-state imaging device may or may not be a global shutter type. It is not limited to the global shutter type.

  In addition, this technique is not restricted to application to a solid-state imaging device, It can apply also to an imaging device. Here, the imaging apparatus refers to a camera system such as a digital still camera or a digital video camera, or an electronic apparatus having an imaging function such as a mobile phone. In some cases, a module-like form mounted on an electronic device, that is, a camera module is used as an imaging device.

<5. Fifth embodiment>
<Configuration example of electronic equipment>
Here, with reference to FIG. 13, the structural example of the electronic device of the 2nd Embodiment of this technique is demonstrated.

  An electronic apparatus 500 shown in FIG. 13 includes a solid-state imaging device (element chip) 501, an optical lens 502, a shutter device 503, a drive circuit 504, and a signal processing circuit 505. As the solid-state imaging device 501, the above-described solid-state imaging devices according to the first to fourth embodiments of the present technology are provided. As a result, it is possible to provide a high-performance electronic device 500 with improved RN and PRNU.

  The optical lens 502 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 501. As a result, signal charges are accumulated in the solid-state imaging device 501 for a certain period. The shutter device 503 controls the light irradiation period and the light shielding period for the solid-state imaging device 501.

  The drive circuit 504 supplies a drive signal for controlling the signal transfer operation of the solid-state imaging device 501 and the shutter operation of the shutter device 503. The solid-state imaging device 501 performs signal transfer according to a drive signal (timing signal) supplied from the drive circuit 504. The signal processing circuit 505 performs various types of signal processing on the signal output from the solid-state imaging device 501. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  In the present specification, the steps describing the series of processes described above are not limited to the processes performed in time series according to the described order, but are not necessarily performed in time series, either in parallel or individually. The process to be executed is also included.

  The embodiments in the present disclosure are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present disclosure.

  In addition, each step described in the above flowchart can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.

  Further, when a plurality of processes are included in one step, the plurality of processes included in the one step can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.

  In addition, in the above description, the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units). Conversely, the configurations described above as a plurality of devices (or processing units) may be combined into a single device (or processing unit). Of course, a configuration other than that described above may be added to the configuration of each device (or each processing unit). Furthermore, if the configuration and operation of the entire system are substantially the same, a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or other processing unit). . That is, the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.

  The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the disclosure is not limited to such examples. It is obvious that various changes and modifications can be conceived within the scope of the technical idea described in the claims if the person has ordinary knowledge in the technical field to which the present disclosure belongs, Of course, it is understood that these also belong to the technical scope of the present disclosure.

    DESCRIPTION OF SYMBOLS 1 Solid-state imaging device, 2 pixels, 3 pixel area, 101 Solid-state imaging device, 111 Photodiode, 112 Transfer Tr., 113 Well contact, 114 Source drain, 115 Selection Tr., 116 Amplification Tr., 117 Dummy Tr., 118 Reset Tr., 121 PD group, 122 Tr group, 151, 201 solid-state imaging device, 211 amplification Tr., 251, 301, 351, 401, 451 solid-state imaging device, 500 electronic device, 501 solid-state imaging device, 502 optical lens , 503 shutter device, 504 drive circuit, 505 signal processing circuit

Claims (18)

One shared shape is a rectangle, and one photoelectric conversion element group including eight photoelectric conversion elements in one shared unit;
A pixel transistor group that is arranged as one group in the long side direction of the photoelectric conversion element group and includes a reset transistor, an amplification transistor, and a selection transistor,
The eight photoelectric conversion elements share one floating fusion with four photoelectric conversion elements,
The arrangement direction of two floating fusions shared by the photoelectric conversion element group is the same as the long side direction of the photoelectric conversion element group. The solid-state imaging device according to claim 1, wherein the pixel transistor group includes a dummy transistor. The solid-state imaging device according to claim 1, wherein the pixel transistor group is arranged to be shifted with respect to one shared rectangle of the photoelectric conversion element group. 4. The solid-state imaging device according to claim 1, wherein an L length of an amplification transistor included in the pixel transistor group is longer than an L length of another transistor included in the pixel transistor group. The solid-state imaging device according to claim 4, wherein an L length of an amplification transistor included in the pixel transistor group is 0.6 to 1.4 times a pitch of the photoelectric conversion element group. The solid-state imaging device according to claim 1, wherein an L length of a selection transistor included in the pixel transistor group is longer than an L length of another transistor included in the pixel transistor group. The solid-state imaging device according to claim 1, further comprising a well contact between the photoelectric conversion element group and another photoelectric conversion element group located next to the photoelectric conversion element group. The solid-state imaging device according to claim 1, further comprising a well contact between the pixel transistor group and another pixel transistor group located next to the pixel transistor group. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is a backside illumination type. One shared shape is a rectangle, and one photoelectric conversion element group including eight photoelectric conversion elements in one shared unit;
A pixel transistor group that is arranged as one group in the long side direction of the photoelectric conversion element group and includes a reset transistor, an amplification transistor, and a selection transistor,
The eight photoelectric conversion elements share one floating fusion with four photoelectric conversion elements,
The solid-state imaging device in which the arrangement direction of the two floating fusions shared by the photoelectric conversion element group is the same as the long side direction of the photoelectric conversion element group;
A signal processing circuit for processing an output signal output from the solid-state imaging device;
And an optical system that makes incident light incident on the solid-state imaging device. The electronic device according to claim 10, wherein the pixel transistor group includes a dummy transistor. The electronic device according to claim 10, wherein the pixel transistor group is arranged so as to be shifted with respect to one shared rectangle of the photoelectric conversion element group. The electronic device according to claim 10, wherein an L length of an amplification transistor included in the pixel transistor group is longer than an L length of other transistors included in the pixel transistor group. The electronic device according to claim 13, wherein an L length of an amplification transistor included in the pixel transistor group is 0.6 to 1.4 times a pitch of the photoelectric conversion element group. The electronic device according to claim 10, wherein an L length of a selection transistor included in the pixel transistor group is longer than an L length of another transistor included in the pixel transistor group. The electronic device according to claim 10, further comprising a well contact between the photoelectric conversion element group and another photoelectric conversion element group located next to the photoelectric conversion element group. The electronic device according to claim 10, further comprising a well contact between the pixel transistor group and another pixel transistor group located next to the pixel transistor group. The electronic device according to claim 10, wherein the solid-state imaging device is a backside illumination type.

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