JP6276297B2 - Solid-state imaging device and electronic device - Google Patents

Description

  The present invention relates to a CMOS-type solid-state imaging device and an electronic apparatus including the solid-state imaging device and applied to, for example, a camera.

  A CMOS solid-state imaging device is known as a solid-state imaging device. CMOS solid-state imaging devices have low power supply voltage and low power consumption, so they are used in various portable terminal devices such as digital still cameras, digital video cameras, and camera-equipped mobile phones, printers, and the like.

  Unlike a CCD solid-state imaging device, a CMOS solid-state imaging device includes a plurality of pixel transistors in addition to a photodiode PD in which pixels arranged in a pixel region are photoelectric conversion units. In a normal unit pixel, a pixel transistor is formed of four transistors, a transfer transistor including a floating diffusion portion FD serving as a voltage conversion portion, a reset transistor, an amplification transistor, and a selection transistor. Alternatively, the pixel transistor is formed of three transistors including a transfer transistor, a reset transistor, and an amplification transistor, omitting the selection transistor. Thus, since a photodiode and a plurality of pixel transistors are required as unit pixels, it has been difficult to reduce the size of the pixels.

  However, in recent years, a so-called multiple pixel sharing structure that suppresses the occupied area other than the photodiode PD per pixel by sharing the pixel transistor with a plurality of pixels has become an essential technology. FIG. 29 shows an example of a solid-state imaging device in which shared pixels having a multi-pixel sharing structure disclosed in Patent Document 1 are two-dimensionally arranged. This solid-state imaging device 91 is an example in which the photodiode PD is shared by four pixels in a zigzag arrangement. In the solid-state imaging device 91, a pair sharing one floating diffusion portion FD is two-dimensionally arranged by two photodiodes PD adjacent obliquely. The shared pixel has four photodiodes PD1 to PD4 in a zigzag arrangement by two sets adjacent in the vertical direction, and two circuit groups (pixel transistors) in the pixel transistor formation region 114 divided into the upper and lower positions of one set. Configured.

  Transfer gate electrodes TG [TG1 to TG4] are formed between the two sets of floating diffusion portions FD and the two photodiodes PD sandwiching the floating diffusion portions FD. In the shared pixel, the above two sets are electrically connected to two circuit groups in the pixel transistor region 94 via the connection wiring 92, and the four photodiodes PD1 to PD4 are shared in the vertical direction. That is, the floating diffusion portions FD1 and FD2, the gate electrode (not shown) of the amplification transistor, and the source (not shown) of the reset transistor are connected by a connection wiring (so-called FD wiring) 92 along the vertical direction.

  Patent Documents 2 to 6 disclose prior art CMOS solid-state imaging devices. Patent Documents 2 and 3 disclose a CMOS solid-state imaging device sharing two pixels. Patent Document 4 discloses a CMOS solid-state imaging device sharing a total of four pixels of two vertical pixels and two horizontal pixels. Patent Document 5 discloses a backside illumination type CMOS solid-state imaging device. Patent Document 5 discloses a CMOS solid-state imaging device that corrects vertical stripes.

JP 2006-54276 A JP 2004-172950 A JP 2005-157953 A JP 2009-135319 A JP 2003-31785 A JP 2005-223860 A

  Incidentally, in the shared pixel configuration shown in FIG. 29, among the divided pixel transistors as shown in FIG. 30, the reset transistor Tr2 is arranged on the upper side, and the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 is arranged on the lower side. Configuration is conceivable. The reset transistor Tr2 includes a reset gate electrode 106, a source region 104, and a drain region 105. The amplification transistor Tr3 includes an amplification gate electrode 109, and the diffusion regions 116 and 117 are configured as a source region and a drain region. The selection transistor Tr4 includes a selection gate electrode 118, and the diffusion regions 115 and 116 are configured as a source region and a drain region.

  The reset transistor Tr2 and the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 are formed in the same layout for each column of the shared pixels. Tr11 to Tr14 indicate transfer transistors. In the shared pixels in each column, the two floating diffusion portions FD1 and FD2, the amplification gate electrode 109, and the source region 104 of the reset transistor Tr2 are electrically connected by FD wirings 92A and 92B.

Considering such a pixel transistor layout, it is desirable that the amplification transistor Tr3 has a gate length as long as possible from the viewpoint of random noise. Further, the amplification transistor Tr3 and the selection transistor Tr4 need to have a certain distance d1.
The diffusion region that becomes the source / drain region of the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 also needs a certain distance d2 in order to be electrically separated from the diffusion region of the same series circuit of the shared pixels in the adjacent columns. It is.

  Then, every time the array of shared pixels is increased, the symmetry between the shared photodiode PD and the series circuit of the amplification / selection transistors is broken. As a result, the wiring lengths of the FD wirings 92A and 92B connecting the floating diffusion portions FD1 and FD2 are different for each column of shared pixels as shown by frames A and B in FIG. There is a difference. In terms of image quality, vertical stripes occur because of the difference between the sensitivity columns.

  FIG. 31 and FIG. 32 show an example of a CMOS solid-state imaging device of a vertical 4-pixel sharing system as another pixel sharing system. In the solid-state imaging device 81 shown in FIG. 31, a set sharing two photodiodes PD adjacent to each other in the vertical (longitudinal) direction and one floating diffusion portion FD is two-dimensionally arranged. The shared pixel is formed by arranging two photodiodes PD1 to PD4 vertically arranged adjacent to each other in the vertical direction and pixel transistors corresponding to two pixel columns below each group. The transfer transistors Tr11 to Tr14 are arranged corresponding to the respective photodiodes PD1 to PD4.

  Here, each transfer gate electrode TG is formed in common with the transfer gate electrodes in adjacent columns. In the pixel transistor arranged on the lower side of each set having two photodiodes PD, a series circuit of an amplification transistor Tr3 and a selection transistor Tr4 and a reset transistor Tr2 are formed along the row direction. In other words, the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 and the reset transistor Tr2 are arranged side by side in the same row direction with respect to the shared pixels in the adjacent columns. The FD wirings 92A and 92B are arranged in the illustrated layout. In FIG. 31, parts corresponding to those in FIG.

  The solid-state imaging device 82 shown in FIG. 32 is different from FIG. 31 in the layout of pixel transistors arranged on the lower side of each set having two photodiodes PD. That is, only the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 is arranged below the one set and arranged in the same row direction, and only the reset transistor Tr2 is arranged below the other set and arranged in the same row direction. Is done. That is, the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 and the reset transistor Tr2 are arranged in the row direction in the same direction with respect to the shared pixels in the adjacent columns. The FD wirings 92A and 92B are arranged in the illustrated layout. In FIG. 32, parts corresponding to those in FIG.

  As shown in FIGS. 31 and 32, in the solid-state imaging devices 81 and 82, the objectivity of the wiring length of the FD wiring 92A92B is lost between the columns, the difference in the conversion efficiency between the columns occurs, and the sensitivity between the columns is generated.

  On the other hand, when, for example, a Bayer color filter is used, in any of the solid-state imaging devices 100, 81, and 82 shown in FIGS. 30 to 32, the Gb pixel that is a green pixel and the pixel Gr overlap the polysilicon gate electrode. Since (areas) are different from each other, a difference occurs in the light absorption of the gate electrode, resulting in a difference in sensitivity.

In view of the above, the present invention provides a solid-state imaging device in which a difference in sensitivity is unlikely to occur in a solid-state imaging device having shared pixels.
The present invention provides an electronic apparatus that includes the solid-state imaging device and is applied to a camera or the like.

The solid-state imaging device according to the present invention includes a first photoelectric conversion unit including a plurality of photoelectric conversion units, a first floating diffusion unit shared by the plurality of photoelectric conversion units of the first photoelectric conversion unit, and a first photoelectric conversion unit. A first shared pixel having one reset transistor, a first amplification transistor, and a first selection transistor; a second photoelectric conversion unit including a plurality of photoelectric conversion units; and a plurality of photoelectric conversion units of the second photoelectric conversion unit And a second shared pixel having a second floating diffusion portion and a second reset transistor, a second amplification transistor, and a second selection transistor, and the second shared pixel and the second shared pixel in adjacent columns. Between the shared pixels, the first photoelectric conversion unit and the second photoelectric conversion unit are arranged in the same direction and arranged in the same row, and the first selection transistors arranged in the row direction And a series circuit of the first amplification transistor and a series circuit of the second amplification transistor and the second selection transistor are arranged in the first row adjacent to each other in a state inverted in the row direction, The reset transistor and the second reset transistor are arranged in the same direction in a second row, the source region of the first reset transistor, the amplification gate electrode of the first amplification transistor, and the first floating diffusion portion A connection wiring electrically connecting the source region of the second reset transistor, an amplification gate electrode of the second amplification transistor, and a connection wiring electrically connecting the second floating diffusion portion. Are the same length.

  In the solid-state imaging device of the present invention, the shared pixel transistors are divided and arranged in the column direction of the shared pixels, and the first selection transistor, the first amplification transistor, the second amplification transistor, and the second selection transistor are shared between the adjacent shared pixels. Are arranged in this order in the first row, the symmetry of each shared pixel including the FD wiring is improved. For example, the wiring length of the FD wiring between adjacent shared pixels becomes the same, and the capacitance applied to the FD wiring becomes constant for each shared pixel, so that a difference in photoelectric conversion efficiency is less likely to occur.

  An electronic apparatus according to the present invention includes the above-described solid-state imaging device, an optical system that guides incident light to a photoelectric conversion unit of the solid-state imaging device, and a signal processing circuit that processes an output signal of the solid-state imaging device.

  Since the electronic apparatus according to the present invention includes the solid-state imaging device according to the present invention described above, a difference in sensitivity between shared pixels is less likely to occur.

  According to the solid-state imaging device according to the present invention, it is possible to provide a solid-state imaging device having a shared pixel that hardly causes a difference in sensitivity in a solid-state imaging device having a shared pixel.

  According to the electronic device according to the present invention, since the solid-state imaging device having the shared pixel that is unlikely to cause a sensitivity difference is provided, an image quality can be improved and a highly reliable electronic device can be provided.

It is a schematic block diagram of the CMOS solid-state imaging device applied to this invention. It is a principal part block diagram which shows 1st Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram of the principal part which shows the solid-state imaging device which concerns on a 1st comparative example. It is a principal part block diagram which shows 2nd Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram of the principal part which shows the solid-state imaging device which concerns on a 2nd comparative example. It is a principal part block diagram which shows 3rd Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram of the principal part which shows the solid-state imaging device which concerns on a 3rd comparative example. It is a principal part block diagram which shows 4th Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram of the principal part which shows the solid-state imaging device which concerns on a 4th-1 comparative example. It is a block diagram of the principal part which shows the solid-state imaging device which concerns on a 4th-2 comparative example. It is a principal part block diagram which shows 5th Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram of the principal part which shows the solid-state imaging device which concerns on a 5th-1 comparative example. It is a block diagram of the principal part which shows the solid-state imaging device concerning the 5-2 comparative example. It is a principal part block diagram which shows 6th Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram of the principal part which shows the solid-state imaging device which concerns on a 6th comparative example. It is a principal part block diagram which shows 7th Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram of the principal part which shows the solid-state imaging device which concerns on a 7th comparative example. It is a principal part block diagram which shows 8th Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram of the principal part which shows the solid-state imaging device which concerns on an 8th comparative example. It is a principal part block diagram which shows 9th Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram of the principal part which shows the solid-state imaging device which concerns on a 9th comparative example. It is an equivalent circuit diagram of 3 pixel type 4 pixel sharing. FIG. 4 is an equivalent circuit diagram of a 4-transistor 4-pixel sharing. It is an equivalent circuit diagram of a 3-transistor type 2-pixel sharing. It is a 4-transistor type 2 pixel sharing equivalent circuit diagram. FIG. 3 is an equivalent circuit diagram of a 3 transistor type 2 × 2 4 total pixel sharing. FIG. 4 is an equivalent circuit diagram of a 4-transistor type 2 × 2 4 total pixel sharing. It is a schematic block diagram of the electronic device which concerns on this invention. It is a block diagram of the principal part of the conventional solid-state imaging device with a common zigzag 4 pixel. It is a block diagram of the principal part of the conventional solid-state imaging device with a common zigzag 4 pixel. It is a block diagram of the principal part of the conventional solid-state imaging device of 3 transistor type | mold vertical 4 pixel sharing. It is a block diagram of the principal part of the conventional 4-transistor type solid-state imaging device sharing 4 vertical pixels.

Hereinafter, modes for carrying out the present invention (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. 1. Schematic configuration example of MOS solid-state imaging device 2. Basic configuration of solid-state imaging device according to embodiment First embodiment (configuration example of solid-state imaging device)
4). Second Embodiment (Configuration Example of Solid-State Imaging Device)
5. Third embodiment (configuration example of solid-state imaging device)
6). Fourth embodiment (configuration example of solid-state imaging device)
7). Fifth embodiment (configuration example of solid-state imaging device)
8). Sixth Embodiment (Configuration Example of Solid-State Imaging Device)
9. Seventh embodiment (configuration example of solid-state imaging device)
10. Eighth embodiment (configuration example of solid-state imaging device)
11. Ninth Embodiment (Configuration Example of Solid-State Imaging Device)
12 Tenth Embodiment (Configuration Example of Electronic Device)

<1. Schematic configuration example of CMOS solid-state imaging device>
FIG. 1 shows a schematic configuration of an example of a CMOS solid-state imaging device applied to each embodiment of the present invention. As shown in FIG. 1, the solid-state imaging device 1 of this example includes a pixel region (so-called imaging region) in which a plurality of pixels 2 including a photoelectric conversion unit are regularly arranged in a semiconductor substrate 11, for example, a silicon substrate. 3 and a peripheral circuit portion. As the pixel 2, a shared pixel in which a plurality of photoelectric conversion units share other pixel transistors excluding the transfer transistor is applied. The plurality of pixel transistors can be constituted by, for example, three transistors including a transfer transistor, a reset transistor, and an amplification transistor, or four transistors including a selection transistor.

  The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

  The control circuit 8 receives an input clock and data for instructing an operation mode, and outputs data such as internal information of the solid-state imaging device. That is, the control circuit 8 generates a clock signal and a control signal that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. These signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixels in units of rows. That is, the vertical drive circuit 4 sequentially selects and runs each pixel 2 in the pixel region 3 in the vertical direction in units of rows. Then, a pixel signal based on a signal charge generated in accordance with the amount of received light in, for example, a photodiode serving as a photoelectric conversion element of each pixel 2 is supplied to the column signal processing circuit 5 through the vertical signal line 9.

  The column signal processing circuit 5 is disposed, for example, for each column of the pixels 2, and performs signal processing such as noise removal on the signal output from the pixels 2 for one row for each pixel column. That is, the column signal processing circuit 5 performs signal processing such as CDS, signal amplification, and AD conversion for removing fixed pattern noise unique to the pixel 2. A horizontal selection switch (not shown) is connected to the horizontal signal line 10 at the output stage of the column signal processing circuit 5.

  The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

  The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10. For example, only buffering may be performed, or black level adjustment, column variation correction, various digital signal processing, and the like may be performed. The input / output terminal 12 exchanges signals with the outside.

  A front-illuminated CMOS solid-state imaging device is a shared pixel in which a pixel transistor is shared by photodiodes PD serving as a plurality of photoelectric conversion units in a first conductivity type, for example, a p-type semiconductor well region corresponding to a pixel region of a semiconductor substrate. A plurality of are formed. Each shared pixel is partitioned by an element isolation region. Above the surface side of the semiconductor substrate, a multilayer wiring layer having a plurality of wirings is formed via an interlayer insulating film except for the photodiode PD, and a color filter and a color filter and a planarizing film are formed on the multilayer wiring layer. On-chip lenses are stacked. Light is applied to the photodiode PD from the surface side of the semiconductor substrate through an on-chip lens.

  A back-illuminated CMOS solid-state imaging device includes a pixel transistor formed of a photodiode PD serving as a plurality of photoelectric conversion portions on a thinned semiconductor substrate, that is, a semiconductor substrate formed of a p-type semiconductor well region of the first conductivity type. A plurality of shared pixels are shared. Each shared pixel is partitioned by an element isolation region. A multilayer wiring layer having a plurality of layers of wirings is formed above the semiconductor substrate in the direction of the surface, and a support substrate made of, for example, a semiconductor substrate is bonded thereon. The wiring is not limited in arrangement and is also formed on the photodiode PD. A color filter and an on-chip lens are laminated on the back side of the semiconductor substrate. Light is irradiated to the photodiode PD from the back side of the semiconductor substrate through an on-chip lens.

<2. Basic Configuration of Solid-State Imaging Device According to Embodiment>
The solid-state imaging device according to the present embodiment, that is, a CMOS solid-state imaging device has a shared pixel that shares a pixel transistor among a plurality of photoelectric conversion units. These shared pixels are regularly arranged two-dimensionally to form a pixel region. The pixel transistor is configured, for example, as a three-transistor type including a transfer transistor, a reset transistor, and an amplifying transistor, or a four-transistor type including a selection transistor. Among the pixel transistors in the shared pixel, the transfer transistor is configured to have the same number of transfer transistors as the photoelectric conversion unit and one other shared pixel transistor. The pixel transistors to be shared, that is, the pixel transistors other than the transfer transistors are divided and arranged in the column direction of the shared pixels.

  In this embodiment, the shared pixel transistors are horizontally reversed, vertically crossed, or horizontally reversed between adjacent shared pixels, for example, between shared pixels in adjacent columns, or between adjacent rows. Arranged vertically crossing. The connection wiring connected to the floating diffusion portion FD, the source of the reset transistor, and the gate of the amplification transistor in each shared pixel, that is, the FD wiring is arranged along the column direction. Here, the row direction is defined as the direction along the row, and the column direction is defined as the direction along the column.

  According to the solid-state imaging device according to the present embodiment, the pixel transistors shared in the shared pixels are divided and arranged in the column direction, and the shared pixel transistors are horizontally reversed or / and vertically crossed between adjacent shared pixels. Be placed. With this configuration, the symmetry of each shared pixel including the FD wiring of the shared pixel is improved, the wiring length difference of the FD wiring is eliminated, and the wiring capacity of the FD wiring is constant for each shared pixel. Accordingly, a difference in photoelectric conversion efficiency between columns or rows is less likely to occur, and there is no sensitivity difference between columns or rows. As a result, in terms of image quality, there is no vertical streak in the so-called sensitivity light amount, which is not the amount of light until the photoelectric conversion unit is fully charged.

  In the case of using a Bayer color filter, the Gr pixel and the Gb pixel can be obtained by arranging the pixel transistors to be shared vertically adjacent to each other between the adjacent shared pixels or by combining the horizontal inversion and the vertical crossover. The occupancy ratio of the overlapping base electrode areas is the same. That is, the degree of light absorption by the gate electrode made of polysilicon is the same, and the difference in sensitivity between the Gr pixel and the Gb pixel is less likely to occur. Therefore, it is possible to provide a solid-state imaging device sharing a plurality of pixels that hardly causes a sensitivity difference.

<3. First Embodiment>
[Configuration example of solid-state imaging device]
FIG. 2 shows a first embodiment of a solid-state imaging device according to the present invention, that is, a CMOS solid-state imaging device. FIG. 2 shows a schematic configuration of a main part applied to a CMOS solid-state imaging device in which a pixel transistor is a three-transistor type and a plurality of shared pixels that are shared by zigzag four pixels are arranged. This embodiment is characterized by the arrangement of pixel transistors, and will be described in comparison with the first comparative example of FIG.

  FIG. 22 shows an equivalent circuit of a shared pixel in which a three-transistor type of four pixels is shared. The shared pixel according to this example includes four photodiodes PD [PD1 to PD4] serving as a photoelectric conversion unit, four transfer transistors Tr1 [Tr11 to Tr14], and one reset transistor Tr2 and one amplification transistor Tr3. Is done. Here, in the shared pixel, the first floating diffusion portion FD1 is shared by the two photodiodes PD1 and PD2, and the second floating diffusion portion FD2 is shared by the two photodiodes PD3 and PD4.

  The photodiodes PD1 to PD4 are connected to transfer transistors Tr11 to Tr14, respectively. That is, the two photodiodes PD1 and PD2 are connected to the first floating diffusion portion FD1 via the transfer transistors Tr11 and Tr12. The two photodiodes PD3 and PD4 are connected to the second floating diffusion portion FD2 via the transfer transistors Tr13 and Tr14. The first floating diffusion portion FD1 and the second floating diffusion portion FD2 are connected, and the connection point is connected to the source of the reset transistor Tr2 and the gate of the amplification transistor Tr3. The drain of the reset transistor Tr2 is connected to the power supply Vdd. The drain of the amplification transistor Tr3 is connected to the power supply Vdd, and the source is connected to the vertical signal line 9.

  First, the solid-state imaging device according to the first comparative example in FIG. 3 will be described. In the solid-state imaging device 101 of the first comparative example, a pair sharing one floating diffusion portion FD is obliquely arranged by two photodiodes PD adjacent to each other diagonally, and zigzag is performed by two pairs adjacent in the vertical (vertical) direction. A shared pixel 102 configured to share four pixels in the array is configured. That is, the first floating diffusion portion FD1 shared by the two photodiodes PD1 and PD2 diagonally adjacent to each other and the second floating diffusion portion FD2 shared by the two photodiodes PD3 and PD4 diagonally adjacent to each other. The second set. The first set and the second set are arranged adjacent to each other in the vertical direction.

  Transfer gate electrodes TG1 and TG2 are formed between the photodiodes PD1 and PD2 and the first floating diffusion FD1, respectively, to form a first transfer transistor Tr11 and a second transfer transistor Tr12. Transfer gate electrodes TG3 and TG4 are formed between the photodiodes PD3 and PD4 and the second floating diffusion FD2, respectively, to form a third transfer transistor Tr13 and a fourth transfer transistor Tr14.

  In the shared pixel 102, the reset transistor Tr2 and the amplification transistor Tr3 are arranged separately in the vertical direction. That is, the reset transistor Tr2 including the source region 104, the drain region 105, and the reset gate electrode 106 is disposed on the upper side of the first set including the two photodiodes PD1 and PD2. In addition, an amplification transistor Tr3 including a source region 107, a drain region 108, and an amplification gate electrode 109 is disposed on the upper side of the second set including the two photodiodes PD3 and PD4. The reset transistor Tr2 and the amplification transistor Tr3 are arranged so as to be shifted from each other in the row (lateral) direction of the shared pixel 102.

  Between the shared pixels adjacent in the row direction, that is, between the shared pixels 102 in the adjacent columns, the amplification transistors Tr3 are arranged in the same direction and arranged in the same row direction, and the reset transistors Tr2 are arranged in the same direction and arranged in the same row direction. Be placed. In the shared pixel 102 in one adjacent column, the source region 104 of the reset transistor, the amplification gate electrode 109 of the amplification transistor, the first floating diffusion portion FD1, and the second floating diffusion portion FD2 are connected by the FD wiring 111A. The In the shared pixel 102 in the other adjacent column, the source region 104 of the reset transistor, the amplification gate electrode 109 of the amplification transistor, the first floating diffusion portion FD1, and the second floating diffusion portion FD2 are connected by the FD wiring 111B. The In the solid-state imaging device 101 of the first comparative example, a shared pixel in which four transistors PD1 to PD4 in a zigzag arrangement illustrated by a broken line 112 and a pixel transistor Tr11 to Tr14, Tr2, and Tr3 share a three-transistor zigzag four pixels 102 is configured.

  In the solid-state imaging device 101 according to the first comparative example, the lengths of the FD wirings 111A and 111B of the shared pixels 102 in adjacent columns are formed with the same length, so that the conversion efficiency between the columns in the FD wiring length is between the columns. There is no difference. However, for example, in a configuration having a color filter with a Bayer array, the Gb pixel includes a reset gate electrode 106 made of polysilicon of the reset transistor Tr2 in the shared pixel (that is, unit cell) 102, as shown in FIG. Yes. The Gr pixel includes an amplification gate electrode 109 made of polysilicon of the amplification transistor Tr3 in the shared pixel (unit cell) 102. The amplification gate electrode 109 has a larger gate length than the reset gate electrode 106. For this reason, although the Gr pixel and the Gb pixel are the same green pixel, the Gr pixel and the Gb pixel include gate electrodes having different areas, and a difference occurs in light absorption by the gate electrode between the Gr pixel and the Gb pixel. As a result, variations in sensitivity occur between columns, causing vertical stripes.

  Next, the solid-state imaging device according to the first embodiment will be described. As shown in FIG. 2, the solid-state imaging device 21 of the first embodiment has a two-dimensional array in which two photodiodes PD diagonally adjacent share one floating diffusion portion FD, and are adjacent in the vertical direction. A shared pixel 22 that is a zigzag 4-pixel shared configuration is configured by the two sets. That is, the first pair in which the first floating diffusion portion FD1 is shared by the two photodiodes PD1 and PD2 diagonally adjacent to each other and the second photodiode FD2 in which the two photodiodes PD3 and PD4 that are diagonally adjacent to each other are shared. Two sets are arranged next to each other in the vertical direction.

  Transfer gate electrodes TG1 and TG2 are formed between the photodiodes PD1 and PD2 and the first floating diffusion FD1, respectively, to form a first transfer transistor Tr11 and a second transfer transistor Tr12. Transfer gate electrodes TG3 and TG4 are formed between the photodiodes PD3 and PD4 and the second floating diffusion FD2, respectively, to form a third transfer transistor Tr13 and a fourth transfer transistor Tr14.

  In the present embodiment, in the shared pixel 22, the reset transistor Tr2 and the amplification transistor Tr3 are divided into upper and lower parts. At this time, between the shared pixels adjacent in the row direction, that is, between the shared pixels 102 in the adjacent columns, the mutual amplification transistors Tr3 are vertically crossed and the reset transistors Tr2 are vertically crossed (see arrows). That is, the reset transistor Tr2 and the amplification transistor Tr3 are provided on the upper side of the first set having two photodiodes PD1 and PD2 in one column and on the upper side of the first set having two photodiodes PD1 and PD2 in the other column. Are arranged side by side. The amplifying transistor Tr3 and the reset transistor Tr2 are arranged side by side on the upper side of the second set having the two photodiodes PD3 and PD4 in one and the other columns so that the arrangement of the reset transistor Tr2 and the amplifying transistor Tr3 intersects vertically. Is done. The reset transistor Tr2 and the amplification transistor Tr3 arranged above and below are arranged at substantially the same position without being shifted in the row direction.

  The reset transistor Tr2 includes a source region 24, a drain region 25, and a reset gate electrode 26. The amplification transistor Tr3 is formed having a source region 27, a drain region 28, and an amplification gate electrode 29.

  In the shared pixel 22 in one adjacent column, the source region 24 of the reset transistor, the amplification gate electrode 29 of the amplification transistor, and the first and second floating diffusion portions FD1 and FD2 are electrically connected by the FD wiring 31A. Is done. In the shared pixel 22 in the other adjacent column, the source region 24 of the reset transistor, the amplification gate electrode 29 of the amplification transistor, and the first and second floating diffusion portions FD1 and FD2 are electrically connected by the FD wiring 31B. Is done. In the present embodiment, a shared pixel 22 configured to share a three-transistor type zigzag four pixels is configured by the four photodiodes PD1 to PD4 in the zigzag arrangement illustrated by the broken line 32 and the pixel transistors Tr11 to Tr14, Tr2, and Tr3. The

  According to the solid-state imaging device 21 according to the first embodiment, the reset transistor Tr2 and the amplification transistor Tr3 that are dividedly arranged are arranged so as to intersect vertically between the shared pixels 22 in adjacent columns. With this configuration, the symmetry of each shared pixel including the FD wiring 31 of the shared pixel 22 is improved, the wiring length difference between the FD wirings 31A and 31B is eliminated, and the wiring capacity of the FD wirings 31A and 31B is constant for each shared pixel. It becomes. Therefore, a difference in photoelectric conversion efficiency for each column is less likely to occur, and there is no difference in sensitivity between columns. As a result, there are no vertical stripes.

  On the other hand, when a Bayer color filter is used, the reset transistor Tr2 and the amplification transistor Tr3 are vertically crossed between the shared pixels in the adjacent columns. A gate electrode 26 is provided. Since the Gr pixel and the Gb pixel have the reset gate electrode 26 of polysilicon having the same area, a difference in light absorption by the reset gate electrode does not occur. As a result, no vertical streak occurs. Therefore, it is possible to provide a solid-state imaging device sharing a plurality of pixels that is unlikely to cause a difference in sensitivity between shared pixels.

<4. Second Embodiment>
[Configuration example of solid-state imaging device]
FIG. 4 shows a second embodiment of a solid-state imaging device, that is, a CMOS solid-state imaging device according to the present invention. FIG. 4 shows a schematic configuration of a main part applied to a CMOS solid-state imaging device in which a pixel transistor is a four-transistor type and a plurality of shared pixels that are shared by zigzag four pixels are arranged. This embodiment is characterized by the arrangement of pixel transistors, and will be described in comparison with the second comparative example of FIG.

  FIG. 23 shows an equivalent circuit of a shared pixel in which a 4-transistor type is shared by four pixels. The shared pixel according to this example includes four photodiodes PD [PD1 to PD4] serving as a photoelectric conversion unit, four transfer transistors Tr1 [Tr11 to Tr14], one reset transistor Tr2, an amplification transistor Tr3, and a selection transistor. Tr4. The drain of the selection transistor Tr4 is connected to the source of the amplification transistor Tr3, and the drain thereof is connected to the vertical signal line 9. Since other configurations have the same connection circuit as described in FIG. 22, the same reference numerals are given to portions corresponding to those in FIG.

First, the solid-state imaging device according to the second comparative example in FIG. 5 will be described. The solid-state imaging device 114 of the second comparative example is a CMOS solid-state imaging device with a zigzag 4-pixel sharing. The solid-state imaging device 114 of the second comparative example is the same as the first comparative example except that the pixel transistor is a four-transistor type of transfer transistor Tr1 [Tr11 to Tr14], reset transistor Tr2, amplification transistor Tr3, and selection transistor Tr4. It is. In the solid-state imaging device 114 of this comparative example, the reset transistor Tr2 is disposed on the upper side of the first set including the two photodiodes PD1 and PD2, and the amplification transistor Tr3 is disposed on the upper side of the second set including the two photodiodes PD3 and PD4. In addition, a series circuit of the selection transistor Tr4 is arranged. This series circuit includes diffusion regions 115, 116, and 117 that become source / drain regions, an amplification gate electrode 109, and a selection gate electrode 118. In other words, the amplification transistor Tr3 is formed with the diffusion regions 116 and 117 as the source region and the drain region and the amplification gate electrode 109. The selection transistor Tr4 is formed to have a selection gate electrode 118 using the diffusion regions 115 and 116 as a source region and a drain region. In the shared pixel 122 in the adjacent column, the reset transistors Tr2 are arranged in the same direction and arranged in the same row direction, and the series circuits of the amplification transistor Tr3 and the selection transistor Tr4 are arranged in the same direction and arranged in the same row direction.
Since the other configuration is the same as that described with reference to FIG. 3, portions corresponding to those in FIG.

  In the solid-state imaging device 114 of the second comparative example, in FIG. 5, the wiring lengths of the FD wiring 111A of the shared pixel 122 in the left column and the FD wiring 111B of the shared pixel 122 in the right column are different. That is, the FD wiring 111B in the right column is longer than the FD wiring 111A in the left column by the length indicated by the ellipse frame C. Therefore, a difference in wiring capacitance occurs between the FD wiring 111A and the FD wiring 111B, and the conversion efficiency differs between the adjacent pixels in the adjacent columns. As a result, a difference in conversion efficiency between columns occurs, and vertical stripes occur.

  Next, a solid-state imaging device according to the second embodiment will be described. The solid-state imaging device 34 according to the second embodiment is a CMOS solid-state imaging device with a zigzag 4-pixel sharing. In the solid-state imaging device 34 of the second embodiment, the pixel transistor is configured as a four-transistor type including a transfer transistor Tr1 [Tr11 to Tr14], a reset transistor Tr2, an amplification transistor Tr3, and a selection transistor Tr4.

As shown in FIG. 4, in the solid-state imaging device 34 according to the second embodiment, the reset transistor Tr2 is arranged on the upper side of the first set having two photodiodes PD1 and PD2 in each of the shared pixels in the adjacent columns. Is done. On the other hand, in the shared pixel of the adjacent column, the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 is horizontally inverted between the adjacent columns and arranged integrally on the upper side of the second set having the two photodiodes PD3 and PD4. Is done. That is, as shown in FIG. 4B, the drain regions of the two amplification transistors Tr3 of the series circuit are formed by a common diffusion region 37, and the series circuit is arranged horizontally inverted between shared pixels in adjacent columns. . The series circuit has a diffusion region 36 and 37 as a source region and a drain region, an amplification transistor Tr3 having an amplification gate electrode 29, and a diffusion region 35 and 36 as a source region and a drain region, and a selection gate electrode 38. It comprises a transistor Tr4.
Since other configurations are the same as those described in the first embodiment, the same reference numerals are given to portions corresponding to those in FIG.

  According to the solid-state imaging device 34 according to the second embodiment, the FD wiring 31A and the FD wiring 31B have the same wiring length between the shared pixels 42 in the adjacent columns. For this reason, no difference in wiring capacitance occurs between the FD wiring 31A and the FD wiring 31B, and no difference in conversion efficiency between columns occurs. As a result, there is no difference in sensitivity between columns, and no vertical stripes are generated. Therefore, it is possible to provide a solid-state imaging device sharing a plurality of pixels that is unlikely to cause a difference in sensitivity between shared pixels.

<5. Third Embodiment>
[Configuration example of solid-state imaging device]
FIG. 6 shows a third embodiment of a solid-state imaging device, that is, a CMOS solid-state imaging device according to the present invention. FIG. 6 shows a schematic configuration of a main part applied to a CMOS solid-state imaging device in which a pixel transistor is a four-transistor type and a plurality of shared pixels that are shared by zigzag four pixels are arranged. This embodiment is characterized by the arrangement of the pixel transistors, and will be described in comparison with the third comparative example of FIG.

  First, the solid-state imaging device according to the third comparative example in FIG. 7 will be described. The solid-state imaging device 124 of the third comparative example is a CMOS solid-state imaging device in which four pixels are shared in a zigzag manner using a Bayer array color filter. Since the configuration other than having the Gr pixel and the Gb pixel is the same as that of the second comparative example described above, the same reference numerals are given to the parts corresponding to those in FIG.

  In the solid-state imaging device 124 of the third comparative example, the wiring lengths of the FD wiring 111A of the shared pixel 122 in the left column and the FD wiring 111B of the shared pixel 122 in the right column are different as described in FIG. . That is, the FD wiring 111B in the right column is longer than the FD wiring 111A in the left column by the length indicated by the ellipse frame C. Therefore, a difference in wiring capacitance occurs between the FD wiring 111A and the FD wiring 111B, and the conversion efficiency differs between the adjacent pixels in the adjacent columns. As a result, a difference in conversion efficiency between columns occurs, and vertical stripes occur.

  Further, the Gb pixel includes a reset gate electrode 106 made of polysilicon of the reset transistor Tr <b> 2 in the shared pixel 122. The Gr pixel includes an amplification gate electrode 109 made of polysilicon of the amplification transistor Tr3 in the shared pixel 122. The amplification gate electrode 109 has a larger gate length than the reset gate electrode 106. For this reason, although the Gr pixel and the Gb pixel are the same green pixel, the Gr pixel and the Gb pixel include gate electrodes having different areas, and a difference occurs in light absorption by the gate electrode between the Gr pixel and the Gb pixel. As a result, variations in sensitivity occur between columns, causing vertical stripes.

  Next, a solid-state imaging device according to the third embodiment will be described. The solid-state imaging device 44 according to the third embodiment is a CMOS solid-state imaging device with a zigzag 4-pixel sharing. The solid-state imaging device 44 of the third embodiment is the same as that of the second embodiment except that the arrangement of the pixel transistors is different.

In the solid-state imaging device 44 according to the third embodiment, the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 is arranged so as not to be horizontally reversed between the shared pixels 45 in adjacent columns, and similarly, the reset transistor Tr2 Are also arranged crossing vertically (see arrows). That is, the reset transistor Tr2 and the series circuit are respectively provided on the upper side of the first group having two photodiodes PD1 and PD2 in one column and on the upper side of the first group having two photodiodes PD1 and PD2 in the other column. Are arranged side by side. The series circuit and the reset transistor Tr2 are arranged side by side on the upper side of the second set having the two photodiodes PD3 and PD4 in one and the other column so that the arrangement of the reset transistor Tr2 and the series circuit intersects vertically. .
Since the other configuration is the same as that of the second embodiment, portions corresponding to those in FIG.

  According to the solid-state imaging device 44 according to the third embodiment, the reset transistor Tr2 and the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 are arranged vertically crossing between the shared pixels 45 in adjacent columns. With this configuration, the FD wiring 31A and the FD wiring 31B have the same wiring length between the shared pixels 45 in adjacent columns, and no difference in wiring capacitance occurs between the FD wiring 31A and the FD wiring 31B. There is no difference in efficiency between columns. As a result, there is no difference in sensitivity between columns, and no vertical stripes are generated.

  When a Bayer color filter is used, the Gr pixel and the Gb pixel include a part of the reset gate electrode 26 and the amplification gate electrode 29, respectively, according to the above configuration. Since the Gr pixel and the Gb pixel have a part of the reset gate electrode 26 and the amplification gate electrode 29 made of polysilicon having the same area, a difference in light absorption by the gate electrode does not occur. As a result, no vertical streak occurs. Therefore, it is possible to provide a four-pixel shared solid-state imaging device in which a difference in sensitivity between shared pixels hardly occurs.

<6. Fourth Embodiment>
[Configuration example of solid-state imaging device]
FIG. 8 shows a fourth embodiment of a solid-state imaging device, that is, a CMOS solid-state imaging device according to the present invention. FIG. 8 shows a schematic configuration of a main part applied to a CMOS solid-state imaging device in which a pixel transistor is a three-transistor type and a plurality of shared pixels that are shared by four vertical pixels are arranged. This embodiment is characterized by the arrangement of pixel transistors, and will be described in comparison with the 4-1 comparative example and the 4-2 comparative example of FIGS. 9 and 10.

  First, the 4-1 comparative example in FIG. 9 will be described. The fourth-first comparative example 126 includes a shared pixel having four vertical pixels shared by four photodiodes PD [PD1 to PD4] arranged in the vertical (vertical) direction. That is, the first floating diffusion portion FD1 shared by the two vertically adjacent photodiodes PD1 and PD2 and the second floating diffusion FD2 shared by the two vertically adjacent photodiodes PD3 and PD4. Has a second set. The first set and the second set are arranged adjacent to each other in the vertical direction.

  Transfer gate electrodes TG1 and TG2 are formed between the photodiodes PD1 and PD2 and the first floating diffusion portion FD1, respectively, to form a first transfer transistor Tr11 and a second transfer transistor Tr12. Transfer gate electrodes TG3 and TG4 are formed between the photodiodes PD3 and PD4 and the second floating diffusion portion FD2, respectively, to form a third transfer transistor Tr13 and a fourth transfer transistor Tr14. Here, the transfer gate electrodes TG1 to TG4 are formed in common with the transfer gate electrodes TG1 to TG4 of the shared pixels in the adjacent columns.

  The amplification transistor Tr3 and the reset transistor Tr2 are arranged in the row direction on the lower side of the first set over the shared pixels 127 in the adjacent columns, and the amplification transistor Tr3 and the reset transistor Tr2 are arranged in the row direction on the lower side of the second set. Arranged. Then, as illustrated, FD wirings 111A and 111B are formed. Since other configurations are the same as those of the comparative example described above, the corresponding parts are denoted by the same reference numerals, and redundant description is omitted.

  In the solid-state imaging device 128 of the 4-2 comparative example in FIG. 10, the set transistors Tr <b> 2 corresponding to the shared pixels in each column are arranged in the row direction below the first set over the shared pixels 127 in the adjacent columns. . In addition, amplification transistors Tr3 corresponding to the shared pixels in each column are arranged in the row direction below the second set over the shared pixels 127 in adjacent columns. Then, FD wirings 111A and 111B are formed as illustrated. Since other configurations are the same as those in FIG. 9, the same reference numerals are assigned to the corresponding portions, and redundant description is omitted.

  In the solid-state imaging device 126 of the 4-1 comparative example and the solid-state imaging device 128 of the 4-2 comparative example, the FD wiring 111A of the left shared pixel and the FD wiring 111B of the right shared pixel have different wiring lengths. The wiring length differs depending on the presence of the wiring portion indicated by the elliptical frames E to G or the elliptical frame H. As a result, a wiring capacity difference occurs, a conversion efficiency difference between columns occurs, and vertical stripes occur. In addition, when a Bayer color filter is used, the areas of the gate electrodes included in the Gr pixel and the Gb pixel are different, so that there is a difference in light absorption at the gate electrode between the Gr pixel and the Gb pixel. Sensitivity variation occurs between columns and becomes a vertical stripe.

  Next, a solid-state imaging device according to a fourth embodiment will be described. As shown in FIG. 8, the solid-state imaging device 47 of the fourth embodiment has a shared pixel that is shared by four vertical pixels having four photodiodes PD [PD1 to PD4] arranged in the vertical (vertical) direction. It consists of That is, the first floating diffusion portion FD1 shared by the two vertically adjacent photodiodes PD1 and PD2 and the second floating diffusion FD2 shared by the two vertically adjacent photodiodes PD3 and PD4. Has a second set. The first set and the second set are arranged adjacent to each other in the vertical direction.

  Transfer gate electrodes TG1 and TG2 are formed between the photodiodes PD1 and PD2 and the first floating diffusion portion FD1, respectively, to form a first transfer transistor Tr11 and a second transfer transistor Tr12. Transfer gate electrodes TG3 and TG4 are formed between the photodiodes PD3 and PD4 and the second floating diffusion portion FD2, respectively, to form a third transfer transistor Tr13 and a fourth transfer transistor Tr14. Here, the transfer gate electrodes TG1 to TG4 are formed in common with the transfer gate electrodes TG1 to TG4 of the shared pixels in the adjacent columns.

  In the present embodiment, the amplification transistors Tr3 of the shared pixels in the adjacent columns are reversed left and right, and the respective drain regions 28 are integrated as a common. Further, the reset transistors Tr2 of the shared pixels in the adjacent columns are reversed left and right to integrate the drain regions 25 in common. Then, a laterally inverted integrated amplification transistor Tr3 and a laterally inverted integrated reset transistor Tr2 are arranged in the row direction. At the same time, the arrangement of the integrated amplification transistor Tr3 and the integrated reset transistor Tr2 is arranged so as to vertically cross between the lower side of the first set and the lower side of the second set.

  In the shared pixel 48 on the left side, the first floating diffusion portion FD1, the upper amplification gate electrode 29, the second floating diffusion FD2, and the source region 24 of the lower reset transistor Tr2 are electrically connected by the FD wiring 31A. Connected to. In the shared pixel 48 on the right side, the first floating diffusion portion FD1, the source region 24 of the upper reset transistor Tr2, the second floating diffusion FD2, and the lower amplification gate electrode 29 are electrically connected by the FD wiring 31B. Connected to. Since other configurations are the same as those of the above-described embodiment, the corresponding portions are denoted by the same reference numerals, and redundant description is omitted.

  According to the solid-state imaging device 47 according to the fourth embodiment, by arranging the pixel transistors as described above, the wiring of the FD wiring 31A of the shared pixel 48 in the left column and the FD wiring 31B of the shared pixel 48 in the right column. The length is the same. Thereby, a difference in wiring capacitance does not occur between the FD wirings 31A and 31B, and a difference in conversion efficiency between columns does not occur. As a result, vertical stripes do not occur.

  When a Bayer color filter is used, the pixel transistors are arranged as described above, so that the Gr pixel and the GB pixel include gate electrodes having the same area. As a result, there is no difference in light absorption at the polysilicon gate electrode between the Gr pixel and the Gb pixel, and no vertical streak occurs. Therefore, it is possible to provide a solid-state imaging device sharing four vertical pixels in which a sensitivity difference between the shared pixels hardly occurs.

<7. Fifth embodiment>
[Configuration example of solid-state imaging device]
FIG. 11 shows a fifth embodiment of a solid-state imaging device, that is, a CMOS solid-state imaging device according to the present invention. FIG. 11 shows a schematic configuration of a main part applied to a CMOS solid-state imaging device in which a pixel transistor is a four-transistor type and a plurality of shared pixels that are vertically shared by four pixels are arranged. This embodiment is characterized by the arrangement of the pixel transistors, and will be described in comparison with the 5-1 comparative example and the 5-2 comparative example of FIGS.

  First, the solid-state imaging device according to the 5-1 comparative example in FIG. 12 will be described. The solid-state imaging device 131 of the 5-1 comparative example is configured by arranging a series circuit of an amplification transistor Tr3 and a selection transistor Tr4 and a reset transistor Tr2 instead of the arrangement of the reset transistor and the amplification transistor in FIG. The The configuration of the series circuit is the same as that described with reference to FIG. Reference numeral 133 denotes a shared pixel. Since other configurations are the same as those in FIG. 9 described above, the corresponding parts are denoted by the same reference numerals, and redundant description is omitted.

  The solid-state imaging device 132 of the 5-2 comparative example of FIG. 13 arranges series circuits of reset transistors Tr2, amplification transistors Tr3, and selection transistors Tr4 in place of the arrangement of reset transistors and amplification transistors in FIG. Configured. The configuration of the series circuit is the same as that described with reference to FIG. Reference numeral 134 denotes a shared pixel. Since other configurations are the same as those in FIG. 10 described above, the corresponding parts are denoted by the same reference numerals and redundant description is omitted.

  In the solid-state imaging device 131 of the 5-1 comparative example and the solid-state imaging device 132 of the 5-2 comparative example, the wiring length is different between the FD wiring 111A of the left shared pixel and the FD wiring 111B of the right shared pixel. The wiring length differs depending on the presence of the wiring portion indicated by the elliptical frames E to G or the elliptical frame H. As a result, a wiring capacity difference occurs, a conversion efficiency difference between columns occurs, and vertical stripes occur. In addition, when a Bayer color filter is used, the areas of the gate electrodes included in the Gr pixel and the Gb pixel are different, so that there is a difference in light absorption at the gate electrode between the Gr pixel and the Gb pixel. Sensitivity variation occurs between columns and becomes a vertical stripe.

Next, a solid-state imaging device according to a fifth embodiment will be described. In the solid-state imaging device 49 according to the fifth embodiment, as shown in FIG. 11, the series circuit of the amplification transistor Tr and the selection transistor Tr4 and the reset transistor Tr2 are horizontally reversed by the shared pixels in the adjacent columns. Further, the series circuit and the reset transistor Tr2 arranged in the left-right direction are arranged so as to intersect vertically. That is, on the lower side of the first set having the two photodiodes PD1 and PD2, the two reset transistors Tr2 in which the drain regions 25 are integrated in common and the two above-mentioned transistors in which the drain regions of the amplification transistors Tr3 are integrated in common. Series circuits are arranged in the row direction. On the other hand, on the lower side of the second set having two photodiodes PD3 and PD4, the integrated reset transistor Tr2 and the series are respectively arranged so as to cross the arrangement of the integrated series circuit and the reset transistor Tr2. A circuit is placed. The configuration of the series circuit is the same as that described with reference to FIG. Reference numeral 51 denotes a shared pixel.
Since other configurations are the same as those in FIG. 8 described above, portions corresponding to those in FIG.

  According to the solid-state imaging device 49 according to the fifth embodiment, by arranging the pixel transistors as described above, the wiring of the FD wiring 31A of the shared pixel 51 in the left column and the FD wiring 31B of the shared pixel 51 in the right column. The length is the same. Thereby, a difference in wiring capacitance does not occur between the FD wirings 31A and 31B, and a difference in conversion efficiency between columns does not occur. As a result, vertical stripes do not occur.

  When a Bayer color filter is used, the pixel transistors are arranged as described above, so that the Gr pixel and the GB pixel include gate electrodes having the same area. As a result, there is no difference in light absorption at the polysilicon gate electrode between the Gr pixel and the Gb pixel, and no vertical streak occurs. Therefore, it is possible to provide a solid-state imaging device sharing four vertical pixels in which a sensitivity difference between the shared pixels hardly occurs.

<8. Sixth Embodiment>
[Configuration example of solid-state imaging device]
FIG. 14 shows a sixth embodiment of a solid-state imaging device, that is, a CMOS solid-state imaging device according to the present invention. FIG. 14 shows a schematic configuration of a main part applied to a CMOS solid-state imaging device in which a pixel transistor is a three-transistor type and a plurality of shared pixels in which two pixels are shared are arranged. This embodiment is characterized by the arrangement of pixel transistors, and will be described in comparison with the sixth comparative example of FIG.

  FIG. 24 shows an equivalent circuit of a shared pixel in which a pixel transistor is a three-transistor type and two pixels are shared. The parts corresponding to those in FIG.

  First, the sixth comparative example in FIG. 15 will be described. In the solid-state imaging device according to the sixth comparative example, a plurality of shared pixels 137 sharing two pixels sharing one floating diffusion portion FD between two photodiodes PD1 and PD2 adjacent in the vertical (vertical) direction are two-dimensionally arranged. Made up. Transfer gate electrodes are formed between the two photodiodes PD1 and PD2 and the floating diffusion portion FD, and transfer transistors Tr11 and Tr12 are formed, respectively. Further, a reset transistor Tr2 and an amplification transistor Tr3 are arranged so as to be divided into upper and lower portions sandwiching the two photodiodes PD1 and PD2. A shared pixel 137 is formed in which two pixels are shared by two photodiodes PD1 and PD2, one floating diffusion portion FD, two transfer transistors Tr11 and Tr12, and each one reset transistor Tr2 and amplification transistor TR3. .

  The reset transistor Tr2 is formed to include a source region 104, a drain region 105, and a reset gate electrode 106. The amplification transistor Tr3 is formed having a source region 107, a drain region 108, and an amplification gate electrode 109. In the shared pixels 137 in adjacent columns, the reset transistors Tr2 are arranged in the same direction and arranged in the same row direction, and the amplification transistors Tr3 are arranged in the same direction and arranged in the same row direction. In the shared pixel 137 in each column, the FD wiring 111 [111A, 111B] is electrically connected to the source region 104, the floating diffusion portion FD, and the amplification gate electrode 109 of the reset transistor Tr2.

  In the solid-state imaging device 136 of the sixth comparative example, the wiring lengths of the FD wirings 111A and 111B in adjacent columns are the same. On the other hand, for example, when a Bayer color filter is used, a part of the reset gate electrode 106 is included in the Gr pixel and a part of the amplification gate electrode 109 is included in the Gb pixel. Since the Gr pixel and the Gb pixel each include a gate electrode having a different area, there is a difference in light absorption at the gate electrode between the Gr pixel and the Gb pixel. As a result, sensitivity variation occurs between the columns and becomes vertical stripes. .

  Next, a solid-state imaging device according to a sixth embodiment of the present invention will be described. As shown in FIG. 14, the solid-state imaging device 53 according to the sixth embodiment is a two-pixel shared type in which two photodiodes PD1 and PD2 adjacent in the vertical (longitudinal) direction share one floating diffusion portion FD. A plurality of shared pixels 54 are two-dimensionally arranged. Transfer gate electrodes TG1 and TG2 are formed between the two photodiodes PD1 and PD2 and the floating diffusion portion FD, and transfer transistors Tr11 and Tr12 are formed, respectively.

  In the present embodiment, the reset transistor TR2 and the amplification transistor Tr3 are arranged separately on the upper and lower sides of the shared pixel 54. Further, the reset Tr2 and the amplification transistor Tr3 are arranged in the row direction on the upper side of the shared pixel of the adjacent column, and the reset transistor Tr2 and the amplification transistor Tr3 are arranged on the lower side so as to intersect the upper arrangement. . The reset transistor Tr2 includes a source region 24, a drain region 25, and a reset gate electrode 26. The amplification transistor Tr3 is formed having a source region 27, a drain region 28, and an amplification gate electrode 29. In each shared pixel 54, the FD wiring 31 [31A, 31B] is electrically connected to the source region 24, the floating diffusion portion FD, and the amplification gate electrode 29 of the reset transistor Tr2.

  According to the solid-state imaging device 53 according to the sixth embodiment, in the two-pixel sharing configuration, the reset transistor Tr2 and the amplification transistor Tr3 are arranged vertically crossing between the shared pixels 54 in the adjacent columns. With this configuration, the FD wiring 31A of the shared pixel 54 in the left column and the FD wiring 31B of the shared pixel 54 in the right column have the same wiring length. Thereby, a difference in wiring capacitance does not occur between the FD wirings 31A and 31B, and a difference in conversion efficiency between columns does not occur. As a result, vertical stripes do not occur.

  When a Bayer color filter is used, the pixel transistors are arranged as described above, so that the Gr pixel and the GB pixel include gate electrodes having the same area. As a result, there is no difference in light absorption at the polysilicon gate electrode between the Gr pixel and the Gb pixel, and no vertical streak occurs. Therefore, it is possible to provide a two-pixel shared solid-state imaging device in which a difference in sensitivity between shared pixels hardly occurs.

<9. Seventh Embodiment>
[Configuration example of solid-state imaging device]
FIG. 16 shows a seventh embodiment of a solid-state imaging device, that is, a CMOS solid-state imaging device according to the present invention. FIG. 16 shows a schematic configuration of a main part applied to a CMOS solid-state imaging device in which a pixel transistor is a four-transistor type and a plurality of shared pixels that share two pixels are arranged. This embodiment is characterized by the arrangement of pixel transistors, and will be described in comparison with the seventh comparative example of FIG.

  FIG. 25 shows an equivalent circuit of a shared pixel in which a pixel transistor is a four-transistor type and two pixels are shared. The parts corresponding to those in FIG.

  First, the solid-state imaging device according to the seventh comparative example in FIG. 17 will be described. In the solid-state imaging device 139 of the seventh comparative example, a reset transistor TR2 and a series circuit of an amplification transistor Tr3 and a selection transistor Tr4 are arranged so as to be divided above and below the shared pixel 141. The reset transistor Tr2 is formed to include a source region 104, a drain region 105, and a reset gate electrode 106. A series circuit of the amplification transistor Tr3 and the selection transistor Tr4 is formed by including three diffusion regions 115, 116, and 117 serving as source / drain regions, an amplification gate electrode 109, and a selection gate electrode 118. In the shared pixel 141 of the adjacent column, the reset transistor Tr2 is arranged in the same row direction in the same direction, and the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 is also arranged in the same row direction in the same direction. Since other configurations are the same as those in FIG. 15, portions corresponding to those in FIG.

  In the solid-state imaging device 139 of the seventh comparative example, the wiring lengths of the FD wirings 111A and 111B in adjacent columns are the same. On the other hand, for example, when a Bayer color filter is used, a part of the reset gate electrode 106 is included in the Gr pixel and a part of the amplification gate electrode 109 is included in the Gb pixel. Since the Gr pixel and the Gb pixel each include a gate electrode having a different area, there is a difference in light absorption at the gate electrode between the Gr pixel and the Gb pixel. As a result, sensitivity variation occurs between the columns and becomes vertical stripes. .

Next, a solid-state imaging device according to a seventh embodiment will be described. In the solid-state imaging device 56 according to the seventh embodiment, a series circuit of a reset transistor Tr2, an amplification transistor Tr3, and a selection transistor Tr4 is arranged so as to be divided above and below the shared pixel 57. Further, between the shared pixels in adjacent columns, the reset Tr2 is arranged so as to cross vertically, and the series circuit is arranged so as to cross vertically. That is, the reset transistor Tr2 corresponding to the adjacent column, the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 are arranged in the row direction, and this arrangement is arranged so as to intersect on the upper side and the lower side. The reset transistor Tr2 includes a source region 24, a drain region 25, and a reset gate electrode 26. The series circuit of the amplification transistor Tr3 and the selection transistor Tr4 is formed by including three diffusion regions 35, 36, and 37 serving as source / drain regions, an amplification gate electrode 29, and a selection gate electrode 38.
Since other configurations are the same as those in FIG. 14, portions corresponding to those in FIG.

  According to the solid-state imaging device 56 according to the seventh embodiment, in the two-pixel shared configuration, the reset transistor Tr2 and the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 are vertically connected between the shared pixels 54 in the adjacent columns. It is arranged to intersect. With this configuration, the wiring length of the FD wiring 31A of the shared pixel 57 in the left column and the FD wiring 31B of the shared pixel 57 in the right column are the same. Thereby, a difference in wiring capacitance does not occur between the FD wirings 31A and 31B, and a difference in conversion efficiency between columns does not occur. As a result, vertical stripes do not occur.

  When a Bayer color filter is used, the pixel transistors are arranged as described above, so that the Gr pixel and the GB pixel include gate electrodes having the same area. As a result, there is no difference in light absorption at the polysilicon gate electrode between the Gr pixel and the Gb pixel, and no vertical streak occurs. Therefore, it is possible to provide a two-pixel shared solid-state imaging device in which a difference in sensitivity between shared pixels hardly occurs.

<10. Eighth Embodiment>
[Configuration example of solid-state imaging device]
FIG. 18 shows an eighth embodiment of a solid-state imaging device, that is, a CMOS solid-state imaging device according to the present invention. FIG. 18 shows a schematic configuration of a main part applied to a CMOS solid-state imaging device in which a pixel transistor is a three-transistor type and a plurality of shared pixels arranged in a total of four pixels of 2 × 2 are arranged. This embodiment is characterized by the arrangement of pixel transistors, and will be described in comparison with the eighth comparative example of FIG.

  FIG. 26 shows an equivalent circuit of a shared pixel in which a pixel transistor is a three-transistor type and a total of four pixels of 2 × 2 is shared. The parts corresponding to those in FIG.

  First, the solid-state imaging device according to the eighth comparative example in FIG. 19 will be described. The solid-state imaging device 143 of the eighth comparative example is configured by sharing one floating diffusion portion FD with a total of four photodiodes PD [PD1 to PD4] of 2 × 2 in the vertical direction. The pixel transistor includes three transistors, ie, four transfer transistors Tr1 [Tr11 to Tr14], one reset transistor Tr2, and an amplification transistor Tr3. The four photodiodes PD1 to PD4, one floating diffusion part FD, the transfer transistors Tr11 to Tr14, the reset transistor Tr2, and the amplification transistor Tr3 constitute a shared pixel 144 that is shared by four pixels.

  Of the four transfer transistors Tr11 to Tr14, the transfer gate electrodes of the transfer transistors Tr11 and Tr12 connected to the two lateral photodiodes PD1 and PD2 are formed by a common gate electrode TG1. The transfer gate electrodes of the transfer transistors Tr13 and Tr14 connected to the two horizontal photodiodes PD3 and PD4 are formed by a common gate electrode TG2. The amplification transistor Tr3 and the reset transistor Tr2 are separately disposed on the upper side and the lower side of the shared pixel 144, respectively. In the shared pixel 144 adjacent in the vertical direction, the reset transistors Tr2 are arranged in the same row direction. The amplification transistors Tr3 are also arranged in the same row direction.

  The reset transistor Tr2 is formed to include a source region 104, a drain region 105, and a reset gate electrode 106. The amplification transistor Tr3 is formed having a source region 107, a drain region 108, and an amplification gate electrode 109. In the shared pixel, the floating diffusion portion FD, the amplification gate electrode 109, and the source region 104 of the reset transistor are connected by the FD wiring 111 [111A, 111B].

  In the solid-state imaging device 143 of the eighth comparative example, the FD wirings 111A and 11B of the shared pixel 144 adjacent in the vertical direction are formed along the column direction, and the wiring length is the same. On the other hand, for example, when a Bayer color filter is used, a part of the reset gate electrode 106 is included in the Gr pixel and a part of the amplification gate electrode 109 is included in the Gb pixel. Since the Gr pixel and the Gb pixel each include a gate electrode having a different area, there is a difference in light absorption at the gate electrode between the Gr pixel and the Gb pixel. As a result, sensitivity variation occurs between the columns and becomes vertical stripes. .

  Next, a solid-state imaging device according to an eighth embodiment will be described. As shown in FIG. 18, the solid-state imaging device 59 of the eighth embodiment is configured by sharing one floating diffusion portion FD with a total of four photodiodes PD [PD1 to PD4] of 2 × 2 vertically. Is done. The pixel transistor includes three transistors, ie, four transfer transistors Tr1 [Tr11 to Tr14], one reset transistor Tr2, and an amplification transistor Tr3. The four photodiodes PD1 to PD4, one floating diffusion portion FD, the transfer transistors Tr11 to Tr14, the reset transistor Tr2, and the amplification transistor Tr3 constitute a shared pixel 61 that is shared by four pixels.

  Of the four transfer transistors Tr11 to Tr14, the transfer gate electrodes of the transfer transistors Tr11 and Tr12 connected to the two lateral photodiodes PD1 and PD2 are formed by a common gate electrode TG1. The transfer gate electrodes of the transfer transistors Tr13 and Tr14 connected to the two horizontal photodiodes PD3 and PD4 are formed by a common gate electrode TG2.

  In the present embodiment, two shared pixels adjacent in the vertical direction are taken as one set, and in this set of shared pixels, the reset transistor TR2 and the amplifying transistor Tr3 are vertically divided with the shared pixel 61 interposed therebetween. At this time, in one set, the reset transistor Tr2 and the amplification transistor Tr3 arranged in the row direction so as to correspond to the two shared pixels 61 are arranged so that the arrangement relationship intersects on the upper side and the lower side. The The reset transistor Tr2 includes a source region 34, a drain region 35, and a reset gate electrode 36. The amplification transistor Tr3 is formed having a source region 27, a drain region 28, and an amplification gate electrode 29.

  In each shared pixel 61, the FD wiring 31 [31A, 31B] is electrically connected to the source region 24, the floating diffusion portion FD, and the amplification gate electrode 29 of the reset transistor Tr2. The FD wirings 31A and 31B of the two shared pixels 61 adjacent in the vertical direction are arranged along the column direction.

  According to the solid-state imaging device 59 according to the eighth embodiment, the reset transistor Tr2 and the amplification transistor Tr arranged side by side in the row direction are arranged so as to intersect vertically with the shared pixel 61 interposed therebetween. As a result, the wiring lengths of the FD wirings 31A and 231B of the shared pixel 61 adjacent in the vertical direction are the same, no difference in wiring capacitance occurs between the FD wirings 31A and 31B, and no inter-row difference in conversion efficiency occurs. As a result, vertical stripes do not occur.

  When a Bayer color filter is used, the pixel transistors are arranged as described above, so that the Gr pixel and the GB pixel include gate electrodes having the same area. As a result, there is no difference in light absorption at the polysilicon gate electrode between the Gr pixel and the Gb pixel, and no vertical streak occurs. Therefore, it is possible to provide a two-pixel shared solid-state imaging device in which a difference in sensitivity between shared pixels hardly occurs.

<11. Ninth Embodiment>
[Configuration example of solid-state imaging device]
FIG. 20 shows a ninth embodiment of a solid-state imaging device, that is, a CMOS solid-state imaging device according to the present invention. FIG. 20 shows a schematic configuration of a main part applied to a CMOS solid-state imaging device in which a pixel transistor is a 4-transistor type and a plurality of shared pixels arranged in a total of 4 pixels of 2 × 2 are arranged. This embodiment is characterized by the arrangement of pixel transistors, and will be described in comparison with the ninth comparative example in FIG.

  FIG. 27 shows an equivalent circuit of a shared pixel in which a pixel transistor is a 4-transistor type and a total of 4 pixels of 2 × 2 is shared. The parts corresponding to those in FIG.

First, the solid-state imaging device according to the ninth comparative example in FIG. 21 will be described. In the solid-state imaging device 146 of the ninth comparative example, the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 and the reset transistor Tr2 are vertically arranged across one shared pixel among the two shared pixels 147 adjacent in the vertical direction. Divided. At this time, the two reset transistors Tr2 corresponding to the two shared pixels 64 are arranged in the same row direction. Further, the two series circuits corresponding to the two shared pixels 64 are arranged in the same row direction. The configuration of the series circuit of the amplification transistor Tr3 and the selection transistor Tr4 is the same as that in FIG.
Since other configurations are the same as those in FIG. 19, the same reference numerals are given to portions corresponding to those in FIG.

  In the solid-state imaging device 146 of the ninth comparative example, the FD wirings 111A and 11B of the shared pixel 147 adjacent in the vertical direction are formed along the column direction, and the wiring lengths are the same. On the other hand, for example, when a Bayer color filter is used, a part of the reset gate electrode 106 is included in the Gr pixel, and a part of the amplification gate electrode 109 and a part of the selection gate electrode 118 are included in the Gb pixel. Since the Gr pixel and the Gb pixel each include a gate electrode having a different area, there is a difference in light absorption at the gate electrode between the Gr pixel and the Gb pixel. As a result, sensitivity variation occurs between the columns and becomes vertical stripes. .

Next, a solid-state imaging device according to a ninth embodiment will be described. As illustrated in FIG. 20, the solid-state imaging device 63 according to the ninth embodiment inverts the series circuit of the amplification transistor Tr and the selection transistor Tr4 and the reset transistor Tr2 with the shared pixels adjacent in the vertical direction. Further, the series circuit and the reset transistor Tr2 arranged in the left-right direction are arranged so as to intersect vertically. That is, on the upper side of one shared pixel 64 adjacent in the vertical direction, the two reset transistors Tr2 in which the drain region 25 is integrated in common, and the two series circuits in which the drain region of the amplification transistor Tr3 is integrated in common. Are arranged in the row direction. On the other hand, the integrated reset transistor Tr2 and the series circuit are respectively arranged below the one shared pixel 64 adjacent in the vertical direction so as to cross the arrangement of the integrated series circuit and the reset transistor Tr2. Be placed. The integrated series circuit and the integrated reset transistor Tr2 have the same configuration as that described with reference to FIG.
Since other configurations are the same as those in FIG. 8 described above, portions corresponding to those in FIG.

  According to the solid-state imaging device 63 according to the ninth embodiment, the series circuit of the two shared pixels 64 adjacent to each other in the vertical direction and the reset transistor Tr2 are horizontally reversed and arranged so as to cross vertically. The wiring lengths of the FD wirings 31A and 231B of the shared pixel 61 adjacent in the direction are the same. As a result, there is no difference in wiring capacitance between the FD wirings 31A and 31B, and no difference in conversion efficiency between rows occurs. As a result, vertical stripes do not occur.

  When a Bayer color filter is used, the pixel transistors are arranged as described above, so that the Gr pixel and the GB pixel include gate electrodes having the same area. As a result, there is no difference in light absorption at the polysilicon gate electrode between the Gr pixel and the Gb pixel, and no vertical streak occurs. Therefore, it is possible to provide a two-pixel shared solid-state imaging device in which a difference in sensitivity between shared pixels hardly occurs.

  The solid-state imaging device according to each embodiment of the present invention described above is applied to both the front-side irradiation type and the back-side irradiation type.

<12. Tenth Embodiment>
[Configuration example of electronic equipment]
The above-described solid-state imaging device according to the present invention can be applied to, for example, digital still cameras, digital video cameras, various mobile terminal devices such as camera-equipped mobile phones, and electronic devices such as printers.

  FIG. 28 shows a tenth embodiment applied to a camera as an example of an electronic apparatus according to the invention. The camera according to the present embodiment is an example of a video camera capable of capturing still images or moving images. The camera 71 of this embodiment also includes a solid-state imaging device 72, an optical system 73 that guides incident light to the light receiving sensor unit of the solid-state imaging device 72, and a shutter device 74. Further, the camera 71 includes a drive circuit 75 that drives the solid-state imaging device 72 and a signal processing circuit 76 that processes an output signal of the solid-state imaging device 72.

  Any of the solid-state imaging devices of the above-described embodiments is applied to the solid-state imaging device 72. The optical system (optical lens) 73 may combine an image light (incident light) from a subject on the imaging surface of the solid-state imaging device 72, and the optical system may be constituted by a plurality of optical lenses. The shutter device 74 controls a light irradiation period and a light shielding period for the solid-state imaging device 72. The drive circuit 75 supplies a drive signal for controlling the transfer operation of the solid-state imaging device 72 and the shutter operation of the shutter device 74. Signal transfer of the solid-state imaging device 72 is performed by a drive signal (timing signal) supplied from the drive circuit 75. The signal processing circuit 76 performs various signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  According to the electronic apparatus such as the camera according to the tenth embodiment, in the solid-state imaging device 72 having the shared pixel, it is difficult to cause a sensitivity difference between the shared pixels, so that the image quality is improved and the reliability is high. An electronic device can be provided.

21, 24, 47, 49, 53, 56, 56, 63 .. Solid-state imaging device, PD [PD1
PD4] .. Photodiode, FD [FD to FD2] .. Floating diffusion part, Tr1 [Tr11 to Tr14] .. Transfer transistor, Tr2..Reset transistor, Tr3..Amplification transistor, Tr4..Select transistor, 31A , 31B ・ ・ FD wiring

Claims (14)

A first photoelectric conversion unit including a plurality of photoelectric conversion units; a first floating diffusion unit shared by the plurality of photoelectric conversion units of the first photoelectric conversion unit; a first reset transistor; a first amplification transistor; A first shared pixel having a first select transistor;
A second photoelectric conversion unit composed of a plurality of photoelectric conversion units; a second floating diffusion unit shared by the plurality of photoelectric conversion units of the second photoelectric conversion unit; a second reset transistor; a second amplification transistor; A second shared pixel having a second select transistor,
Between the first shared pixel and the second shared pixel in adjacent columns,
The first photoelectric conversion unit and the second photoelectric conversion unit are arranged in the same direction and arranged in the same row,
A series circuit of the first selection transistor and the first amplifying transistor arranged in the row direction, a series circuit of said second amplifying transistor and the second selection transistor, adjacent to each other physician while inverted in the row direction Placed in the first row ,
The first reset transistor and the second reset transistor are arranged in a second row side by side in the same direction;
A connection line that electrically connects a source region of the first reset transistor, an amplification gate electrode of the first amplification transistor, and the first floating diffusion portion; a source region of the second reset transistor; The solid-state imaging device, wherein an amplification gate electrode of the second amplification transistor and a connection wiring that electrically connects the second floating diffusion portion have the same length. The first photoelectric conversion unit includes a first photodiode and a second photodiode,
The solid-state imaging device according to claim 1, wherein the second photoelectric conversion unit includes a third photodiode and a fourth photodiode. The first photodiode and the third photodiode are arranged in a third row;
The solid-state imaging device according to claim 2, wherein the third row is disposed between the first row and the second row. The second photodiode and the fourth photodiode are arranged in a fourth row;
The solid-state imaging device according to claim 2, wherein the fourth row is disposed between the first row and the second row. The first photodiode and the third photodiode are arranged in a third row, and the third row is arranged between the first row and the second row;
The second photodiode and the fourth photodiode are arranged in a fourth row, and the fourth row is arranged between the first row and the second row. The solid-state imaging device described in 1. The first selection transistor has a first selection source region connected to a first vertical signal line in a first signal connection unit,
The second selection transistor has a second selection source region connected to the second vertical signal line in the second signal connection unit,
The solid-state imaging device according to claim 1, wherein the first amplification transistor and the second amplification transistor are arranged between the first signal connection unit and the second signal connection unit in the first row. The first amplifying transistor has a first amplifying drain region connected to a power source at a first amplifying gate electrode and a power source connecting portion,
The second amplifying transistor has a second amplifying drain region connected to a power source at a second amplifying gate electrode and the power source connecting portion,
The power supply connection portion is disposed between the first amplification gate electrode and the second amplification gate electrode,
The solid-state imaging device according to claim 1, wherein the first amplification transistor has a gate length larger than that of the first selection transistor, and a second amplification transistor has a gate length larger than that of the second selection transistor. A solid-state imaging device;
An optical system for guiding incident light to the photoelectric conversion unit of the solid-state imaging device;
A signal processing circuit for processing an output signal of the solid-state imaging device,
The solid-state imaging device
A first photoelectric conversion unit including a plurality of photoelectric conversion units; a first floating diffusion unit shared by the plurality of photoelectric conversion units of the first photoelectric conversion unit; a first reset transistor; a first amplification transistor; A first shared pixel having a first select transistor;
A second photoelectric conversion unit composed of a plurality of photoelectric conversion units; a second floating diffusion unit shared by the plurality of photoelectric conversion units of the second photoelectric conversion unit; a second reset transistor; a second amplification transistor; A second shared pixel having a second select transistor,
Between the first shared pixel and the second shared pixel in adjacent columns,
The first photoelectric conversion unit and the second photoelectric conversion unit are arranged in the same direction and arranged in the same row. The first selection transistor and the first amplification transistor arranged in the row direction, and the second amplification a series circuit of transistors and the second selection transistor is disposed in a first row adjacent to each other physician inverted state in the row direction,
The first reset transistor and the second reset transistor are arranged in a second row side by side in the same direction;
A connection line that electrically connects a source region of the first reset transistor, an amplification gate electrode of the first amplification transistor, and the first floating diffusion portion; a source region of the second reset transistor; An electronic device, wherein an amplification gate electrode of the second amplification transistor and a connection wiring that electrically connects the second floating diffusion portion have the same length. The first photoelectric conversion unit includes a first photodiode and a second photodiode,
The electronic device according to claim 8, wherein the second photoelectric conversion unit includes a third photodiode and a fourth photodiode. The first photodiode and the third photodiode are arranged in a third row;
The electronic device according to claim 9, wherein the third row is disposed between the first row and the second row. The second photodiode and the fourth photodiode are arranged in a fourth row;
The electronic device according to claim 9, wherein the fourth row is disposed between the first row and the second row. The first photodiode and the third photodiode are arranged in a third row, and the third row is arranged between the first row and the second row;
The second photodiode and the fourth photodiode are arranged in a fourth row, and the fourth row is arranged between the first row and the second row. The electronic device as described in. The first selection transistor has a first selection source region connected to a first vertical signal line in a first signal connection unit,
The second selection transistor has a second selection source region connected to the second vertical signal line in the second signal connection unit,
The electronic device according to claim 8, wherein the first amplification transistor and the second amplification transistor are disposed between the first signal connection unit and the second signal connection unit in the first row. The first amplifying transistor has a first amplifying drain region connected to a power source at a first amplifying gate electrode and a power source connecting portion,
The second amplifying transistor has a second amplifying drain region connected to a power source at a second amplifying gate electrode and the power source connecting portion,
The power supply connection portion is disposed between the first amplification gate electrode and the second amplification gate electrode,
The electronic device according to claim 8, wherein the first amplification transistor has a larger gate length than the first selection transistor, and the second amplification transistor has a larger gate length than the second selection transistor.

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