WO2007105478A1 - Dispositif semiconducteur de type en couches dote d'un capteur integre - Google Patents

Dispositif semiconducteur de type en couches dote d'un capteur integre Download PDF

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Publication number
WO2007105478A1
WO2007105478A1 PCT/JP2007/053557 JP2007053557W WO2007105478A1 WO 2007105478 A1 WO2007105478 A1 WO 2007105478A1 JP 2007053557 W JP2007053557 W JP 2007053557W WO 2007105478 A1 WO2007105478 A1 WO 2007105478A1
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image sensor
transistor
pixels
pixel
output
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PCT/JP2007/053557
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Japanese (ja)
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Mitsumasa Koyanagi
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Mitsumasa Koyanagi
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures

Definitions

  • the present invention relates to a stacked semiconductor device equipped with an integrated sensor, and more specifically, a sensor circuit including a photoelectric conversion element, a transfer (transfer) gate, a reset transistor, and an amplification transistor, and using the sensor circuit
  • the present invention relates to an addressable image sensor that enables simultaneous shuttering (global 'shutter, simultaneous exposure) for all pixels with a simple configuration.
  • CMOS image sensors XY addressing type image sensors
  • CMOS image sensors XY addressing type image sensors
  • CMOS image sensors XY addressing type image sensors
  • SLR digital 'still' cameras and mobile phones This is a system that can be manufactured with a standard CMOS (Complementary Metal-Oxide-Semiconductor) process, which requires only one power supply and has low power consumption compared to a CCD image sensor. This is probably because the advantages of CMOS image sensors such as on-chip are easy to realize.
  • CMOS addressing type image sensor
  • the first problem is that simultaneous accumulation of signal charges for all pixels (in other words, simultaneous or global shirt tie) is not possible.
  • the signal charge accumulation period (which is equal to the exposure period) is the same for all pixels.
  • signal charge accumulation is started for each row of the pixel matrix or for each pixel, and the signal charge accumulated in each pixel is time-sequentially in order of each pixel force by addressing. Since it is read out, there is a temporal shift (timing shift) in the signal charge accumulation period of each pixel. Therefore, signal charge cannot be accumulated simultaneously as in a CCD image sensor. The reason is explained with reference to Fig. 33 and Fig. 30.
  • FIG. 33 (a) is a conceptual diagram showing a general circuit configuration of a CCD image sensor.
  • FIG. 30 (b) is a conceptual diagram showing a signal charge accumulation period of the CCD image sensor.
  • FIG. 30 (a) is a conceptual diagram showing a general circuit configuration of a conventional CMOS image sensor
  • FIG. 30 (b) is a conceptual diagram showing a signal charge accumulation period of the CMOS image sensor.
  • each of a plurality of pixels arranged in a matrix includes a photodiode as a photoelectric conversion element, and each of these photodiodes is irradiated.
  • An amount of signal charge corresponding to the intensity of the emitted light is accumulated.
  • the signal charges accumulated in each pixel are simultaneously read out to vertical CCDs arranged along each column of the pixel matrix via a transfer gate (not shown) provided for each pixel. This readout to the vertical CCD is usually performed simultaneously at the end of the vertical blanking period.
  • the signal charge read out to each vertical CCD is sequentially transferred to a common horizontal CCD arranged along the row of the pixel matrix by the vertical transfer action of the vertical CCD.
  • the signal charges transferred to the horizontal CCD in this way are further transferred horizontally by the horizontal CCD toward the output end, and amplified by a FD (floating diffusion) amplifier provided at the output end for signal output. It becomes.
  • FD floating diffusion
  • the signal charge accumulation period of the CCD image sensor is, as can be easily understood from FIG. 33 (b), the pixel corresponding to each of the N scanning lines (1 to N) constituting one frame. ! /, The accumulation period is the same, in other words, the accumulation period is set at the same timing. It will be clear that this is the case when considering the operation that the signal charge accumulated in each pixel is read out to the vertical CCD all at once.
  • the conventional CMOS image sensor as shown in FIG. 30 (a), each of a plurality of pixels arranged in a matrix has a photodiode as a photoelectric conversion element, and the photodiode. And an amplifier for amplifying the signal charge accumulated by the.
  • Each pixel in the pixel matrix is selected by sequentially selecting row selection lines in the vertical scanning circuit and sequentially selecting column signal lines in the horizontal scanning circuit (that is, designating XY addresses in order). .
  • this is shown by the switch provided in each pixel and the switch provided in each column signal line.
  • CDS Correlated Double
  • the Sampling (correlated double sampling) circuit is a circuit for removing signal charge power noise flowing through each column signal line. The signal charges selectively output from each pixel are sequentially sent to a common horizontal signal line, and become a signal output through an output circuit connected to one end of the horizontal signal line.
  • the pixel corresponding to each of the N scanning lines (1 to N) constituting one frame is arranged. ! / It can be seen that the current accumulation period is shifted in time in accordance with the scanning timing of each scanning line. This is because a CMOS image sensor does not have a vertical register (vertical CCD) like a CCD image sensor, so changing the timing of resetting the signal charge of each pixel changes the signal charge to the corresponding column signal. This is because the timing of sending to the line is shifted.
  • FIG. 31 is a circuit diagram showing a schematic circuit configuration of a conventional CMOS image sensor
  • FIG. 32 is a cross-sectional view of an essential part showing the schematic device structure.
  • the circuit configuration shown in FIG. 31 is that of a CMOS image sensor having a 4-transistor type pixel.
  • CMOS image sensor having a 4-transistor type pixel.
  • transistors transfer gate, reset transistor, Amplifying transistor, four MOS transistors for selection gate. These transistors are formed and arranged on a p-type silicon (Si) substrate as shown in the device structure of FIG. V is the power supply voltage and V is the reset voltage.
  • the reset transistor applies a voltage pulse ⁇ through the reset line in the i-th row
  • the signal charge accumulated in the photodiode is reset at a predetermined timing (applying a predetermined reset voltage V to the photodiode) via the transfer gate in the conductive state.
  • the star has a source follower configuration and amplifies the signal charge sent to the node.
  • the selection gate is connected to a voltage pulse ⁇ through a row selection line (not shown) of the i-th row.
  • a circuit configuration of a pixel of a CMOS image sensor includes a three-transistor type.
  • one pixel includes three transistors (a reset transistor, an amplifying transistor, and a MOS transistor for a select gate) in addition to a photodiode.
  • the four-transistor type configuration gate and the transfer gate are omitted.
  • the circuit configuration of FIG. 31 is specifically realized as the structure shown in FIG. In other words, a plurality of element regions defined by element isolation insulating films on the surface region of a P-type silicon (Si) substrate. Within the region, there are formed four MOS transistors constituting a photodiode, a transfer gate, a reset transistor, an amplification transistor, and a selection gate.
  • CMOS image sensor device structure As is clear from the cross-sectional view of the main part of FIG. 32, four or three MOS transistors have a pixel area of either the four-transistor type or the three-transistor type. Therefore, the ratio of the area occupied by the photodiode (the opening) in the pixel area, that is, the “aperture ratio” is considerably small.
  • the aperture ratio of conventional CMOS image sensors is usually as low as about 30%. For this reason, there is a problem that the sensitivity is lowered, and in order to eliminate the sensitivity reduction, it is necessary to increase the pixel area (pixel size).
  • CMOS image sensor that realizes simultaneous shirting of all pixels mentioned as the first problem is disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2004-266597).
  • the CMOS image sensor includes, in a pixel, a light receiving element, a first transfer unit that transfers signal charges generated by the light receiving element to the next stage, a storage unit that temporarily stores an output of the first transfer unit, An initialization means for initializing the charge of the light receiving element and the storage section, a second transfer means connected to the storage section, and a charge detection section for reading the charge from the second transfer means as a voltage to the outside
  • the stored charge is read by operating the first transfer means all at once for the pixels, and the signal charge is initialized by operating the initialization means for all the pixels all at once.
  • This image sensor chip has a four-layer structure in which a processor array and an output circuit are arranged in the first semiconductor circuit layer, and a data latch and a masking circuit are arranged in the second semiconductor circuit layer. An amplifier and an analog / digital converter are arranged in the third semiconductor circuit layer, and an image sensor array is arranged in the fourth semiconductor circuit layer. The uppermost surface of the image sensor array is covered with a quartz glass layer including the microlens array, and the microlens array is formed on the surface of the quartz glass layer. Image sensor A photodiode is formed as a semiconductor light receiving element in each image sensor in the array.
  • the semiconductor circuit layers that constitute the four-layer structure are mechanically connected using an adhesive, and embedded wiring using conductive plugs and the micro-contacts that are in contact with the embedded wiring. It is electrically connected using bump electrodes.
  • Both the conventional image sensor chip and the image processing chip disclosed in Non-Patent Documents 1 and 2 each include a plurality of semiconductor wafers (hereinafter also simply referred to as wafers) incorporating desired semiconductor circuits. After being stacked and fixed to each other, the obtained wafer stack is cut (diced) and divided into a plurality of chip groups. That is, a semiconductor wafer having a semiconductor circuit formed therein is laminated at the wafer level to form a three-dimensional laminated structure, which is divided to obtain an image sensor chip or an image processing chip. It is.
  • Non-Patent Document 1 Kurino et al., “Intelligent 'Image Sensor' Chip with Three-dimensional Structure”, 1999 I'D. 1 D. 1-Tech. 'Digest' p. 36. 4.1 1-3 4 4 (H. Kunno et al., Intelligent Image Sensor Cnip with Three Dimensional Structure, 1999 IEDM Technical Digest, pp. 36.4.1-36.4.4, 1999)
  • Non-Patent Document 2 Lee et al., “Development of three-dimensional integration technology for highly parallel image processing chips”, “Japan Journal of the Japan Society of Applied Physics, Vol. 39, p. 2473-2477, Part 1 4B, April 2000, (K. Lee et al "Development of fhree—Dimensional Integration Technology ror Highly Paralle 1 Image-Processing Chip", (Jpn. J. Appl. Phys. Vol. 39, pp. 2474-2477, April 2000)
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2004-266597 (FIG. 1—FIG. 2, FIG. 8, FIG. 12, FIG. 15) Disclosure of Invention
  • the conventional general CMOS (addressing type) image sensor cannot simultaneously store signal charges for all the pixels (in other words, simultaneous shirting), and has a low pixel aperture ratio. There are two problems.
  • CMOS image sensor In the conventional CMOS image sensor disclosed in Patent Document 1, all pixels can be simultaneously shirted. However, in each pixel, in addition to the light receiving element, a first transfer means for transferring the signal charge generated in the light receiving element to the next stage, a storage unit for temporarily storing the output of the first transfer means, Since it is necessary to provide an initialization means for initializing the charge of the light receiving element and the storage section and a second transfer means connected to the storage section, the storage section is provided in the 3-transistor type CMOS image sensor. This is an added configuration. Therefore, this CMOS image sensor still has the problem that the pixel aperture ratio is low.
  • Non-Patent Documents 1 and 2 only disclose that a three-dimensional stacked structure can be realized by stacking and fixing semiconductor wafers or semiconductor chips.
  • CMOS complementary metal-oxide-semiconductor
  • the present invention has been made in consideration of these points, and the object of the present invention is to allow substantially simultaneous accumulation of signal charges (substantially simultaneous shirting) for all pixels. Another object of the present invention is to provide a sensor circuit and an addressable image sensor that can realize a higher pixel aperture ratio than a conventional addressable image sensor.
  • a sensor circuit having a plurality of pixels arranged in a matrix and used for an addressing type image sensor that selects each of the pixels by addressing.
  • a plurality of pixel blocks configured by connecting a plurality of the pixels in parallel to a common node every predetermined number, and a plurality of the pixels in the pixel block connected to the common node of each of the pixel blocks.
  • An amplification transistor that is connected to the common node of each of the plurality of pixel blocks and that amplifies signals transmitted from the plurality of pixels in the pixel block, and in each of the pixel blocks, each of the pixels Includes a photoelectric conversion element that generates a signal charge according to the irradiated light, and a first gate element provided in a path between the photoelectric conversion element and the common node of the pixel block. It is characterized by being.
  • a sensor circuit includes a plurality of pixels configured by connecting a plurality of pixels in parallel to a common node every predetermined number (for example, n, n is an integer of 2 or more).
  • each of the pixels is provided in a path between the photoelectric conversion element that generates a signal charge in response to irradiated light and the photoelectric conversion element and the common node of the pixel block.
  • First gate element formed. Since the reset transistor and the amplification transistor are connected to the common node of each pixel block, the reset transistor and the amplification transistor can be shared by each pixel block. This means that a reset transistor and an amplification transistor are provided inside the pixel.
  • the signal charge generation / accumulation ability is operated up to the signal output as follows.
  • the signal corresponding to the signal charge accumulated in the pixels in the pixel block is handled by sequentially turning on the first gate element in time series. To the common node to read in time series. This operation is performed in parallel in a plurality of the blocks. At this time, it is necessary to reset the common node using the reset transistor until the signal is read from one of the pixels in the pixel block and the signal is read from the other one of the pixels. The This is because if the common node is not reset, the influence of the signal read out first remains and the subsequent signal may fluctuate.
  • the signals read out in each of the pixel blocks are amplified in order or in parallel by the corresponding amplification transistors, and are output from the output terminals.
  • the signals sent in order from the plurality of pixels in the pixel block are amplified by the amplification transistor and then time-series from the output terminal. Are output in order.
  • the total number of output terminals of the amplification transistor is equal to the total number of the pixels in the pixel block, the signals are output in parallel from the plurality of output terminals of the amplification transistor.
  • the reset transistor and the amplification transistor are provided outside the block for each of the pixel blocks. It only needs to include one photoelectric conversion element and one first gate element (usually a MOS transistor). Therefore, if this sensor circuit is used, a higher pixel aperture ratio can be achieved compared to a conventional address-designated image sensor that includes three or four MOS transistors in addition to the photoelectric conversion element in the pixel. it can.
  • the amplification transistor has a single output terminal. In this case, there is an advantage that the wiring of the next stage connected to the output terminal of the amplification transistor is simplified.
  • a storage capacitive element connected to the output terminal of the amplification transistor and an output transistor for controlling the output of a signal stored in the capacitive element are further provided.
  • the output transistor there is an advantage that the signal stored in the capacitive element can be output at a timing different from the opening / closing of the first gate element.
  • the amplification transistor has a number of output terminals equal to the total number of the pixels in the pixel block corresponding to the amplification transistor.
  • a second gate element is connected to each of the output terminals.
  • a plurality of storage capacitive elements respectively connected to the plurality of output terminals of the amplification transistor, and a plurality of output transistors for controlling the output of signals stored in the capacitive elements It is preferable to further provide.
  • the signals stored in the plurality of capacitive elements can be output at a timing different from the opening / closing of the first gate element.
  • all of the reset transistors are used before the signal charges are generated and accumulated all at once in the pixels. All of the pixels are collectively reset, and in each of the pixel blocks, signals corresponding to the signal charges accumulated in the pixels are read out in time series via the corresponding common nodes. It is sent to the corresponding amplification transistor. In this case, there is an advantage that substantial simultaneous shirting can be easily realized.
  • a sensor circuit according to a second aspect of the present invention provides:
  • a sensor circuit having a plurality of pixels arranged in a matrix and used for an addressing type image sensor that selects each of the pixels by addressing.
  • each of the pixels includes a photoelectric conversion element that generates a signal charge according to irradiated light, and the photoelectric conversion element.
  • a sensor circuit includes a plurality of pixels configured by connecting a plurality of pixels in parallel to a common node every predetermined number (for example, n, n is an integer of 2 or more).
  • each of the pixels responds to irradiated light.
  • the photoelectric conversion element that generates signal charges and the first gate element provided in the path between the photoelectric conversion element and the common node of the pixel block the photoelectric conversion element and the first And a reset transistor connected to a connection point with the gate element for resetting the pixel.
  • An amplifier transistor is connected to each common node of the pixel block. Therefore, each of the pixel blocks can share the amplification transistor. This means that an amplification transistor is provided inside the pixel.
  • the configuration relating to the reset transistor is different from the sensor circuit according to the first aspect of the present invention. That is, in the sensor circuit according to the first aspect of the present invention, the reset transistor power is provided for each of the pixel blocks (that is, the reset transistor is provided outside each pixel block). In contrast, in the sensor circuit according to the second aspect of the present invention, the reset transistor power is provided for each of the plurality of pixels belonging to each of the pixel blocks (that is, the reset transistor is provided). Provided for each of the pixels). For this reason, the operation up to the signal charge generation / accumulation signal output is performed as follows.
  • the first gate element is put in a cut-off state, and then all of the pixels (photoelectric conversion elements) are irradiated with light, and the pixels are collectively collected. To generate and store signal charges.
  • the signal corresponding to the signal charge accumulated in the pixels in the pixel block is handled by sequentially turning on the first gate element in time series. To the common node to read in time series. This operation is performed in parallel in a plurality of the blocks. At this time, in the pixel block Before the signal is read from one of the pixels and the signal is read from the other one of the pixels, the first gate element is temporarily turned on, and the common node is turned on using the reset transistor. Need to reset. This is because if the common node is not reset, the influence of the signal read out may remain and the subsequent signal may fluctuate.
  • the signal thus read out in each of the pixel blocks is amplified in order or in parallel by the corresponding amplification transistor, and is output from the output end thereof.
  • the signals sent in order from the plurality of pixels in the pixel block are amplified by the amplification transistor and then time-series from the output terminal. Are output in order.
  • the total number of output terminals of the amplification transistor is equal to the total number of the pixels in the pixel block, the signals are output in parallel from the plurality of output terminals of the amplification transistor. This is the same as the sensor circuit according to the first aspect of the present invention.
  • the reset operation of the common node by the reset transistor is required as many times as necessary. (E.g., (n-1) times) time required to execute (total reset time) and time required to amplify the signal charge of the pixel by the corresponding amplification transistor in each of the pixel blocks (total amplification time )),
  • the pixel includes one photoelectric conversion element. And one first gate element (usually a MOS transistor) and one It only needs to include a set transistor (usually a MOS transistor). Therefore, if this sensor circuit is used, a higher pixel aperture ratio can be realized compared to a conventional addressing type image sensor that includes three or four MOS transistors in a pixel. Can do.
  • the amplification transistor has a single output terminal. In this case, there is an advantage that the wiring of the next stage connected to the output terminal of the amplification transistor is simplified.
  • a storage capacitive element connected to the output terminal of the amplification transistor and an output transistor for controlling the output of the signal stored in the capacitive element.
  • the amplification transistor has a number of output terminals equal to the total number of the pixels in the pixel block corresponding to the amplification transistor.
  • a second gate element is connected to each of the output terminals.
  • a plurality of storage capacitive elements respectively connected to the plurality of output terminals of the amplification transistor, and a plurality of output transistors for controlling the output of signals stored in the capacitive elements It is preferable to further provide.
  • the signals stored in the plurality of capacitive elements can be output at a timing different from the opening / closing of the first gate element.
  • the reset transistors are all used to generate and store the signal charges. All of the pixels are collectively reset, and in each of the pixel blocks, a signal corresponding to the signal charge accumulated in the pixel corresponds to the corresponding It is read out in time series through the common node and sent to the corresponding amplification transistor. In this case, there is an advantage that substantial simultaneous shirting can be easily realized.
  • An addressing type image sensor according to a third aspect of the present invention provides:
  • An addressing type image sensor having a three-dimensional stacked structure, which has a plurality of pixels arranged in a matrix and selects each of the pixels by addressing.
  • a plurality of pixel blocks configured by connecting a plurality of the pixels in a predetermined number in parallel to a common node
  • a reset transistor connected to the common node of each of the pixel blocks for resetting a plurality of the pixels in the pixel block;
  • An amplification transistor that is connected to the common node of each of the plurality of pixel blocks and that amplifies signals transmitted from the plurality of pixels in the pixel block, and in each of the pixel blocks, each of the pixels Includes a photoelectric conversion element that generates a signal charge according to the irradiated light, and a first gate element provided in a path between the photoelectric conversion element and the common node of the pixel block.
  • At least the photoelectric conversion element is formed in a first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate element, the reset transistor, and the amplification transistor constitute the three-dimensional laminated structure. It is characterized by being formed in the second or third or subsequent semiconductor circuit layer.
  • An addressing type image sensor uses the sensor circuit according to the first aspect of the present invention described above, and includes at least a plurality of the photoelectric conversion elements in the three-dimensional stacked structure.
  • the first gate element, the reset transistor, and the amplification transistor are formed in the first semiconductor circuit layer to be configured, and the second gate circuit, the reset transistor, and the amplification transistor are in the second or subsequent semiconductor circuit layers that constitute the three-dimensional stacked structure. It corresponds to what was formed.
  • signal charges can be substantially simultaneously accumulated (substantially simultaneous shirting) for all the pixels.
  • a pixel aperture ratio higher than that of the addressing type image sensor can be realized.
  • image distortion in conventional addressing type image sensors It is possible to image a subject that moves at a high speed without occurring.
  • the ratio of the total area of the light receiving region to the total area of the imaging region can be increased.
  • the plurality of first gate elements are included in the first semiconductor circuit layer.
  • the plurality of amplification transistors and the plurality of reset transistors are formed in the second or third and subsequent semiconductor circuit layers.
  • the first semiconductor circuit layer includes a plurality of the first gate elements in addition to the plurality of photoelectric conversion elements, but each pixel includes the first gate in addition to the photoelectric conversion elements. Since only one transistor constituting the element is included, the pixel aperture ratio is improved as compared with a conventional addressed image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element.
  • the plurality of first gate elements and the plurality of reset transistors are formed in the first semiconductor circuit layer, and a plurality of amplification transistors are formed in the second or third and subsequent semiconductor circuit layers.
  • the first semiconductor circuit layer includes a plurality of the first gate elements and a plurality of reset transistors in addition to the plurality of photoelectric conversion elements.
  • only one transistor constituting the first gate element is included, and the total number of the reset transistors may be (lZn) of the total number of pixels. Therefore, the pixel aperture ratio is improved as compared with a conventional addressing type image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element.
  • the number of output terminals equal to the total number of the pixels in the pixel block corresponding to the amplification transistor force is the amplification transistor force.
  • a second gate element is connected to each of the output terminals.
  • An amplification transistor is formed in the first semiconductor circuit layer, and a plurality of the second gate elements (selection transistors) are formed in the second or third and subsequent semiconductor circuit layers.
  • the first semiconductor circuit layer includes a plurality of the first gate elements, a plurality of reset transistors, and a plurality of amplification transistors in addition to the plurality of photoelectric conversion elements.
  • the pixel only includes one transistor that constitutes the first gate element in addition to the photoelectric conversion element, and the total number of the reset transistor and the amplification transistor is (lZn) of the total number of pixels. That's it. Therefore, the pixel aperture ratio is improved as compared with the conventional addressing type image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element.
  • the addressing type image sensor In still another preferable example of the addressing type image sensor according to the third aspect of the present invention, only a plurality of the photoelectric conversion elements are formed in the first semiconductor circuit layer, and the plurality of the first image sensors are formed. A gate element, a plurality of reset transistors, and a plurality of amplification transistors are formed in the second or third and subsequent semiconductor circuit layers.
  • each pixel since only the plurality of photoelectric conversion elements are formed in the first semiconductor circuit layer, each pixel does not include any transistor. Therefore, the pixel aperture ratio is improved as compared with a conventional addressing type image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element. In particular, the improvement in pixel aperture ratio is maximized.
  • each of the amplification transistors has a single output terminal. In this case, there is an advantage that the next-stage wiring connected to the output terminal of the amplification transistor is simplified.
  • a storage capacitor element connected to the output terminal of the amplification transistor and an output of a signal stored in the capacitor element are provided in the second or third and subsequent semiconductor circuit layers. It is preferable to further include an output transistor to be controlled. In this case, by using the output transistor, there is an advantage that the signal stored in the capacitive element can be output at a timing different from the opening / closing of the first gate element.
  • each of the amplification transistors is equal to the total number of the pixels in the pixel block corresponding to the amplification transistor.
  • a number of outputs and each of these outputs Second gate elements are connected to each other.
  • signals from the plurality of pixels in the pixel block are output in parallel from the plurality of output terminals. can do.
  • a plurality of storage capacitive elements respectively connected to the plurality of output terminals of the amplification transistor in the second or third and subsequent semiconductor circuit layers, and the capacitance elements It is preferable to further include a plurality of output transistors for controlling the output of the stored signal.
  • a plurality of the output transistors there is an advantage that signals stored in a plurality of the capacitive elements can be output at a timing different from the opening / closing of the first gate element.
  • all of the reset transistors are set before generating and accumulating signal charges in all of the pixels. All of the pixels are collectively reset using a signal, and in each of the pixel blocks, a signal corresponding to the signal charge accumulated in the pixel is passed through the corresponding common node. After being read out in time series, it is sent to the corresponding amplification transistor. In this case, there is an IJ point that a substantial simultaneous shirting can be realized easily.
  • An addressing type image sensor is:
  • An addressing type image sensor having a three-dimensional stacked structure, which has a plurality of pixels arranged in a matrix and selects each of the pixels by addressing.
  • a plurality of pixel blocks configured by connecting a plurality of the pixels in a predetermined number in parallel to a common node
  • An amplification transistor that is connected to the common node of each of the plurality of pixel blocks and that amplifies signals transmitted from the plurality of pixels in the pixel block, and in each of the pixel blocks, each of the pixels Includes a photoelectric conversion element that generates a signal charge according to the irradiated light, a first gate element provided in a path between the photoelectric conversion element and the common node of the pixel block, and the photoelectric conversion element.
  • the conversion element and the first A reset transistor connected to a connection point with the gate element for resetting the pixel,
  • At least the photoelectric conversion element is formed in a first semiconductor circuit layer constituting the three-dimensional laminated structure, and the first gate element, the reset transistor, and the amplification transistor constitute the three-dimensional laminated structure. It is characterized by being formed in the second or subsequent semiconductor circuit layer.
  • An addressing type image sensor uses the sensor circuit according to the second aspect of the present invention described above, and includes at least a plurality of the photoelectric conversion elements described above in the three-dimensional stack.
  • the first gate element, the reset transistor, and the amplification transistor are formed in the first semiconductor circuit layer constituting the structure, and the second and subsequent semiconductor circuit layers constituting the three-dimensional stacked structure are formed. It corresponds to what was formed inside.
  • signal charges can be accumulated substantially simultaneously (substantially simultaneous shirting) for all the pixels, A pixel aperture ratio higher than that of the addressing type image sensor can be realized.
  • a preferred example of the addressing type image sensor according to the fourth aspect of the present invention is the same as that of the addressing type image sensor according to the third aspect of the present invention described above. This is because in the addressing type image sensor according to the third aspect of the present invention, a reset transistor is provided for each of the blocks (that is, a reset transistor is provided outside each block). On the other hand, in the addressing type image sensor according to the fourth aspect of the present invention, the reset transistor is provided for each of the plurality of photoelectric conversion elements belonging to each of the blocks, and therefore both are different. It is.
  • a plurality of first gate elements are formed in the first semiconductor circuit layer, and a plurality of amplification transistors and a plurality of reset transistors are provided in the second semiconductor circuit layer.
  • the first semiconductor circuit layer includes a plurality of the first gate elements in addition to the plurality of photoelectric conversion elements, but each pixel includes the first gate in addition to the photoelectric conversion elements. Since only one transistor constituting the element is included, the pixel aperture ratio is improved as compared with a conventional addressed image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element.
  • the plurality of first gate elements and the plurality of reset transistors are A plurality of amplification transistors are formed in the first semiconductor circuit layer, and a plurality of amplification transistors are formed in the second or third and subsequent semiconductor circuit layers.
  • the first semiconductor circuit layer includes a plurality of the first gate elements and a plurality of reset transistors in addition to the plurality of photoelectric conversion elements.
  • each pixel since it only includes two transistors, that is, the transistor constituting the first gate element and the reset transistor, each pixel has a conventional addressing type image sensor including four transistors or three transistors in addition to the photoelectric conversion element. Compared with pixel aperture ratio
  • the amplification transistor force is equal to the total number of the pixels in the pixel block corresponding to the amplification transistor.
  • a second gate element (selection transistor) is connected to each of the output terminals.
  • a plurality of the first gate elements, a plurality of the reset transistors, and a plurality of the amplification transistors are formed in the first semiconductor circuit layer, and the plurality of the second gates are arranged on the plurality of the photoelectric conversion elements.
  • An element (selection transistor) is formed in the second or third or subsequent semiconductor circuit layers.
  • the first semiconductor circuit layer includes a plurality of the first gate elements, a plurality of reset transistors, and a plurality of amplification transistors in addition to the plurality of photoelectric conversion elements.
  • a pixel constitutes the first gate element in addition to the photoelectric conversion element.
  • the reset transistor and the reset transistor There are only two transistors, the reset transistor and the reset transistor, and the total number of the amplification transistors may be (lZn) of the total number of pixels. Therefore, the pixel aperture ratio is improved as compared with a conventional addressing type image sensor in which each pixel includes four transistors or three transistors in addition to the photoelectric conversion element.
  • the addressing type image sensor In still another preferred example of the addressing type image sensor according to the fourth aspect of the present invention, only a plurality of the photoelectric conversion elements are formed in the first semiconductor circuit layer, and a plurality of the first image sensors are formed. A gate element, a plurality of reset transistors, and a plurality of amplification transistors are formed in the second or third and subsequent semiconductor circuit layers.
  • each pixel since only the plurality of photoelectric conversion elements are formed in the first semiconductor circuit layer, each pixel does not include any transistor. Therefore, the pixel aperture ratio is improved as compared with a conventional addressing type image sensor in which each pixel includes four or three transistors in addition to the photoelectric conversion element. In particular, the improvement in pixel aperture ratio is maximized.
  • each of the amplification transistors has a single output terminal. In this case, there is an advantage that the next-stage wiring connected to the output terminal of the amplification transistor is simplified.
  • a storage capacitive element connected to the output terminal of the amplification transistor and an output of a signal stored in the capacitive element are provided in the second or third and subsequent semiconductor circuit layers. It is preferable to further include an output transistor to be controlled. In this case, by using the output transistor, there is an advantage that the signal stored in the capacitive element can be output at a timing different from the opening / closing of the first gate element.
  • each of the amplification transistors is equal to the total number of the pixels in the pixel block corresponding to the amplification transistor.
  • the second gate element is connected to each of the output terminals. In this case, by opening and closing each of the second gate elements in synchronization with the corresponding first gate element, signals from the plurality of pixels in the pixel block are output in parallel from the plurality of output terminals. can do. As a result, there is an advantage that the next signal processing can be performed quickly.
  • the amplification transistor is included in the second or third and subsequent semiconductor circuit layers. It is preferable to further include a plurality of storage capacitive elements respectively connected to the plurality of output terminals of the star, and a plurality of output transistors for controlling the output of signals stored in these capacitive elements. In this case, by using a plurality of the output transistors, there is an advantage that signals stored in a plurality of the capacitive elements can be output at a timing different from the opening / closing of the first gate element.
  • all the reset transistors must be connected before generating and accumulating signal charges all over the pixels. All of the pixels are collectively reset using a signal, and in each of the pixel blocks, a signal corresponding to the signal charge accumulated in the pixel is passed through the corresponding common node. After being read out in time series, it is sent to the corresponding amplification transistor. In this case, there is an IJ point that a substantial simultaneous shirting can be realized easily.
  • the “photoelectric conversion element” was irradiated. It means an element that generates a charge in response to light.
  • a photodiode which is a semiconductor element, can be suitably used.
  • the present invention is not limited to this as long as the element has a function of generating electric charge according to irradiated light. Anything can be used.
  • the “first gate element” means an element having a gate function for opening and closing a path connecting each of the plurality of photoelectric conversion elements and the corresponding common node. Force that MOS transistor can be used suitably The present invention is not limited to this.
  • any transistor can be used as long as it has a function of resetting signal charges generated in the plurality of pixels (the photoelectric conversion elements) belonging to the group.
  • the “reset transistor” is a power that can be suitably used as a MOS transistor. The present invention is not limited to this.
  • the “amplifying transistor” has a function of amplifying signals corresponding to signal charges generated by the plurality of pixels (the photoelectric conversion elements) belonging to the pixel block in time series to generate an output signal. Any transistor can be used as long as it has a transistor. "Increase As the “width transistor”, a MOS transistor can be suitably used. The present invention is not limited to this.
  • First semiconductor circuit layer and “second or third and subsequent semiconductor circuit layers” mean semiconductor circuit layers, in other words, semiconductor circuits formed in layers. Usually, it includes, but is not limited to, “semiconductor substrate” and “elements” and “wirings” formed inside or on the surface of the semiconductor substrate.
  • the material of the “semiconductor substrate” is arbitrary, and may be silicon, a compound semiconductor, or other semiconductors as long as a desired semiconductor element or circuit can be formed.
  • the structure of the “semiconductor substrate” is arbitrary, and may be a simple plate made of a semiconductor or a so-called SOI (Silicon On Insulator) substrate.
  • first semiconductor circuit layer and the “second or third and subsequent semiconductor circuit layers” are defined as necessary (for example, the first semiconductor circuit layer and the second or third and subsequent semiconductor circuit layers alone If the desired stiffness is not obtained, it is fixed to any “support substrate” that is rigid enough to support them.
  • the material of the “support substrate” is arbitrary. That is, it may be a semiconductor, glass, or other material.
  • a semiconductor substrate having a circuit formed therein, that is, a so-called LSI wafer or LSI chip may be used.
  • “Embedded wiring” refers to a wiring or conductor for electrical connection in the stacking direction embedded in “first semiconductor circuit layer” or “second or third or subsequent semiconductor circuit layers”. . “Built-in wiring” is usually filled with (insulating film) and “insulating film” that covers the entire inner wall surface of “trench” or “through hole” formed in the semiconductor substrate, and the space inside the insulating film. ) "Conductive material” and force are also composed. However, it is not necessarily limited to this configuration.
  • the “trench” or “through hole” may have any desired configuration as long as it has a desired depth and accommodates a conductive material to be an embedded wiring.
  • the depth, opening shape, opening size, cross-sectional shape, etc. of the “trench” or “through hole” can be arbitrarily set as required.
  • any method for forming “trench” or “through hole” any method can be used as long as it can be formed by selectively removing the semiconductor substrate from the surface side. For example, an anisotropic etching method using a mask can be suitably used.
  • the “insulating film” covering the inner wall surface of the “trench” or “through hole” electrically connects the semiconductor substrate and the “conductive material” filled in the “trench” or “through hole”. If it can be insulated, Any insulating film can be used. For example, silicon dioxide (SiO 2), silicon nitride (SiN)
  • Etc. can be used suitably.
  • a method of forming the “insulating film” is arbitrary.
  • any material can be used as long as it can be used as a buried wiring (for example, a conductive plug).
  • semiconductors such as polysilicon, metals such as tungsten (W), copper (Cu), and aluminum (A1) can be preferably used.
  • the filling method of the “conductive material” any method can be used as long as the “conductive material” can be filled into the “trench” or “through hole” from one side of the semiconductor substrate.
  • signal charges can be substantially simultaneously accumulated (substantially simultaneous shirting) for all the pixels, and moreover than a conventional addressed image sensor. It is possible to achieve a high pixel aperture ratio, and (b) to image a subject moving at high speed without causing image distortion in a conventional addressing type image sensor.
  • signal charges can be substantially simultaneously accumulated (substantially simultaneous shirting) for all pixels, and moreover than a conventional addressing type image sensor.
  • a signal charges can be substantially simultaneously accumulated (substantially simultaneous shirting) for all pixels, and moreover than a conventional addressing type image sensor.
  • Can achieve high pixel aperture ratios (b) can capture high-speed moving subjects without image distortion in conventional addressing-type image sensors, and (c) receive light with respect to the total area of the imaging area The effect is that the ratio of the total area of the region is high.
  • FIG. 1 is a functional block diagram showing an overall configuration of an addressing type image sensor in which a sensor circuit according to a first embodiment of the present invention is used.
  • FIG. 2 is a diagram showing a main circuit configuration of the sensor circuit according to the first embodiment of the present invention, and shows a circuit configuration of two pixel blocks belonging to the j-th column.
  • FIG. 3 is a view similar to FIG. 2 showing a principal circuit configuration of a sensor circuit according to a second embodiment of the present invention.
  • FIG. 4 is the same as FIG. 2 showing the main circuit configuration of the sensor circuit according to the third embodiment of the present invention.
  • FIG. 4 is the same as FIG. 2 showing the main circuit configuration of the sensor circuit according to the third embodiment of the present invention.
  • FIG. 5 is a view similar to FIG. 2 showing a principal circuit configuration of a sensor circuit according to a fourth embodiment of the present invention.
  • FIG. 6 A circuit diagram showing a main circuit configuration of an addressing type image sensor according to a fifth embodiment of the present invention.
  • FIG. 7 A circuit diagram showing the main circuit configuration of the addressing type image sensor according to the sixth embodiment of the present invention.
  • FIG. 8 is a cross-sectional view of a main part showing an actual structure of an addressing type image sensor according to a fifth embodiment of the present invention.
  • FIG. 10 A circuit diagram showing the main circuit configuration of the addressing type image sensor according to the seventh embodiment of the present invention.
  • FIG. 11 is a cross-sectional view of a principal part showing an actual structure of an addressing type image sensor according to a seventh embodiment of the present invention.
  • FIG. 13 A circuit diagram showing the main circuit configuration of the addressing type image sensor according to the ninth embodiment of the present invention.
  • FIG. 16 is a circuit diagram showing the main circuit configuration of the addressing type image sensor according to the eleventh embodiment of the present invention.
  • ⁇ 17 It is a sectional view of the main part showing the actual structure of the addressing type image sensor according to the eleventh embodiment of the present invention.
  • FIG. 18 An actual structure of an addressing type image sensor according to a twelfth embodiment of the present invention is shown.
  • FIG. 19 is a functional block diagram showing an overall configuration of an addressing type image sensor in which a sensor circuit according to a thirteenth embodiment of the present invention is used.
  • ⁇ 23 A sectional view of the principal part showing the actual structure of the addressing type image sensor according to the fourteenth embodiment of the present invention.
  • FIG. 25 is a cross-sectional view of a main part showing a configuration example of a storage capacitor element used in the addressing type image sensor of the present invention.
  • FIG. 26 is a cross-sectional view of the principal part showing another configuration example of the storage capacitor element used in the addressing type image sensor of the present invention.
  • FIG. 27 is a cross-sectional view of the principal part showing still another configuration example of the storage capacitor element used in the addressing type image sensor of the present invention.
  • FIG. 28 is a circuit diagram showing a main circuit configuration of an addressing type image sensor according to a sixteenth embodiment of the present invention.
  • FIG. 29 is a cross-sectional view of an essential part showing the actual structure of the addressing type image sensor according to the sixteenth embodiment of the present invention.
  • FIG. 30 (a) is a conceptual diagram showing a general circuit configuration of a conventional CMOS (addressing type) image sensor, and (b) is a conceptual diagram showing a signal charge accumulation period of the image sensor. 31] A circuit diagram showing a main circuit configuration of a conventional CMOS (addressing type) image sensor.
  • FIG. 32 is a cross-sectional view of an essential part showing the actual structure of a conventional CMOS (addressing type) image sensor.
  • FIG. 33 (a) is a conceptual diagram showing a general circuit configuration of a conventional CCD (charge transfer type) image sensor, and (b) is a conceptual diagram showing a signal charge accumulation period of the image sensor.
  • CCD charge transfer type
  • FIG. 34 (a) is a conceptual diagram showing an image obtained by imaging a high-speed rotating blade with a CCD (charge transfer type) image sensor. The same blade is imaged with a conventional CMOS (addressing type) image sensor. It is a conceptual diagram which shows the image obtained in this way.
  • CCD charge transfer type
  • CMOS addressing type
  • FIG. 2 is a diagram showing a main circuit configuration of the sensor circuit 1 according to the first embodiment of the present invention.
  • FIG. 1 is a functional block diagram showing an overall configuration of an addressing type image sensor (hereinafter also referred to as a CM OS image sensor) in which the sensor circuit 1 is used. This sensor circuit 1 corresponds to the sensor circuit according to the first aspect of the present invention.
  • CM OS image sensor an addressing type image sensor
  • the overall configuration of the image sensor in Fig. 1 is the conventional CMOS (address specification) shown in Fig. 30 (a).
  • Type Almost the same as an image sensor, & 11) arranged in a matrix of rows and 111 columns (n and m are integers greater than or equal to 2) (k X n) 111 pixels 11 (hereinafter these The matrix formed by the pixels 11 is also referred to as a “pixel matrix”).
  • pixel matrix The matrix formed by the pixels 11 is also referred to as a “pixel matrix”.
  • these pixels 11 are divided into (k X m) pixel blocks 12 (blocky), and each pixel 11 does not include a reset transistor and an amplification transistor.
  • C MOS image sensors Different from conventional C MOS image sensors.
  • each pixel block 12 n pixels 11 belonging to the same column are grouped every n and connected in parallel to a common node (not shown in FIG. 1 and corresponding to the common node 13 in FIG. 2) This constitutes a pixel block 12 (see FIG. 2).
  • the pixel blocks 12 are also arranged in a matrix.
  • One pixel block 12 is provided.
  • the reset transistor Tr and the amplifying transistor Tr are respectively n pixels 1 in each pixel block 12.
  • the total number of amplification transistors Tr is also (k X m).
  • each reset line 31 In the vicinity of each pixel block 12, m reset lines 31 are formed, each extending along a corresponding column of the pixel matrix. Since one reset transistor Tr is provided for each pixel block 12, each reset line 31 has k reset transistors.
  • the transistor Tr is connected. Each output terminal of the reset transistor Tr
  • Each reset line 31 corresponds to
  • Each amplification transistor Tr corresponds to
  • the signal amplified by each amplification transistor Tr is the output of the amplification transistor Tr.
  • the signals are sequentially sent to the corresponding column signal lines 37 via the ends.
  • (k X n) read control lines 32 each extending along a corresponding row of the pixel matrix are formed. These read control lines 32 Are provided for each of m pixel blocks 12 belonging to the same row, and each force of n pixels 11 in each pixel block 12 is also used for reading out a signal.
  • n readout control lines 32 provided for m pixel blocks 12 belonging to the same row are collectively shown as a single line.
  • each vertical scanning circuit 34 In the vicinity of the left end of the pixel matrix, one vertical scanning circuit 34 extending along the column of the pixel matrix is provided.
  • the vertical scanning circuit 34 sequentially scans (k X n) read control lines 32 and selects them in time series. At this time, each readout control line 32 is supplied with a signal for selecting the n pixels 11 included in each of the m pixel blocks 12 belonging to the corresponding row in time series (the transfer gate in FIG. 2). Supports control signals ⁇ to ⁇
  • one horizontal signal line 33 and one horizontal scanning circuit 35 extending along the row of the pixel matrix and m CDS circuits 36 for noise removal are provided. It has been.
  • the horizontal scanning circuit 35 selects these CDS circuits 36 in time series by m column selection signals 38.
  • Each of the m CDS circuits 36 includes k amplification transistors Tr belonging to the column.
  • K column signal lines 37 respectively connected to the output terminals are connected in parallel. Therefore, the k output signals of k amplification transistors Tr belonging to the same row correspond to the corresponding CD.
  • FIG. 2 shows a circuit configuration of two pixel blocks 12 belonging to the j-th column (where l ⁇ j ⁇ m) of the pixel matrix.
  • the upper pixel block 12 has the upper force located at the i-th (where l ⁇ i ⁇ k), and the lower pixel block 12 has the upper force located at the (i + 1) -th. Therefore, the upper pixel block 12 is displayed as 12 (i, j) and the lower pixel block 12 is displayed as 12 (i + 1, j) as necessary.
  • the upper pixel block 12 (i, j) belongs to the [n X (i— 1) + 1] row to the (n X i) row of the j-th column. Pixel 11 to be included.
  • the lower pixel block 12 (i + 1, j) includes pixels 11 belonging to the [nX i + 1] row to the [n X (i + 1)] row of the jth column. Since these two pixel blocks 12 (i, j) and 12 (i + 1, j) have the same configuration, in the following description, the upper pixel block 12 (i, j) will be mainly described.
  • each pixel 11 includes one photodiode and one transfer gate. Accordingly, each pixel 11 includes n photodiodes PD to PD and n transfer gates TG to TG.
  • Each of the transfer gates TG to TG is composed of a MOS transistor.
  • the anode of each photodiode PD to PD is connected to one of the source and drain regions of the corresponding one of the transfer gates TG to TG.
  • the other source and drain regions of each of the transfer gates TG to TG are commonly connected to a common node 13 in the pixel block 12 (i, j). That is, n pixels 11 in the pixel block 12 (i, j) are connected in parallel to the common node 13.
  • the common node 13 of the pixel block 12 (i, j) has one source'drain region of the common reset transistor T provided corresponding to the pixel block 12 (i, j) and the pixel block 12
  • One source / drain region of the amplification transistor T is connected to a DC power supply (power supply voltage).
  • the other source / drain region (output side) is connected to the output terminal of the pixel block 12 (i, j) (that is, the corresponding column signal line 37).
  • the output terminal of the amplifying transistor T (source side / drain region on the output side) is connected to a predetermined potential (through
  • the capacitance C connected to the node 14 is a parasitic capacitance generated at the node 14 and is sn
  • Node 14 is connected to a terminal of a predetermined potential (usually ground potential) or sn through parasitic capacitance C.
  • the output terminal of the amplifying transistor T (the source-drain region on the output side) is shown in Fig. 1.
  • the output signal of the amplification transistor T is connected to the corresponding column signal line 37.
  • the serial (time-series) output signals of the n photodiodes PD to PD are sent to the corresponding CDS circuit 36 via the corresponding column signal line 37.
  • the column signal line 37 is selected via the m column selection signals 38 by the scanning of the horizontal scanning circuit 35, whereby the serial output signal is sent.
  • the signal is sent to the horizontal signal line 33.
  • the signal is sent to the output terminal (not shown) of the image sensor provided at one end of the horizontal signal line 33 (the right end in FIG. 1).
  • All the pixel blocks 12 other than the pixel block 12 (i, j) have the same configuration as the pixel block 12 (i, so that n photodiodes are formed in the same manner as described above.
  • the serial output signal from PD to PD is sent to the output terminal of the image sensor, so that the subject can be imaged.
  • pulse signals respectively applied to the gate electrodes of the MOS transistors constituting the transfer gates TG to TG (first gate elements) provided for the photodiodes PD to PD of all the pixels 11.
  • Gate control signal ⁇
  • the logic state of the signal (reset control signal) ⁇ is H, and all reset transistors Tr
  • the voltage applied to the photodiodes PD to PD of all the pixels 11 is made approximately equal to the reset voltage V, in other words, the photo diodes of all the pixels 11.
  • the logic state of the transfer gate control signals ⁇ to ⁇ applied to the transfer gates TG to TG of all the pixels 11 is set to Low (L), and all the transfer gates TG to TG are set.
  • Tl Tn 1 is turned off.
  • the logic state of the reset control signal ⁇ is set to L, and n RST
  • the photodiodes PD to PD of all the pixels 11 are irradiated with light, and signal charges are generated and accumulated all at once in all the photodiodes PD to PD.
  • the irradiation time is usually several hundreds / z sec to several msec and is very long.
  • the reset voltage V is temporarily applied to the gate electrode of the transistor Tr, and all the amplification transistors T
  • the gate voltage of r is set to a predetermined reference voltage.
  • a signal proportional to the amount of charge generated and accumulated in all the photodiodes PD to PD as described above is read out from each pixel 11 in the form of voltage and amplified as follows.
  • n transfer gate control signals ⁇ ⁇ in the pixel block 12 are selected.
  • the logic state of ⁇ is changed from L to H in order, and the transfer gates TG to TG are turned on sequentially.
  • the amplification transistor Tr connected to the node 14 in the form of a source follower has its gate
  • the voltage signal read to the node 14 is immediately amplified by the amplification transistor Tr.
  • the amplified signal is then transferred to the amplified traffic.
  • the source / drain region force on the output terminal side of the transistor Tr is also output toward the column signal line 37.
  • the reset voltage V is temporarily applied to node 14 by turning on the transistor Tr.
  • the node 14 (the gate electrode of the amplification transistor Tr) is set to the reference potential.
  • the total number of amplification operations by r is n, and the total number of reset operations of the amplification transistor Tr
  • the first transfer gate TG of the pixel block 12 is temporarily turned on, and the voltage proportional to the signal charge accumulated in the first photodiode PD is set. Read the signal to node 14. The voltage signal is immediately amplified by the amplifying transistor Tr, and the obtained amplified signal is sent to the column signal line 37.
  • the reset transistor Tr is temporarily turned on, and the amplification transistor Tr
  • the signal is immediately amplified by the amplifying transistor Tr, and the obtained amplified signal is the column signal line 37.
  • the reset transistor Tr is temporarily turned on and increased.
  • n signals from which all the photodiodes PD to PD in the pixel block 12 can also be obtained are connected to the source terminal n AMP on the output terminal side of the amplification transistor Tr.
  • the rain region force is also output in sequence toward the column signal line 37 in time series.
  • the signal output from the pixel block 12 is a signal in which n pulse waveforms that reflect the amount of signal charges (the amount of irradiated light) of the photodiodes PD to PD are connected at a predetermined interval.
  • the image sensor has (k X m) pixel blocks 12 in total, the above-described operation is repeated (k X m) times while all the pixels 11 are scanned. .
  • a signal output from the pixel block 12, that is, one serial signal in which n signal pulses are connected at a predetermined interval, is a known sample and hold circuit, The signal is sent to an analog-to-digital (AZD) conversion circuit and subjected to predetermined signal processing.
  • a signal output from the pixel block 12 that is, one serial signal in which n signal pulses are connected at a predetermined interval, is a known sample and hold circuit, The signal is sent to an analog-to-digital (AZD) conversion circuit and subjected to predetermined signal processing.
  • a signal output from the pixel block 12 that is, one serial signal in which n signal pulses are connected at a predetermined interval, is a known sample and hold circuit, The signal is sent to an analog-to-digital (AZD) conversion circuit and subjected to predetermined signal processing.
  • a signal output from the pixel block 12 that is, one serial signal in which n signal pulses are connected at a predetermined interval
  • n value total number of pixels 11 in each pixel block 12
  • shortest signal charge accumulation period 125 sec
  • each force of all pixel blocks 12 outputs (k X m) output serial signals independently, so that these output serial signals are processed by analog-digital (AZD) conversion and the like. Can be done in parallel. Therefore, data processing can be performed at a higher speed than that in the conventional CMOS image sensor. This also contributes to the realization of practical simultaneous shirting. Is.
  • each pixel block 12 is provided with a common reset transistor Tr and a common amplification transistor Tr outside the pixel block 12, the pixel block 12
  • Each pixel 11 in the lock 12 only needs to include one photodiode and one gate element (MOS transistor). Therefore, in addition to the photodiode in one pixel, there are three! Compared with a conventional CMOS image sensor including four MOS transistors, a high pixel aperture ratio (for example, about 60%) can be realized.
  • the sensor circuit 1 of the first embodiment is In image sensors, the processing speed of each serial output signal of the amplifying transistor Tr is increased by increasing the parallelism by setting the n value to be smaller than the number of scanning lines.
  • n output signal powers of n photodiodes PD to PD force are output from each of the amplification transistors Tr in a serially connected form, so that the amplification transistor Tr
  • FIG. 3 is a circuit diagram showing a configuration of a sensor circuit 1A according to the second embodiment of the present invention. Since the entire configuration of the addressing type image sensor using this sensor circuit 1A is the same as that shown in FIG. 1, its description is omitted.
  • This sensor circuit 1A corresponds to the sensor circuit according to the first aspect of the present invention.
  • the circuit configuration of the sensor circuit 1A shown in FIG. 3 is substantially the same as the circuit configuration of the sensor circuit 1 according to the first embodiment (see FIG. 2), and the amplification provided for each pixel block 12 A storage capacitor C and an output transistor Tr are added to the output side of the transistor Tr.
  • the storage capacitor element C temporarily receives the signal amplified by the corresponding amplification transistor Tr.
  • One terminal is the output side of the amplifying transistor Tr
  • the other terminal is connected to a terminal or region having a predetermined potential (usually ground potential).
  • the signal is sent to the corresponding column signal line 37, and the output side source / drain region is connected to the output terminal (column signal line 37) of the pixel block 12.
  • the output transistor Tr sets the logic state of the output control signal ⁇ applied to its gate electrode to H.
  • the output transistor Tr opens the transfer gates TG to TG in the pixel block 12.
  • the serial output signals of the n photodiodes PD to PD force in the corresponding pixel block 12 are amplified by the amplification transistor Tr. Immediately after that, it is output toward the column signal line 37. to this
  • the serial output signals from the n photodiodes PD to PD in the pixel block 12 are the amplification transistors Tr.
  • the signal ⁇ is used to read signals from the photodiodes PD to PD.
  • the opening and closing of the transfer gates TG to TG are shifted in timing and output toward the column signal line 37. You can make it stronger.
  • the signal charges for all the pixels 11 are substantially simultaneously accumulated (substantially) for the same reason as in the first embodiment. Simultaneous simultaneous shots).
  • it is possible to make a substantially simultaneous shutter in this way it is possible to image a subject that moves at high speed without causing image distortion in a conventional CMOS image sensor.
  • each pixel block 12 is provided with a common reset transistor Tr and a common amplification transistor Tr outside the pixel block 12, the pixel block 12
  • Each pixel 11 in the gate 12 only needs to include one photodiode and one gate element (MOS transistor). Therefore, a higher pixel opening ratio can be realized as compared with a conventional CMOS image sensor that includes three or four MOS transistors in addition to a photodiode in one pixel.
  • MOS transistor gate element
  • the transfer gates TG to T in the pixel block 12 are controlled by the output control signal ⁇ .
  • the signal can be output to the column signal line 37 at a different timing from the opening and closing of G, there is also an effect that imaging can be performed at a higher speed than when the sensor circuit 1 of the first embodiment is used.
  • FIG. 4 is a circuit diagram showing a configuration of a sensor circuit 1B according to the third embodiment of the present invention. Since the entire configuration of the addressing type image sensor using this sensor circuit 1B is the same as that shown in FIG. 1, its description is omitted.
  • This sensor circuit 1B corresponds to the sensor circuit according to the first aspect of the present invention.
  • the circuit configuration of the sensor circuit 1B shown in FIG. 4 is substantially the same as the circuit configuration of the sensor circuit 1 (see FIG. 2) according to the first embodiment, and the amplification provided for each pixel block 12 N select transistors Tr to Tr in the source and drain regions on the output side of the transistor Tr
  • the logic states of the output selection signals ⁇ to ⁇ applied to the gate electrodes are set to H, respectively.
  • n selection transistors Tr to Tr correspond to corresponding pixels.
  • the column signal line 37 is passed through the selection transistor Tr.
  • the signal charges for all the pixels 11 are substantially simultaneously accumulated (substantially) for the same reason as in the first embodiment. Simultaneous simultaneous shots).
  • it is possible to make a substantially simultaneous shutter in this way it is possible to image a subject that moves at high speed without causing image distortion in a conventional CMOS image sensor.
  • each pixel block 12 is provided with a common reset transistor Tr and a common amplification transistor Tr outside the pixel block 12, the pixel block 12
  • Each pixel 11 of the lock 12 only needs to include one photodiode and one gate element (MOS transistor). Therefore, a higher pixel aperture ratio can be realized compared to a conventional CMOS image sensor that includes three or four MOS transistors in addition to a photodiode in one pixel.
  • MOS transistor gate element
  • n output signal forces of n photodiodes PD to PD forces that have been amplified are directed to the column signal line 37 in parallel via the corresponding n select transistors Tr to Tr.
  • FIG. 5 is a circuit diagram showing a configuration of a sensor circuit 1C according to the fourth embodiment of the present invention. Since the entire configuration of the addressing type image sensor using the sensor circuit 1C is the same as that shown in FIG. 1, its description is omitted.
  • This sensor circuit 1C is the first of the present invention. It corresponds to the sensor circuit from the viewpoint of 1.
  • the circuit configuration of the sensor circuit 1C shown in FIG. 5 is substantially the same as the circuit configuration of the sensor circuit 1B according to the third embodiment (see FIG. 4), and the amplification provided for each pixel block 12 N selection transistors Tr to Tr (second gate element) on the output side of the transistor Tr
  • AMP SEL1 SELn are connected in parallel, and n transistors are connected to the output side of the selection transistors Tr to Tr.
  • the storage capacitor elements C to C include n photodiodes amplified by the amplification transistor Tr.
  • the other terminal is connected to a terminal or region having a predetermined potential (usually ground potential).
  • the stored signal is sent in parallel to the corresponding column signal line 37, and the source and drain regions on the output side are connected to the output terminal (column signal line 37) of the pixel block 12. Has been.
  • the output transistors Tr to Tr are marked on their gate electrodes.
  • the conduction state is established by setting the logic state of the applied output control signal ⁇ to ⁇ ⁇ to ⁇
  • the output transistors Tr to Tr are different from the open / close states of the transfer gates TG to TG in the pixel block 12.
  • n output signals from the n photodiodes PD to PD in the corresponding pixel block 12 are amplified by the transistor Tr. Immediately after being amplified, the signals are output in parallel toward the column signal line 37.
  • the output signals from the n photodiodes PD to PD in the pixel block 12 are amplified transistors Tr.
  • the transfer gates for reading the signals can be output in parallel toward the column signal line 37 at different timings from the opening and closing of the transfer gates TG to TG.
  • the signal charges for all the pixels 11 are substantially simultaneously accumulated (substantially) for the same reason as in the first embodiment. Simultaneous simultaneous shots).
  • simultaneous shirt tying is possible in this manner, it is possible to image a subject that moves at a high speed that causes image distortion in a conventional CMOS image sensor.
  • each pixel block 12 is provided with a common reset transistor Tr and a common amplification transistor Tr outside the pixel block 12, the pixel block 12
  • Each pixel 11 in the gate 12 only needs to include one photodiode and one gate element (MOS transistor). Therefore, a higher pixel opening ratio can be realized as compared with a conventional CMOS image sensor that includes three or four MOS transistors in addition to a photodiode in one pixel.
  • MOS transistor gate element
  • transfer gates in the pixel block 12 are controlled by the output control signals ⁇ to ⁇ .
  • the signal can be output to the column signal line 37 at a different timing from the opening / closing of TG to TG, it is possible to take an image at a higher speed than when the sensor circuit 1B of the third embodiment is used. is there.
  • FIG. 6 is a circuit diagram showing the circuit configuration of the main part of the addressing type image sensor 2 according to the fifth embodiment of the present invention
  • FIG. 8 is a cross-sectional view of the main part showing the actual structure of the image sensor 2. It is.
  • This image sensor 2 uses the sensor circuit 1B of the third embodiment described above (see FIG. 4).
  • the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 are stacked to form a two-stage three-dimensional stack. It is structured.
  • This image sensor 2 corresponds to the image sensor according to the third aspect of the present invention.
  • the image sensor 2 includes an upper semiconductor circuit layer 21 and a lower semiconductor circuit layer 22, embedded wiring 23, fine bump electrodes (for example, indium (In) and gold ( Au) laminate, or tungsten (W), etc.) 90 and an electrically insulating adhesive (eg, polyimide) 91, and mechanically and electrically connected.
  • fine bump electrodes for example, indium (In) and gold ( Au) laminate, or tungsten (W), etc.
  • an electrically insulating adhesive eg, polyimide
  • the upper semiconductor circuit layer 21 includes (k X n) X m photodiodes (that is, (k X m) sets of photodiode groups PD to PD) and (k X n) X m transfer gates. (That is, (k X m) sets of transfer gate groups TG to TG).
  • (k ⁇ m) embedded wirings 23 are further formed.
  • the lower semiconductor circuit layer 22 includes (k X m) reset transistors Tr and (k X m)
  • a selection transistor group Tr-Tr) is formed!
  • the element isolation insulating film 41 is formed in a predetermined pattern on the surface region of the p-type single crystal silicon (Si) substrate 40, so that the layout of FIG. 1 is obtained.
  • element regions for (k X n) X m pixels 11 are formed in a matrix. Yes. Each of these element regions corresponds to one pixel 11. Since all the pixel blocks 12 have the same configuration, only one pixel block 12 (i, j) will be described here.
  • n photodiodes PD to PD and n transfer gates TG to TG are formed.
  • the photodiode PD is composed of an n + type region 42 formed on the p-type substrate 40 (that is, the photodiode PD is a p-n junction photodiode).
  • the transfer gate TG is formed of a MOS transistor including a gate electrode 44 and an n + type region 43 facing the n + type region 42 with the gate electrode 44 interposed therebetween.
  • the transfer gate TG shares the n + type region 42 of the photodiode PD, one source / drain region force of the transfer gate TG is electrically connected to the anode of the photodiode PD.
  • the gate insulating film existing between the gate electrode 44 and the surface of the substrate 40 is omitted in FIG. (Since the existence of the gate insulating film between the gate electrode 44 and the surface of the substrate 40 is self-explanatory, the description of the gate insulating film is omitted in the following description as well.)
  • the gate electrode 44 is formed on the surface of the substrate 40.
  • the wiring structure 47 is electrically connected to the corresponding read control line 32 via the wiring.
  • the wiring structure 47 includes a wiring conductor formed on the surface of the substrate 40 and an insulator including the conductor, and does not include a gate insulating film and a gate electrode existing on the surface of the substrate 40. (This also applies to the following embodiments.) Other photodiodes PD to PD and transfer gates TG to TG
  • n n + -type regions 43 of the transfer gates TG to TG are electrically connected to the wiring film 46.
  • the conductive contact plug 45 is formed inside the wiring structure 47. Since the n transfer gates TG to TG in the pixel block 12 (i, j) are electrically connected to the wiring film 46 by the contact plugs 45, the transfer gates TG to TG are common nodes. 13 is connected in parallel.
  • the element isolation insulating film 41 and the substrate 40 are arranged in the up and down direction so as to overlap with the element isolation insulating film 41 adjacent to the n + type regions (source and drain regions) 43 of the transfer gates TG to TG.
  • (K X m) through-holes are formed (in a direction perpendicular to the main surface of the substrate 40). ing.
  • the entire inner wall of the portion of the through hole that contacts the Si portion of the substrate 40 is covered with an insulating film 24.
  • the inside of the through hole (the inside of the insulating film 24 and the inside of the element isolation insulating film 41) is filled with a conductive material such as polysilicon, and the conductive material forms the embedded wiring 23.
  • the upper end of the embedded wiring 23 also exposes the surface force of the substrate 40 (element isolation insulating film 41), and is connected to the lower end of the conductive contact plug 23a formed inside the wiring structure 47.
  • the upper end of the conductive contact plug 23 a is connected to a wiring film 46 formed inside the wiring structure 47. Therefore, the embedded wiring 23 is electrically connected to the corresponding wiring film 46 through the conductive contact plug 23a.
  • the n + type regions (source and drain regions) 43 of the n transfer gates TG to TG of the pixel block 12 (i, j) are correspondingly embedded as in the circuit configuration shown in FIG.
  • the wiring 23 is electrically connected in common.
  • the back surface force of the substrate 40 is also exposed, and mechanically and electrically connected to the corresponding bump electrode 90 across the lower end!
  • an element isolation insulating film 61 is formed in a predetermined pattern on the surface region of the p-type single crystal Si substrate 60, whereby a predetermined number of elements for the reset transistor T r are formed. Region, element region for a predetermined number of amplification transistors Tr, and a predetermined number of elements.
  • Element regions for the select transistors Tr to Tr are formed.
  • the reset transistor Tr includes a gate electrode 63 and the gate electrode 63.
  • n + -type regions (source and drain regions) 62 formed on both sides of the MOS transistor.
  • the gate electrode 63 is electrically connected to the corresponding reset line 31 via the wiring in the wiring structure 74 formed on the surface of the substrate 60.
  • the wiring structure 74 includes a wiring conductor formed on the surface of the substrate 60 and an insulating body that includes the wiring conductor, and does not include a gate insulating film and a gate electrode existing on the surface of the substrate 60 (this).
  • One n + type region 62 (source / drain region) has a corresponding bump through the conductive contact plug 68, the wiring film 72, the conductive contact plug 74a, and the wiring film 75 formed in the wiring structure 74. Electrically connected to electrode 90.
  • one source 'drain region of the reset transistor Tr corresponds to the corresponding one.
  • the reset voltage V is applied to the other n + type region 62 (source / drain region) via a wiring (not shown).
  • the amplification transistor Tr is formed on both sides of the gate electrode 65 with the gate electrode 65 interposed therebetween.
  • a MOS transistor force including a pair of n + type regions (source / drain regions) 64 is also formed.
  • the gate electrode 65 is electrically connected to the corresponding bump electrode 90 through the conductive contact plug 71, the wiring film 72, the conductive contact plug 74a, and the wiring film 75 formed inside the wiring structure 74. Yes.
  • n + type region 64 is electrically connected to the wiring film 73 formed in the wiring structure 74 through the conductive contact plug 69 formed in the wiring structure 74. It is connected to the.
  • the power supply voltage V is applied to the other n + type region 64 (source / drain region) via a wiring (not shown).
  • Each of the n selection transistors Tr 1 to Tr 4 includes a gate electrode 67 and a gate electrode 6
  • a MOS transistor force including a pair of n + -type regions (source and drain regions) 66 formed on both sides of 7 is also formed.
  • One n + type region (source / drain region) 66 is connected to one of the corresponding amplifying transistors Tr via the conductive contact plug 70, the wiring film 73, and the conductive contact plug 69 formed in the wiring structure 74.
  • Drain region 64 is electrically connected!
  • the other n + type region (source / drain region) 66 is connected to the corresponding output terminal of the image sensor 2.
  • the gate electrode 67 is electrically connected to the output selection line 39 via a wiring formed inside the wiring structure 74. The corresponding output selection is applied to the gate electrode 67 of the selection transistors Tr to Tr.
  • Predetermined output selection signals ⁇ to ⁇ are applied via selection lines 39, respectively.
  • n + regions (source and drain regions) 66 are formed in parallel at a predetermined distance, and the central n + region 66 is shared by the two selection transistors Tr and Tr. is doing. And shared
  • SELl SEL2 N-type region 66 is electrically connected to one n-type region 64 of the corresponding amplification transistor Tr.
  • Each non-shared n + region 66 is connected to the corresponding output terminal.
  • the image sensor 2 according to the fifth embodiment shown in FIGS. 6 and 8 is an application of the sensor circuit 1B of the third embodiment shown in FIG. (k X m) pixel blocks 12 (each block 12 includes n pixels 11) and (k X m) embedded wirings 23 are formed in the upper semiconductor circuit layer 21, and ( (k X m) reset transistors Tr, (k X m) amplifier transistors Tr, and (k X m) selected transistor groups Tr
  • ⁇ Tr is formed in the lower semiconductor layer 22 and further, the embedded wiring 23 and the bump electrode 90
  • the pixel block 12 in the upper semiconductor circuit layer 21 is electrically connected to the corresponding reset transistor Tr and amplification transistor Tr in the lower semiconductor circuit layer 22 via
  • the upper main surface of the lower semiconductor circuit layer 22 (the surface of the wiring structure 74) is formed below the upper main surface of the upper semiconductor circuit layer 21 (the back surface of the substrate 40) by the bump electrode 90 and the adhesive 91. Since both are electrically and mechanically connected to each other, the circuit layers 21 and 22 form a two-stage semiconductor laminated structure (three-dimensional structure).
  • the signal charges for all the pixels 11 are substantially simultaneously accumulated (substantially simultaneous shirt tie). It is possible to image a subject that moves at a high speed that causes image distortion in a conventional CMOS image sensor.
  • each pixel 11 of the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor). Compared to a conventional CMOS image sensor including three or four MOS transistors, it can achieve a high pixel aperture ratio (eg, about 60%) and can reduce the size of the pixel 11 itself. It becomes possible.
  • MOS transistor gate element
  • FIG. 7 is a circuit diagram showing the circuit configuration of the main part of the addressing type image sensor 2A according to the sixth embodiment of the present invention
  • FIG. 9 is a cross-sectional view of the main part showing the actual structure of the image sensor 2A.
  • FIG. This image sensor 2A uses the sensor circuit 1C of the fourth embodiment described above (see FIG. 5).
  • the upper semiconductor circuit layer 21 and the lower semiconductor circuit layer 22 ′ are stacked to form a two-stage three-dimensional stack. It is structured.
  • This image sensor 2A corresponds to the image sensor according to the third aspect of the present invention.
  • FIG. 7 corresponds to the sensor circuit 1C of the fourth embodiment shown in FIG. 5 (n selected transistors at the output terminal of each amplification transistor Tr).
  • Transistors Tr to Tr are connected, and the output side of these selection transistors Tr to Tr
  • SEL1 SELn SEL1 SELn is connected to storage capacitors C to C and output transistors Tr to Tr, respectively.
  • the embedded wiring 23 and the parasitic resistance R and the parasitic capacitances C and C generated by the embedded wiring 23 are additionally shown in FIG.
  • One embedded wiring 23 is provided for each pixel block 12 (that is, n pixels 11).
  • the image sensor 2A includes the upper semiconductor circuit layer 21 and the lower semiconductor.
  • the circuit layer 22 ' is mechanically and electrically connected using the embedded wiring 23, the fine bump electrode 90, and an electrically insulating adhesive (for example, polyimide) 91. .
  • the upper semiconductor circuit layer 21 has the same configuration as that of the image sensor 2 (see FIG. 8) of the fifth embodiment described above. & 111) 12 pixel blocks & 11) Xm pixels 11 and (k X m) embedded wirings 23 are formed. Since the internal configuration of the upper semiconductor circuit layer 21 is the same as that of the image sensor 2 of the fifth embodiment described above, the same reference numerals as those in the case of the fifth embodiment are given and detailed description thereof is omitted.
  • the lower semiconductor circuit layer 22 has substantially the same configuration as the lower semiconductor circuit layer 22 of the image sensor 2 (see Fig. 8) of the fifth embodiment described above, but outputs the storage capacitors C to C and outputs.
  • transistors Tr to Tr are additionally formed. Ie, below
  • ⁇ Tr is additionally formed.
  • the element isolation insulating film 61 is formed in a predetermined pattern in the surface region of the p-type single crystal Si substrate 60, thereby Element regions for a number of reset transistors Tr and a number of elements for amplifying transistors Tr
  • Element regions for SEL1 SELn ST1 STn and output transistors Tr to Tr are formed. Here is one
  • the MOS transistor force including a gate electrode 63 and a pair of n + type regions (source / drain regions) 62 formed on both sides of the gate electrode 63 is also configured.
  • the electrical connection of the reset transistor Tr is also the image sensor of the fifth embodiment.
  • the configuration of the amplification transistor Tr is the same as that of the image sensor 2 of the fifth embodiment described above (see Fig. 8).
  • the MOS transistor force including the gate electrode 65 and a pair of n + type regions (source / drain regions) 64 formed on both sides of the gate electrode 65 is also configured. It is.
  • the electrical connection of the amplification transistor Tr is also the same as that of the image sensor 2 (
  • each of the n selection transistors Tr to Tr is the same as that of the fifth embodiment described above.
  • the MOS transistor stacker includes a gate electrode 67 and a pair of n + type regions (source and drain regions) 66 formed on both sides of the gate electrode 67. It is configured. A storage capacitor and an output transistor are connected to the MOS transistor so as to have a circuit configuration as shown in FIG.
  • (Region) 66 is one n + type region (source drain) of the corresponding amplifying transistor Tr via the conductive contact plugs 70 and 69 formed in the wiring structure 74 and the wiring film 73.
  • the gate electrode 67 is electrically connected to the output selection line 39 via a wiring formed inside the wiring structure 74, and the output selection signal ⁇
  • n + region 6 constitutes a MOS capacitor that functions as a storage capacitor C together with an n + -type region 66a formed on the opposite side of the gate electrode 67a. This n + region 6
  • 6a is a MOS transistor that functions as an output transistor Tr together with a gate electrode 67b and an n + region 66a formed on the opposite side of the gate electrode 67b from the n + region 66a.
  • the gate electrode 67a is at the end of a predetermined potential (usually the power supply voltage V).
  • the gate electrode 67b is electrically connected to the output control line 39a via a wiring (not shown), and the output control signal ⁇ is applied.
  • Block 12 (each including 11 pixels), (k X m) pairs of transfer gates TG to TG) and (k X m) embedded wirings 23 are formed in the upper semiconductor circuit layer 21
  • RST AMP Storage Capacitor Groups C to C and (kX m) Sets of Transistor Groups Tr to Tr and (kX m) Sets
  • Output transistor groups Tr to Tr are formed in the lower semiconductor layer 22 ′ and further embedded.
  • the pixel block 12 in the upper semiconductor circuit layer 21 and the reset transistor Tr and amplification transistor Tr in the lower semiconductor circuit layer 22 ′ are connected.
  • the main surface above the lower semiconductor circuit layer 22 ' (the surface of the wiring structure 74) is formed on the main surface below the upper semiconductor circuit layer 21 (the back surface of the substrate 40) by the bump electrode 90 and the adhesive 91. ) Are electrically and mechanically connected to each other, so that both circuit layers 21 and 22 'constitute a two-stage semiconductor laminated structure (three-dimensional structure).
  • each pixel 11 in the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor), three to four pixels are arranged in one pixel.
  • MOS transistor gate element
  • output transistors Tr to Tr are controlled by output control signals ⁇ to ⁇ .
  • the transfer gates TG to TG and the selection transistor groups T r to Tr in the pixel block 12 can be output to the column signal line 37 at different timings.
  • FIG. 10 shows the main part of the addressing type image sensor 2B according to the seventh embodiment of the invention.
  • FIG. 11 is a circuit diagram showing a circuit configuration, and FIG. 11 is a cross-sectional view of a principal part showing an actual structure of the image sensor 2B.
  • This image sensor 2B uses the sensor circuit 1C of the fourth embodiment (see FIG. 5).
  • the upper semiconductor circuit layer 21A and the lower semiconductor circuit layer 22A ′ are stacked to form a two-dimensional three-dimensional image sensor 2B. It is a laminated structure.
  • the image sensor 2B corresponds to the image sensor according to the third aspect of the present invention.
  • the overall configuration and operation of the image sensor 2B are the same as those shown in FIG. Therefore, the description regarding them is omitted.
  • the circuit configuration shown in FIG. 10 is the same as the sensor circuit 1C of the fourth embodiment in FIG. 5 except that the embedded wiring 23 is added. The description is omitted.
  • the image sensor 2B includes an upper semiconductor circuit layer 21A and a lower semiconductor circuit layer 22A ′, an embedded wiring 23, a fine bump electrode 90, and an electrically insulating material. It is configured to be mechanically and electrically connected using an adhesive 91.
  • the configuration is that the image sensor 2A of the sixth embodiment (see FIGS. 7 and 9) is formed in the lower semiconductor circuit layer 22 ′, and (k X m) reset transistors Tr are connected to the upper semiconductor circuit layer 21. inside
  • the upper semiconductor circuit layer 21A includes (k X n) X m photodiodes (that is, (k X m) photodiode groups PD to PD) and (k X n) X m photodiodes.
  • Transfer gates that is, (k X m) pairs of transfer gates TG to TG
  • (k X m) reset transistors Tr and (k X m) embedded wirings 23 are formed.
  • the reset transistor Tr includes the gate electrode 49 and the gate electrode 4
  • a MOS transistor force including a pair of n + type regions (source / drain regions) 48 formed on both sides of 9 is also formed.
  • the gate electrode 49 is electrically connected to the corresponding reset line 31 via the wiring in the wiring structure 47 formed on the surface of the substrate 40.
  • One n + type region 48 (source and drain region) is supported by the conductive contact plug 50, the wiring film 46, the conductive contact plug 23a, and the embedded wiring 23 formed in the wiring structure 47.
  • the bump electrode 90 is electrically connected.
  • the source “drain region” of the reset transistor Tr corresponds to the corresponding amplification transistor of the lower semiconductor circuit layer 22A. It is electrically connected to the gate electrode 65 of the transistor Tr.
  • the lower semiconductor circuit layer 22A includes (k X m) amplifier transistors Tr and (k X m) pairs.
  • the image sensor 2B according to the seventh embodiment shown in FIGS. 10 and 11 is an application of the sensor circuit 1C (see FIG. 5) of the fourth embodiment.
  • (k X m) pixel blocks 12 each block 12 includes n pixels 11
  • the embedded wiring 23 is formed in the upper semiconductor circuit layer 21A, and (k X m) amplification transistors Tr and (k X m) sets of selection transistor groups Tr to Tr and (k X m) sets are used for storage. Yong
  • the reset transistor Tr in the upper semiconductor circuit layer 21 and the amplification transistor in the lower semiconductor circuit layer 22A ′ are formed in the body layer 22A ′ and further passed through the embedded wiring 23 and the bump electrode 90.
  • both circuit layers 21A and 22A constitute a two-stage semiconductor multilayer structure (three-dimensional structure).
  • each pixel 11 in the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor), three to four pixels can be arranged in one pixel.
  • MOS transistor gate element
  • output transistors Tr to Tr are controlled by output control signals ⁇ to ⁇ .
  • the transfer gates TG to TG and the selection transistor groups T r to Tr in the pixel block 12 can be output to the column signal line 37 at different timings.
  • FIG. 12 is a cross-sectional view of the main part showing the actual structure of the addressing type image sensor 2C according to the eighth embodiment of the present invention.
  • This image sensor 2C is the same as the output of the storage capacitors C to C in the image sensor 2B of the seventh embodiment described above (see FIGS. 10 and 11).
  • the image sensor 2C includes an upper semiconductor circuit layer 21A and a lower semiconductor circuit layer 22A, an embedded wiring 23, a fine bump electrode 90, and an electrical isolation. It is configured to be mechanically and electrically connected using an edge adhesive 91.
  • the configuration of the upper semiconductor circuit layer 21A is the same as that of the image sensor 2B of the seventh embodiment.
  • the configuration of the lower semiconductor circuit layer 22A is such that the memory capacitors C to C and the output transistors Tr to Tr are deleted from the lower semiconductor circuit layer 22A ′ of the image sensor 2B of the seventh embodiment.
  • the signal charges of all the pixels 11 are reduced for the same reason as described in the image sensor 2B of the seventh embodiment.
  • Substantially simultaneous storage substantially simultaneous shirting is possible, and a moving subject can be imaged at high speed without causing image distortion in a conventional CMOS image sensor.
  • each pixel 11 in the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor), three to four pixels can be arranged in one pixel.
  • MOS transistor gate element
  • a high pixel aperture ratio for example, about 60%
  • the size of the pixel 11 itself can be reduced.
  • FIG. 13 is a circuit diagram showing the circuit configuration of the main part of the addressing type image sensor 2D according to the ninth embodiment of the present invention
  • FIG. 14 is a cross-sectional view of the main part showing the actual structure of the image sensor 2D.
  • This image sensor 2D uses the sensor circuit 1C of the fourth embodiment (see FIG. 5).
  • the upper semiconductor circuit layer 21B and the lower semiconductor circuit layer 22B ′ are stacked to form a two-stage three-dimensional stack. It is structured.
  • the image sensor 2B corresponds to the image sensor according to the third aspect of the present invention.
  • the image sensor 2D includes an upper semiconductor circuit layer 21B and a lower semiconductor circuit layer 22B ′, an embedded wiring 23, a fine bump electrode 90, and an electrically insulating material. It is configured to be mechanically and electrically connected using an adhesive 91.
  • the configuration is such that (k X m) amplifying transistors Tr formed in the lower semiconductor circuit layer 22A ′ in the image sensor 2B of the seventh embodiment (see FIGS. 10 and 11) are connected to the upper semiconductor circuit.
  • the upper semiconductor circuit layer 21B has (k X n) X m photodiodes (ie, That is, (k X m) sets of photodiode groups PD to PD), (k X n) X m transfer gates (that is, (k X m) sets of transfer gate groups TG to TG), (K X m) reset transistors Tr, (k X m) amplifier transistors Tr, and (k X m) embedded wirings 23
  • the configuration of the photodiodes PD to PD, transfer gates TG to TG, and reset transistor Tr is the same as that of the image sensor 2B of the seventh embodiment.
  • the amplification transistor Tr includes a gate electrode 53 and a gate electrode 53.
  • n + -type regions (source and drain regions) 52 formed on both sides of the MOS transistor.
  • the gate electrode 53 is connected to the reset transistor Tr and the transformer via the conductive contact plug 54 and the wiring film 46 formed in the wiring structure 47.
  • n + type region 52 (source / drain region) is supported through the conductive contact plug 55, the wiring film 56, the conductive contact plug 23a, and the buried wiring 23 formed in the wiring structure 47.
  • the bump electrode 90 is electrically connected. As a result, the source / drain region of the amplification transistor Tr
  • Area corresponds to the corresponding selection transistor Tr in the lower semiconductor circuit layer 22B ′.
  • the lower semiconductor circuit layer 22B includes (k X m) sets of select transistor groups Tr T
  • ⁇ Tr is formed. This configuration is the same as that of the seventh embodiment (see FIGS. 10 and 11).
  • OUT1 to Tr are the same as in the seventh embodiment.
  • the image sensor 2D according to the ninth embodiment shown in FIGS. 13 and 14 is an application of the sensor circuit 1C (see FIG. 5) of the fourth embodiment, ( k x m) pixel blocks 12 (each block 12 contains n pixels 11) and (k X m) Sfagate group TG to TG) and (k X m) reset transistors Tr
  • the amplification transistor Tr in the upper semiconductor circuit layer 21B and the selection transistor in the lower semiconductor circuit layer 22B ′ are formed in the body layer 22B ′ through the embedded wiring 23 and the bump electrode 90.
  • Transistors Tr to Tr are electrically interconnected.
  • the upper main surface (the surface of the wiring structure 74) of the lower semiconductor circuit layer 22B ' is formed on the lower main surface (the back surface of the substrate 40) by the bump electrode 90 and the adhesive 91.
  • the circuit layers 21B and 22B ' constitute a two-stage semiconductor multilayer structure (three-dimensional structure).
  • signal charges for all the pixels 11 can be substantially simultaneously accumulated (substantially simultaneous chattering), and a conventional CMOS can be used. An object that moves at high speed without causing image distortion in the image sensor can be captured.
  • each pixel 11 in the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor), three to four pixels can be arranged in one pixel.
  • MOS transistor gate element
  • a high pixel aperture ratio for example, about 60%
  • the size of the pixel 11 itself can be reduced.
  • output transistors Tr to Tr are controlled by output control signals ⁇ to ⁇ .
  • the transfer gates TG to TG and the selection transistor groups T r to Tr in the pixel block 12 can be output to the column signal line 37 at different timings.
  • FIG. 15 is a cross-sectional view of the principal part showing the actual structure of the addressing type image sensor 2E according to the tenth embodiment of the present invention.
  • the image sensor 2E includes storage capacitors C to C in the image sensor 2C of the ninth embodiment described above (see FIGS. 13 and 14).
  • the image sensor 2 ⁇ ⁇ ⁇ ⁇ of the tenth embodiment includes an upper semiconductor circuit layer 21B and a lower semiconductor circuit layer 22 ⁇ , embedded wiring 23, fine bump electrodes 90, and electrical insulation.
  • the adhesive 91 is used to mechanically and electrically connect.
  • the configuration of the upper semiconductor circuit layer 21B is the same as that of the image sensor 2D of the ninth embodiment.
  • the structure of the lower semiconductor circuit layer 22 ⁇ is composed of the storage capacitor elements C to C and the output transistors Tr to Tr from the lower semiconductor circuit layer 22B ′ of the image sensor 2D of the ninth embodiment.
  • the signal charges of all the pixels 11 are substantially equal. Simultaneous storage (substantially simultaneous shirting) is possible, and it is possible to image a subject moving at high speed without causing image distortion in a conventional CMOS image sensor.
  • each pixel 11 of the pixel block 12 only needs to include one photodiode and one gate element (MOS transistor), so three or four pixels can be arranged in one pixel.
  • MOS transistor gate element
  • a high pixel aperture ratio for example, about 60%
  • the size of the pixel 11 itself can be reduced.
  • FIG. 16 shows the main part of the addressing type image sensor 2F according to the eleventh embodiment of the present invention.
  • FIG. 17 is a cross-sectional view of the main part showing the actual structure of the image sensor 2F.
  • This image sensor 2F uses the sensor circuit 1C of the fourth embodiment (see FIG. 5).
  • the upper semiconductor circuit layer 21C and the lower semiconductor circuit layer 22C ′ are stacked to form a two-stage three-dimensional stack. It is structured.
  • the image sensor 2F corresponds to an image sensor according to the third aspect of the present invention.
  • the image sensor 2F includes an upper semiconductor circuit layer 21C and a lower semiconductor circuit layer 22C ′, an embedded wiring 23, a fine bump electrode 90, and an electrically insulating layer. It is configured to be mechanically and electrically connected using an adhesive 91.
  • the configuration is such that (k X m) sets of transfer gate groups TG to TG formed in the upper semiconductor circuit layer 21 in the image sensor 2A according to the sixth embodiment (see FIGS. 7 and 9), It corresponds to the one moved into the lower semiconductor circuit layer 22 ′.
  • the upper semiconductor circuit layer 21C includes (k X n) X m photodiodes (that is, (k X m) sets of photodiode groups PD to PD) and (k X m) embedded wirings. Only 23 are formed.
  • the configuration of the photodiodes PD to PD is almost the same as that of the image sensor 2A of the sixth embodiment (see Figs. 7 and 9), but one photodiode is provided in each element region of the substrate 40. Is different.
  • an n + region 42 is formed over the entire surface of one of a plurality of element regions formed on the surface region of the p-type substrate 40 by the element isolation insulating film 41.
  • the n + region 42 forms the photodiode PD.
  • a through-hole penetrating the element isolation insulating film 41 and the substrate 40 in the vertical direction (in a direction perpendicular to the main surface of the substrate 40) is formed at an appropriate position overlapping the element isolation insulating film 41.
  • the entire inner wall of the through hole in contact with the substrate 40 is covered with an insulating film 24.
  • the inside of the through hole (the inside of the insulating film 24 and the inside of the element isolation insulating film 41) is filled with a conductive material, and the conductive material forms the embedded wiring 23.
  • the upper end of the embedded wiring 23 is exposed from the surface of the substrate 40 (element isolation insulating film 41) and is connected to the lower surface of the wiring film 57 formed inside the wiring structure 47. Has been.
  • the n + region 42 is electrically connected to the embedded wiring 23.
  • the lower end of the embedded wiring 23 is exposed from the back surface of the substrate 40 (element isolation insulating film 41) and is mechanically and electrically connected to the corresponding bump electrode 90 !.
  • the lower semiconductor circuit layer 22C includes (k X m) sets of transfer gate groups TG to TG, and (k
  • the quantum elements C to C and the output transistors Tr to Tr are the same as those in the sixth embodiment.
  • the transfer gates TG to TG have the following configuration.
  • a MOS transistor including a gate electrode 77 and a pair of n + type regions (source and drain regions) 76 formed on both sides of the gate electrode 77 is sandwiched. Jistaka et al.
  • a transfer gate control signal ⁇ is applied to the gate electrode 77 via a wiring (not shown).
  • the conductive bumps 90 are electrically connected to the corresponding bump electrodes 90 through the conductive contact plugs 78, 80 and 82 formed in the line structure 74 and the wiring films 79, 81 and 83.
  • the source / drain region of the transfer gate TG is electrically connected to the corresponding photodiode PD of the upper semiconductor circuit layer 21 C through the buried wiring 23.
  • the other n + type region 76 (source / drain region) of the MOS transistor is amplified with the corresponding reset transistor Tr via a conductive contact plug 78 formed inside the wiring structure 74 and a wiring film (not shown). It is electrically connected to the transistor Tr.
  • the transfer gates TG to TG have the same structure as the transfer gate TG. This
  • the transfer gates TG to TG in the lower semiconductor circuit layer 22C ′ are electrically connected to the photodiodes PD to PD in the upper semiconductor circuit layer 21C through the embedded wiring 23, respectively.
  • the image sensor 2F according to the eleventh embodiment shown in FIGS. 16 and 17 is an application of the sensor circuit 1C (see FIG. 5) of the fourth embodiment.
  • (K X m) pixel blocks 12 each block 12 includes n pixels 11) and (k X m) embedded wirings 23 are formed in the upper semiconductor circuit layer 21C, and (k X m) thread gate transfer gate group TG to TG), (k X m) reset transistors Tr and (k X m) amplification transistors
  • both circuit layers 21C and 22C constitute a two-stage semiconductor multilayer structure (three-dimensional structure).
  • signal charges for all the pixels 11 can be substantially simultaneously accumulated (substantially simultaneous chattering), and a conventional CMOS can be used. An object that moves at high speed without causing image distortion in the image sensor can be captured.
  • each pixel 11 of the pixel block 12 includes only one photodiode, so that one pixel includes three or four MOS transistors in addition to the photodiode, compared to a conventional CMOS image sensor. Therefore, a high pixel aperture ratio (for example, about 60%) can be realized, and the size of the pixel 11 itself can be reduced. In particular, it can be made smaller than in the case of the fifth to tenth embodiments.
  • the total area of the light receiving region (opening portion of each photodiode) with respect to the total area of the imaging region on the surface of the upper semiconductor circuit layer 21C It is possible to increase the ratio of. In particular, it can be made higher than in the case of the fifth to tenth embodiments.
  • output transistors Tr to Tr are controlled by output control signals ⁇ to ⁇ .
  • the transfer gates TG to TG and the selection transistor groups T r to Tr in the pixel block 12 can be output to the column signal line 37 at different timings.
  • FIG. 18 is a cross-sectional view of the principal part showing the actual structure of the addressing type image sensor 2G according to the twelfth embodiment of the present invention.
  • This image sensor 2G is the same as the image sensor 2F of the eleventh embodiment described above (see FIGS. 16 and 17), with the lower semiconductor circuit layer 22C ′ being left as it is, and the substrate 40 in the upper semiconductor circuit layer 21C being turned upside down. Corresponds to the orientation.
  • This image sensor 2G corresponds to the addressing type image sensor according to the third aspect of the present invention.
  • the image sensor 2G includes an upper semiconductor circuit layer 21D and a lower semiconductor circuit layer 22D ′, a fine bump electrode 90, and an electrically insulating adhesive. 91 and mechanically and electrically connected.
  • the configuration of the lower semiconductor circuit layer 21 D ′ is the same as that of the lower semiconductor circuit layer 21 C ′ of the image sensor 2F of the eleventh embodiment.
  • the embedded wiring 23 is not used.
  • the substrate 40 is turned upside down with respect to the upper semiconductor circuit layer 21C of the image sensor 2F of the eleventh embodiment, the wiring structure 47 is on the lower side, and the substrate 40 is on the upper side. Is located. Since external light passes through the substrate 40 and is irradiated to the photodiodes PD to PD, the thickness of the substrate 40 is made thinner than in the case of the image sensor 2F of the eleventh embodiment.
  • conductive contact plugs 58 electrically and mechanically connected to the respective surfaces of the plurality of n + type regions 42 constituting the photodiodes PD to PD, and those A plurality of wiring films 59 that are electrically and mechanically connected to the conductive contact plug 58 are formed. These wiring films 59 are disposed in the vicinity of the surface of the wiring structure 47 and are electrically and mechanically connected to the corresponding bump electrodes 90. In this way, the photodiodes PD to PD correspond to the corresponding bump electrodes.
  • the corresponding transfer gates TGi and TGj in the lower semiconductor circuit layer 22D ′ are electrically connected through 90.
  • FIG. 20 is a diagram showing a main circuit configuration of the sensor circuit 3 according to the thirteenth embodiment of the present invention.
  • FIG. 19 is a functional block diagram showing the overall configuration of an addressing type image sensor in which the sensor circuit 3 is used. This sensor circuit 3 corresponds to the sensor circuit according to the second aspect of the present invention.
  • the overall configuration of the image sensor of FIG. 19 is the addressing type image sensor shown in FIG. 1 except that each reset line 31 is provided through k pixel blocks 12a belonging to the same column. Is identical to that of That is, (k X n) X m pixels 11a arranged in a matrix of (k X n) rows and m columns are provided. In each pixel block 12a, n pixels 11a belonging to the same column are grouped and connected in parallel to a common node (not shown in FIG. 19, corresponding to the common node 13a in FIG. 20).
  • each pixel block 12a m reset lines 31 each extending along a corresponding column of the pixel matrix are formed so as to penetrate through the pixel block 12a belonging to the column.
  • Each reset line 31 is connected to one reset transistor for each pixel 11a.
  • the n transistors 11a belonging to the pixel block 12a are connected to the reset transistor Tr.
  • the amplification transistor T is connected to each pixel block 12a.
  • n reset transistor groups T to Tr are the corresponding pixels
  • An amplifying transistor T is arranged in each of the n pixels 11a in the block 12a.
  • Each reset line 31 is used to reset the signal charge of the pixel 1la in the k pixel blocks 12a belonging to the corresponding column.
  • the application is performed using the corresponding reset transistors T to Tr. Each amplification run
  • the register T increases the signal read from the pixel l la in the corresponding pixel block 12a.
  • AMP Width is used to send to the corresponding column signal line 37.
  • the signals amplified in (1) are sent to the corresponding column signal lines 37 in order.
  • FIG. 20 shows a circuit configuration of two pixel blocks 12a (i, j) and 12a (i + 1, j) belonging to the j-th column.
  • the upper pixel block 12 (i, j) includes pixels 11 belonging to the [ n x (i ⁇ 1) +1] row to the (n X i) row of the j-th column.
  • the lower pixel block 12 (i + 1, j) includes pixels 11 belonging to the [n X i + 1] row to the [n X (i + 1)] row of the j th column. Since these two pixel blocks 12 (i, j) and 12 (i + 1, j) have the same configuration, in the following description, the upper pixel block 12 (i, j) will be mainly described.
  • the pixel block 12a (i, j) includes n pixels 11a.
  • n photodiodes PD to PD, n transfer gates TG to TG, and n reset transistors Tr to Tr are included.
  • Each pixel 11a has one photo diode
  • Each of the transfer gates TG to TG is composed of a MOS transistor. Reset transistor Tr
  • Each of .about.Tr is also composed of MOS transistors.
  • Each anode of D is one source of the corresponding one of the transfer gates TG to TG 'the drain region and one source of the corresponding one of the reset transistors Tr to Tr'
  • the force sword is connected in common to a terminal or region having a predetermined potential (usually ground potential).
  • Reset transistor T to Tr
  • the common node 13a of the pixel block 12a (i, j) is the gate of the corresponding amplification transistor T.
  • the amplification transistor T is provided outside the pixel block 12a (i, j).
  • AMP I was kicked.
  • One source / drain region of the amplification transistor T is connected to a DC power source (electrical
  • Source voltage v
  • drain region output side
  • the source-drain region on the output side of the amplification transistor T is connected to the corresponding column signal line 37.
  • the serial (time-series) output signals of the photodiodes PD to PD are sequentially sent to the corresponding CDS circuit 36. Then, when sent from the CDS circuit 36 to the horizontal signal line 33, the column signal line 37 is selected via the m column selection signals 38 by the scanning of the horizontal scanning circuit 35, whereby the serial output signal is Sent to horizontal signal line 33. Thereafter, the signal is sent to an output terminal (not shown) of the image sensor provided at one end (right end in FIG. 19) of the horizontal signal line 33.
  • All the pixel blocks 12a other than the pixel block 12a (i, j) have the same configuration as the pixel block 12a (i, j).
  • the serial output signals of the photodiodes PD to PD are sent to the output terminal of the image sensor. Thus, the subject can be imaged.
  • Transfer gates TG to TG are turned on.
  • the logic state of ⁇ is set to H, and all reset transistors Tr to Tr are turned on.
  • the diodes are applied simultaneously to PD PD.
  • a batch reset of all the pixels 11a that is, a “global reset” is performed.
  • the voltage at the gate electrode is also reset.
  • the logic state of ⁇ is set to L, and all transfer gates TG to TG are turned off.
  • the transistors Tr to Tr are also shut off.
  • the photodiodes PD to PD of all the pixels 11a are irradiated with light, and signal charges are generated and accumulated in all the photodiodes PD to PD collectively.
  • the irradiation time is usually several hundred ⁇ sec to 3 ⁇ 4Cmsec.
  • RST The logic state of RST is set to H, all reset transistors Tr to Tr are turned on at once, and
  • the logic state of the gate control signals ⁇ to ⁇ is H, and all the transfer gates TG to TG are
  • the RST logic state is set to L again and all reset transistors Tr to Tr are turned off at once.
  • a signal proportional to the amount of charge generated and accumulated in all the photodiodes PD to PD as described above is read out from each pixel 11a and amplified in the form of voltage as follows.
  • n transfer gate control signals ⁇ in the pixel block 12a are selected.
  • the amplification transistor Tr connected to the node 13a in the source follower form is the gate of the amplification transistor Tr.
  • the signal read out to the node 13a is immediately amplified by the amplification transistor Tr.
  • the amplified signal is then transferred to the amplification transistor.
  • the source / drain region force on the output terminal side of the transistor Tr is output toward the column signal line 37.
  • the reset voltage V is applied to the node 1 by turning on the reset transistor Tr.
  • the total number of amplification operations by the amplification transistor Tr is n.
  • the total number of set operations is n.
  • the first transfer gate TG of the pixel block 12a is temporarily turned on, and the signal proportional to the signal charge accumulated in the first photodiode PD. To node 13a. The signal is immediately amplified by the amplification transistor Tr, and the obtained amplified signal is sent to the column signal line 37. Continued
  • the reset transistor Tr connected to this photodiode PD is temporarily turned on.
  • the reset voltage V is temporarily applied to the node 13a, so that the amplification transistor Tr
  • a signal proportional to the signal charge stored in the second photodiode PD is a signal proportional to the signal charge stored in the second photodiode PD.
  • the amplified signal is sent to the column signal line 37. Next, contact the photodiode PD.
  • n signals from which all the photodiodes PD to PD in the pixel block 12a can also be obtained are connected to the source terminal n AMP on the output terminal side of the amplification transistor Tr.
  • the rain region force is also output in sequence toward the column signal line 37 in time series.
  • the signal output from the pixel block 12a is a signal in which n pulse waveforms reflecting the amount of signal charges (the amount of irradiated light) of the photodiodes PD to PD are connected at a predetermined interval.
  • a signal output from the pixel block 12a that is, one serial signal in which n pulses are connected at a predetermined interval, is sent to a known sample 'and' hold circuit or AZD conversion circuit. Predetermined signal processing is performed.
  • RSTl RSTn AMP gate electrode reset operation required number of times (that is, n times) (total reset time) and the time from all the pixels 11a (photodiodes PD to PD) in the pixel block 12a
  • Time required to amplify the signal with the corresponding amplification transistor Tr (total amplification time) N times (total number of pixels 11a in each pixel block 12a) so that it is sufficiently smaller than the shortest signal charge accumulation period ( 125 sec) Is set, signal charge accumulation (exposure) is performed substantially simultaneously on the pixels 11a (photodiodes PD to PD) belonging to all the pixel blocks 12a.
  • the signal charges for all the pixels 11a can be accumulated substantially simultaneously (substantially simultaneous shirting).
  • each power of all pixel blocks 12a outputs (k X m) output serial signals independently, so that these output serial signals are processed by analog-digital (AZD) conversion and the like. Can be done in parallel. Therefore, data processing can be performed at a higher speed than that in the conventional CMOS image sensor. This also contributes to the realization of practical simultaneous shirting.
  • the serial output signal output from each pixel block 12a is generated at the beginning of the scanning period as the closer to the end of the scanning period, '
  • the charge accumulation period is slightly longer than the output one. For this reason, when it is desired to obtain image data with higher fidelity or to increase the n value, a known circuit that performs signal correction in accordance with the change in the charge accumulation period may be provided in the subsequent stage. This is because the influence of fluctuations in the charge accumulation period can be suppressed or avoided.
  • each pixel 11a in the pixel block 12a is assigned to one pixel block 12a.
  • a high pixel aperture ratio (for example, about 60%) can be realized as compared with a conventional CMOS image sensor that includes three or four MOS transistors in addition to a photodiode in one pixel.
  • This pixel aperture ratio includes only one photodiode and one gate element in the first embodiment. Compared to an image sensor using the sensor circuit 1 (see Fig. 1 and Fig. 2), it is lower by the reset transistor.
  • n output signal powers of n photodiodes PD to PD force are output from each of the amplification transistors Tr in a serially connected form, so that the amplification transistor Tr
  • FIG. 21 is a circuit diagram showing the circuit configuration of the main part of the addressing type image sensor 4 according to the fourteenth embodiment of the present invention
  • FIG. 23 is a cross-sectional view of the main part showing the actual structure of the image sensor 4.
  • the image sensor 4 includes an amplification transistor Tr provided for each pixel block 12a in the sensor circuit 3 (see FIG. 20) of the thirteenth embodiment described above.
  • n select transistors Tr to Tr (second gate
  • n output signals from n photodiodes PD to PD amplified are output in parallel via select transistors Tr to Tr
  • a sensor circuit is used, and the upper semiconductor circuit layer 21E and the lower semiconductor circuit layer 22E are stacked to form a two-stage three-dimensional stacked structure.
  • the image sensor 4 corresponds to the image sensor according to the fourth aspect of the present invention, and the sensor circuit used therein corresponds to the sensor circuit according to the second aspect of the present invention.
  • the overall configuration and operation of the image sensor 4 are the same as those shown in FIG. 19, and a description thereof will be omitted.
  • the circuit configuration of FIG. 21 is obtained by adding n selection transistors Tr to Tr (second gate elements) to the sensor circuit 3 of the thirteenth embodiment of FIG.
  • each pixel block 12a formed in the semiconductor circuit layer 21E is electrically connected to the gate electrode of the amplification transistor Tr formed in the lower semiconductor circuit layer 22E.
  • the One embedded wiring 23 is provided for each pixel block 12a (ie, n pixels 11a).
  • the image sensor 4 includes an upper semiconductor circuit layer 21E and a lower semiconductor circuit layer 22E, embedded wiring 23, fine bump electrodes 90, and an electrically insulating adhesive. 91, and mechanically and electrically connected.
  • the upper semiconductor circuit layer 21E includes (kXn) Xm photodiodes (that is, (kXm) photodiode groups PD to PD) and (k Xn) Xm transfer gates (that is, (kXm) groups. Transfer gate groups TG to TG) and (kXn) Xm reset transistors (that is, (kXm) sets of reset transistor groups Tr 1 to Tr 3).
  • the upper semiconductor circuit layer 21E further includes (kXn)
  • the embedded wiring 23 is formed.
  • the lower semiconductor circuit layer 22E includes (kXm) amplifying transistors Tr and (kXn) Xm
  • the element isolation insulating film 41 is formed in a predetermined pattern on the surface region of the p-type single crystal Si substrate 40, so that the layout of FIG. (KXn) Xm element regions are formed in a matrix. Each of these element regions corresponds to one pixel 11a.
  • the photodiode PD is a p-type as shown in FIG.
  • the transfer gate TG is formed of a MOS transistor including a gate electrode 44 and an n + type region 43 facing the n + type region 42 with the gate electrode 44 interposed therebetween. Since the transfer gate TG shares the n + type region 42 of the photodiode PD, it is electrically connected to the anode of the photodiode PD of one source'drain region force of the transfer gate TG.
  • the gate insulating film existing between the gate electrode 44 and the surface of the substrate 40 is omitted in FIG.
  • the gate electrode 44 is electrically connected to the corresponding read control line 32 via the wiring in the wiring structure 47 formed on the surface of the substrate 40.
  • the reset transistor Tr is composed of a gate electrode 49 and an n + type sandwiching the gate electrode 44 therebetween.
  • the reset transistor Tr shares the n + region 42 of the photodiode PD.
  • one source / drain region of the reset transistor Tr is connected to the photodiode PD.
  • n + type region 43a (source / drain region) is applied with a reset voltage V via a wiring (not shown).
  • Tr to Tr are the photodiode PD, transfer gate TG, and reset transistor, respectively.
  • RST2 RSTn 1 1 Has the same configuration as the transistor Tr.
  • n wiring films 46 formed in a predetermined pattern and n n + type regions 43 of the transfer gates TG to TG are electrically connected to the wiring film 46.
  • the conductive contact plug 45 is formed inside the wiring structure 47. Since the n transfer gates TG to TG in the pixel block 12a (i, j) are electrically connected to the wiring film 46 by the contact plugs 45, the transfer gates TG to TG are common. This means that it is connected to node 13a in parallel.
  • n + type region 43 in the upper semiconductor circuit layer 21E is a function of the FD (floating diffusion) region, that is, a function of converting the signal charge accumulated in the photodiodes PD to PD into a voltage signal by photoelectric conversion. have.
  • the element isolation insulating film 41 and the substrate 40 are placed on the substrate 40 at a position overlapping the element isolation insulating film 41 adjacent to the n + type regions (source and drain regions) 43 of the transfer gates TG to TG.
  • the entire inner wall of the portion of the through hole in contact with the substrate 40 is covered with the insulating film 24.
  • the inside of the through hole (the inside of the insulating film 24 and the inside of the element isolation insulating film 41) is filled with a conductive material, and the conductive material forms the embedded wiring 23.
  • the upper end of the embedded wiring 23 is exposed from the surface of the substrate 40 (element isolation insulating film 41) and is connected to the lower end of the conductive contact plug 23a formed inside the wiring structure 47. .
  • the upper end of the conductive contact plug 23 a is connected to a wiring film 46 formed inside the wiring structure 47. Therefore, the embedded wiring 23 is electrically connected to the corresponding wiring film 46 through the conductive contact plug 23a.
  • the n + type regions (source and drain regions) 43 of the n transfer gates TG to TG of the pixel block 12a (i, j) correspond to the corresponding embedded wirings 23 as in the circuit configuration shown in FIG. Are electrically connected to each other.
  • the back surface force of the substrate 40 is also exposed, and mechanically and electrically connected to the corresponding bump electrode 90 at the lower end.
  • the element isolation insulating film 61 is formed in a predetermined pattern on the surface region of the p-type single crystal Si substrate 60, and accordingly, a predetermined number of amplification transistors T r are used. An element area and an element area for a predetermined number of select transistors Tr to Tr are formed.

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Abstract

L'invention concerne un circuit de détection et un capteur d'image de type à spécification d'adresse, apte à accumuler des charges de signal de tous les pixels, de façon sensiblement simultanée, et à réaliser une ouverture numérique à nombre de pixels élevé. Une pluralité de pixels (11) agencés dans une matrice sont divisés en groupes de n pixels, connectés en parallèle à un noeud commun (13) de sorte à constituer une pluralité de blocs de pixels (12). Chaque bloc de pixels (12) comprend : n éléments de conversion photoélectrique (PD1 à PDn) connectés en parallèle au noeud commun (13); et n grilles de transfert (TG1 à TGn) destinées à ouvrir et fermer des canaux reliant les éléments de conversion photoélectrique (PD1 à PDn) et le noeud commun (13). En dehors de chaque bloc de pixels (12), un transistor de réinitialisation commun (TrRST) sert à réinitialiser tous les pixels (11) et un transistor d'amplification commun (TrAMP) sert à amplifier le signal lu à partir des n pixels (11).
PCT/JP2007/053557 2006-02-27 2007-02-27 Dispositif semiconducteur de type en couches dote d'un capteur integre WO2007105478A1 (fr)

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