JP2652255B2 - Solid-state imaging device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-resolution charge-coupled solid-state imaging device.

[Conventional technology]

The conventional solid-state imaging device is set to a vertical resolution that is compatible with a standard television system such as NTSC having 525 scanning lines, for example.

[Problems to be solved by the invention]

However, in order to perform high-resolution imaging that can be applied to a higher-definition television system or the like,
The conventional solid-state imaging device lacks the vertical resolution. Therefore, it has been desired to develop a solid-state imaging device having a larger number of pixels.

[Means for solving the problem]

In order to achieve such an object, the present invention forms a plurality of photoelectric conversion elements corresponding to pixels in a matrix along a row direction and a column direction, and forms a plurality of photoelectric conversion elements along the above-described photoelectric conversion elements arranged in each column. A solid-state imaging device comprising a vertical charge transfer path and a horizontal charge transfer path connected to an end of the vertical charge transfer path.

As one embodiment of such a solid-state imaging device, the photoelectric conversion element group arranged in the 4n-3 (n is a natural number) row is a first field, and the photoelectric conversion element group is arranged in the 4n-2 (n is a natural number) row. The photoelectric conversion element group to be arranged is in the second field, the photoelectric conversion element group to be arranged in the 4n-1 (n is a natural number) row is the third field, and the photoelectric conversion element group is to be arranged in the 4n (n is a natural number) row. Are located in a fourth field, and a drive signal for generating a transfer element for a photoelectric conversion element corresponding to the first field via a transfer gate is applied to the vertical charge transfer path.
A second gate electrode to which a drive signal for generating a transfer element for a photoelectric conversion element corresponding to the second field via a transfer gate is applied;
A third gate electrode to which a drive signal for generating a transfer element for the photoelectric conversion element corresponding to the third field via a transfer gate is applied, and a transfer gate for the transfer element for the photoelectric conversion element corresponding to the fourth field. A fourth gate electrode to which a driving signal generated through the gate electrode is applied is provided, and a transfer element and a potential barrier are generated between the first and second gate electrodes and between the third and fourth gate electrodes. A fifth gate electrode to which a fifth drive signal to be applied is applied;
A transfer element and a potential barrier between the fourth and first gate electrodes.
And a sixth gate electrode to which a drive signal of
Pixel signals are read out for each of the fields by the first to sixth six-phase drive signals.

In another embodiment, the horizontal charge transfer path includes a pair of horizontal additive transfer paths each for transferring a separate signal charge, and the photoelectric conversion elements arranged in the 4n-3rd row (n is a natural number) The photoelectric conversion element group in which the groups are arranged in the first field in the first frame area and in the 4n-1 (n is a natural number) row is the second field in the first frame area, 4n-
The photoelectric conversion element group arranged in the second row (n is a natural number) is
The photoelectric conversion element group arranged in the first field, 4n (n is a natural number) row in the frame area is located in the second field in the second frame area, and the vertical charge transfer path is provided in the first frame. A first gate electrode to which a drive signal for generating a transfer element for a photoelectric conversion element corresponding to a first field in a region via a transfer gate is applied, and a photoelectric conversion element corresponding to a first field in a second frame region A second gate electrode to which a drive signal for generating a transfer element via a transfer gate is applied, and a drive for generating a transfer element for a photoelectric conversion element corresponding to a second field in the first frame region via a transfer gate. A third gate electrode to which a signal is applied, in a second frame region A fourth gate electrode to which a drive signal for generating a transfer element for the photoelectric conversion element corresponding to the second field via a transfer gate is provided, and a fourth gate electrode is provided between the first and second gate electrodes and the third gate electrode. , A fifth gate electrode to which a fifth drive signal for generating a transfer element or a potential barrier between the fourth gate electrode is applied, between the second and third gate electrodes, and between the fourth and first gate electrodes. A sixth gate electrode to which a sixth drive signal for generating a transfer element or a potential barrier is applied is provided between the first and sixth gate electrodes. After reading out the pixel signals corresponding to the first field in the second frame area, next, read out the pixel signals corresponding to the second field in the first and second frame areas. I did it.

[Action]

According to such a solid-state imaging device, there are six types, that is, six types.
Since the drive signal can be transferred by the vertical charge transfer path according to the phase drive signal, the transfer drive circuit and the wiring associated therewith can be simplified, so that the solid-state imaging device having an increased number of pixels can be used. In addition to being suitable, high-resolution imaging can be performed.

〔Example〕

Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
First, the configuration of the imaging device will be described with reference to FIG. This imaging device is a charge-coupled solid-state imaging device manufactured by a semiconductor integrated circuit technology on a semiconductor substrate having a predetermined concentration of impurities. The light receiving region has 1000 rows in the vertical direction X and 800 rows in the horizontal direction Y. Photodiodes for a total of 800,000 pixels in a column are provided in a matrix, and 80 photodiodes are arranged between photodiode groups arranged in the vertical direction X.
Zero vertical charge transfer paths are formed. A horizontal charge transfer path is provided at the end of each vertical charge transfer path.

That is, the portions indicated by A1, B1, A2, and B2 in the drawing are the photodiodes corresponding to the respective pixels, the portions indicated by l1, l2 to lm are the vertical charge transfer paths, and the portions indicated by the HCCD are the horizontal charge transfer paths. The pixel signal is output via an output amplifier AMP provided at the end of the horizontal charge transfer path HCCD.

Further, the vertical charge transfer paths l1 to lm are provided with a gate electrode made of a polysilicon layer of VA1 with respect to the photodiodes A1 arranged in the first row, the fifth row, and so on every fourth row in the vertical direction X. Are formed so as to be arranged in the vertical direction, and a gate electrode made of a polysilicon layer of VB1 is provided for the photodiodes B1 arranged in every other four rows such as the second row, the sixth row, and so on in the vertical direction X. , The third in the vertical direction X
A gate electrode made of a polysilicon layer of VA2 is provided for the photodiodes A2 arranged in every fourth row, such as the seventh row to the seventh row, and the fourth row and the eighth row in the vertical direction X are provided as shown in FIG. For photodiodes B2 arranged every fourth row
A gate electrode made of a VB2 polysilicon layer is provided,
Further, a gate electrode V2 made of a polysilicon layer is provided between the gate electrodes VA1 and VB1 and between the gate electrodes VA2 and VB2, respectively, between the gate electrodes VB1 and VA2 and between the gate electrodes VB2 and VA1. A gate electrode V4 made of a layer is provided.

The gate electrodes on the same row are formed of a common polysilicon layer, and the gate electrode VA1 has driving signals φ _A1 ,
Driving signals phi ₂ to the gate electrode _V2, the drive signal phi _B1 to the gate electrode VB1, the drive signal phi _B1 to the gate electrode VB1, the drive signal phi ₄ is a gate electrode _V4, the gate electrode VA2 driving signal phi
_A2, the gate electrode VB2 is applied driving signal phi _B2, these drive signals _{φ A1, φ 2, φ B1} , φ 4, φ A2, φ B2 potential level of the potential well corresponding to the applied voltage (hereinafter, (The potential well is called the transfer element.)
By generating potential barriers in the vertical charge transfer paths l1 to lm, signal charges are transferred to the horizontal charge transfer path HCCD. The horizontal charge transfer path HCC
The portion VV closest to D is a gate portion for controlling the connection between the transfer element formed below the gate electrode VB2 located next to the horizontal electrode and the horizontal charge transfer path HCCD. It becomes conductive or non-conductive in synchronization with a signal (not shown). Further, a transfer gate (represented by Tg in the figure) is provided between each of the photodiodes A1, B1, A2, and B2 and the transfer element under the corresponding gate electrode VA1, VB1, VA2, and VB2 of the vertical charge transfer path. And the respective transfer gates are overlapped and stacked on the transfer gate, and the gate electrodes VA1, VB1, VA2, VB
2 is made conductive by applying a predetermined high voltage.

And these photodiodes A1, B1, A2, B2,
The transfer gate and impurity regions of a predetermined concentration formed around the vertical charge transfer paths l1 to lm and the horizontal charge transfer path HCCD serve as channel stops.

Next, the operation of the solid-state imaging device will be described. As described above, this solid-state imaging device has six types (ie, six phases) of drive signals φ _A1 , φ _B1 , φ _A2 , φ _B2 and φ ₂ , φ
₄ is applied to gate electrodes VA1, VB1, VA2, VB2, V2, V4 provided in a predetermined arrangement as shown in FIG. 1, and a so-called four-phase driving method is applied to the horizontal charge transfer path HCCD. By applying the signals φ _H1 , φ _H2 , φ _H3 , φ _H4 , the pixel signals generated in the respective photodiodes are read out and scanned in time series.

In this embodiment, it is defined that the photodiodes A1 and A2 are arranged in the first frame region and the photodiodes B1 and B2 are arranged in the second frame region, respectively. It is defined that one field, the photodiode A2 is arranged in the second field in the first frame area, the photodiode B1 is arranged in the first field in the second frame area, and the photodiode B2 is arranged in the second field in the second frame area.

Next, the scanning read operation will be described in detail based on the timing charts shown in FIGS. 2 to 6 and the potential profiles of the vertical charge transfer paths shown in FIGS. 7 to 10. In this embodiment, the pixel signals of all the photodiodes are read out by sequentially performing the scanning readout for each field according to the above definition.

First, an operation for reading out a pixel signal generated in the photodiode A1 corresponding to the first field in the first frame region will be described with reference to FIG. The second
In the figure, it is assumed that the exposure by all photodiodes at time t ₀ before is completed.

First, the read operation by the horizontal charge transfer path HCCD starts at time t.
During the period from ₀ to time t ₁ immediately after completed up to the time t ₅ (as field shift period), the vertical charge transfer path the pixel signals of the photodiodes A1 via the transfer gate l1
Lmlm is transferred to a predetermined transfer element. That is, first, as shown at time t _1, the logic value level of each of the drive _{signals, φ A1 = H, φ B1} = L, φ A2 = H, φ B2 = L, φ 2 =
L, φ ₄ = H, the time t _{1 in} FIG.
Allowed transfer elements shown in generated under predetermined gate electrode, then, as shown at time t _2, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = H, φ A2 = H, φ _B2 =
By setting H, φ ₂ = L and φ ₄ = H, the transfer element shown at the time point t ₂ in FIG. 7 is generated below a predetermined gate electrode, and then, as shown at the time point t ₃ , The logical value levels of the respective drive signals are represented by φ _A1 = HH, φ _B1 = L, φ _A2 = H,
By setting φ _B2 = L, φ ₂ = L, φ ₄ = H,
As shown in the time t ₃ in FIG. 7, with the transfer gate corresponding to the photodiode A1 in the conductive state,
By generating a deep transfer element below the gate electrode VA1 corresponding to the photodiode A1, to transfer the pixel signal q _A1 of photodiodes A1 to the transfer element. Note that the logical value levels HH, H, L are set to have a predetermined voltage relationship of HH>H> L, and in particular, the logical value level HH is set to a sufficiently high voltage to make the transfer gate conductive. . Next, as shown at time t _4, the logic value level of each of the drive _{signals, φ A1 = H, φ B1} = H, φ A2 = H, φ B2 =
By setting H, φ ₂ = L and φ ₄ = H, as shown at a time point t ₄ in FIG. 7, a potential barrier below the gate electrode V ₂ to which the drive signal φ ₂ is applied, and a drive signal φ _B2 , φ ₄ ,
phi _A1 as a transfer element to the gate electrode VB2, V4, VA1 lower applied holds the pixel signal q _A1 to the transfer element. Next, as shown in time point t _5, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = L, φ A2 = H, φ B2 =
L, phi _{2 =} L, by phi _{4 =} H, and, as shown in time t ₅ in FIG. 7, by the gate electrode VB2 underlying driving signal phi _B2 is applied as a potential barrier, moving the pixel signal q _A1 to the transfer direction (direction of the position of the horizontal charge transfer path HCCD).

Such, the transfer operation of the time t ₁ ~ time t ₅ is completed by performing the following operation shown in period τ in Fig. 2, to transfer the pixel signal q _A1 only the transfer direction one horizontal line . The timing of each drive signal during this period τ is set as shown in FIG. That is, each drive signal is composed of a rectangular signal for two cycles, and as shown in FIG. 6, the drive signal φ _A1 changes from “H” → “L” → “H” → “L” → “H”. relative to the drive signal phi ₂ is set to the same waveform delayed by a predetermined phase Δ than the drive signal phi _B1 is set to the same waveform delayed by a phase Δ from further driving signals phi _2, the driving signal phi ₄ is set further delayed by the same waveform phase Δ the driving signals phi _B1, the driving signal phi _A2 is set to the same waveform delayed by a phase Δ from further driving signal phi _4, the driving signal phi _B2 further drive signal The waveform is set to be the same as the waveform delayed by a phase Δ from φ _A2 .

When driving the vertical charge transfer paths l1~lm by a drive signal of such a time, the time t ₆ in FIG. 6 ~
7 becomes a potential profile as shown in time point t ₆ ~t ₉ in figure corresponding to the waveform of the time t _9, the gate electrode VA1
The pixel signal q _{A1 in the} lower transfer element is the gate electrode V
4 and transfer to the lower transfer element. Further, a potential profile similar to that at time t _{6 to} t _{9 in} FIG. 7 is generated corresponding to the waveform at time t _{10 to} t ₁₃ in FIG. since, the pixel signal q _A1 becomes to be further transferred to the transfer elements of the gate electrode V4 under the following. Although not illustrated, the period of time t ₁₀ ~t _13, the vertical charge transfer path l1~lm
The gate portion VV (see FIG. 1) interposed between the horizontal charge transfer path HCCD and the horizontal charge transfer path HCCD becomes conductive by the application of the gate signal of the logical value "H", and one horizontal scanning line closest to the horizontal charge transfer path HCCD. Pixel signal q _A1 is applied to the horizontal charge transfer path HC.
It will be transferred to CD.

Next, in FIG. 2, during the time t ₁₄ ~t _15, respectively a drive signal s _{φ A1 = H, φ B1 =} L, φ A2 = H, φ B2 = L, φ
_By supplying drive signals φ _{H1 to} φ _H4 by a so-called four-phase drive method to the horizontal charge transfer HCDD while keeping the states of ₂ = L and φ ₄ = H, the pixel signal q for the first horizontal scan line is provided. _A1 is output in chronological order. The signals read in time series are converted into digital signals by an A / D converter (not shown), and are sequentially written to a predetermined address area of a semiconductor memory (not shown).

Thus completes the reading of the pixel signals corresponding to the first horizontal scanning line, then performs the operation time t ₁₅ ~t _16. That is, the operation time t ₁₅ ~t ₁₆ is time preceding t ₅ ~t
It is the same as _14, by the rest of the pixel signal q _A1 to move the overall vertical charge transfer paths L1～lm, pixel signals q _A1 of the next one horizontal scanning line are transferred to the horizontal charge transfer path HCCD You. Then, at time points t _{16 to} t ₁₇ , the previous time point t ₁₄
By performing the same operation as ~t _15, reads the next pixel signals of one horizontal scanning line in a time-series manner. The pixel signal read out in this way is digitized and written into the memory.

The reading of the pixel signals for two horizontal scanning lines has been described above. However, until all the pixel signals q _A1 corresponding to the first field in the first frame area are read (time t _{18 in the} figure), time t ₁₈ t ₅ ~t operations similar to those described as a representative at ₁₅ is continuously repeated.

Next, scan reading of the pixel signals q _A2 generated in the photodiode A2 corresponding to the second field in the first frame area is started. That is, if all the pixel signals q _A1 is read out at time t ₁₈ shown in FIG. 3, then begins scanning reading according to the timing of the drive signal shown in Figure 3.

First, in FIG. 3, the period from the time point t ₁₉ immediately after time t ₁₈ to time t _23, the pixel signal from the photodiode A2 q
_A2 is transferred to vertical charge transfer path l1-lm via transfer gate
To a predetermined transfer element. That is, first
As shown at t ₁₉ , the logical value level of each drive signal is φ
_{A1 = H, φ B1 = L} , φ A2 = H, φ B2 = L, φ 2 = L, φ
_{4 =} H, by a, to generate the transfer elements shown at time t ₁₉ in Figure 8 under the predetermined gate electrode, then, as shown at time t _20, the theoretical value level of each of the drive signals Where φ _A1 = H, φ _B1 = H, φ _A2 = H, φ _B2 = H, φ
By setting ₂ = L and φ ₄ = H, the time point in FIG.
The transfer element as shown in t ₂₀ is generated under a predetermined gate electrode, then, as shown at time t _21, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = L, φ A2 = HH, φ _B2
= L, φ ₂ = L, φ ₄ = H, the eighth
As shown in time t ₂₁ in the figure, with the transfer gate corresponding to the photodiode A2 conductive, by to generate a deep transfer element under the gate electrode VA2 corresponding to the photodiode A2, photodiode A2 the pixel signals q _A2 is transferred to the transfer element. Next, as illustrated time t _22, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = H, φ A2 = H, φ B2 =
_{H, φ 2 = L, φ} 4 = H, by a, as shown in time t ₂₂ in FIG. 8, the gate electrode V2 underlying driving signal phi ₂ is applied a potential barrier, the driving signals phi _B2 ,
phi _4, phi _A1 as a transfer element to the gate electrode VB2, V4, VA1 lower applied holds the pixel signals q _A2 to the transfer element. Next, as shown at time t _23, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = L, φ A2 = H,
By setting φ _B2 = L, φ ₂ = L, φ ₄ = H,
As shown in time t ₂₃ in FIG. 8, driven No. phi _A2 by a potential barrier gate electrode VA2 below to be applied, the transfer direction of the pixel signals q _A2 (the horizontal charge transfer path HC
In the direction of the CD).

When such a transfer operation from time t _{19 to} t ₂₃ is completed,
By performing an operation indicating a period in FIG. 3 tau (period from time t ₂₃ ~t _24), to transfer the pixel signal q _A2 one horizontal scan line to the transfer direction. That is, the operation shown in the period τ in FIG. 3 is the same as the operation shown in the period τ in FIG.
As a result, the pixel signal q _{A2 for} the first horizontal scanning line is obtained.
Is transferred by the horizontal charge transfer path HCCD. still,
The potential profile from time t _{A21 to} t _A24 shown in FIG. 8 corresponds to one cycle (time t _{6 to} t ₉ ) of the timing chart shown in FIG.

Then, during the third time point t ₂₄ ~t ₂₅ in the figure, respectively the drive signals s _{φ A1 = H, φ B1 =} L, φ A2 = H, φ B2 = L, φ 2 =
By supplying drive signals φ _{H1 to} φ _H4 by a so-called four-phase drive method to the horizontal charge transfer HCCD while keeping L, φ ₄ = H, the pixel signal q _A2 for the first one horizontal scanning line is obtained. Output in chronological order. The signals read out in chronological order are converted into digital signals by an A / D converter (not shown) and sequentially written to a predetermined address area of a semiconductor memory (not shown).

And then, at time t ₂₅ ~t _27, the previous time point t ₂₃
By repeating the same operation as to time t _25, the following 1
Reads the pixel signals q _A2 of the horizontal scanning lines, further, the time t
The same operation as that explained as a representative in ₂₃ ~t _25, Repeats for all of the remaining pixel signals q _A2.

Thus, when the reading of the pixel signals q _A2 of the second field in the first frame area is completed (completion time t _28), then generated in the photodiode B1 corresponding to the first field in the second frame region Pixel signal q
Start reading _B1 .

Showing a read operation of the pixel signal q _B1 in a timing chart of Figure 4. That is, the pixel signal q _A2 at the time point t ₂₈ as shown in FIG. 4
Is completed, then scanning and reading are started according to the timing of the drive signal shown in FIG.

First, in FIG. 4, the period from the time point t ₂₉ immediately after time t ₂₈ to time t _33, the pixel signal q of the photodiodes B1
_B1 is transferred to the vertical charge transfer path l1-lm through the transfer gate.
Of a predetermined transfer element. That is, first, time t
_As shown in FIG. ₂₉ , the logical value level of each drive signal is φ
_{A1 = H, φ B1 = L} , φ A2 = H, φ B2 = L, φ 2 = L, φ
_{4 =} H, by a, to generate the transfer elements shown at time t ₂₉ in FIG. 9 under a predetermined gate electrode, then, as shown at time t _30, the logical value levels of each of the drive signals Where φ _A1 = H, φ _B1 = H, φ _A2 = H, φ _B2 = H, φ
_{2 =} L, by phi _{4 =} H, and generates a transfer elements shown at time t ₃₀ in FIG. 9 under a predetermined gate electrode, then, as shown at time t _31, the respective drive The logical value levels of the signals are φ _A1 = L, φ _B1 = HH, φ _A2 = L, φ
_{B2 = H, φ 2 = L} , by phi _{4 =} H, and, as shown in time t ₃₁ in FIG. 9, as well as the transfer gate corresponding to the photodiode B1 into a conductive state,
By generating a deep transfer element below the gate electrode VB1 corresponding to the photodiode B1, to transfer the pixel signal q _B1 of the photodiodes B1 to the transfer element. Next, as shown at time t _32, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = H, φ A2 = H, φ B2
= H, φ ₂ = L, φ ₄ = H, the ninth
As shown in time t ₃₂ in the figure, the driving signals phi ₂ gate electrode V2 down the potential barrier to be applied, the driving signals phi _B2,
phi _4, phi _A1 as a transfer element to the gate electrode VB2, V4, VA1 lower applied holds the pixel signal q _B1 to the transfer element. Next, as shown at time t _33, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = L, φ A2 = H, φ
_{B2 = L, φ 2 = L} , by phi _{4 =} H, and, as shown in time t ₃₃ in FIG. 9, the gate electrode VB1 underlying driving signal phi _B1 is applied to the potential barrier The pixel signal _qB1 in the transfer direction (horizontal charge transfer path HCCD
In the direction in which is located).

Such, the transfer operation of the time t ₂₉ ~t ₃₃ is completed,
By performing the operations shown in the period in FIG. 4 tau (period from time t ₃₃ ~t _34), to transfer the pixel signal q _B1 by one horizontal scan line to the transfer direction. That is, the operation shown in the period τ in FIG. 4 is the same as the operation shown in the period τ in FIG.
Thereby, the pixel signal q _{B1 for} the first horizontal scanning line is obtained.
Is transferred by the horizontal charge transfer path HCCD. still,
Potential profile at the time t ₃₄ ~t ₃₈ shown in FIG. 9 is one period of the timing chart shown in FIG. 6 (point
which corresponds to t ₆ ~t _9).

Then, during a fourth time point t ₃₄ ~t ₃₅ in the figure, respectively the drive signals s _{φ A1 = H, φ B1 =} L, φ A2 = H, φ B2 = L, φ 2 =
By supplying drive signals φ _{H1 to} φ _H4 by a so-called four-phase drive method to the horizontal charge transfer HCCD while maintaining the state of L, φ ₄ = H, the pixel signal q _B1 for the first horizontal scan line is obtained. Output in chronological order. The signals read out in time series are converted into digital signals by an A / D converter (not shown), and are sequentially written to a predetermined address area of a semiconductor memory (not shown).

And then, at time t ₃₅ ~t _37, the previous time point t ₃₃
By repeating the same operation as ~t _35, reads out the pixel signals q _B1 of the next one horizontal scanning line, and further, the time t ₃₃ ~
iterating the operation of represented by t ₃₅ for all of the remaining pixel signal q _B1.

Thus, when the reading of the pixel signals q _B1 of the first field in the second frame region is completed (completion time t _38), then generated in the photodiode B2 corresponding to the second field in the second frame region Pixel signal q
Start reading _B2 .

Showing a read operation of the pixel signals q _B2 in the timing chart of Figure 5. That is, the pixel signal q _B1 at t ₃₈ shown in FIG. 5
When all the readings are completed, the scanning reading is started in accordance with the timing of the drive signal shown in FIG.

First, in FIG. 5, the period from the time point t ₃₉ immediately after time t ₃₈ to time t _43, the image signal from the photodiode B2 q
_B2 is transferred to the vertical charge transfer path l1-lm through the transfer gate.
To a predetermined transfer element. That is, first
As shown at t ₃₉ , the logical level of each drive signal is
φ _A1 = H, φ _B1 = L, φ _A2 = H, φ _B2 = L, φ ₂ = L,
By setting φ ₄ = H, a transfer element shown at a time point t ₃₉ in FIG. 10 is generated under a predetermined gate electrode,
Next, as shown at time t _40, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = H, φ A2 = H, φ B2 = H,
phi _{2 =} L, by phi _{4 =} H, and the transfer elements shown at time t ₄₀ in FIG. 10 is generated under a predetermined gate electrode, then, as shown at time t _41, each of The logical value levels of the drive signals are φ _A1 = L, φ _B1 = H, φ _A2 = L,
By setting φ _B2 = HH, φ ₂ = L, φ ₄ = H,
As shown in time t ₄₁ in FIG. 10, a photodiode B2
While the transfer gate to a conducting state corresponding to, by generating a deep transfer element below the gate electrode VB2 corresponding to the photodiode B2, to transfer the pixel signal q _B2 photodiode B2 to the transfer element. Next, as shown at time t _42, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = H, φ A2 = H,
By setting φ _B2 = H, φ ₂ = L, φ ₄ = H,
As shown in time t ₄₂ in FIG. 10, the driving signals phi ₂ gate electrode V2 down the potential barrier to be applied, the driving signal phi
_B2 , φ ₄ and φ _A1 are applied to the transfer electrodes below the gate electrodes VB2, V4 and VA1 to which the pixel signals q _{B2 are applied.}
Hold. Next, as shown at time t _43, the theoretical level of the respective drive _{signals, φ A1 = H, φ B1} = L, φ A2 =
_{H, φ B2 = L, φ} 2 = L, φ 4 = H, and by, as shown in time t ₄₃ in FIG. 10, the driving signals phi _B2 gate electrode VB2 lower the potential barrier to be applied by a moves the pixel signals q _B2 to the transfer direction (direction of the position of the horizontal charge transfer path HCCD).

When such a transfer operation from time t _{39 to} t ₄₃ is completed,
By performing the operations shown in the period in FIG. 5 tau (period from time t ₄₃ ~t _44), to transfer the pixel signal q _B2 by one horizontal scan line to the transfer direction. That is, the operation shown in the period τ in FIG. 5 is the same as the operation shown in the period τ in FIG.
so that the q _B2 are transferred by the horizontal charge transfer path HCCD.
Incidentally, the potential profiles at the time t ₄₄ ~t ₄₈ shown in FIG. 10 corresponds to one cycle of the timing chart shown in FIG. 6 (time t ₆ ~t _9).

Next, during a fifth time point t ₄₄ ~t ₄₅ in the figure, respectively the drive signals s _{φ A1 = H, φ B1 =} L, φ A2 = H, φ B2 = L, φ 2 =
By supplying drive signals φ _{H1 to} φ _H4 by the so-called four-phase drive method to the horizontal charge transfer HCCD while keeping the state of L, φ ₄ = H, the pixel signal q _B2 for the first horizontal scanning line is obtained. Output in chronological order. The signals read out in chronological order are converted into digital signals by an A / D converter (not shown) and sequentially written to a predetermined address area of a semiconductor memory (not shown).

Then, at time points t _{45 to} t ₄₇ , the previous time point t ₄₃
By repeating the same operation as ~t _45, reads out the pixel signals q _B2 the next one horizontal scanning line, and further, the time t ₄₃ ~
The same operation as that explained as a representative in t _45, is repeated for all the remaining pixel signals q _B2.

As described above, according to the first embodiment, the number of pixels in the vertical direction is increased, the photodiodes corresponding to the respective pixels are divided into four fields, and the six-phase driving is sequentially performed for each field. Since the scanning readout is performed in synchronization with the drive signal, a high-resolution pixel signal can be obtained. In particular, since the vertical transfer operation is performed using the six-phase drive signals, the signal generation circuit for generating these drive signals can be simplified. That is, in view of the fact that a conventional general charge-coupled solid-state imaging device employs a four-phase driving method, when the vertical resolution is about twice that of the conventional one as in this embodiment, the eight-phase driving method is used. Although it is conceivable to adopt this, if this eight-phase driving method is applied, peripheral driving circuits become complicated and large as the types of driving signals increase. On the other hand, in this embodiment, 6
Since the phase driving is performed, effects such as simplification of the circuit scale can be obtained. This embodiment is suitable for capturing a high-definition still image.

Next, a second embodiment will be described. First, the structure will be described with reference to FIG. This is a charge-coupled solid-state imaging device manufactured by semiconductor integrated circuit technology on a semiconductor substrate having a predetermined concentration of impurities, similarly to the first embodiment shown in FIG. 1000 for X
Photodiodes (indicated by A1, B1, A2, and B2) of 800,000 pixels in a row and a horizontal direction of 800 columns in total are provided in a matrix, and a photodiode group arranged in the vertical direction X 800 vertical charge transfer lines l1 to lm are formed between them. Then, the six-phase drive type drive signals φ _A1 , φ ₂ , φ _B1 , φ ₄ , φ _A2 , φ _B2 are applied to the upper surfaces of the respective vertical charge transfer paths l1 to lm by wirings as illustrated. Gate electrodes V _A1 , V ₂ , V _B1 , V ₄ , V _A2 , V _B2 are formed.

Structural difference from the first embodiment, the first horizontal charge transfer path HCCD1 is provided at the end portions of the vertical charge transfer paths each, the gate electrode a gate signal phi _SG is applied G
, A second horizontal charge transfer path HCCD2 is provided, and pixel signals are read out via output amplifiers AMP1 and AMP2 formed at the output terminals of the respective horizontal charge transfer paths HCCD1 and HCCD2. It should be noted that any one of the horizontal charge transfer paths HCCD1 and HCD
D2 also performs a transfer operation based on the drive signals φ _H1 , φ _H2 , φ _H3 , φ _H4 of the four-phase drive method. The portion VV closest to the horizontal charge transfer path HCCD1 in the terminal portions of the vertical charge transfer paths l1 to lm is the gate electrode VB located adjacent thereto.
2 and the horizontal charge transfer path HC
This is a gate section for controlling connection to CD1, and is turned on or off in synchronization with a gate signal (not shown) at a predetermined timing.

Also in this embodiment, the photodiodes A1 and A2 are defined as being arranged in the first frame region, and the photodiodes B1 and B2 are defined as being arranged in the second frame region. Further, the photodiode A1 is arranged in the first frame region. One field defines that the photodiode A2 is arranged in the second field in the first frame area, the photodiode B1 is arranged in the first field in the second frame area, and the photodiode B2 is arranged in the second field in the second frame area. .

Next, FIG. 12 and FIG.
The scanning read operation will be described based on the timing chart shown in FIG. 13 and the potential profile of the vertical charge transfer path shown in FIG.

In this embodiment, first, pixel signals generated in the photodiodes A1 and B1 corresponding to the first field in the first and second frame regions are simultaneously read (this reading period is set to A
Next, pixel signals generated in the photodiodes A2 and B2 corresponding to the second field in the first and second frame areas are simultaneously read out (this reading period is referred to as a B-field scanning reading period). That is, the pixel signals for all the pixels are read out by scanning.

First, the scanning reading in the A field scanning reading period will be described with reference to FIG. In addition, in FIG.
It is assumed that the exposure by all the photodiodes are completed T ₀ previously.

Then, the period from the time point T ₁ of the immediately after the read operation by the horizontal charge transfer path HCCD1 and HCCD2 is completed at time T ₀ to time T ₆ (referred to field shift period), the transfer gate pixel signals of the photodiodes A1 and B1 To the predetermined transfer elements of the vertical charge transfer paths l1 to lm. That is, first, as shown at time T _1, the logical value levels of the drive signals _{respectively, φ A1 = H, φ B1} = H, φ A2 = H, φ B2
= H, φ ₂ = L, φ ₄ = H,
The transfer elements shown at time T ₁ of the in the figure is generated under a predetermined gate electrode, then, as shown at time T _2, the logical value levels of each of the drive _{signals, φ A1 = L, φ B1} = HH , Φ _A2 =
By setting L, φ _B2 = H, φ ₂ = L, φ ₄ = H, as shown at time T ₂ in FIG.
The transfer gate corresponding to B1 is turned on, and a deep transfer element is generated under the gate electrode VB1 corresponding to the photodiode B1, thereby generating a photodiode.
The pixel signal qB1 of _B1 is transferred to the transfer element.
Note that the logical value levels HH, H, L are set to have a predetermined voltage relationship of HH>H> L, and in particular, the logical value level HH is set to a sufficiently high voltage to make the transfer gate conductive. .

Next, as shown at time T _3, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = H, φ A2 = H, φ B2 = H,
phi _{2 =} L, by phi _{4 =} H, and, to indicate the time T ₃ in FIG. 15, the driving signals phi ₂ gate electrode V2 down the potential barrier to be applied, the driving signals phi _B2, phi ₄ , φ _A1
There as a transfer element to the gate electrode VB2, V4, VA1 lower applied, the pixel signals to the transfer element to hold the q _B1.

Next, as shown at time T _4, the logical value levels of each of the drive _{signals, φ A1 = HH, φ B1} = L, φ A2 = H, φ B2 = L,
phi _{2 =} L, by phi _{4 =} H, and the gate as shown in the time T ₄ in FIG. 15, which together with the transfer gate corresponding to the photodiode B1 into a conductive state, corresponds to the photodiode A1 By generating a deep transfer element under the electrode VA1, the pixel signal q of the photodiode A1 is generated.
_A1 is transferred to the transfer element.

Next, as shown at time T _5, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = H, φ A2 = H, φ B2 = H,
phi _{2 =} L, by phi _{4 =} H, and, as shown in the time T ₅ in FIG. 15, the gate electrode V2 underlying driving signal phi ₂ is applied as a potential barrier, the gate electrode VB1, V
4, the pixel signal related photodiode A1 to transfer elements under VA2 q _A1, holds the pixel signal q _B1 relates photodiode B1 to the transfer element of the gate electrode VB2, V4, VA1 below. Further, as shown at time T _6, the logical value levels of each of the drive _{signals, φ A1 = H, φ B1} = L, φ A2 = H, φ B2 =
By setting L, φ ₂ = L, φ ₄ = H, as shown at time T ₆ in FIG. 15, the area under the gate electrodes V 2, VB 1, VB 2 is used as a potential barrier, and the area under the gate electrodes, V 4, VA 2. pixel signal q _A1 relates photodiode A1 to transfer elements, the gate electrodes V4, VA1 lower photodiode to the transfer element
The pixel signal qB1 for _B1 is held.

Such, the transfer operation time T ₁ through T ₆ is completed by performing the following operation shown in period τ in Fig. 12, 1
Respectively transferring pixel signals q _A1 of horizontal scanning lines of the first pixel signal q _B1 of the horizontal charge transfer path HCCD1,1 horizontal scanning line to the second horizontal charge transfer path HCCD2. The timing of each drive signal during this period τ is set as shown in FIG. That is, each drive signal is composed of a rectangular signal for two cycles, and as shown in FIG. 15, the drive signal φ _A1 is “H”.
→ respect "L" → "H" → "L" → to change to "H", the driving signal phi ₂ is set to the same waveform delayed by a predetermined phase Δ than the drive signal phi _B1 is further Phase Δ from drive signal φ ₂
The drive signal φ ₄ is set to the same waveform delayed by a phase Δ by the drive signal φ _B1 , and the drive signal φ _A2 is set to the same waveform further delayed by a phase Δ from the drive signal φ ₄ The drive signal φ _B2 is set to have the same waveform that is further delayed from the drive signal φ _A2 by the phase Δ.

When driving the vertical charge transfer paths l1~lm by a drive signal of such a timing, the time T ₇ in FIG. 14 -
15 becomes the potential profile shown at time T ₇ through T ₁₁ in Figure corresponds to the waveform of the T _11, the pixel signal q _B1 closest to the horizontal charge transfer path HCCD1 horizontal scanning line is the first
Is transferred to the horizontal charge transfer path HCCD1. Further, as shown in FIG. 14, after the gate signal φ _SG changes from “L” to “H” level in synchronization with the first rise of the drive signal φ _B2 , the second rise of the drive signal φ ₂ “H” in synchronization with
To the "L" level, the gate G is turned on during that period, so that the first horizontal charge transfer path HCCD1
Pixel signal q _B1 transferred to is held further forward second to the horizontal charge transfer path HCCD2.

Further, in the period tau, with the same operation as the time T ₇ through T ₁₁ in Figure 14 is performed at the next time point T ₁₁ through T _15, "a gate signal phi _SG in this period T ₁₁ through T ₁₅ L since remains "level, then the pixel signal q _A1 is transferred to the first horizontal charge transfer path HCCD. The operation of the period T ₁₁ through T ₁₅ are carried out according to the same potential profile as that shown at time T ₇ through T ₁₁ in FIG. 15.

Next, the first and second horizontal charge transfer paths HCCD1 and HCCD2
Pixel signal q _{A1 for} the first horizontal scanning line transferred to
And q _B1 , as shown at time points T _{16 to} T ₁₇ in FIG. 12, drive signals are φ _A1 = H, φ _B1 = L, φ _A2 = H, φ _B2 = L, φ
_While keeping the states of ₂ = L and φ ₄ = H, the driving signals φ _{H1 to} φ _H4 by the so-called four-phase driving method are transferred to the horizontal charge transfer HCCD1, HCD1.
By supplying to CCD2, it is output in time series.

Thus completes the reading of the pixel signals q _A1 and q _B1 corresponding to the first horizontal scanning line, then the time T ₁₈ through T
Perform the operation of ₁₉ . That is, the operation time t ₁₈ ~t ₁₉ is the same as the previous time point t ₆ ~t _16, by the rest of the pixel signal q _A1 to move the overall vertical charge transfer paths L1～lm, the following 1
Pixel signal q _A1 and q _B1 horizontal scanning line are transferred to the horizontal charge transfer path HCDD1, HCDD2. At a time T ₁₈ through T _19, by performing the same operation as the previous time point T ₁₆ through T _17, reads the next pixel signals of one horizontal scanning line in a time-series manner.

Although the reading of pixel signals for two horizontal scanning lines has been described above, the first signal in the first and second frame regions is read out.
Until all the pixel signals q _A1, q _B1 corresponding to the field is read out (in the figure, a time T _20), is repeated subsequently the same operation as that explained as a representative to the time T ₆ through T ₁₇ .

Next, scanning reading of the pixel signals q _A2 , q _B2 generated in the photodiodes A2, B2 corresponding to the second field in the first and second frame areas starts. FIG. 13 shows the timing of the scanning readout of the second field. In addition,
In 13 time T ₂₀ in FIG, assuming that the scanning reading of the first field is completed, then, as shown at time T ₂₁ through T _27, by changes the logical value levels of each of the drive signals, pixel signals q _A2 and q _B2 are transferred by the horizontal charge transfer path HCCD1 and HCCD2 1 horizontal scanning line. That is,
According to the driving signal at the time T ₂₁ through T ₂₆ shown in FIG. 13, be transferred in time T ₁ through T ₆ of Fig. 12 and FIG. 15, the pixel signals q _A2 to the transfer elements to transfer the pixel signal q _A1 becomes possible, whereas, the transferring the pixel signals q _B2 to the transfer elements to transfer the pixel signal q _B1. Next, at time T in FIG.
In ₂₆ through T _27, the pixel signal at the same timing as that shown in FIG. 14 q _A2 and q _B2 are transferred by the horizontal charge transfer path HCCD1 and HCCD2 1 horizontal scanning line.

And then, by the same timing as the time T ₁₆ through T ₁₇ in Figure 12 at time T ₂₇ through T ₂₈ of FIG. 13, a horizontal charge transfer path HCCD1 and HCCD2 transfers pixel signal, one horizontal scanning line the minute pixel signals q _A2 and q _B2 chronologically read.

Then, for the remaining pixel signals, repeated operation of the timing described as a representative at T ₂₆ through T _28, the read completion (time point T ₃₀ of all the pixel signals of the repetition operation
To).

As described above, according to the second embodiment, the vertical resolution is improved because the number of pixels in the vertical direction is increased, and the array of photodiodes corresponding to each pixel is changed to four.
Since the pixels are divided into fields and the pixel signals generated in the photodiodes are transferred two fields at a time in synchronization with the drive signal of the six-phase drive, the pixels are scanned and read out via the two horizontal charge transfer paths. Scanning and reading can be performed at a higher speed than in the embodiment, which is suitable for capturing a moving image with high definition. Further, since scanning and reading can be performed only by generating a driving signal of six-phase driving, wiring and a driving circuit for driving can be simplified.

In the second embodiment, the horizontal charge transfer paths HCCD1 and HCCC
The case where D2 is operated based on the four-phase drive system has been described. However, the present invention is not limited to this, and a two-phase drive system or another system may be used.

According to this embodiment, it goes without saying that a high-definition still image can be captured. However, this second
In this embodiment, since two horizontal charge transfer paths HCCD1 and HCCD2 are used, flicker due to the difference in the transfer characteristics may occur. In order to solve such a problem, the gate signal φ _SG applied to the gate electrode G shown in FIG. 11 is always set to “L” level, and the drive timing described in the first embodiment is applied. For example, the pixel signal can be read out only by the first horizontal charge transfer path HCCD1, and the occurrence of flicker can be prevented.

〔The invention's effect〕

As described above, according to the present invention, there are six types, that is, six types.
Since the pixel signal is transferred by the vertical charge transfer path according to the phase drive signal, the transfer drive circuit and the wiring associated therewith can be simplified, which is suitable for a solid-state imaging device with an increased number of pixels. At the same time, it enables high-definition imaging.

[Brief description of the drawings]

FIG. 1 is a structural explanatory view of a solid-state imaging device according to an embodiment of the present invention, FIG. 2 to FIG. 6 are timing charts for explaining the operation of the embodiment, FIG. FIG. 10 is an explanatory diagram showing a potential profile for explaining the operation of one embodiment. FIG. 11 is an embodiment structural explanatory diagram for explaining the structure of another embodiment of the solid-state imaging device according to the present invention. FIG. 14 to FIG. 14 are timing charts for explaining the operation of another embodiment, and FIG. 15 is an explanatory diagram showing a potential profile for explaining the operation of another embodiment. Symbols in the figure: A1, B1, A2, B2; photodiodes VA1, VB1, VA2, VB2; gate electrodes l1 to lm; vertical charge transfer paths HCCD HCCD1, HCCD2; horizontal charge transfer paths AMP, AMP1, AMP2; output amplifier

Claims (2)

(57) [Claims] 1. A plurality of photoelectric conversion elements corresponding to pixels are formed in a matrix along a row direction and a column direction, and a vertical charge transfer path is formed along the photoelectric conversion elements arranged in each column. In addition, in a solid-state imaging device formed by forming a horizontal charge transfer path connected to an end portion of these vertical charge transfer paths, the photoelectric conversion element group arranged in the 4n-3 (n is a natural number) row is a first photoelectric conversion element group. In the field, 4n-2 (n is a natural number) rows, the photoelectric conversion element group arranged in the second field, 4n-1 (n
The photoelectric conversion element group arranged in the (n is a natural number) row is located in the third field, and the photoelectric conversion element group arranged in the 4n (n is a natural number) row is located in the fourth field. Are a first gate electrode (VA1) to which a drive signal (φ _A1 ) for generating a transfer element for a photoelectric conversion element corresponding to a first field via a transfer gate is applied, and a photoelectric element corresponding to a second field. A second gate electrode (VB1) to which a drive signal (φ _B1 ) for generating a transfer element for a conversion element via a transfer gate is applied, and a transfer element for a photoelectric conversion element corresponding to a third field via a transfer gate. third gate electrode driving signal is generated (phi _A2) is applied Te (VA2), the transfer error for the photoelectric conversion elements corresponding to the fourth field Instruments with a fourth providing the gate electrode (VB2) a driving signal for generating via a transfer gate (phi _B2) is applied to said first, and between said second gate electrode (VA1, VB1) first 3. The fifth gate electrode (V2) to which a fifth drive signal (φ ₂ ) for generating a transfer element and a potential barrier is applied between the fourth gate electrode (VA2, VB2); Between the third gate electrode (VB1, VA2) and the fourth,
A sixth gate electrode (V4) to which a sixth drive signal (φ ₄ ) for generating a transfer element and a potential barrier is applied between the first gate electrodes (VB2, VA1); After the pixel signal generated in the photoelectric conversion element corresponding to one of the fourth fields is field-shifted to the transfer element corresponding to the field, the first to sixth drive signals (φ _A1 , φ _B1) ,
According to φ _A2 , φ _B2 , φ ₂ , φ ₄ ), each pixel signal is transferred in the direction of the horizontal charge transfer path in a separated state, and
The horizontal charge transfer path performs horizontal transfer of pixel signals for each row to read pixel signals for the field,
Next, after the pixel signal generated in the photoelectric conversion element corresponding to one of the remaining fields is field-shifted to the transfer element corresponding to the field, the first to sixth drive signals (φ _A1 , φ _B1 , φ _A2 , φ _B2 , φ
₂ , φ ₄ ), each pixel signal is transferred in the direction of the horizontal charge transfer path in a state of being separated, and the pixel signals for each row are transferred horizontally by the horizontal charge transfer path for the field. The pixel signal is read out, and the pixel signal generated in the photoelectric conversion element corresponding to one of the remaining fields is field-shifted to the transfer element corresponding to the field. drive signal _{(φ A1, φ B1, φ} A2, φ B2, φ 2, φ 4)
, Each pixel signal is transferred in the direction of the horizontal charge transfer path in a separated state, and the pixel signals of each row are transferred in the direction of the horizontal charge transfer path, and the pixel signals of each row are transferred in the horizontal direction. The charge transfer path reads out the pixel signals for the field by performing horizontal transfer, and then performs a field shift of the pixel signal generated in the photoelectric conversion element corresponding to the last field to the transfer element corresponding to the field. In accordance with the first to sixth drive signals (φ _A1 , φ _B1 , φ _A2 , φ _B2 , φ ₂ , φ ₄ ), each pixel signal is transferred in the direction of the horizontal charge transfer path in a separated state, and The driving signals (φ _A1 , φ _B1 , φ _A2 , φ A) are read such that the horizontal charge transfer path performs horizontal transfer of pixel signals for each row to read out pixel signals for the field.
_B2, phi _2, the solid-state imaging device and controls the phi _4). 2. A plurality of photoelectric conversion elements corresponding to pixels are formed in a matrix along a row direction and a column direction, and a vertical charge transfer path is formed along the photoelectric conversion elements arranged in each column. In addition, in a solid-state imaging device formed by forming a horizontal charge transfer path connected to an end portion of the vertical charge transfer path, the horizontal charge transfer path includes a pair of horizontal charge transfer paths each transferring a separate signal charge. (HCCD1, HCCD2), and the photoelectric conversion element group arranged in the 4n-3 (n is a natural number) row is a first field in the first frame area, 4n-
The photoelectric conversion element group arranged in the first (n is a natural number) row is
The photoelectric conversion element group arranged in the second field, 4n-2 (n is a natural number) row in the frame area, and the photoelectric conversion element arranged in the first field, 4n (n is a natural number) row in the second frame area The group is located in a second field in a second frame area, and a transfer element for a photoelectric conversion element corresponding to the first field in the first frame area is generated in the vertical charge transfer path via a transfer gate. A first gate electrode (VA1) to which a drive signal (φ _A1 ) to be applied is applied;
A second gate electrode (VB1) to which a drive signal (φ _B1 ) for generating, via a transfer gate, a transfer element for a photoelectric conversion element corresponding to a first field in a second frame region is applied; A third gate electrode (VA) to which a drive signal (φ _A2 ) for generating a transfer element for the photoelectric conversion element corresponding to the second field via a transfer gate is applied.
2) A fourth gate electrode (VB2) to which a drive signal (φ _B2 ) for generating a transfer element for a photoelectric conversion element corresponding to a second field in the second frame region via a transfer gate is provided. A fifth drive signal (φ) for generating a transfer element or a potential barrier between the first and second gate electrodes (VA1, VB1) and between the third and fourth gate electrodes (VA2, VB2). ₂ ) the fifth gate electrode (V2) to which the voltage is applied, between the second and third gate electrodes (VB1, VA2), and between the fourth and fourth gate electrodes (VB1, VA2).
A sixth drive signal (φ) for generating transfer element or potential barrier between the first gate electrodes (VB2, VA1).
₄ ) A sixth gate electrode (V4) to which a voltage is applied is provided, and a pixel signal generated in the photoelectric conversion element corresponding to each first field of the first and second frames corresponds to each first field. After field-shifting the transfer elements, respectively, the first to sixth drive signals (φ _A1 , φ _B1 ,
According to φ _A2 , φ _B2 , φ ₂ , φ ₄ ), the horizontal charge transfer paths (HCCD1, HCCD2) are divided into two rows with each pixel signal separated.
, And the horizontal charge transfer paths (HCCD1, HCCD2) perform horizontal transfer of the pixel signals of every two rows to read out the pixel signals of each first field. After the pixel signals generated in the photoelectric conversion elements corresponding to the respective second fields of the second frame are field-shifted by the respective transfer elements corresponding to the respective second fields, the first to sixth drive signals (φ _A1 , φ _B1 ,, φ
_A2, φ _B2, φ _2, according to phi _4), and transfers in the direction of the two rows at a time the horizontal charge transfer path in a state in which separate each pixel signal (HCCD1, HCCD2), the pixel signals of two rows at a time The drive signals (φ _A1 , φ _B1 , φ _A2 , φ _B2 , φ ₂ , φ ₂ ) are read out so that the horizontal charge transfer paths (HCCD1, HCCD2) read out the pixel signals for the respective second fields by performing horizontal transfer. ₄ ) A solid-state imaging device characterized by controlling the following.