JPH04286283A - Charge coupled type solid-state image pick-up device - Google Patents

Abstract

PURPOSE:To provide a charge coupled type solid-state image pick-up device which can perform the image pick-up with high frequency and high resolution to adapt to an EDTV type system. CONSTITUTION:At vertical charge transfer lines L1-Lm in correspondence to each picture element, each pair of transfer gate electrode is provided, and while it is dislocated in order from the picture element signal at a hirizontal charge transfer line 8 side, reading is performed. Then, according to a charge coupled type solid-state image pick-up device having such a constitution, the vertical charge transfer lines L1-Lm transfers and reads like the so-called domino in order from the signal charge located at the line at the most outputted side, and thus, the number of the transfer gate electrodes can be reduced and the structure becomes simplified. As this result, when manufacturing by the semiconductor manufacturing technics, the yield can be improved, the high resolution is easy, the image pick-up of the high frequency to adopt to the EDTV system can be corresponded to.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge-coupled solid-state imaging device for performing high-resolution imaging suitable for an EDTV broadcasting system.

0002

2. Description of the Related Art In the current television broadcasting system such as the NTSC system, in order to reproduce one frame of image using, for example, 525 scanning lines, one field has 26
Interlaced scanning is performed with 2.5 lines each. On the other hand, the EDTV broadcasting system, for example, reproduces one frame of image by performing non-interlaced scanning of 525 lines per field twice.
It provides a reproduced image that is clearer than the NTSC system while maintaining compatibility with other systems. In order to realize this EDTV system image reproduction, a television receiver has a second
It is equipped with a video signal processing unit as shown in Figure 5, which receives television signals such as the current NTSC system transmitted from broadcasting stations using the tuner inside the television receiver.
After one field's worth of video signals (that is, 262.5 TV lines) is temporarily stored in the first field memory and the second field memory, each video signal is transferred from the first and second field memories in synchronization with a predetermined timing. At the same time as reading the signal, the video signal read from the first field memory is directly supplied to the addition circuit, and the signal read from the second field memory is supplied to the addition circuit via the interpolation circuit. 525 TV field signals are generated by interpolating between scanning lines. Therefore, as shown in FIG. 26, by adding the interlaced signal (A) of a predetermined period and the interlaced signal (B) whose phase has been shifted by interpolation processing, one field image with twice the vertical resolution is generated. A video signal (C) corresponding to the EDTV system is formed. Although not shown, the image quality is further improved by providing a processing circuit for improving the separation of luminance signals and color signals, improving ghost removal, and the like.

On the other hand, imaging devices such as video cameras that are compatible with EDTV systems have also been developed. As such an imaging device, for example, (C) in FIG.
As shown in Figure 2, field imaging is performed in advance with the same vertical resolution as the reproduced image, and from the signal obtained by this imaging, N
There is a system that forms 262.5 interlaced signals in accordance with the TSC system to form a television signal of the NTSC system. Further, development of charge-coupled solid-state imaging devices for performing such high-resolution imaging is also progressing. First, as an example of a conventional high-resolution charge-coupled solid-state imaging device, there are charge-coupled solid-state imaging devices using the commonly known interline transfer method (IT method) and frame interline transfer method (FIT method). There is a known device that follows the same structure as the device but doubles the number of pixels in the vertical direction.

Therefore, as shown in FIG. 27, the light receiving section of such a charge-coupled solid-state imaging device includes photodiodes P11, P12, P2 corresponding to each pixel.
2, P22, etc. are formed in a matrix, and vertical charge transfer paths are formed adjacent to each photodiode group arranged in each row direction, and furthermore, on these vertical charge transfer paths, charge transfer paths are arranged in each column direction. Transfer gate electrodes G11 and G12 correspond to each pair of photodiode groups.
, G21, G22, etc. are arranged in parallel, and drive signals φ1 to φ1 of a so-called four-phase drive system are applied to these transfer gate electrodes.
Interlaced scanning readout is performed by applying φ4. In addition, as another charge-coupled solid-state imaging device,
A light receiving section is known in which the light receiving section is composed of pixels arranged as shown in FIG. 8 and a vertical charge transfer path. This corresponds to each photodiode PD1, PD2, PD3 corresponding to each pixel.
, PD3, etc., three transfer gate electrodes G1 each.
1, G12, and G13 are arranged in parallel, and pixel signals are read out in non-interlace scanning in synchronization with drive signals φ1, φ2, and φ3 of a three-phase drive system. or,
As shown in FIG. 29, the drive signal φ1 of the four-phase drive system
A device that performs non-interlaced scanning readout in synchronization with ~φ4 has also been developed. That is, in this charge-coupled solid-state imaging device, the light receiving section is composed of pixels and vertical charge transfer paths arranged as shown in FIG. 29, and each photodiode PD1, PD2, PD3,
For each PD4 etc., four transfer gate electrodes G11,
G12, G13, G14 ~ are arranged in parallel, and non-interlaced scanning and readout are performed in synchronization with drive signals φ1 ~ φ4 of a four-phase drive system.

[0005]

[Problems to be Solved by the Invention] However, in such conventional charge-coupled solid-state imaging devices for EDTV systems, the number of transfer gate electrodes also increases in proportion to the increase in the number of pixels in the vertical direction. As a result, there is a problem in that the aperture ratio and charge transfer rate decrease, leading to deterioration in sensitivity. Furthermore, if an attempt is made to increase the number of transfer gate electrodes using semiconductor manufacturing technology, the transfer gate electrodes will have a complicated structure such as a multilayer structure, which causes problems such as a decrease in yield. The present invention has been made in view of such problems, and an object of the present invention is to provide a charge-coupled solid-state imaging device suitable for an ECTV video system.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention forms a plurality of photoelectric conversion elements corresponding to pixels in a matrix in the row and column directions, and arranges them in the column direction. A light receiving section is provided with a vertical charge transfer path formed adjacent to each photoelectric conversion element group, and after transferring a pixel signal generated in a pixel to the vertical charge transfer path of the light receiving section, vertical charge transfer of the light receiving section is provided. In a charge-coupled solid-state imaging device in which a gate signal at a predetermined timing is applied to a transfer gate electrode in a horizontal charge transfer path, and pixel signals for each row are scanned and read out using a horizontal charge transfer path, the transfer gate electrode of the light receiving section is connected to each photoelectric conversion element. At the time of scan readout, a predetermined number of sets of adjacent transfer gate electrodes are formed, and gate electrodes are set at a predetermined timing in order from the set of transfer gate electrodes closest to the horizontal charge transfer path. By applying a signal, pixel signals are transferred in order from the row closest to the horizontal charge transfer path side, and furthermore, one frame worth of scanning readout is performed by performing two non-interlaced field scanning readouts.

Furthermore, a plurality of photoelectric conversion elements corresponding to pixels are arranged in a matrix in the row and column directions, and a vertical charge transfer path is formed adjacent to each group of photoelectric conversion elements arranged in the column direction. and an accumulation section having a vertical charge transfer path connected to these vertical charge transfer paths of the light receiving section, the pixel signal generated in the pixel being transferred to the vertical charge transfer path of the light receiving section. After that, by applying a gate signal at a predetermined timing to the transfer gate electrode of the vertical charge transfer path of the light receiving section and the storage section, all pixel signals are transferred at high speed to the vertical charge transfer path of the storage section. In a charge-coupled solid-state imaging device in which a gate signal at a predetermined timing is applied to a transfer gate electrode of a vertical charge transfer path in the light receiving section, and a pixel signal for each row is scanned and read out by a horizontal charge transfer path, the transfer gate electrode of the light receiving section Two transfer gate electrodes are provided for each photoelectric conversion element, and the number of transfer gate electrodes in the storage section is made equal to the number of transfer gate electrodes in the light receiving section. A gate signal at a predetermined timing is applied to the transfer gate electrodes in the accumulation section in order from the transfer gate electrodes of the transfer gate electrodes of the group on the side closer to the storage section. When the application of the gate signal is stopped and the scanning readout is performed, a predetermined number of sets of mutually adjacent transfer gate electrodes are formed in the storage section, and a predetermined set of transfer gate electrodes are sequentially arranged starting from the set of transfer gate electrodes closest to the horizontal charge transfer path. By applying a timing gate signal, the pixel signals are transferred in order starting from the row closest to the horizontal charge transfer path, and then one frame's worth of scan readout is performed by performing two non-interlaced field scan readouts. I made it.

[0008]

[Operation] According to the charge-coupled solid-state imaging device having such a configuration, the vertical charge transfer path sequentially transfers and reads the signal charges from the row closest to the output side like a so-called domino toppling. The number of gate electrodes can be reduced and the structure can be simplified. As a result, when manufacturing using semiconductor manufacturing technology, the yield can be improved, resolution can be easily increased, and high frequency imaging compatible with the EDTV system can be supported.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a charge-coupled solid-state imaging device according to the present invention will be described below with reference to the drawings. First, the overall structure of an EDTV camera-integrated video tape recorder to which this charge-coupled solid-state imaging device is applied will be explained with reference to FIG. 1. In FIG. 1, 1 is an imaging optical system consisting of an imaging lens, etc.; A mechanical diaphragm mechanism 3 is a charge-coupled solid-state imaging device to which the present invention is applied, and each is arranged in order along the optical axis of the imaging optical system 1.
The configuration is such that the optical image of the object is incident on the light receiving area of the charge-coupled solid-state imaging device 3. Furthermore, 4 is a signal processing circuit, and 5 is a recording mechanism. The signal processing circuit 4 performs color separation, γ correction, white balance adjustment, etc. on the pixel signal output from the charge-coupled solid-state imaging device 3, and also converts it into a luminance signal. Color difference signals are formed, and the recording mechanism 5 performs recordable modulation processing on these luminance signals and color difference signals, and then records them on a magnetic recording medium or the like.

The synchronous control circuit 6 controls the aperture mechanism 2,
By synchronously controlling the readout timing of the charge-coupled solid-state imaging device 3 and the operations of the signal processing circuit 4 and recording mechanism 5, a series of operations from imaging to recording is processed. The charge-coupled solid-state imaging device 3 has the configuration shown in FIG. That is, the light receiving area 7 for receiving the optical image of the subject.
is a plurality of photodiodes corresponding to pixels arranged in a matrix along the row direction Y and the column direction Vertical charge transfer path L1 formed adjacent to each other
~Lm is provided. These vertical charge transfer paths L
A horizontal charge transfer path 8 is formed at the end of each of the horizontal charge transfer paths 1 to Lm, and an output amplifier 9 is formed at the end of the horizontal charge transfer path 8. Furthermore, in the vertical charge transfer paths L1 to Lm,
As will be described later, gate electrodes are provided in a predetermined arrangement, and a light shielding layer for blocking the incidence of light is laminated on the upper surface of these gate electrodes. These gate electrodes have a vertical charge transfer path L.
1 to Lm, the driving gate signals for performing the charge transfer operation in synchronization with a predetermined timing are the first, second, and third gate signals.
It is supplied from drive circuits 10, 11, and 12 of. Incidentally, the timing signals φH, VL, φG, φFS, VS, φH, VL, φG, φFS, VS,
The synchronous control circuit 6 generates the start pulse signals φ1, φ2, φ3, φ4.

Further, the horizontal charge transfer path 8 receives signal charges transferred from the vertical charge transfer paths L1 to Lm,
Furthermore, gate electrodes are provided for horizontal transfer to the output amplifier 8 side, and gate signals α1 and α2 to be applied to the gate electrodes to perform these operations are supplied from the synchronization control circuit 6. Next, the structure of the light receiving area 7 and the circuit configuration of the drive circuits 10, 11, 12 connected thereto will be described in detail with reference to FIGS. 3 to 6. 3 is a circuit diagram of the third drive circuit 12, FIG. 4 is a circuit diagram of the main part of the light-receiving area 7 when viewed from the light-receiving surface side, and FIG. FIG. 6 is a longitudinal sectional view taken along the y-y line of FIG. 4;

First, based on FIG. 3, the third drive circuit 1
The second circuit configuration will be explained. The drive circuit 12 converts the start pulse signal φS into a two-phase clock signal φA with a phase shift.
This is a shift register that sequentially generates a drive signal of logical value "H" from the lower bit output to the upper bit output by transferring in synchronization with and φB. That is, at first, only the drive signal S1 is at the "H" level and all other upper bits are at the "L" level, and in the next cycle, the lower two bits of the drive signals S1 and S2 are at the "H" level and the other upper bits are at the "L" level. All outputs become “L” level, and in the next cycle, the lower 3 bits of drive signals S1, S2, and S3 become “L” level.
The "H" output level of the drive signal changes so that it spreads from the lower bits to the upper bits in order, such that when the output of the other upper bits becomes "H" level, all other upper bits output becomes "L" level.As shown in FIG. Since each bit has a cell structure, the circuit for the first bit will be described as a representative circuit. Three MOS transistors u11, u12, u1
3 connects the source-drain path in series between the signal line of voltage VL and the signal line of clock signal φB, and the signal line of reset signal RS is connected to the gate contact of transistor u13. A bootstrap capacitor ε11 is connected between the gate contact and the drain contact of the transistor u11, the gate contact and the source contact of the transistor u12 are commonly connected, and the bootstrap capacitor ε11 is connected to the source contact of another MOS transistor u14, and the drain of the transistor u14 is connected to the gate contact and the source contact of the transistor u12. The contact is the signal line of voltage VL, and the gate contact is the clock signal φ
They are connected to the signal lines of A.

Furthermore, MOS transistors u11, u1
2, u13, and u14 have the same configuration as the MOS transistors u21, u22, and u23.
, u24 and a bootstrap capacitor ε21, and the drain contact (output point) of the transistor u12 and the gate contact (input point) of the transistor u22 are connected. However, the connections of the signals φA and φB are reversed. This bit input corresponds to the gate contact of the transistor u11, and the bit output corresponds to the drain contact of the transistor u22. By cascading the inputs and outputs of these bit cells, an n-bit output shift register is constructed, and the input of the start pulse signal φS to the least significant bit cell is an analog signal that becomes conductive in synchronization with the clock signal φA. This is done via switch u00. Next, in FIGS. 4 to 6, a p-well layer 14 for forming a light-receiving region 7 and a p-well layer 14 for forming a first drive circuit 10 are formed on the front side of the n-type semiconductor substrate 13.
A well layer 15 and a p-well layer 16 for forming the second and third drive circuits 11 and 12 are buried, and these p-well layers 16 are buried.
Predetermined circuits are formed in the well layers 14, 15, and 16, respectively.

First, the light-receiving region 7 is formed by forming an n
A photodiode indicated by P in FIG. 2 is formed by arranging a plurality of impurity layers 17 made of + type impurities in a matrix along the row direction By forming an n-type impurity layer 18 (portion indicated by a dotted line in FIG. 6) adjacent to each arranged impurity layer 17, vertical charge transfer paths L1 to L in FIG.
m is formed. Then, by forming a p+ type impurity layer 19 around the area except for the part that will become the transfer gate, the photodiode part, and the vertical charge transfer path part shown by Tg in FIG. 4 (only one place is shown as a representative). , forming a channel stopper region (shaded area surrounded by dotted lines in FIG. 4). In addition, in FIG. 4, the photodiodes P in FIG. 2 are replaced by P1, P2, P3, P4 for each row.
...is shown. Furthermore, in FIG. 4, on the upper surface of the vertical charge transfer paths L1 to Ln, there are two photodiodes arranged adjacent to the photodiodes P1, P2, P3, P4, etc. arranged in each row, as shown in the figure. gate electrodes G11 to G41, G1 each consisting of separate polysilicon layers;
2~G41, G13~G43, ...G1n~G4n
are stacked, and if the gate electrode G11 is the first gate electrode, as shown in FIGS. 4 and 5, the odd-numbered gate electrodes G11, G31, G12, G32,
By narrowing the width W1 of G13, G33, ..., the even numbered gate electrodes G21, G41, G22, G42, G23,
G43... has a wide width W2.

[0015] Gate signals φ11, φ21, φ31, φ31, φ21, φ31, φ21, φ31, φ21, φ31, φ21, φ31, φ21, φ31,
By applying φ41, φ12, φ22, φ32, and φ42, potential wells (hereinafter referred to as transfer pixels) and potential barriers for charge transfer are generated in the vertical charge transfer path under each gate electrode. Moreover, even-numbered gate electrodes G21, G41, G22, G42,
When a predetermined high voltage signal is applied to G23, G43, ..., the transfer gate Tg becomes conductive, and
Each photodiode P1, P2, P3, P
4...and adjacent even-numbered gate electrodes G21,
The structure is such that the transfer pixels generated under G41, G22, G42, G23, G43, .

Furthermore, as shown in FIG. 4, a horizontal charge transfer path 8 is formed at the end of the vertical charge transfer paths L1 to Lm, and transfers signal charges at a timing conforming to the four-phase drive system or the two-phase drive system. A gate electrode is provided for horizontal transfer. Next, the circuit configuration of the first drive circuit 10 will be explained with reference to FIGS. 4 and 6. Horizontal charge transfer path 8
If the gate electrode G11 closest to is the first gate electrode, then the odd-numbered gate electrodes G11, G31, G12
, G32, G13, G33, ... each tip is NM
OS transistors M11, M31, M12, M32,
Connected to the signal line of the signal VL through M13, M33, . . . and connected to the even-numbered gate electrodes G21, G41, G2.
2, G42, G23, G43, ... each tip is N
MOS transistors M21, M41, M22, M42,
It is connected to the signal line of the drive signal φH via M23, M43, . . . Further, a drive signal φG is supplied to the gate contacts of these transistors. Furthermore, even numbered gate electrodes G21, G41, G22, G42,
At each tip of G23, G43, ..., there are npn transistors Q21, Q41, Q22, Q42, Q23,
The emitter contacts of Q43, . . . are connected, and a drive signal φFS is applied to the base contact of each npn transistor, and a voltage VS is applied to the collector contact.

These NMOS transistors, as shown in the structure inside the p-well layer 15 in FIG. 6, consist of a pair of n+ type impurity layers 20 and 21 and a gate electrode laminated on the surface portion. n+ becomes the drain contact
A drive signal φH is applied to the type impurity layer 20, and the n+ type impurity layer 21, which serves as a source contact, is connected to the gate electrode on the vertical charge transfer path. Further, the signal VL is applied to the p+ type impurity layer 22 buried in the p well layer 15. The npn transistor is composed of a p+ type impurity layer 23 buried in a p well layer 15, an n+ type impurity layer 24, and an n type semiconductor substrate 13, and an n+ type impurity layer 24 serving as an emitter contact is connected to each gate electrode. A p-well layer 15 and a p+ type impurity layer 23 are connected and serve as a base contact.
A timing signal φFS is applied to the n-type semiconductor substrate 13, which serves as a collector contact, and a bias voltage V of the substrate 13 is applied to the n-type semiconductor substrate 13, which serves as a collector contact.
S is applied.

Next, the second drive circuit 11 converts the timing signals φ1 to φ4 supplied from the synchronous control circuit 6 into drive signals S1, S2, S3, S from the third drive circuit 12.
It consists of NMOS transistors m11, m21, m31, m41, . Drive signals S1, S2, S3, S4... are applied, and the first NMOS transistors m11, m11,
The timing signal φ1 is applied to the drain contacts of m12, m13, m14..., and the second NMOS transistor m
The timing signal φ2 is applied to the drain contacts of 21, m22, m23, m24..., the timing signal φ3 is applied to the drain contacts of the third NMOS transistor m31, m32, m33, m34..., and the fourth NMOS transistor
MOS transistors m41, m42, m43, m
A timing signal φ4 is supplied to the drain contacts of 44.... In addition, in FIG. 4, the NMOS transistor m1
The signals φ11, φ21, φ31, φ41, . As shown in the figure, the source contacts of the NOMS transistors are connected in order from the gate electrode G11 closest to the horizontal charge transfer path 8. As described above, the third drive circuit 12 receives the drive signal S1 at a predetermined timing.
, S2, S3, S4 to Sn. The second and third drive circuits 11 and 12 are formed of NMOS transistors and electronic elements formed in the p-well layer 16 shown in FIG. In the p-well layer 16 in FIG. 6, as an example, there is an n+ type impurity layer 2 constituting an NMOS transistor.
5, 26 and gate contacts are shown. Next, the imaging operation of the charge-coupled solid-state imaging device having such a structure will be described in the case of moving image imaging.

First, the general operation will be explained with reference to FIG. The current NTSC system scans 512 TV lines,
1/60 second interlaced field running output 2
By repeating this process twice, a 1/30 second frame image is obtained. In contrast, in this embodiment, scanning readout is performed at twice this frequency. That is, by performing non-interlaced field scanning and readout of 512 TV lines twice in 1/60 second, imaging with twice the conventional vertical resolution is performed in 1/30 second. In FIG. 7, period F1 is the first field scanning period, and period F2 is the second field scanning period, both of which are 1/
It is set to 60 seconds. Assuming that scanning readout of pixel signals is started from a certain time point t1 in the figure, first,
During the period TVB, which corresponds to the vertical blanking period of a standard television system such as NTSC, the pixel signals of all photodiodes are simultaneously transferred to the transfer pixels of the vertical charge transfer paths L1 to Lm, and the period corresponds to the next horizontal blanking period. In the period THB, the pixel signal of the transfer pixel closest to the horizontal charge transfer path 8 is transferred to the horizontal charge transfer path 8, and then, in the period T1H corresponding to the horizontal scanning period, the horizontal charge transfer path 8 is transferred in one row. The pixel signals of the first row are read out by horizontally transferring the pixel signals for the first row. Note that the period T1H is 1/2 of the so-called 1H period in the case of the current NTSC system.

[0020] Then, during the period THB corresponding to the next horizontal blanking period, the vertical charge transfer paths L1 to Lm
transfers the pixel signals of the next row to the horizontal charge transfer path 8, and furthermore, the horizontal charge transfer path 8 horizontally transfers the pixel signals of the second row in the period T1H corresponding to the next horizontal scanning period. read out. Furthermore, the pixel signals of the third row are read out during each period THB and T1H corresponding to the next horizontal blanking period and horizontal scanning period. Then, the pixel signals of the remaining rows are sequentially read out by repeating the same process, and finally all 512 TV pixel signals corresponding to one field picture are read out (time tF1). Next, time t
In the period from F1 to tF2, the second field is scanned and read out, and the same operation as in the first field scanned and readout is repeated. Then, 512 respectively indicated by periods F1 and F2
Imaging operations are performed by repeating non-interlaced reading and reading of TV programs. Next, the eighth
The scanning readout operation will be described in detail based on the timing chart for each drive signal and timing signal shown in the figure. Note that the period TVB in FIG. 8 corresponds to the vertical blanking period, the period THB corresponds to the horizontal blanking period, and the period T1H corresponds to the horizontal scanning period. Further, in the figure, the symbol "H" indicates 12 volts, "M" indicates 0 volts, "L" indicates -8 volts, and "HH" indicates a voltage level of about 15 to 25 volts, which is equal to the voltage of the substrate.

[0021] Also, the first field scanning period F1 and the second field scanning period F1 are
Since the operations during the field scanning period F2 are the same, they will be explained in common with reference to FIG. First, in the period TVB corresponding to the vertical blanking period, the timing signal φH
goes to "H" level at a predetermined time t2, otherwise goes to "M" level, timing signal φG always goes to "M" level, and timing signal φFS reaches timing signal φH.
goes to "H" level in synchronization with "H" level, and all other drive signals S1 to Sn output from the third drive circuit 12 are always at "L" level. Become. Therefore, during this period TVB, the timing signal φG at the "M" level causes the first drive circuit 1 to
All the NMOS transistors S1 and S of the third drive circuit 12 are in a conductive state, while all the drive signals S1 and S of the third drive circuit 12 are in a conductive state.
2, S3 to Sn are at "L" level, all NMOS transistors in the second drive circuit 11 become non-conductive, and all gate electrodes G11, G21
, G31 , G41~G1n , G2n , G3n ,
G4n is controlled by the first drive circuit 10. That is, when the timing signals φH and φFS are not at the "H" level, the odd-numbered gate electrodes G11 and G31
, G12, G32 to G1n, and gate signals φ11, φ31, φ12, φ32 to φ1n applied to G3n.
, φ3n are equal to the "L" level signal VL (this signal is always set to -8 volts), and a potential barrier is generated in the vertical charge transfer paths L1 to Lm below these gate electrodes.

On the other hand, even-numbered gate electrodes G21, G
Gate signals φ21, φ41, φ22, φ42 applied to 41, G22, G42 to G2n, G4n
~φ2n, φ4n are equal to the "M" level signal φH, and the vertical charge transfer path L1 under these gate electrodes is
A transfer pixel occurs at ~Lm. therefore,
Portion adjacent to transfer gate Tg (see Figure 4)
all become transfer pixels, and these transfer pixels are separated by a potential barrier. In this state, when the timing signals φH and φFS go to the "H" level at a predetermined time t2, all the npn transistors Q21, Q41, Q61... become conductive, and the even-numbered gate electrodes G21, G41, G22
, G42 to G2n, and G4n are applied with the "H" level substrate voltage VS of approximately 15 to 25 volts, so all transfer gates Tg become conductive, and the pixel signals of all photodiodes are transferred to the respective adjacent transfer pixels. be transferred.

In this way, during the period TVB, a so-called field shift operation is performed, and as shown at time t2 in FIG. will be moved to In addition, FIG. 12 shows the charge transfer operation of a certain vertical charge transfer path, where the part indicated by □ indicates an empty transfer element or a potential barrier, and the shaded part indicates a transfer element in which signal charges exist. . Next, a period TH corresponding to the first horizontal blanking period
In B, since the timing signal φG is always at the "L" level, all NMOS transistors in the first drive circuit 10 are rendered non-conductive and are isolated from all gate electrodes. On the other hand, only the drive signal S1 at the first output terminal of the third drive circuit 12 is at "M" level, and the other drive signal S2
~Sn becomes “L” level, so that the first set of N related to the drive signal S1 in the second drive circuit 11
MOS transistors m11, m21, m31, m
Only 41 becomes conductive.

During the period when only the drive signal S1 is at the "M" level, four-phase timing signals φ1, φ2, φ3, and φ4 for performing vertical charge transfer are input to the second drive circuit 11. , the first to fourth gate signals φ11, φ21, φ31,
Only φ41 has timing signals φ1, φ2, φ3
, φ4, and the charge transfer operation is performed by the first to fourth gate electrodes G11, G21, G31, and G41 of the first set. Note that during this period THB (time t3
FIG. 9 shows enlarged signal waveforms during the period from t4 to t4. As a result, the signal charge becomes the gate signal φ1 in FIG.
1, φ21, φ31, and φ41 (indicated by symbols 1, 2, 3, 4, 5, 6, and 7).
As in the first transfer shown in FIG. 2, the pixel signal q1j of the first row closest to the horizontal charge transfer path 8 is transferred to the horizontal charge transfer path 8, and at the same time, 2
The pixel signal q2j of the row moves to the position of the first row. Next, the first horizontal scanning period T1H (time t4 to t
5), the signal to the gate electrode stops changing, and the horizontal charge transfer path 8 receives the gate signals α1 and α2 at predetermined timing according to the four-phase drive system or the two-phase drive system.
By performing horizontal transfer in synchronization with , pixel signals for the first row are read out.

Next, during the period from time t5 to t7, the same operation as at time t3 to t5 is repeated to read out the pixel signals of the next row. However, at time t3
During the horizontal blanking period THB from ~t4, the drive signals S1 and S2 of the third drive circuit 12 are simultaneously set to "M".
The remaining drive signals S3 to Sn become "L" level. Incidentally, the waveforms of each gate signal during this period THB are shown in an enlarged manner in FIG. As a result, the first to fourth gate electrodes G11 of the first set
~G41 and the fifth to eighth gate electrodes G1 of the second set
2 to G42 are driven by gate signals φ11 to φ41 and φ12 to φ42, which are equal to the timing signals φ1 to φ4, and the pixel signals under these gate electrodes are vertically transferred. That is, according to the timing shown in FIG. 10, as shown in the second vertical scan of FIG.
The pixel signal q2j of the second row moves to the horizontal charge transfer path 8,
Two rows of the third row and one row of the fourth row are transferred to the horizontal charge transfer path 8 side. Then, in the horizontal scanning period T1H from time t6 to t7, the horizontal charge transfer path 8 reads out the pixel signal q2j of the second row.

Next, when the third scanning readout is started from time t7, the drive signal S1 of the third drive circuit 12 is
, S2 and S3 are at "M" level, and the remaining drive signals S4 to Sn are at "L" level, so that the first to twelfth gate electrodes G11 to G4 of the first to third sets are
1, G12 to G42, and G13 to G43 perform vertical charge transfer. Therefore, like the third transfer in FIG. 12, the pixel signal q3j of the third row is transferred to the horizontal charge transfer path 8, and the pixel signal q4 of the fourth to sixth rows
pixel signals j and q5j for two rows each and pixel signal q6j for one row are transferred to the horizontal charge transfer path 8 side. Then, the pixel signal q3j of the third row is read out by the horizontal charge transfer path 8.

From then on, each time the pixel signals of each row are read out,
By sequentially inverting the drive signals S4 to Sn of the third drive circuit 12 to the "M" level, the number of gate electrodes to be driven is sequentially expanded in groups of four,
Last horizontal blanking period THB (time t9 to t1
0), all gate signals φ
11 to φ4n have a waveform equal to the timing signals φ1 to φ4, and the pixel signals of the last row can be read out in the last scanning readout. FIG. 13 shows potential profiles of vertical charge transfer operations in an arbitrary order, that is, the k-th and k+1-th vertical charge transfer operations. By increasing the spacing of empty transferred pixels,
The pixel signals are read out in order from the side closest to the horizontal charge transfer path 8.

[0028] The read pixel signals are subjected to signal processing to form a video signal suitable for the EDTV system. According to the embodiment described above, the number of pixels in the vertical direction is set to the same number as the conventional one compatible with the NTSC system, and the number of corresponding transfer gate electrodes is also kept the same, and the pixel signal is By applying a new non-interlaced scanning readout method that sequentially reads data from the horizontal charge transfer path side like falling dominoes, the ED
Scanning readout with high vertical resolution suitable for TV systems can be realized. Furthermore, since the structure of the light receiving area is simple, the yield can be improved. Furthermore, since the drive circuit that supplies gate signals to the gate electrode is not formed using transistors with a CMOS structure, but is formed using MOS transistors with an NMOS structure and transistors with a bipolar structure, it is possible to realize a drive circuit with high breakdown voltage. It can also be equipped with a vertical overflow drain and an electronic shutter function. By providing a vertical overflow drain structure, the excess charge of the photodiode is discarded to the substrate side, thereby eliminating the occurrence of blooming and the like, and also enabling an electronic shutter without the substrate.

Next, another example of a charge-coupled solid-state imaging device will be described. This embodiment is a non-interline accumulation type charge-coupled solid-state imaging device in which a pixel signal generated in a light receiving area is temporarily held in an accumulation area and then scanned and read out. When applied to an EDTV camera-integrated video tape recorder, the configuration is similar to that shown in FIG. 1. First, the configuration of the charge-coupled solid-state imaging device of this example will be explained with reference to FIG. 14. In FIG. 14, the same parts as in FIG. 2 are designated by the same reference numerals, and the storage section is designated by the reference numeral 100. That is, the light receiving unit 7 for receiving the optical image of the subject corresponds to pixels arranged in a matrix of n pixels along the column direction Y and m pixels along the row direction X, for a total of n×m pixels. A plurality of photodiodes (portions indicated by P in the figure) and m vertical charge transfer paths L1 to Lm are formed adjacent to each photodiode group arranged in the column direction Y.

Furthermore, below the light receiving section 7, an accumulation section 100 having a group of vertical charge transfer paths L1 to Lm is arranged in series. A horizontal charge transfer path 8 is formed at the end of each of the vertical charge transfer paths L1 to Lm of the storage section 100, and an output amplifier 9 is formed at the end of the horizontal charge transfer path 8. Further, the vertical charge transfer paths L1 to Lm are provided with gate electrodes arranged in a predetermined manner, as will be described later, and furthermore, a light shielding layer for blocking the incidence of light is laminated on the upper surface of these gate electrodes. Drive signals for causing the vertical charge transfer paths L1 to Lm to perform charge transfer operations in synchronization with predetermined timing are supplied to these gate electrodes from first, second, and third drive circuits 10, 11, and 12. be done. Note that the timing signals φH, VL, φG, φFS supplied to each drive circuit 10, 11, 12
, VS , φ1 , φ2 , φ3, φ4 , φ
IN, φRS, φA, and φB are generated by the synchronous control circuit 6.

Further, the horizontal charge transfer path 8 receives signal charges transferred from the vertical charge transfer paths L1 to Lm,
Furthermore, gate electrodes are provided for horizontal transfer to the output amplifier 11 side, and gate signals α1 and α2 applied to each gate electrode to perform these operations are supplied from the synchronous control circuit 6 (see Figure 1). be done. Next, the structure of this charge-coupled solid-state imaging device will be described in detail with reference to FIGS. 15 and 16. Note that FIG. 15 shows an enlarged view of the main structure of the light receiving section 7 and the storage section 100, and also shows the circuit configuration of the first and second drive circuits 10 and 11, and FIG. 16 shows the structure of the third drive circuit 10 and 11. The circuit of circuit 12 is shown. First, in FIG. 15, this charge-coupled solid-state imaging device is constructed by embedding layers of appropriate types and impurity concentrations in a semiconductor substrate using semiconductor integrated circuit manufacturing technology, and laminating electrode layers and the like on the semiconductor substrate. It is formed by

The light receiving section 7 is located in a p-well layer (
By arranging a plurality of impurity layers made of n+ type impurities in a matrix along the column direction Y and the row direction X in the photodiode group shown by P in FIG. are P1, P2, P3,
By forming an n-type impurity layer adjacent to each photodiode group arranged in the column direction Y, the vertical charge transfer path L in FIG.
1 to Lm (in FIG. 15, some vertical charge transfer paths L
i-1, Li, Li+1, Li+2) are formed. Furthermore, on the vertical charge transfer path,
One pair of transfer gate electrodes G11, G21, G31, G41, G12 for each row of photodiodes.
, G22 , G32 , G42~G1n/2, G2n
/2, G3n/2, and G4n/2 are stacked. Note that since n rows of photodiodes P1 to Pn are formed in the Y column direction, the total number of transfer gate electrodes is 2.times.n. For convenience of explanation, transfer gate electrodes are generally represented by the symbol Gik, where the subscript k indicates the order of each set of four transfer gate electrodes, and the subscript j indicates the order of the four transfer gate electrodes in each set. The order of transfer gate electrodes is shown. Therefore, the first set (k=1
) transfer gate electrodes are G11, G21, G31,
The transfer gate electrodes of the final set (k=n/2) are G1n/2, G2n/2, G3n/2, G4n.
/2 indicates.

[0033] Then, a portion that will become a transfer gate, shown as Tg in Fig. 15 (only one place is shown as a representative),
A channel stopper (shaded area surrounded by dotted lines in FIG. 15) made of a p+ type impurity layer is formed around the photodiode area and the vertical charge transfer path area. Further, a transfer gate electrode g11 for realizing charge transfer is also provided on the upper surface of the vertical charge transfer path extending to the storage section 100.
, g21, g31, g41, g12, g22, g32,
g42 ~g1n/2, g2n/2, g3n/2
, g4n/2 are stacked, and furthermore, the vertical charge transfer path is surrounded by a channel stopper (shaded area surrounded by a dotted line). Note that the total number of transfer gate electrodes in the region of the storage section 100 is also 2×n, and for convenience of explanation, four transfer gate electrodes are shown as one set. And storage section 10
A horizontal charge transfer path 8 is formed at the end of the vertical charge transfer path group 0 in the same manner as shown in FIG. Since this horizontal charge transfer path 8 has a well-known structure, the details are omitted, but charge transfer is performed by a two-phase drive method using timing signals α1 and α2, a four-phase drive method, or other methods. Further, a drain section for discarding unnecessary charges is formed at the end of the vertical charge transfer path on the light receiving section 7 side.

Next, the first, second and third drive circuits 10,
11 and 12 will be explained. First, the first drive circuit 1
0, if the gate electrode g11 closest to the horizontal charge transfer path 8 of the storage section 100 is the first gate electrode, then the odd-numbered gate electrodes g11, g31, g12, g
32, g13, g33 ~g1n/2, g3n/
Each tip of 2 is an NMOS transistor D11, D31,
D12, D32, D13, D33~D1n/2, D
3n/2 to the signal line of the signal VL, and the even numbered gate electrodes g21, g41, g22, g42, g
23, each tip of g43 to g2n/2, g4n/2 is N
MOS transistors D21, D41, D22, D42,
It is connected to the signal line of the drive signal φH via D23, D43 to D2n/2, D4n/2. Further, a drive signal φG is supplied to the gate contacts of these transistors. For convenience of explanation, these NM
OS transistors also have transfer gate electrodes g11 to g
It is shown corresponding to 4n/2. In addition, in the transfer gate electrode of the light receiving section 7, the transfer gate electrode g on the final side of the storage section 100
If the transfer gate electrode G11 adjacent to 4n/2 is the first transfer gate electrode, the odd-numbered gate electrode G11
,G31,G12,G32,G13,G33~G1n
/2, G3n/2, each tip end is an NMOS transistor M11, M31, M12, M32, M13, M3
3 to M1n/2, M3n/2 to the signal line of the signal VL, and the even numbered gate electrodes G21, G41, G
22, G42, G23, G43 ~ G2n/2, G
Each tip of 4n/2 is an NMOS transistor M21, M
41, M22, M42, M23, M43 ~M2
It is connected to the signal line of the drive signal φH via M4n/2 and M4n/2. Further, a drive signal φG is supplied to the gate contacts of these transistors.

Furthermore, even-numbered gate electrodes G21 and G4
1, G22, G42, G23, G43 ~G4n
/2, npn transistors Q21 and Q4 are installed at each tip.
The emitter contacts of 1, Q22, Q42, Q23, Q43 to Q4n/2 are connected, and the drive signal φFS is connected to the base contact of each npn transistor, and the voltage VS is applied to the collector contact.
is applied. For convenience of explanation, these npn transistors also have transfer gate electrodes G11 to G4n/
2. Next, the second drive circuit 11 receives timing signals φ1 to φ4 supplied from the synchronous control circuit 6.
drive signals SS1, SS from the third drive circuit 12
2~SSn/2, SSn/2+1~NMOS transistors d11, d21 that switch and operate in synchronization with SSn
, d31 , d41 to d4n/2 and m11 , m21
, m31 , m41 ~ m4n/2, and 2
×n NMOS transistors d11, d21, d
31, d41 to d4n/2 are the storage section 100 transfer gate electrodes g11, g21, g31, g41 to
g4n/2 in order, and the remaining 2×n NMOS
Transistors m11, m21, m31, m41~
m4n/2 is the transfer gate electrode G11, G21 of the light receiving section 7
, G31, G41 to G4n/2 in order. For convenience of explanation, NMOS transistors d41 to d4n/2 and m41 to m4n/2 are shown corresponding to the arrangement of transfer gate electrodes g41 to g4n/2 and G41 to G4n/2.

Furthermore, these NMOS transistors of the storage section 100 are arranged in groups of four, and their gate contacts are sequentially supplied with drive signals SS1, SS1, and SMOS of the third drive circuit 14, respectively.
SS2 ~SSn/2, SSn/2+1~ SS
n is applied, and the first NMOS transistors d11, d12, d13, d14 to d1 of each set
Timing signal φ1 is connected to the drain contact of n/2, second NMOS transistor d21, d22, d23
, d24 to d2n/2, the timing signal φ2 is applied to the drain contact of the third NMOS transistor d.
Timing signal φ3 is applied to the drain contacts of 31, d32, d33, d34 to d3n/2, and the fourth NMOS
Transistors d41, d42, d43, d44~
A timing signal φ4 is supplied to the drain contact of d4n/2. Similarly, these NMOS transistors of the light receiving section 7 are also set as a set of four, and the drive signals SSn/2+1, SSn/2+1 of the third drive circuit 12 are applied to their gate contacts in order.
SSn/2+2 to SSn are applied to the first NMOS transistors m11, m12, m13 of each set.
, m14 to m1n/2, the timing signal φ1 is applied to the drain contacts, and the second NMOS transistor m21, m
22, m23, m24 to m2n/2, and the third NMOS transistor m31, m32, m33, m34 to m3.
The timing signal φ3 is connected to the drain contact of n/2, and the fourth NMOS transistor m41, m42, m43
, m44 to m4n/2 are supplied with a timing signal φ4. It should be noted that the signals S11 and S11 in FIG.
S21, S31, S41 ~S4n/2 and I1
1, I21, I31, I41 to I4n/2 are signals supplied to each transfer gate electrode.

As shown in FIG. 16, the third drive circuit 12 receives drive signals SS1, SS2, and S at predetermined timings.
S3, SS4 ~ SSn/2, SSn/2+1
~ It is formed of an n-bit output type shift register that outputs SSn. That is, this shift register transfers the start pulse signal φIN from the lower output bit to the upper output bit in synchronization with the two-phase timing signals φA and φB, as shown in the timing diagram of FIG. The configuration is such that drive signals of logical value "M" are sequentially generated. That is, initially only the lowest drive signal SS1 is at "M" level and the other upper bit outputs are at "M" level.
In the next cycle, the drive signals SS1 and SS2 of the lower two bits are at the "M" level, and the remaining upper bit outputs are at the "L" level.
The "M" level output of the drive signal is sequentially transferred from the lower bit to the upper bit, such that the bit drive signals SS1, SS2, and SS3 are at the "M" level, and the remaining upper bit outputs are at the "L" level. It changes as it expands.

As shown in FIG. 16, the circuit for each bit has a cell structure, and a shift register is constructed by connecting 4×n cell structure circuits in a subordinate manner. Therefore, to explain the circuit of the first bit as a representative,
MOS transistors u11 and u12 are connected in series with their drain-source paths between the signal line of one timing signal φB and the ground terminal, and the gate contact of MOS transistor u11 is connected to the input contact θIN, and the gate contact of MOS transistor u12 is connected to the input contact θIN. is the other timing signal φA
connected to the signal line. A bootstrap capacitor ε11 using a gate oxide film is connected between the gate and drain contacts of the MOS transistor u11, and further,
The drain contacts of the MOS transistor u11 are connected to the intermediate junction θx via the source-drain path of the MOS transistor u13. Also, there is an M between the signal line of the signal VM and the signal line of the signal VL.
OS transistors u14 and u15 have their drain-source paths connected in series, and a signal VM is applied to the gate contact of the MOS transistor u14.
15 gate contacts are connected to the input contact θIN. In addition, there is a MOS between the intermediate junction θX and the signal line of the signal VL.
The transistor u17 is connected, and the connection contact between the MOS transistors u14 and u15 and the MOS transistor u
A MOS transistor u16 is connected between the gate contacts of 17, and a signal φB is connected to the gate contact of the MOS transistor u16.
is applied.

Further, a rear stage circuit having the same structure as the front stage circuit consisting of MOS transistors u11 to u17 and capacitor ε11 is composed of MOS transistors u21 to u27 and capacitor ε21. However, the signals φA and φB applied to the respective gate contacts of the transistor u21 corresponding to the MOS transistor u11, the transistor u22 corresponding to the MOS transistor u12, and the transistor u26 corresponding to the MOS transistor u16 are opposite signals. The input contact of the subsequent circuit is connected to the intermediate contact θX, and the output contact of the transistor u23 is the output contact θO of the first bit. The first bit drive signal SS1 is generated at the drain contact of the MOS transistor u21 in the subsequent circuit, and is wired so as to be supplied to the second drive circuit 13 shown in FIG.

The upper bit circuit is also formed by connecting the input contact θIN and the output contact θO of the remaining circuits having the same cell structure in a subordinate manner. The input contact θIN of the first bit is supplied with a start pulse signal φIN via a MOS transistor u00 to which a timing signal φA is applied to the gate contact. Furthermore, the 16th
Signals ν1 to ν17 generated at each contact point in the figure are the 18th
At the timing shown in the figure, this shift register in particular has the effect of shaping the waveform of each signal propagating inside due to the boosting effect of the bootstrap capacitors ε11 and ε21. Further, the light receiving section 7 and the storage section 100 have a cross-sectional structure as shown in FIGS. 5 and 6.

Next, a case will be described in which the operation of the charge-coupled solid-state imaging device having such a structure is applied to an electronic still camera that takes still images. The current NTSC system obtains a 1/30 second frame image by performing 1/60 second interlaced field scan readout twice for 512 TV scans. On the contrary,
In this embodiment, scanning readout is performed at twice this frequency. That is, by performing non-interlaced field scanning and readout of 512 TV lines twice in 1/60 second, imaging with twice the conventional vertical resolution is performed in 1/30 second. Furthermore, in this embodiment, all of the pixel signals generated in the light receiving section 7 are temporarily stored in the storage section 1 during the period TVB corresponding to the vertical blanking period of a standard television system such as NTSC.
00, and the pixel signals are sequentially read out during the next horizontal blanking period THB and horizontal scanning period T1H.

In FIG. 19, a period F1 is a first field scanning period, and a period F2 is a second field scanning period, both of which are set to 1/60 seconds. At a certain time t1 in the same figure
Assuming that scanning readout of pixel signals is started from
First, during a period TVB corresponding to the vertical blanking period of a standard television system such as NTSC, pixel signals of all photodiodes are simultaneously transferred to vertical charge transfer paths L1 to L.
The data is transferred to the transfer pixel m, and further transferred to the storage unit 100 and temporarily held. During a period THB corresponding to the next horizontal blanking period, the pixel signal of the transfer pixel of the storage section 100 closest to the horizontal charge transfer path 8 is transferred to the horizontal charge transfer path 8, and then, corresponding to the horizontal scanning period. During the period T1H, the horizontal charge transfer path 8 horizontally transfers the pixel signals for one row, thereby reading out the pixel signals of the first row. Note that the period T1H is 1/2 of the so-called 1H period in the case of the current NTSC system.

Then, during the period THB corresponding to the next horizontal blanking period, the vertical charge transfer paths L1 to Lm of the storage section 100 transfer the pixel signals of the next row to the horizontal charge transfer path 8, and then the next horizontal Period T1 corresponding to the scanning period
At H, the horizontal charge transfer path 8 performs horizontal transfer to read out pixel signals in the second row. Furthermore, each period THB corresponding to the next horizontal blanking period and horizontal scanning period
At T1H, the pixel signals of the third row are read out. Then, the pixel signals of the remaining rows are sequentially read out by repeating the same process, and finally all 512 TV pixel signals corresponding to one field picture are read out (time tF1).

Next, the second field is scanned and read out during the period from time tF1 to tF2, and the same operation as in the first field scan and readout is repeated. And period F
The imaging operation is performed by repeating the non-interlaced scanning and readout of 512 TVs indicated by 1 and F2. Hereinafter, the imaging operation in FIG.
Each drive signal and timing signal will be described in detail based on timing charts shown in FIGS. The horizontal axes in FIGS. 20 and 21 are shown on the same time scale, and the period TVB in the figures corresponds to the vertical blanking period, the period THB corresponds to the horizontal blanking period, and the period T1H corresponds to the horizontal scanning period. ing. Furthermore, FIG. 22 shows an enlarged view of the main timing during the high-speed transfer period TVBF in FIGS. 20 and 21, and furthermore,
FIG. 23 shows signals S11 to S41, S12 to S12 in FIG.
The timing of each portion surrounded by dotted lines from S42 to S1n to S4n is shown in an enlarged manner. Also, in these figures, the symbol "H" is 12 volts, "M" is 0 volts, "
"L" indicates a voltage level of -8 volts, and "HH" indicates a voltage level of about 15 to 25 volts, which is equal to the voltage of the semiconductor substrate.

First, the operation of the vertical blanking period TVB will be explained. As shown in FIGS. 20 and 21, a field shift operation is performed at the initial time point t2 of the vertical blanking period TVB. That is, the signals φG and φH
As the field shift signal φFS becomes "H" level, all npn transistors Q21, Q41
, Q22, Q42 ~ become conductive, and the even numbered transfer gate electrodes G21, G41, in the light receiving section 7
“H” for G22, G42~G2n/2, G4n/2
Level signals I21, I41, I22, I42
~ I2n/2, I4n/2 are applied to odd numbered transfer gate electrodes G11, G31, G12, G3
2~G3n/2, G3n/2 equal to signal VL"
L” level signals I11, I31, I12, I3
2 to I1n/2, I3n/2 are applied.

Furthermore, at this time t2, all the output signals SS1 to SSn of the third drive circuit 12 are at "L" level, so that the transistor d11 in the second drive circuit 11 is
~d4n/2 and m11~m4n/2 become non-conductive, and transfer gate electrodes g11~g4n/2 and G11~G
4n/2 and the third drive circuit 12 are electrically cut off. Therefore, at time t2, even-numbered transfer gate electrodes G21, G41, G22, G42 to G2n/2
, G4n/2, potential wells (transfer pixels) are generated corresponding to all the photodiodes, and at the same time, the odd-numbered transfer gate electrodes G11, G31, G
12, G32 ~ G1n/2, Since a potential barrier is generated under G3n/2, all pixel signals are transferred to these potential wells (transfer pixels) via the transfer gate Tg without mixing with each other. . Then, when field shift signal φFS goes to "L" level, transfer gate Tg is cut off again.

Next, TVBF for a predetermined period following time t2
During this process, all pixel signals are transferred from the light receiving section 7 to the storage section 100 at high speed. That is, as shown in FIG. 20, during this period TVBF, the signal φFS is always set to the "L" level, the signal φH is always set to the "M" level, and the signal φG is a signal with the same timing as the inverted signal φA. becomes. As shown in FIG. 22, when the start pulse signal φIN is applied to the shift register constituting the third drive circuit 12, the signals SS1 to SSn are sequentially " From “L” level to “M”
” level, and in synchronization with this, the second drive circuit 11
Transistors d11 to d4n/2 and m11 to m4n inside
/2 are sequentially turned on in groups of four. As a result, transistors d11 to d4n/2 and m1
The signals φ1 to φ4 are transferred to the transfer gate electrodes g11 to g via the transistors 1 to m4n/2 that are in the on state.
4n/2 and G11 to G4n/2, and become transfer gate signals S11 to S4n/2 and I11 to I4n/2.

That is, transfer gate signals synchronized with the signals φ1 to φ4 are generated within the rectangular range indicated by the dotted lines in FIG. 22, and the timings within the rectangular range indicated by the dotted lines of the transfer gate signals S11 to S41 are representative. The waveform becomes as shown in FIG. 23. When charge transfer is performed at such timing, the range of transferred pixels changes like so-called dominoes, so the first row of the light receiving section 7 (row P1 in FIG. 15)
The second row from the signal charge (row P2 in FIG. 15),
The data is transferred to the storage unit 100 in the order of the third line (line P3 in FIG. 15).

Further, this charge transfer operation will be explained using a typical example shown in FIG. The figure representatively shows the operation of one vertical charge transfer path, and the four signal charges q1, q2, q3, q4 generated by the four photodiodes are
The case where the data is transferred to the storage unit 8 is shown. It is also assumed that the shaded portions are each signal charge within the transfer pixel, and □ is a potential barrier or an empty transfer pixel. First, time t2
The signal charges q1, q2, q3, and q4 are field-shifted to the transfer pixel, and the transfer of the signal charge q1 starts from the timing of the code "1", and the transfer of the signal charge q2 starts from the timing of the code "3", “9”
The transfer of signal charge q3 starts from the timing of “1
Transfer of the signal charge q4 starts from the timing of 1". In this way, the signal charge q4 is transferred in order starting from the storage section 100 side.
This is because the transferred pixels gradually expand from the boundary portion (indicated by the dashed-dotted line in the figure) like a so-called domino effect. Then, at the timing of "28", the signal charges q1, which were present in the light receiving section 7 at the timing of "0",
q2, q3, q4 have the same arrangement and are stored in storage unit 1.
It is accommodated in the transfer element 00.

[0050] When all the signal charges have been transferred to the storage section 100 in this way, the contents of the third drive circuit 12 are reset, and then the readout operation of the signal charges is performed in synchronization with the horizontal scanning timing. Start. That is, FIG. 20 and FIG.
To explain based on FIG. 1, during the first horizontal blanking period THB (period from time t3 to t4), the signal φG
is always at the "L" level, so the first drive circuit 10
All NMOS transistors inside become non-conductive,
Electrically isolated from all transfer gate electrodes. or,
The third drive circuit 12 receives signals φA and φ of the first period.
Even if B is applied, all outputs are still at the "L" level, so no signal charge transfer operation is performed.

Next, the first horizontal scanning period THB (time t
4 to t5), the horizontal charge transfer path 8 performs horizontal transfer in synchronization with the gate signals α1 to α4 at predetermined timing according to the four-phase drive method or the two-phase drive method, so that the horizontal charge transfer path 8 Discard unnecessary charges to the outside. Next, the second horizontal blanking period THB (time t
5 to t6), only the drive signal SS1 of the first output terminal of the third drive circuit 12 is the signal φA, φB.
"M" level in synchronization with the other drive signals SS2 to SS
When n becomes "L" level, only the first set of NMOS transistors d11, d21, d31, and d41 related to the drive signal SS1 in the second drive circuit 11 become conductive.

[0052] During the period when only the drive signal SS1 is at the "M" level, the four-phase timing signals φ1, φ2, φ3, φ4 for performing vertical charge transfer are input to the second drive circuit 11. , the first to fourth first set of gate signals S11, S21, S31,
Only S41 uses timing signals φ1, φ2, φ3
, φ4, and the charge transfer operation is performed by the first to fourth gate electrodes g11, g21, g31, and g41 of the first set. As a result, the pixel signals of the first row closest to the horizontal charge transfer path 8 are transferred to the horizontal charge transfer path 8, and the pixel signals of the second row are moved to the position of the first row. . Next, the second horizontal scanning period T
1H (period between time points t6 and t7), the change in the signals to the transfer gate electrodes g11 to g4n/2 stops, and on the other hand,
The horizontal charge transfer path 8 performs horizontal transfer in synchronization with the gate signals α1 and α2 at predetermined timing according to the four-phase drive method or the two-phase drive method, so that the pixel signals for the first row are transferred in dot-sequential scanning. Read at the right time.

Next, during the period from time t7 to t8, the same operation as at time t5 to t6 is repeated to read out the pixel signals of the next row. However, at time t7
During the horizontal blanking period THB from ~t8, the drive signals SS1 and SS2 of the third drive circuit 12 are simultaneously set to "M".
The remaining drive signals SS3 to SSn become "L" level. As a result, the first to fourth gate electrodes g11 to g41 and the fifth to eighth gate electrodes g12 to g42 correspond to the timing signals φ1 to φ4.
The pixel signals under these gate electrodes are vertically transferred. Then, by repeating the same charge transfer operation, the output of the third drive circuit 12 gradually increases to the "M" level, thereby reading out the signal charges in the remaining rows.

The signal charge in the last row (the row closest to the light receiving section 7) is at time t9 in FIGS. 20 and 21.
The signals are vertically transferred to the horizontal charge transfer path 8 during the period from t10 to t10, and further read out by the horizontal charge transfer path 8 during the horizontal transfer period from time t10 to t11, completing the reading of all signal charges for one frame. Thus, according to this embodiment,
Since the vertical charge transfer path transfers the signal charges in a so-called domino-like manner starting from the row closest to the output side, it is possible to reduce the number of transfer gate electrodes, making it possible to implement a high vertical resolution imaging device required for an EDTV system. can be provided.

[0055]

As explained above, according to the present invention, pixel signals in the vertical charge transfer path are scanned and read out sequentially from the horizontal charge transfer path side in a so-called domino pattern, so that the transfer gate electrode The number can be reduced, and as a result, it becomes easy to increase the resolution, making it possible to perform high-resolution scanning readout that is compatible with the EDTV system. Further, by reducing the number of transfer gate electrodes, it is possible to improve the yield in manufacturing using semiconductor manufacturing technology.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an EDTV camera-integrated videotape recorder to which a charge-coupled solid-state imaging device according to an embodiment of the present invention is applied.

FIG. 2 is a schematic configuration diagram of a charge-coupled solid-state imaging device according to an embodiment.

FIG. 3 is a circuit diagram showing the configuration of a third drive circuit according to an embodiment.

FIG. 4 is an explanatory diagram showing the main part structure and peripheral circuit configuration of a light receiving section in one embodiment.

FIG. 5 is a longitudinal sectional view taken along the line xx in FIG. 4;

6 is a longitudinal sectional view taken along the line y-y in FIG. 4; FIG.

FIG. 7 is an explanatory diagram schematically showing the scanning readout operation of one embodiment.

FIG. 8 is a timing chart showing in detail the scanning readout operation of one embodiment.

9 is a timing chart showing an enlarged view of the main timing in FIG. 8; FIG.

10 is a timing chart showing an enlarged view of the main timing in FIG. 8; FIG.

11 is a timing chart showing an enlarged view of the main timing in FIG. 8; FIG.

FIG. 12 is a diagram conceptually showing a charge transfer operation during scanning readout in one embodiment.

FIG. 13 is a diagram showing a charge transfer operation during scanning readout in one embodiment using a potential profile.

FIG. 14 is a schematic configuration diagram of a charge-coupled solid-state imaging device according to another example.

FIG. 15 is an explanatory diagram showing the main part structure and peripheral circuit configuration of a light receiving section in another embodiment.

FIG. 16 is a circuit diagram showing the configuration of a third drive circuit in another embodiment.

17 is a timing chart illustrating the operation of the third drive circuit shown in FIG. 16. FIG.

18 is a timing chart illustrating the operation of the third drive circuit shown in FIG. 16. FIG.

FIG. 19 is an explanatory diagram schematically showing a scanning readout operation in another embodiment.

FIG. 20 is a timing chart showing the operation of FIG. 19 in detail.

FIG. 21 is a timing chart showing the operation of FIG. 19 in detail.

22 is a timing chart showing in detail the operation during the high-speed charge transfer period in FIGS. 20 and 21. FIG.

FIG. 23 is a timing chart for explaining in detail the operation of the main parts in FIG. 22;

FIG. 24 is an explanatory diagram schematically showing a scanning readout operation in another embodiment.

FIG. 25 is a diagram showing the configuration of an EDTV television system.

FIG. 26 is a diagram illustrating the operating principle of an EDTV television system.

FIG. 27 is a diagram illustrating the configuration of a charge-coupled imaging device applied to a conventional EDTV system.

FIG. 28 is a diagram illustrating the configuration of another charge-coupled imaging device applied to the conventional EDTV system.

FIG. 29 is a diagram illustrating the configuration of another charge-coupled imaging device applied to the conventional EDTV system.

[0011]

[Explanation of symbols]

1; Imaging optical system 2; Mechanical aperture mechanism 3; Charge-coupled solid-state imaging device 4; Signal processing circuit 5; Recording mechanism 6; Synchronization control circuit 7; Light receiving section 8; Horizontal charge transfer path 100; Horizontal charge transfer path 10, 11, 12; Drive circuits L1 to Lm; Vertical charge transfer paths M11, M21, M31, M41 to; NMOS transistors D11, D21, D31, D41 to;
NMOS transistors d11, d21, d31,
d41~; NMOS transistors m11, m21,
m31, m41~; NMOS transistor G11,
G21, G31, G41~; Transfer gate electrode g11
, g21 , g31 , g41 ~; Transfer gate electrode Q
21, Q41, Q22, Q42~; Transfer gate electrode.

Claims (2)

[Claims] 1. A plurality of photoelectric conversion elements corresponding to pixels are arranged in a matrix in the row and column directions, and a vertical charge transfer path is formed adjacent to each group of photoelectric conversion elements arranged in the column direction. After transferring the pixel signal generated in the pixel to the vertical charge transfer path of the light receiving section, a gate signal at a predetermined timing is applied to the transfer gate electrode of the vertical charge transfer path of the light receiving section, and a horizontal In a charge-coupled solid-state imaging device in which pixel signals for each row are scanned and read out using a charge transfer path, two transfer gate electrodes of the light receiving section are provided corresponding to each photoelectric conversion element, and when scanned and read out, two transfer gate electrodes are provided adjacent to each other. By forming a predetermined number of sets of transfer gate electrodes and applying a gate signal at a predetermined timing sequentially from the set of transfer gate electrodes closest to the horizontal charge transfer path side, the transfer gate electrodes are placed in the row closest to the horizontal charge transfer path side. 1. A charge-coupled solid-state imaging device characterized in that pixel signals are sequentially transferred starting from pixel signals, and further, one frame's worth of scanning readout is performed by performing two non-interlaced field scanning readouts. 2. A plurality of photoelectric conversion elements corresponding to pixels are arranged in a matrix in the row and column directions, and a vertical charge transfer path is formed adjacent to each group of photoelectric conversion elements arranged in the column direction. and an accumulation section having a vertical charge transfer path connected to these vertical charge transfer paths of the light receiving section, the pixel signal generated in the pixel being transferred to the vertical charge transfer path of the light receiving section. After that, by applying a gate signal at a predetermined timing to the transfer gate electrode of the vertical charge transfer path of the light receiving section and the storage section, all pixel signals are transferred at high speed to the vertical charge transfer path of the storage section. In a charge-coupled solid-state imaging device in which a gate signal at a predetermined timing is applied to a transfer gate electrode of a vertical charge transfer path in a section, and pixel signals for each row are scanned and read out by a horizontal charge transfer path,
Two transfer gate electrodes are provided in the light receiving section corresponding to each photoelectric conversion element, and the number of transfer gate electrodes in the storage section is formed to be equal to the number of transfer gate electrodes in the light receiving section. A predetermined number of sets of mutually adjacent transfer gate electrodes are formed, and a gate signal is applied at a predetermined timing sequentially from the set of transfer gate electrodes closest to the storage section.
Application of gate signals to the transfer gate electrodes in the storage section is stopped from the set closest to the horizontal charge transfer path, and during scanning readout, a predetermined number of sets of adjacent transfer gate electrodes are arranged in the storage section. By applying gate signals at a predetermined timing sequentially from the set of transfer gate electrodes closest to the horizontal charge transfer path side, pixel signals are transferred in order from the row closest to the horizontal charge transfer path side, and further, 2
Based on the non-interlaced field running readout,
A charge-coupled solid-state imaging device characterized by scanning and reading out one frame.