GB2065974A - Integrated CCD Image Sensor of the Interline Transfer Type - Google Patents
Integrated CCD Image Sensor of the Interline Transfer Type Download PDFInfo
- Publication number
- GB2065974A GB2065974A GB8039991A GB8039991A GB2065974A GB 2065974 A GB2065974 A GB 2065974A GB 8039991 A GB8039991 A GB 8039991A GB 8039991 A GB8039991 A GB 8039991A GB 2065974 A GB2065974 A GB 2065974A
- Authority
- GB
- United Kingdom
- Prior art keywords
- register
- ccd
- image sensor
- elements
- vertical shift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005036 potential barrier Methods 0.000 claims abstract description 13
- 239000011159 matrix material Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
Abstract
An interline transfer CCD image sensor includes 488x385 PN junction photosensor elements 14 disposed in a matrix fashion. 385 columns of CCD vertical shift registers are associated with the matrix aligned PN junction photosensor elements. Each CCD vertical shift register includes 488 register elements, each of which includes a buried channel 38 connected to a corresponding PN junction photosensor element 14 via a surface channel potential barrier 28. A register electrode 42 formed on the buried channel 38 is extended toward the corresponding PN junction photosensor element 14 to cover the surface channel potential barrier 28. A three level drive signal is applied to the register electrode 42 to control the charge transfer operation from the PN junction photosensor element 14 to the buried channel 38 in addition to control the shift operation in the CCD vertical shift register. <IMAGE>
Description
SPECIFICATION integrated CCD Image Sensor of the Interline
Transfer Type
Background and Summary of the Invention
The present invention relates to a CCD (Charge-Coupled-Device) image sensor including PN-junction photosensor elements.
Recently, an interline transfer CCD image sensor has been developed for use in a video camera. The conventional interline transfer CCD image sensor comprises a plurality of shift register implemented with CCD and a plurality of photosensor elements made of CCD. That is, the entire electrodes on the image sensor are made of semitransparent polysilicon. Therefore, the conventional CCD image sensor shows the low blue sensitivity due to the semitransparency of the polysilicon electrode formed on the photosensor CCD element.
To enhance the blue sensitivity, it is proposed to employ PN-junction photosensor elements associated with each of the CCD shift register elements. However, the thus proposed CCD image sensor requires a transfer gate electrode, for transferring the photogenerated charges collected in the PN-junction photodiode to the
CCD shift register element, in addition to the twolayered register electrodes inevitably required for the shift register operation. Hence, the electrodes must be three-layered construction.
Accordingly, an object of the present invention is to provide an interline transfer CCD image sensor showing high sensitivity.
Another object of the present invention is to provide a highly integrated CCD image sensor including PN-junction photosensor elements.
Still another object of the present invention is to minimize the required electrode number in an interline transfer CCD image sensor including PNjunction photosensor elements.
Yet another object of the present invention is to provide an interline transfer CCD image sensor suited for mass production.
Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
To achieve the above objects, pursuant to an embodiment of the present invention, a PNjunction photosensor element is connected to a buried channel of CCD via a surface channel potential barrier. A polysilicon register electrode formed on the burried channel is extended to the surface channel formed between the burried channel and the PN-junction photodiode, thereby eliminating the transfer gate electrode. The thus constructed unit cell is aligned in a vertical direction by 488 to form a vertical shift register.
The thus formed vertical shift register is provided by 385 columns, whereby a 488x385 matrix interline transfer CCD image sensor is formed.
In a preferred form, a three-level drive signal is applied to the polysilicon register electrode. The first and second levels function as a clock pulse for the shift operation. The third level functions as a timing signal for transferring photogenerated charges collected in the photodiodes to the CCD vertical shift registers. Output signals of the CCD vertical shift registers are applied to a CCD horizontal shift register in a parallel fashion, which develops a video output signal through an output amplifier.
Brief Description of the Drawings
The present invention will be better understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein:
Figure 1 is a block diagram of a conventional interline transfer CCD image sensor including PN junction photosensor elements;
Figure 2 is a sectional view of a unit cell included in the conventional interline transfer
CCD image sensor of Figure 1;
Figure 3 is a time chart showing drive signals applied to the conventional interline transfer CCD image sensor of Figure 1;
Figure 4 is a block diagram of an embodiment of an interline transfer CCD image sensor of the present invention;
Figure 5 is a plan view of an essential part of the interline transfer CCD image sensor of Figure 4;;
Figure 6 is a sectional view taken along line VI-VI of Figure 5;
Figure 7 is a sectional view taken along line VIl-VIl of Figure 5;
Figure 8 is a time chart showing drive signals applied to the interline transfer CCD image sensor of Figure 4;
Figures 9 and 10 are time charts showing other examples of the driven signals to be applied to the interline transfer CCD image sensor of
Figure 4; and
Figure 11 is a schematic chart showing potential relationships between the PN-junction, surface channel and buried channel formed in the interline transfer CCD image sensor of Figure 4.
Description of the Preferred Embodiments
In order to facilitate a more complete understanding of the present invention, the conventional interline transfer CCD image sensor including PN junction photosensor elements will be first described with reference to Figures 1 to 3.
A plurality of CCD vertical shift registers 10 are connected to a CCD horizontal shift register 12 in a parallel fashion. Each CCD register element 100 of the CCD vertical shift register 10 is connected to a PN junction photosensor element 14 via a potential barrier 16 and a transfer gate 18. The
CCD vertical shift register 10 includes, for example, 488 CCD register elements 100.
Adjacent two CCD register elements 100 in the
CCD vertical shift register 10 are combined to each other to form one bit storage element. A first clock signal Xv is applied to the odd numbered
CCD register elements 100, and a second clock signal Xv2, which has a phase opposite to the first clock signal 5v, as shown in Figure 3, is applied to the even numbered CCD register elements 100.
The CCD horizontal shift register 12 receives clock signals XHr and XH2 to develop a video signal Vout through an output amplifier 20.
Figure 2 shows a unit cell construction. An N+ diffusion layer 22 and an N- diffusion layer 24 are formed on a P-type semiconductor substrate 26 with a predetermined distance therebetween, thereby forming the PN junction photosensor element 14 and a buried channel for the CCD register element 100, respectively. A surface channel 28 is formed between the diffusion layers 22 and 24, which functions as the potential barrier 16. A transparent insulator layer 30 made of SiO2 is formed on the semiconductor substrate 26 to cover the substrate surface. A polysilicon transfer gate electrode 32 is formed above the surface channel 28, and a polysilicon register electrode 34 is formed above the N- diffusion layer 24 and the surface channel 28. That is, the register electrode 34 covers the buried channel, and is extended over the transfer gate electrode 32.The above-mentioned first or second clock signal Xvg or fv2 is applied to the register electrode 34 to perform the shift register operation, and a transfer clock signal ~TG is applied to the transfer gate electrode 32 to control the transfer operation of the photogenerated charges collected in the PN junction photosensor element 14 toward the buried channel of the CCD register element 1 00.
An aluminum light shield 36 is formed on the substrate except the N+ diffusion layer 22.
The above-discussed interline transfer CCD image sensor of the prior art requires the transfer gate electrode 32 in addition to the two-layered register electrode 34. That is, the polysilicon electrode must be the three-layered construction.
The present invention is to eliminate the transfer gate electrode 32. Figures 4 through 7 show an embodiment of an interline transfer CCD image sensor of the present invention. Like elements corresponding to those of Figures 1 and 2 are indicated by like numerals.
The CCD vertical shift register 10 includes 488
CCD register elements 100. 385 CCD vertical shift registers 10 are connected to the CCD horizontal shift register 12 in a parallel fashion, whereby the 488x385 matrix image sensor is formed. The CCD register element 100 is
connected to the PN junction photosensor element 100 via the potential barrier 1 6. A first
clock signal fv is applied to the odd numbered
CCD register elements 100, and a second clock signal stV2, which has a phase opposite to the first clock signal v, as shown in Figure 8, is applied to the even numbered CCD register elements 100.A preferred frequency of the first and second clock signals ~v and v is 15.75 KHz, and a preferred frequency of the horizontal shift register clock signals 4H1 and ~H2 is 7.16 MHz.
Figures 5 5 through 7 show the device structure of the interline transfer CCD image sensor of the present invention. The N- diffusion layer 24 is formed on the P-type semiconductor substrate 26 to provide a buried channel 38 for the CCD vertical shift register 10. The N+ diffusion layer 22 is also formed on the P-type semiconductor substrate 26 to provide the PN junction photosensor element 14. The N+ diffusion layer 22 and the N- diffusion layer 24 are spaced apart from each other to provide the surface channel 28 therebetween. A channel stopper 40 is formed between the adjacent two PN junction photosensor elements 14, and between the PN junction photosensor element 14 and the adjacent buried channel 38 not associated with the specific PN junction photosensor element 14.
The buried channel 38 is constructed to always have the potential higher than the surface channel 28 as shown in Figure 11.
The SiO2 transparent insulator layer 30 is formed on the entire surface of the semiconductor substrate 26. A first polysilicon register electrode 42 is formed on the insulator layer 30 to cover the buried channel 38 and the surface channel 28. A second polysilicon register electrode 44 is also formed on the insulator layer 30 to cover the buried channel 38 not covered by the first register electrode 42. The first and second register electrodes 42 and 44 slightly overlap each other as shown in Figure 7 and aligned, one after the other, in the vertical direction to provide the CCD vertical shift register 10. The aluminum light shield 36 is formed on the first and second register electrodes 42 and 44.
The adjacent first and second register electrodes 42 and 44 are combined with each other to receive the same clock signal Xva or fv2 More specifically, a specific pair of the first and second register electrodes 42 and 44 receives the first clock signal fvr, and the adjacent pair of the first and second register electrodes 42 and 44 receives the second clock signal Xv2 as shown in
Figure 7. The first and second clock signals fvt and dv are three-level drive signals as shown In Figure28. At a timing of the high level, photogenerated charges which are collected in the PN junction photosensor element 14 are transferred to the buried channel 38 of the CCD register element 100. The intermediate level and the low level function as the shift timing signal of the CCD vertical shift register 10 for transferring the stored charges toward the CCD horizontal shift register 12. While the intermediate and low levels appear, the photogenerated charges collected in the PN junction photosensor element
14 are not transferred to the buried channel 38.
Preferred voltages of the high, intermediate and
low eves are 1 1 V, 6 V and 0 V, respectively.
It is well known that charges are generated and collected in the PN junction photosensor element 14 in response to the light beam impinging thereon. The thus collected charges are transferred to the buried channel 38 when the clock signal Xv, or 4,2 bears the high level (t12- t13, t22-t23, t32-t33 in Figure 8) because the potential level of the potential barrier 1 6 becomes high. It will be clear from Figures 4 and 8 that the charges collected in the PN junction photosensor elements 14 associated with the odd numbered
CCD register elements 100 are transferred to the buried channel 38 when the first clock signal Xv, bears the high level.The PN junction potential is reset to the potential of the potential barrier 1 6 when the transfer operation is completed. The thus transferred charges are shifted in the CCD vertical shift registers 10 toward the CCD horizontal shift register 12 in response to the low level-intermediate level repetition of the first and second clock signals ~vs and Xv .The shift operation has been completed till the second clock signal Xv2 bears the high level.The PN junction photosensor elements 14 perform the charge collecting operation until the next high level appears in the first clock signal Xv The charges collected in the PN junction photosensor elements 14 associated with the even numbered CCD register elements 100 are transferred to the buried channel 38 when the second clock signal ~v2 bears the high level. Then, the transferred charges are shifted in the CCD vertical shift registers 10 toward the CCD horizontal shift register 12 in response to the low level-intermediate level repetion of the first and second clock signals sXv1 and fv . The shift operation has been completed till the first clock signal XvX bears the next high level.The PN junction photosensor elements 14 initiate the charge collecting operation when the abovementioned transfer operation is completed, and the collecting operation continues till the next high level of the second clock signal sJv2 The above-mentioned operation is repeated to obtain the video output Vout through the output amplifier 20 in the interlace fashion.
The drive fashion is not limited to the abovementioned two-phase interlace type. A threephase drive or a four-phase drive can be employed. Moreover, the clock signals 4,1 and fv2 are not limited to the waveforms as shown in
Figure 8. Figure 9 shows another example of the clock signals v1 and Xv2 applicable to the CCD image sensor of Figure 4.
Figure 8 shows the clock signals 5v, and 49 suited for the frame accumulation/interlace drive.
Figure 10 shows still another example of the clock signals Xv, and (jv2 suited for the field accumulation/interlace drive.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following
Claims (9)
1. An interline transfer CCD image sensor comprising:
a CCD vertical shift register including a plurality of CCD register elements;
a plurality of PN junction photosensor elements aligned along said CCD vertical shift register, each one of said plurality of PN junction photosensor elements being associated with a corresponding one of said plurality of CCD register elements to form a sensor unit; and
a potential barrier interposed between said one of said plurality of PN junction photosensor elements and said corresponding one of said plurality of CCD register elements in said sensor unit, said corresponding one of said plurality of
CCD register elements comprising:
a buried channel; and
a register electrode formed on said buried
channel for performing a shift operation in
said CCD vertical shift register, said register
electrode being extended toward said one
of said plurality of PN junction photosensor
elements to cover said potential barrier and
reach the edge of said one of said plurality of
PN junction photosensor elements included
in said sensor unit.
2. The interline transfer CCD image sensor of
Claim 1, wherein said CCD vertical shift register and said plurality of PN junction photosensor elements are integrated on a semiconductor substrate, and wherein said potential barrier comprises a surface channel formed between said buried channel and said PN junction photosensor element included in said sensor unit.
3. The interline transfer CCD image sensor of
Claim 1, further comprising a drive source for applying a drive signal to said register electrode, said drive signal being a three-level signal, wherein:
the low and intermediate levels function as a clock signal for performing the shift operation in said CCD vertical shift register; and
the high level functions as a timing signal for transferring charges corrected in said PN junction photosensor element to said buried channel in said corresponding CCD register element.
4. The interline transfer CCD image sensor of
Claim 1, 2 or 3, wherein said CCD vertical shift register is provided by a plural number to form a matrix shaped image sensor.
5. The interline transfer CCD image sensor of
Claim 4, wherein said matrix image sensor comprises:
385 columns of CCD vertical shift registers; and
each of CCD vertical shift registers includes 488 CCD register elements.
6. The interline transfer CCD image sensor of
Claim 5, further comprising:
a CCD horizontal shift register connected to receive output signals of said 385 columns of
CCD vertical shift registers in a parallel fashion; and
an amplifier for providing a video signal in response to an output signal of said CCD horizontal shift register.
7. A CCD image sensor comprising a CCD shift register having a plurality of CCD register elements each of which has a register electrode to which signals can be applied to perform register shift operations, and a plurality of photosensor elements each associated with a respective register element but separated therefrom by a potential barrier, wherein each register electrode is so arranged as to be capable, by application of a voltage thereto, of overcoming said potential barrier and thereby controlling charge transfer to the register element from the associated photosensor element.
8. A sensor as claimed in Claim 7, wherein the register electrode is operable to cause a register shift operation to be performed upon application thereto of a voltage of a first level, and is operable to cause charge transfer from the photosensor element to the register element upon application thereto of a voltage of a second, higher level.
9. A CCD image sensor substantially as herein described with reference to Figures 4 to 1 1 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16338079A JPS5685981A (en) | 1979-12-15 | 1979-12-15 | Solid image pickup apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2065974A true GB2065974A (en) | 1981-07-01 |
| GB2065974B GB2065974B (en) | 1984-02-15 |
Family
ID=15772776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8039991A Expired GB2065974B (en) | 1979-12-15 | 1980-12-12 | Integrated ccd image sensor of the interline transfer type |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS5685981A (en) |
| DE (1) | DE3047216C2 (en) |
| GB (1) | GB2065974B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2509909A1 (en) * | 1981-07-20 | 1983-01-21 | Sony Corp | IMAGE DETECTOR IN SOLID STATE |
| EP0073144A2 (en) * | 1981-08-20 | 1983-03-02 | Matsushita Electric Industrial Co., Ltd. | Solid state image sensor |
| EP0100199A2 (en) * | 1982-07-19 | 1984-02-08 | Sharp Kabushiki Kaisha | An interline transfer CCD image sensor and a drive circuit therefor |
| EP0103023A1 (en) * | 1982-02-19 | 1984-03-21 | Sony Corporation | Solid-state image pickup device |
| EP0106286A2 (en) * | 1982-10-07 | 1984-04-25 | Kabushiki Kaisha Toshiba | Solid state image sensor |
| FR2540291A1 (en) * | 1983-02-01 | 1984-08-03 | Philips Nv | SEMICONDUCTOR LOADING VIEWING DEVICE |
| EP0185343A1 (en) * | 1984-12-19 | 1986-06-25 | Kabushiki Kaisha Toshiba | Charge transfer device |
| EP0185990A1 (en) * | 1984-12-06 | 1986-07-02 | Kabushiki Kaisha Toshiba | Charge coupled device |
| EP0212803A1 (en) * | 1985-08-13 | 1987-03-04 | Mitsubishi Denki Kabushiki Kaisha | Solid-state image sensor |
| EP0213803A1 (en) * | 1985-08-13 | 1987-03-11 | Mitsubishi Denki Kabushiki Kaisha | Solid-state image sensor |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56104582A (en) * | 1980-01-25 | 1981-08-20 | Toshiba Corp | Solid image pickup device |
| JPS56147569A (en) * | 1980-04-18 | 1981-11-16 | Nec Corp | Charge transfer image pickup device and its driving method |
| JPS56159900A (en) * | 1980-05-14 | 1981-12-09 | Matsushita Electronics Corp | Method for driving electric charge transfer element |
| DE3121494A1 (en) * | 1981-05-29 | 1983-01-05 | Siemens AG, 1000 Berlin und 8000 München | ARRANGEMENT FOR THE CONTACTLESS MEASUREMENT OF ELECTRICAL CHARGE IMAGES IN ELECTRORADIOGRAPHIC RECORDING METHODS |
| JPS5813080A (en) * | 1981-07-16 | 1983-01-25 | Matsushita Electric Ind Co Ltd | Solid-state image pickup element |
| DE3138314A1 (en) * | 1981-09-25 | 1983-04-14 | Siemens AG, 1000 Berlin und 8000 München | TWO-DIMENSIONAL SEMICONDUCTOR IMAGE SENSOR HIGH PACKING DENSITY WITH PHOTOCONDUCTOR LAYER |
| DE3138295A1 (en) * | 1981-09-25 | 1983-04-14 | Siemens AG, 1000 Berlin und 8000 München | TWO-DIMENSIONAL SEMICONDUCTOR IMAGE SENSOR WITH HIGH PACKING DENSITY |
| JPS5931056A (en) * | 1982-08-13 | 1984-02-18 | Mitsubishi Electric Corp | Solid-state image pickup element |
| DE3236146A1 (en) * | 1982-09-29 | 1984-03-29 | Siemens AG, 1000 Berlin und 8000 München | TWO-DIMENSIONAL SEMICONDUCTOR IMAGE SENSOR AND METHOD FOR ITS OPERATION |
| JPS604380A (en) * | 1983-06-22 | 1985-01-10 | Matsushita Electric Ind Co Ltd | Solid-state image pickup device |
| JPS604379A (en) * | 1983-06-22 | 1985-01-10 | Matsushita Electric Ind Co Ltd | Solid-state camera |
| JPS60134677A (en) * | 1983-12-23 | 1985-07-17 | Sony Corp | Method of driving solid-state image pickup device |
| JP2714379B2 (en) * | 1986-06-27 | 1998-02-16 | テキサス インスツルメンツ インコ−ポレイテツド | Charge-coupled device |
| JPH02131682A (en) * | 1989-09-07 | 1990-05-21 | Matsushita Electric Ind Co Ltd | Solid-state image pickup device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5451318A (en) * | 1977-09-29 | 1979-04-23 | Sony Corp | Solid pickup unit |
-
1979
- 1979-12-15 JP JP16338079A patent/JPS5685981A/en active Pending
-
1980
- 1980-12-12 GB GB8039991A patent/GB2065974B/en not_active Expired
- 1980-12-15 DE DE19803047216 patent/DE3047216C2/en not_active Expired
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2509909A1 (en) * | 1981-07-20 | 1983-01-21 | Sony Corp | IMAGE DETECTOR IN SOLID STATE |
| EP0073144A3 (en) * | 1981-08-20 | 1985-10-30 | Matsushita Electric Industrial Co., Ltd. | Solid state image sensor |
| EP0073144A2 (en) * | 1981-08-20 | 1983-03-02 | Matsushita Electric Industrial Co., Ltd. | Solid state image sensor |
| EP0103023A1 (en) * | 1982-02-19 | 1984-03-21 | Sony Corporation | Solid-state image pickup device |
| EP0103023A4 (en) * | 1982-02-19 | 1986-01-07 | Sony Corp | Solid-state image pickup device. |
| EP0100199A2 (en) * | 1982-07-19 | 1984-02-08 | Sharp Kabushiki Kaisha | An interline transfer CCD image sensor and a drive circuit therefor |
| EP0100199A3 (en) * | 1982-07-19 | 1985-04-03 | Sharp Kabushiki Kaisha | Structure and driving method of interline transfer ccd image sensor |
| EP0106286A2 (en) * | 1982-10-07 | 1984-04-25 | Kabushiki Kaisha Toshiba | Solid state image sensor |
| EP0106286A3 (en) * | 1982-10-07 | 1985-09-18 | Kabushiki Kaisha Toshiba | Solid state image sensor |
| US4591917A (en) * | 1982-10-07 | 1986-05-27 | Tokyo Shibaura Denki Kabushiki Kaisha | Solid state image sensor |
| FR2540291A1 (en) * | 1983-02-01 | 1984-08-03 | Philips Nv | SEMICONDUCTOR LOADING VIEWING DEVICE |
| AT393181B (en) * | 1983-02-01 | 1991-08-26 | Philips Nv | IMAGE ARRANGEMENT |
| EP0185990A1 (en) * | 1984-12-06 | 1986-07-02 | Kabushiki Kaisha Toshiba | Charge coupled device |
| US4901125A (en) * | 1984-12-06 | 1990-02-13 | Kabushiki Kaisha Toshiba | Charge coupled device capable of efficiently transferring charge |
| EP0185343A1 (en) * | 1984-12-19 | 1986-06-25 | Kabushiki Kaisha Toshiba | Charge transfer device |
| US4721989A (en) * | 1984-12-19 | 1988-01-26 | Kabushiki Kaisha Toshiba | CCD with transfer channel at lower potential than supply channel |
| EP0212803A1 (en) * | 1985-08-13 | 1987-03-04 | Mitsubishi Denki Kabushiki Kaisha | Solid-state image sensor |
| EP0213803A1 (en) * | 1985-08-13 | 1987-03-11 | Mitsubishi Denki Kabushiki Kaisha | Solid-state image sensor |
| US4707744A (en) * | 1985-08-13 | 1987-11-17 | Mitsubishi Denki Kabushiki Kaisha | Solid-state image sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3047216C2 (en) | 1983-02-03 |
| GB2065974B (en) | 1984-02-15 |
| JPS5685981A (en) | 1981-07-13 |
| DE3047216A1 (en) | 1981-09-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB2065974A (en) | Integrated CCD Image Sensor of the Interline Transfer Type | |
| US4322753A (en) | Smear and/or blooming in a solid state charge transfer image pickup device | |
| US5051832A (en) | Selective operation in interlaced and non-interlaced modes of interline transfer CCD image sensing device | |
| US4200892A (en) | Solid state image sensor | |
| US4117514A (en) | Solid state imaging device | |
| US4697200A (en) | Field storage drive in interline transfer CCD image sensor | |
| EP0593139A2 (en) | Photoelectric converting apparatus | |
| US3983395A (en) | MIS structures for background rejection in infrared imaging devices | |
| US4758895A (en) | Storage registers with charge packet accumulation capability, as for solid-state imagers | |
| US4040092A (en) | Smear reduction in ccd imagers | |
| KR900005875B1 (en) | Solid state image device | |
| US20050029553A1 (en) | Clocked barrier virtual phase charge coupled device image sensor | |
| US5748232A (en) | Image sensor and driving method for the same | |
| US4032903A (en) | Charge injection device arrays | |
| US4720746A (en) | Frame transfer CCD area image sensor with improved horizontal resolution | |
| US5703642A (en) | Full depletion mode clocking of solid-state image sensors for improved MTF performance | |
| JPS6141468B2 (en) | ||
| JPS60254886A (en) | Solid-state image pickup device | |
| JP2002151673A (en) | Solid-state image pickup element | |
| US5055931A (en) | Image sensor with high storage capacity per pixel | |
| JPH0130306B2 (en) | ||
| JPH07322143A (en) | Method for driving solid-state image pickup device | |
| JP2699895B2 (en) | Driving method of image sensor | |
| JPH0150156B2 (en) | ||
| JPS63234677A (en) | Drive method of charge coupling element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PG | Patent granted |