JPH0150156B2 - - Google Patents
Info
- Publication number
- JPH0150156B2 JPH0150156B2 JP54072016A JP7201679A JPH0150156B2 JP H0150156 B2 JPH0150156 B2 JP H0150156B2 JP 54072016 A JP54072016 A JP 54072016A JP 7201679 A JP7201679 A JP 7201679A JP H0150156 B2 JPH0150156 B2 JP H0150156B2
- Authority
- JP
- Japan
- Prior art keywords
- charge transfer
- transfer channel
- charge
- vertical
- horizontal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 31
- 238000006243 chemical reaction Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000001444 catalytic combustion detection Methods 0.000 description 7
- 238000003384 imaging method Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 206010047571 Visual impairment Diseases 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
- H04N25/621—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
- H04N25/622—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming by controlling anti-blooming drains
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
- H04N25/625—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of smear
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/713—Transfer or readout registers; Split readout registers or multiple readout registers
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【発明の詳細な説明】
本発明は電荷結合型二次元撮像素子の駆動法に
関する。電荷結合素子（以後CCDと略す）は
1970年にその概念が発表されて以来、従来からの
高度の集積回路技術を背景として急速な開発が進
められ近年固体撮像、アナログ遅延線、フイル
タ、デイジタルメモリ等への応用がおこなわれる
ようになつた。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for driving a charge-coupled two-dimensional imaging device. A charge-coupled device (hereinafter abbreviated as CCD) is
Since the concept was announced in 1970, rapid development has progressed against the background of conventional advanced integrated circuit technology, and in recent years it has been applied to solid-state imaging, analog delay lines, filters, digital memory, etc. Ta.
特にCCDの固体撮像素子は低消費電力、小型
軽量、残像がない等の特徴がある他、従来の
MOS型固体撮像素子と比較してＳ／Ｎがよく高
集積化が可能であるという利点を持つている。現
在では光電変換領域をＰ−Ｎ接合で形成し、光電
変換された信号を読みだすための垂直、水平レジ
スタをCCDで構成したインターライン方式の高
感度二次元固体撮像素子が開発されている。この
固体撮像素子は従来のMOS型固体撮像素子と
CCD固体撮像素子両者の特徴を併わ持ち光電感
度が高くＳ／Ｎがよいという利点を有する。 In particular, CCD solid-state image sensors have features such as low power consumption, small size and light weight, and no afterimage.
Compared to MOS type solid-state image sensors, it has the advantage of having a good S/N ratio and being highly integrated. Currently, an interline type high-sensitivity two-dimensional solid-state imaging device has been developed in which the photoelectric conversion region is formed by a P-N junction and the vertical and horizontal registers for reading out the photoelectrically converted signals are configured by CCDs. This solid-state image sensor is different from the conventional MOS solid-state image sensor.
It has the characteristics of both CCD solid-state image sensors and has the advantage of high photoelectric sensitivity and good S/N ratio.
しかしながら従来のデバイスではＰ−Ｎ接合へ
の入射光量が増加して信号電荷が増加すると垂直
レジスタがオーバーフローしていわゆるブルーミ
ングを起すという欠点や、基板内部で発生した信
号電荷が水平方向位置情報を持たない信号として
垂直レジスタに流れこみいわゆるスミアを起すと
いう欠点があつた。 However, in conventional devices, when the amount of light incident on the P-N junction increases and the signal charge increases, the vertical register overflows and so-called blooming occurs, and the signal charge generated inside the substrate has horizontal position information. This has the disadvantage that the signal flows into the vertical register as an unused signal, causing so-called smear.
第１図はインターライン方式を用いた従来の
CCD二次元撮像デバイスの受光部および垂直レ
ジスタ部の上面図であり、第２図は同デバイスの
全体構成を示す図である。本明細書においては半
導体基板としてＰ基板を用いた場合について説明
するがその内容がＮ基板を用いた場合にも適用出
来ることは当然である。まず１０１はシリコン基
板上に形成された厚さ5000〜10000ÅのSiO2層で
チヤンネルの形成を防止するフイールド酸化膜と
呼ばれる。通常フイールド酸化膜下はチヤネルス
トツプ拡散がおこなわれ基板と同一導電形ではあ
るが基板よりは高不純物濃度になつている。シリ
コン基板上にはN+領域１０２、Ｎ領域１０４、
N-領域１０５が形成されている。N+領域は基板
とＰ−N+接合を形成して光電変換用のダイオー
ドとして働き、Ｎ領域１０４およびN-領域１０
５は垂直CCDレジスタ１０８の蓄積領域および
バリア領域として働らく。N+領域、Ｎ領域、N-
領域上には1000〜3000ÅのSiO2層が設けられ更
にその上からトランスフアーゲート電極１０３と
転送電極１０９が設けられている。転送電極１０
９の範囲は斜線で示されている。トランスフアー
ゲート電極はＰ−N+接合に蓄わえられた電荷を
シフトレジスタ１０８に送りこむ際のコントロー
ルゲートとして作用し、転送電極１０９はシフト
レジスタ１０９内の電荷転送を制御する。これら
の転送電極は各水平ラインごとにそれぞれ結線さ
れ、１ラインおきに垂直転送用パルスφ1１０６
およびφ2１０７が供給されている。次にこの従
来の駆動法について説明しておく。 Figure 1 shows the conventional method using the interline method.
FIG. 2 is a top view of a light receiving section and a vertical register section of a CCD two-dimensional imaging device, and FIG. 2 is a diagram showing the overall configuration of the device. In this specification, a case will be described in which a P substrate is used as a semiconductor substrate, but it goes without saying that the contents can also be applied to a case in which an N substrate is used. First, reference numeral 101 is a 5,000 to 10,000 Å thick SiO 2 layer formed on a silicon substrate and is called a field oxide film that prevents channel formation. Normally, channel stop diffusion occurs under the field oxide film, and although it has the same conductivity type as the substrate, it has a higher impurity concentration than the substrate. On the silicon substrate, an N + region 102, an N region 104,
An N − region 105 is formed. The N + region forms a P-N + junction with the substrate and acts as a diode for photoelectric conversion, and the N region 104 and the N - region 10
5 serves as the storage area and barrier area of the vertical CCD register 108. N + area, N area, N-
A SiO 2 layer with a thickness of 1000 to 3000 Å is provided on the region, and a transfer gate electrode 103 and a transfer electrode 109 are further provided thereon. Transfer electrode 10
The range 9 is shown with diagonal lines. The transfer gate electrode acts as a control gate when sending the charge stored in the P-N + junction to the shift register 108, and the transfer electrode 109 controls charge transfer within the shift register 109. These transfer electrodes are connected for each horizontal line, and a vertical transfer pulse φ 1 106 is applied every other line.
and φ 2 107 are supplied. Next, this conventional driving method will be explained.
先ず入射した光によつて生じた電子はN+領域
に蓄わえられる。生じた電子の数は入射した光の
強度に比例する。第１のフイールドではφ1１０
６をON、φ2をOFFとした状態でトランスフアー
ゲート電極１０３をONにするとφ1パルスが印加
されている転送電極の蓄積領域に対向したN+領
域から、この蓄積領域に光によつて生じた電子が
転送される。次にトランスフアーゲート１０３を
オフにした後φ1をOFF、φ2をONにすれば電子は
φ1に連なる電荷転送電極下の蓄積領域からその
下方にあるφ2に連らなる転送電極下の蓄積領域
に移る。このようにφ1、φ2のON、OFFを反転す
る度に電荷は一般ずつ下方に移動してゆく。フイ
ールド酸化膜１０１、N+領域１０２、トランス
フアーゲート１０８、垂直レジスタ１０８を一組
する、いわゆる一次元センサ構造の下方には、そ
れぞれ等価な二つの転送段２０１，２０２が設け
られそれらの転送電極は一つおきにクロツクライ
ンφH1、φH2に接続されている。今第２図において
クロツクラインφH1をOFF、φH2をONの状態にし
てφ2をON→OFF、φ1をOFF→ONにするとシフ
トレジスタの最下段にあつた電荷は水平レジスタ
のφH2電極下の蓄積領域に転送される。これらの
電荷はφ1H、φ2Hによつて水平レジスタ内を右方に
転送され、出力増巾器から映像信号として読みだ
される。次にフイールドではφ2に連らなる転送
電極下の蓄積領域に対向したN+領域から信号電
荷が垂直レジスタに取り出され前述したと同様の
手段によつて映像信号として読みだされる。この
二つのフイールドを順次くり返すことによつてイ
ンターレースされた映像信号を得ることが出来
る。以上はかなり理想化された状態での動作説明
であつて実際には次に述べるような過程で次のよ
うな困難が生ずる。その一つはいわゆるブルーミ
ングと呼ばれるもので強い光に照射された１個
N+領域に対応する垂直シフトレジスタの転送段
の蓄積領域には多量の電荷が転送されてくるので
蓄積領域には入り切れずこの前記転送段のバリア
領域や隣接する転送段へ次から次へともれてい
く。これらの電荷は転送時に更に垂直レジスタの
中を上下に拡がつていくから映像上では一本の垂
直の線として見える。もう一つの困難は１個の
N+領域に入射した光によつて生じた電子がすべ
て前記N+領域に集められるのではなく一部は左
右のシフトレジスタにもれていくいわゆるスミア
と呼ばれる現象が起ることである。水平レジスタ
はこれらのもれ電荷をひろい集めることになるか
ら映像上では輝線として見える。このようなブル
ーミングやスミアが起ると低品位の画像となるの
で少しでも軽減することは大きな意味がある。 First, electrons generated by the incident light are stored in the N + region. The number of electrons generated is proportional to the intensity of the incident light. In the first field φ 1 10
When the transfer gate electrode 103 is turned ON with φ 6 ON and φ 2 OFF, light is applied to this storage region from the N + region facing the storage region of the transfer electrode to which the φ 1 pulse is applied. The generated electrons are transferred. Next, after turning off the transfer gate 103, turning φ 1 off and turning φ 2 on, electrons are transferred from the storage region under the charge transfer electrode connected to φ 1 to the transfer electrode connected to φ 2 below. Move to the storage area. In this way, each time φ 1 and φ 2 are turned ON or OFF, the charge generally moves downward. Two equivalent transfer stages 201 and 202 are provided below the so-called one-dimensional sensor structure, which includes a set of field oxide film 101, N + region 102, transfer gate 108, and vertical resistor 108, and their transfer electrodes. are connected to every other clock line φ H1 and φ H2 . Now, in Fig. 2, when the clock line φ H1 is turned OFF and φ H2 is turned on, φ 2 is turned from ON to OFF, and φ 1 is turned from OFF to ON, the charge at the bottom stage of the shift register is transferred to φ H2 of the horizontal register. transferred to the storage area under the electrode. These charges are transferred to the right in the horizontal register by φ 1H and φ 2H and read out from the output amplifier as a video signal. Next, in the field, signal charges are taken out to the vertical register from the N + region opposite the storage region under the transfer electrode connected to φ 2 and read out as a video signal by the same means as described above. By sequentially repeating these two fields, an interlaced video signal can be obtained. The above is an explanation of the operation in a highly idealized state, and in reality, the following difficulties arise in the process described below. One of them is what is called blooming, where one piece is irradiated with strong light.
A large amount of charge is transferred to the storage area of the transfer stage of the vertical shift register corresponding to the N + area, so it cannot fit into the storage area and is transferred to the barrier area of this transfer stage or to the adjacent transfer stage. It fades away. Since these charges further spread up and down in the vertical register during transfer, they appear as a single vertical line on the image. Another difficulty is one
A phenomenon called smear occurs in which electrons generated by light incident on the N + region are not all collected in the N + region, but some of them leak into the left and right shift registers. Since the horizontal register collects these leaked charges, they appear as bright lines on the image. If such blooming or smearing occurs, the resulting image will be of low quality, so it is of great significance to reduce it even a little.
第３図は通常のTV方式での映像信号を示した
もので３０１はＡフイールド期間、３０２はＢフ
イールド期間を示し、AB両フイールド間は垂直
ブランキング期間である。 FIG. 3 shows a video signal in a normal TV system, where 301 indicates an A field period, 302 a B field period, and a vertical blanking period between both fields AB.
Ａフイールドが終了した時点３０３において垂
直シフトレジスタはＰ−Ｎ接合から受け取つた電
荷を水平レジスタに転送してしまつているが、先
に述べたようなブルーミングやスミアによる残留
電荷を蓄積してる。 At the end of the A field 303, the vertical shift register has transferred the charge received from the P-N junction to the horizontal register, but has accumulated residual charge due to blooming and smearing as described above.
Ｂフイールドが開始するとこの残留電荷の上に
映像情報をもつＰ−Ｎ接合からの電荷がつけ加わ
わり両者は区別がつかなくなるのでＢフイールド
が始まる前に前記残留電荷をクリアする必要があ
る。このクリア機能を加えることによつて、ブル
ーミングおよびスミアを半減出来る。前記残留電
荷をクリアするための第１の方法は垂直ブランキ
ング期間に第２図のトランスフアーゲートを
OFF、垂直シフトレジスタに対向した水平レジ
スタの転送電極２０２をON状態にして垂直レジ
スタの電荷を水平レジスタ２０３に転送し、次に
水平レジスタを駆動して出力手段２０４へ送りこ
めばよい。Ａフイールドのブランキング期間が終
了した時点でシフトレジスタ中に存在する電荷が
少ない場合はこのような動作をおこなうことによ
つてすべて出力端へ送り込まれる。しかし垂直シ
フトレジスタ１０８中の電荷が多い場合には水平
レジスタ２０３がオーバーフローしてしまうとい
う新たな欠点が生じる。 When the B field starts, the charge from the P-N junction having image information is added to this residual charge, and the two become indistinguishable, so it is necessary to clear the residual charge before the B field starts. By adding this clearing function, blooming and smearing can be halved. The first method for clearing the residual charge is to operate the transfer gate in Figure 2 during the vertical blanking period.
OFF, the transfer electrode 202 of the horizontal register facing the vertical shift register is turned ON to transfer the charge in the vertical register to the horizontal register 203, and then the horizontal register is driven to send it to the output means 204. If the amount of charge existing in the shift register is small at the end of the blanking period of the A field, all of the charge is sent to the output terminal by performing such an operation. However, if there are many charges in the vertical shift register 108, a new drawback arises in that the horizontal register 203 overflows.
本願第１の発明の目的はスミア、ブルーミング
を減らししかもこの欠点をとりのぞいたインター
ライン方式電荷転送デバイスの駆動法を提供する
ことにある。また第２の発明の目的は２ 1/2相、
３相、４相駆動デバイスでスミア、ブルーミング
を減らす簡単な方法を提供することにある。 A first object of the present invention is to provide a method for driving an interline charge transfer device that reduces smear and blooming and eliminates these drawbacks. Furthermore, the purpose of the second invention is to provide 2 1/2 phase,
The objective is to provide a simple method to reduce smear and blooming in 3-phase and 4-phase drive devices.
本願第１の発明によれば、一導電型を有する半
導体基板に形成され、該半導体基板と反対導電型
を有する半導体領域により構成された複数の互い
に分離された光電変換領域と該光電変換領域に隣
接して設けられたゲート電極と、該ゲート電極に
隣接し前記複数の光電変換領域に対応して設けら
れた電荷転送電極を有する垂直電荷転送チヤネル
とを二次元的に配列し、かつ各垂直電荷転送チヤ
ネルに対応して複数の電荷転送段を有する水平電
荷転送チヤネルを配列した電荷転送デバイスにお
いて、前記光電変換領域からの信号を同時に対応
する垂直電荷転送チヤネルに転送したのち、垂直
電荷転送チヤネルの一水平ライン分の信号を順次
水平電荷転送チヤネルに転送してその出力手段か
ら光電変換信号がすべて出力された時点から次に
光電変換領域からの電荷を垂直電荷転送チヤネル
に移す間の時点までに前記垂直電荷転送チヤネル
に残留する電荷を前記水平電荷転送チヤネルを通
してとりだす電荷転送デバイスの駆動法であつ
て、前記残留する電荷が少ないときは、前記ゲー
ト電極をOFF状態にし前記水平電荷転送チヤネ
ルの転送電極のうち前記垂直電荷転送チヤネルに
対向した電極をON状態にして、垂直電荷転送チ
ヤネルの全段数を駆動して前記残留電荷を一度に
水平電荷転送チヤネルに送り込み、次いで水平電
荷転送チヤネルを駆動して前記残留電荷を出力手
段に送り込む第一の駆動手段を行ない、前記残留
電荷が多いときは、前記ゲート電極をOFF状態
にし前記水平電荷転送チヤネルの転送電極のうち
前記垂直電荷転送チヤネルに対向した電極をON
状態にして、垂直電荷転送チヤネルの一部の段数
分のみを駆動して前記残留電荷の一部を水平電荷
転送チヤネルに送り込み、次いで水平電荷転送チ
ヤネルを駆動して前記残留電荷の一部を出力手段
に送り込むことを複数回行なう第二の駆動手段を
行ない、あるいは前記第一と第二の駆動手段の両
方を行なうことを特徴とする電荷転送デバイスの
駆動法が得られる。 According to the first invention of the present application, a plurality of mutually separated photoelectric conversion regions formed on a semiconductor substrate having one conductivity type and constituted by a semiconductor region having a conductivity type opposite to that of the semiconductor substrate; Gate electrodes provided adjacent to each other and vertical charge transfer channels having charge transfer electrodes provided adjacent to the gate electrodes corresponding to the plurality of photoelectric conversion regions are arranged two-dimensionally, and each vertical In a charge transfer device in which horizontal charge transfer channels having a plurality of charge transfer stages are arranged in correspondence with the charge transfer channels, the signal from the photoelectric conversion region is simultaneously transferred to the corresponding vertical charge transfer channel, and then the vertical charge transfer channel From the time when the signals for one horizontal line are sequentially transferred to the horizontal charge transfer channel and all the photoelectric conversion signals are output from the output means to the time when the charges from the photoelectric conversion area are transferred to the vertical charge transfer channel. A method of driving a charge transfer device in which charge remaining in the vertical charge transfer channel is taken out through the horizontal charge transfer channel, and when the remaining charge is small, the gate electrode is turned OFF and the charge transfer channel is removed. Among the transfer electrodes, the electrode facing the vertical charge transfer channel is turned on, and all stages of the vertical charge transfer channel are driven to send the residual charge to the horizontal charge transfer channel at once, and then the horizontal charge transfer channel is driven. and performs a first driving means to send the residual charge to the output means, and when the residual charge is large, the gate electrode is turned OFF and one of the transfer electrodes of the horizontal charge transfer channel facing the vertical charge transfer channel is operated. Turn on the electrode
drive only some stages of the vertical charge transfer channel to send some of the residual charge to the horizontal charge transfer channel, and then drive the horizontal charge transfer channel to output some of the residual charge. There is obtained a method for driving a charge transfer device, characterized in that the second driving means performs feeding into the charge transfer means a plurality of times, or both the first and second driving means are performed.
更に本願第２の発明によれば２ 1/2、３相、あ
るいは４相の電荷転送デバイスの駆動法として、
前記残留する電荷をとりだす際に垂直及び水平電
荷転送チヤネルを駆動する転送電極を全部同一電
位とすることを特徴とする電荷転送デバイスの駆
動法が得られる。 Furthermore, according to the second invention of the present application, as a method for driving a 2 1/2, 3-phase, or 4-phase charge transfer device,
A method for driving a charge transfer device is obtained, which is characterized in that the transfer electrodes for driving the vertical and horizontal charge transfer channels are all set to the same potential when the remaining charge is taken out.
前述の第１の方法と対比させて本願第１の発明
の方法を以後第２の方法と称する。第２の方法で
は水平レジスタ２０３がオーバフローしないよう
に、垂直レジスタ１０８の全段数分の電荷を一度
に水平レジスタ２０３に転送せず一部の段数分の
電荷を水平レジスタ２０３に転送し一たんこれら
を出力端に送り込んだ後残りの全部の段数あるに
は残りの段数のうち一部の段数分だけ水平レジス
タ２０３を駆動して残留電荷を水平レジスタに移
し、出力手段２０４に転送すればよい。このよう
に２回あるいはそれ以上の回数に分けて転送す
る。またブランキング期間に第１の方法と第２の
方法を複数回行なつてもよく、第１の方法と第２
の方法を適当に組合わせておこなつてもよい。 In contrast to the first method described above, the method of the first invention of the present application will be hereinafter referred to as the second method. In the second method, in order to prevent the horizontal register 203 from overflowing, charges for all stages of the vertical register 108 are not transferred to the horizontal register 203 at once, but charges for a part of the stages are transferred to the horizontal register 203, and then the charges are transferred to the horizontal register 203. After sending the charge to the output terminal, in order to obtain all the remaining stages, the horizontal register 203 may be driven by a portion of the remaining stages to transfer the residual charge to the horizontal register and transfer it to the output means 204. In this way, the data is transferred twice or more times. Further, the first method and the second method may be performed multiple times during the blanking period, and the first method and the second method may be performed multiple times.
You may use a suitable combination of these methods.
今述べた二つの方法すなわちブランキング期間
に垂直レジスタ中の残留電荷を水平レジスタに移
し、更にこれらを水平レジスタから取りだすとい
う方法はレジスタが１ 1/2相、２相、２ 1/2、３
相、４相などのいかなる駆動方法においても有効
である。しかし２ 1/2相、３相、４相などの場合
にはもつと簡単な駆動法がある。次にその方法を
述べる。 In the two methods just described, that is, during the blanking period, the residual charges in the vertical register are transferred to the horizontal register, and then these are taken out from the horizontal register.
It is effective in any drive method such as phase, four-phase, etc. However, in the case of 2 1/2 phase, 3 phase, 4 phase, etc., there is a simple driving method. The method will be described next.
２ 1/2相、３相、４相駆動デバイスにおいては
各転送電極下は単一の領域で出来ており転送電極
下のポテンシヤルは一様になる。従つて垂直ブラ
ンキング期間に垂直および水平レジスタを駆動す
る転送電極を全部同一電位にすると二つのレジス
タのチヤネル電位はすべて同一となるので、垂直
レジスタ中の過剰電荷は水平レジスタを通つてそ
の出力端へ拡散していく。 In 2 1/2-phase, 3-phase, and 4-phase drive devices, a single region is formed under each transfer electrode, and the potential under each transfer electrode is uniform. Therefore, if the transfer electrodes that drive the vertical and horizontal registers are all set to the same potential during the vertical blanking period, the channel potentials of the two registers will all be the same, so excess charge in the vertical register will pass through the horizontal register and be transferred to its output terminal. It spreads to.
しかしすべての転送電極を同一の電位にして
も、基板や基板上に設けた拡散層の局部的な不純
物濃度の差によつて小さなポテンシヤルの井戸が
出来ることはさけられないのでここに蓄積した電
荷は出力端に拡散することが出来ない。しかし、
転送電極電位をすべて同一にしてほとんどの電荷
を出力端に追いだした後、先に説明した第１の方
法あるいは第２の方法あるいはそれらの組合せを
用いれば、垂直レジスタ中の電荷は完全に出力端
からとりだせる。 However, even if all transfer electrodes are set to the same potential, it is unavoidable that small potential wells will be formed due to local differences in impurity concentration in the substrate or the diffusion layer provided on the substrate. cannot be diffused to the output end. but,
After making all the transfer electrode potentials the same and driving most of the charge out to the output terminal, if you use the first method, second method, or a combination thereof described above, the charge in the vertical register can be completely output. You can take it out from the end.
本発明は従来の構造のデバイスのスミア、ブル
ーミングを半減する手段として非常に有効であ
る。 The present invention is very effective as a means for halving the smear and blooming of devices with conventional structures.
第１図は従来のインターライン方式CCD撮像
デバイスの光電変換部の上面図、第２図はこのデ
バイスの全体構成図第３図は本発明の駆動法を説
明するための図である。
１０１……フイールド酸化膜、１０２……N+
領域、１０３……トランスフアーゲート、１０４
……蓄積領域、１０５……バリアー領域、１０
６，１０７……駆動パルス供給源、１０８……垂
直方向レジスタ、１０９……転送電極、２０１，
２０２……水平レジスタの転送段、２０３……水
平レジスタ、２０４……出力手段、２０５……出
力端、３０１……Ａフイールド期間、３０２……
Ｂフイールド期間、３０３……ブランキング期間
の開始時点。
FIG. 1 is a top view of a photoelectric conversion section of a conventional interline type CCD imaging device, FIG. 2 is a diagram showing the overall configuration of this device, and FIG. 3 is a diagram for explaining the driving method of the present invention. 101...Field oxide film, 102...N +
Area, 103...Transfer gate, 104
...Accumulation area, 105...Barrier area, 10
6,107... Drive pulse supply source, 108... Vertical register, 109... Transfer electrode, 201,
202... Transfer stage of horizontal register, 203... Horizontal register, 204... Output means, 205... Output end, 301... A field period, 302...
B field period, 303...Start point of blanking period.
Claims (1)
半導体基板と反対導電型を有する半導体領域によ
り構成された複数の互いに分離された光電変換領
域と該光電変換領域に隣接して設けられたゲート
電極と、該ゲート電極に隣接し前記複数の光電変
換領域に対応して設けられた電荷転送電極を有す
る垂直電荷転送チヤネルとを二次元的に配列し、
かつ各垂直電荷転送チヤネルに対応して複数の電
荷転送段を有する水平電荷転送チヤネルを配列し
た電荷転送デバイスにおいて、前記光電変換領域
からの信号を同時に対応する垂直電荷転送チヤネ
ルに転送したのち、垂直電荷転送チヤネルの一水
平ライン分の信号を順次水平電荷転送チヤネルに
転送してその出力手段から光電変換信号がすべて
出力された時点から次に光電変換領域からの電荷
を垂直電荷転送チヤネルに移す間の時点までに前
記垂直電荷転送チヤネルに残留する電荷を前記水
平電荷転送チヤネルを通してとりだす電荷転送デ
バイスの駆動法であつて、前記残留する電荷が少
ないときは、前記ゲート電極をOFF状態にし前
記水平電荷転送チヤネルの転送電極のうち前記垂
直電荷転送チヤネルに対向した電極をON状態に
して、垂直電荷転送チヤネルの全段数を駆動して
前記残留電荷を一度に水平電荷転送チヤネルに送
り込み、次いで水平電荷転送チヤネルを駆動して
前記残留電荷を出力手段に送り込む第一の駆動手
段を行ない、前記残留電荷が多いときは、前記ゲ
ート電極をOFF状態にし前記水平電荷転送チヤ
ネルの転送電極のうち前記垂直電荷転送チヤネル
に対向した電極をON状態にして、垂直電荷転送
チヤネルの一部の段数分のみを駆動して前記残留
電荷の一部を水平電荷転送チヤネルに送り込み、
次いで水平電荷転送チヤネルを駆動して前記残留
電荷の一部を出力手段に送り込むことを複数回行
なう第二の駆動手段を行ない、あるいは前記第一
と第二の駆動手段の両方を行なうことを特徴とす
る電荷転送デバイスの駆動法。 ２ 一導電型を有する半導体基板に形成され、該
半導体基板と反対導電型を有する半導体領域によ
り構成された複数の互いに分離された光電変換領
域と該光電変換領域に隣接して設けられたゲート
電極と、該ゲート電極に隣接し前記複数の光電変
換領域に対応して設けられた電荷転送電極を有す
る垂直電荷転送チヤネルとを二次元的に配列し、
かつ各垂直電荷転送チヤネルに対応して複数の電
荷転送段を有する水平電荷転送チヤネルを配列し
た電荷転送デバイスにおいて、前記光電変換領域
からの信号を同時に対応する垂直電荷転送チヤネ
ルに転送したのち、垂直電荷転送チヤネルの一水
平ライン分の信号を順次水平電荷転送チヤネルに
転送してその出力手段から光電変換信号がすべて
出力された時点から次に光電変換領域からの電荷
を垂直電荷転送チヤネルに移す間の時点までに前
記垂直電荷転送チヤネルに残留する電荷を前記水
平電荷転送チヤネルを通してとりだす２ 1/2相、
３相、あるいは４相の電荷転送デバイスの駆動法
であつて、前記残留する電荷をとりだす際に垂直
及び水平電荷転送チヤネルを駆動する転送電極を
全部同一電位とすることを特徴とする電荷転送デ
バイスの駆動法。[Claims] 1. A plurality of mutually separated photoelectric conversion regions formed on a semiconductor substrate having one conductivity type and constituted by semiconductor regions having a conductivity type opposite to the semiconductor substrate, and adjacent to the photoelectric conversion regions. two-dimensionally arranging a gate electrode provided with a gate electrode and a vertical charge transfer channel having a charge transfer electrode adjacent to the gate electrode and provided corresponding to the plurality of photoelectric conversion regions;
In a charge transfer device in which horizontal charge transfer channels having a plurality of charge transfer stages are arranged corresponding to each vertical charge transfer channel, the signal from the photoelectric conversion region is simultaneously transferred to the corresponding vertical charge transfer channel, and then the vertical charge transfer channel is From the time when the signal for one horizontal line of the charge transfer channel is sequentially transferred to the horizontal charge transfer channel and all the photoelectric conversion signals are output from the output means, to the time when the charge from the photoelectric conversion area is transferred to the vertical charge transfer channel. A method of driving a charge transfer device in which charge remaining in the vertical charge transfer channel is taken out through the horizontal charge transfer channel until the point in time, when the remaining charge is small, the gate electrode is turned OFF and the horizontal charge is Among the transfer electrodes of the transfer channel, the electrode facing the vertical charge transfer channel is turned on, and all stages of the vertical charge transfer channel are driven to send the residual charge to the horizontal charge transfer channel at once, and then the horizontal charge transfer is performed. The first driving means drives the channel to send the residual charge to the output means, and when the residual charge is large, the gate electrode is turned OFF and the vertical charge transfer is performed among the transfer electrodes of the horizontal charge transfer channel. Turning on the electrode facing the channel and driving only a portion of the stages of the vertical charge transfer channel to send a portion of the residual charge to the horizontal charge transfer channel;
Then, a second driving means is performed for driving a horizontal charge transfer channel to send a portion of the residual charge to the output means a plurality of times, or both the first and second driving means are performed. Driving method of charge transfer device. 2. A plurality of mutually separated photoelectric conversion regions formed on a semiconductor substrate having one conductivity type and constituted by semiconductor regions having a conductivity type opposite to that of the semiconductor substrate, and a gate electrode provided adjacent to the photoelectric conversion region. and a vertical charge transfer channel having a charge transfer electrode adjacent to the gate electrode and provided corresponding to the plurality of photoelectric conversion regions,
In a charge transfer device in which horizontal charge transfer channels having a plurality of charge transfer stages are arranged corresponding to each vertical charge transfer channel, the signal from the photoelectric conversion region is simultaneously transferred to the corresponding vertical charge transfer channel, and then the vertical charge transfer channel is From the time when the signal for one horizontal line of the charge transfer channel is sequentially transferred to the horizontal charge transfer channel and all the photoelectric conversion signals are output from the output means, to the time when the charge from the photoelectric conversion area is transferred to the vertical charge transfer channel. a 2 1/2 phase for extracting the charge remaining in the vertical charge transfer channel through the horizontal charge transfer channel up to the point in time;
A method for driving a three-phase or four-phase charge transfer device, characterized in that transfer electrodes for driving vertical and horizontal charge transfer channels are all set to the same potential when taking out the residual charge. driving method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7201679A JPS55163957A (en) | 1979-06-08 | 1979-06-08 | Driving method for electric charge transfer device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7201679A JPS55163957A (en) | 1979-06-08 | 1979-06-08 | Driving method for electric charge transfer device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55163957A JPS55163957A (en) | 1980-12-20 |
| JPH0150156B2 true JPH0150156B2 (en) | 1989-10-27 |
Family
ID=13477186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7201679A Granted JPS55163957A (en) | 1979-06-08 | 1979-06-08 | Driving method for electric charge transfer device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55163957A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5870687A (en) * | 1981-10-22 | 1983-04-27 | Matsushita Electric Ind Co Ltd | Driving method for solid-state image pickup element |
| JPS58117777A (en) * | 1981-12-30 | 1983-07-13 | Sony Corp | Solid-state image pickup device |
| JPS58117776A (en) * | 1981-12-30 | 1983-07-13 | Sony Corp | Solid-state image pickup device |
| JPS5928769A (en) * | 1982-08-10 | 1984-02-15 | Sony Corp | Still video camera |
| JPS60210079A (en) * | 1984-02-25 | 1985-10-22 | Shoichi Tanaka | Solid state area sensor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5370716A (en) * | 1976-12-07 | 1978-06-23 | Sony Corp | Image pickup device |
| JPS53126815A (en) * | 1977-04-12 | 1978-11-06 | Sony Corp | Solid state image tube |
| JPS5456718A (en) * | 1977-10-14 | 1979-05-08 | Sony Corp | Solid state pickup device |
-
1979
- 1979-06-08 JP JP7201679A patent/JPS55163957A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5370716A (en) * | 1976-12-07 | 1978-06-23 | Sony Corp | Image pickup device |
| JPS53126815A (en) * | 1977-04-12 | 1978-11-06 | Sony Corp | Solid state image tube |
| JPS5456718A (en) * | 1977-10-14 | 1979-05-08 | Sony Corp | Solid state pickup device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55163957A (en) | 1980-12-20 |
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