JP2513177B2 - Solid-state imaging device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a solid-state image sensor, and particularly to a CCD (Charge Co
The present invention relates to a circuit configuration suitable for realizing high sensitivity, high resolution, low smear, and high yield in an upled device type solid-state imaging device and a control method thereof.

[Background of the Invention]

CCD known as a type of two-dimensional solid-state image sensor
The solid-state imaging device of the interline CCD, one of the systems is Sequin, Tompsett "Charge Transfer Device".
s ”Academic Press 1975 PP152-, and has a circuit configuration as shown in FIG. In FIG. 4, 1 is a photodiode arranged two-dimensionally for photoelectric conversion, 2 is a vertical charge transfer element arranged for each column for vertical scanning, and 3 is a horizontal charge transfer element for horizontal scanning. ,
4 is the output part of the horizontal charge transfer element, 5 is the photodiode 1
It is a photogate for transferring signal charges from the vertical charge transfer device 2 to the vertical charge transfer device 2. The vertical solid line in the horizontal charge transfer element 3 and the horizontal solid line in the vertical charge transfer element 2 indicate the boundary of one transfer element in both charge transfer elements.

In the illustrated circuit, first, in the vertical blanking period, the photogate 5 is opened, and the signal charge photoelectrically converted and accumulated by the photodiode 1 is transferred to the vertical charge transfer element 2. Next, when an external clock is received in the horizontal blanking period, the signal charges are transferred by one transfer element in the vertical charge transfer element 2, and the signal charges in the first row are transferred to the horizontal charge transfer element 3. During the horizontal scanning period, the signal charges are sequentially transferred in the horizontal charge transfer element 3 and output from the output unit 4. By repeating this operation within the vertical scanning period, the signal charges of each row are sequentially read. Further, in this circuit, in order to improve the resolution, the interlaced scanning, that is, the odd-numbered rows in the first field and the even-numbered rows in the second field are read out.

In this circuit, at least one transfer element of the vertical charge transfer element is provided for each of the two photodiodes 1 so that the signal charges of the photodiodes 1 are not mixed in the vertical transfer, and one transfer element of the vertical charge transfer element is 1 It is necessary to have a capacity for accumulating and transferring the signal charges of the two photodiodes 1. Further, the vertical charge transfer device 2 needs to be optically shielded in order to prevent exposure during vertical scanning. As a result, the area where light is sensed (hereinafter,
The opening) is only about 30 to 40% of the entire device.

By the way, in the above interlaced scanning, the signal storage time for one photodiode is one frame, and an afterimage of one field is generated. N.Koike et al 1979 I sscc Digest is a method for reducing this afterimage and realizing a high-resolution, high-quality single-chip color image sensor.
There is a vertical 2-pixel simultaneous reading method that performs interlaced scanning described in PP193-.

In this method, for example, the signal charges of two rows of n rows and n + 1 rows are read in one scanning period of a certain field, and the signal charges of two rows of n−1 row and n rows are read in one horizontal scanning period of the next field. Is read.

When the above readout method is applied to an interline CCD, in Japanese Utility Model Publication No. 58-56458, two vertical charge transfer elements 2 are arranged for one row of photodiodes 1 to realize simultaneous readout of two pixels. , Improving the image quality.

However, no consideration is given to a decrease in sensitivity due to a decrease in the ratio of openings, and a decrease in yield due to a relatively complicated planar structure of a pixel portion that occupies most of the device, and a dense structure.

On the other hand, when a bright subject is photographed on all the solid-state image pickup devices, a vertical smear phenomenon in which a white tail is drawn above and below the reproduced image occurs, which causes deterioration of image quality at high illuminance. As a method of reducing the vertical smear under any object condition, there is a smear differential method described in Ozawa et al., 1984 Television Society National Congress Proceedings 3-15, PP67-.

In this method, first, only the vertical smear is read out, then the signal charge on which the vertical smear is superposed is read out, and the difference between the two is taken out to output only the signal charge. Further, in order to apply this method to the interline CCD, the vertical charge transfer element 2 for transferring the charges of the vertical smear is required. As a result, the opening area is further reduced as compared to the device of FIG.

[Object of the Invention]

An object of the present invention is to solve such a conventional problem and reduce the ratio of openings in an interline CCD, without complicating the planar structure of the pixel portion and overcrowding,
Achieves 2-pixel simultaneous readout and smear differential method, high sensitivity,
It is to provide a solid-state image sensor with high resolution, low smear, and high yield.

[Outline of Invention]

In order to achieve the above object, the solid-state imaging device of the present invention,
A two-dimensionally arranged photoelectric conversion element, a vertical charge transfer element having a plurality of electrodes for vertically transferring the signal charges from the photoelectric conversion element, and a vertical charge transfer element for each of the signal charges of the photoelectric conversion element. Row selection means for selectively transferring to the charge transfer element, a shift register for transmitting a drive pulse to each electrode of the vertical charge transfer element, and a signal charge for outputting the signal charge from the vertical charge transfer element In the solid-state image pickup device provided with the horizontal scanning means, the drive pulse is formed so that a potential well across a plurality of electrodes for transferring signal charges in the vertical charge transfer device is formed and moved.

Further, the drive pulse forms a potential barrier under the electrode of the vertical charge transfer element at an interval n times (n: an integer of 3 or more) the data shift cycle of the shift register. The data shift is completed at a predetermined time in the ranking, and the signal charges are added to the row selected by the row selecting means so as to be transferred from the photoelectric conversion element to the potential well formed in the vertical charge transfer element. The application time of the signal transfer pulse is different for each row, the selecting means takes the logical product of the drive pulse and the signal transfer pulse sent from the shift register to each electrode, and the pulse train sent by the shift register To form and move a plurality of potential wells for independently transferring a plurality of signal charges in the vertical charge transfer device, The potential train for transferring at least one signal charge to the vertical charge transfer element and the potential well for transferring smear charges mixed in the vertical charge transfer element are formed and moved by the pulse train to be generated, and independently of the vertical charge transfer element. Smear differential means for subtracting the read signal charge and smear charge to obtain a signal corresponding to a pure signal charge, and the number of electrodes of the vertical charge transfer element forming a potential well for transferring the smear charge is It is also characterized in that the number of electrodes is larger than the number of electrodes of a vertical charge transfer element forming a potential well for transferring a signal charge.

[Examples and Reference Examples of the Invention]

Hereinafter, reference examples related to the present invention and embodiments of the present invention will be described with reference to the drawings. First, a first reference example related to the present invention will be described with reference to FIGS.

FIG. 1 is a circuit configuration diagram of the solid-state image pickup device, FIG. 2 is a timing diagram of the drive pulse of FIG. 1, and FIG. 3 is a potential of the vertical charge transfer device, the transfer gate, and the horizontal charge transfer device at the timing of FIG. It is a figure. For simplification of description, FIG. 1 shows only a 3 × 3 photodiode matrix.

In FIG. 1, 11 is a two-dimensionally arranged photodiode for photoelectric conversion, 12 is a vertical charge transfer element arranged for each column for vertical charge transfer, 13 is a horizontal charge transfer element for horizontal scanning, 14 is an output part of the horizontal charge transfer element 13,
Reference numeral 15 is a vertical charge transfer element 12 for transferring the signal charge of the photodiode 11
16 is a photogate for transferring to the vertical charge transfer element 12, 16 is a vertical transfer shift register for generating a pulse train for driving the vertical charge transfer element 12, 17 is a pulse train of the vertical transfer shift register 16 to be a desired voltage, and a vertical charge line 51 A buffer circuit for outputting to the transfer element 12, a vertical shift register 18 for turning on the photogates 15 in the same row to an'on 'state, a transfer gate 19 for switching between the vertical charge transfer element 12 and the horizontal charge transfer element 13, 20H, 20V is a storage region, and 21H and 21V are transfer regions. These are provided in the vertical charge transfer device 12 for each photodiode 11 and in one horizontal charge transfer device 13 for each column, and one transfer stage is provided. Make up. Reference numeral 50 is a vertical gate line for sending the output from the vertical shift register 18 to the photogates 15 in the same row, and 51 is a vertical pulse line for sending the output from the buffer circuit 17 to each transfer stage of the vertical charge transfer device 12.

As the horizontal charge transfer element 13, an embedded charge transfer element which is composed of a two-layer polysilicon electrode described in U.S. Pat.
For this purpose, an embedded charge transfer device composed of a two-layer polysilicon electrode is used.

Vertical transfer shift register 16 and vertical shift register 18
Is a two-phase ratioless type disclosed in Japanese Patent Application No. 53-69793.
Consists of a dynamic shift register.

The buffer circuit 17 includes an inverter circuit that outputs the signal input from the vertical transfer shift register 16 to each vertical pulse line 51.

The timing for driving the solid-state image sensor shown in FIG. 2 is when the vertical photodiode 11 has a minimum number of 485 corresponding to the standard NTSC system. For convenience of explanation, the potential of the vertical pulse line 51 is V1, V2, V3, ... V485 are shown in order from the one closest to the horizontal charge transfer device 13. In addition, the potential of a certain vertical gate line 50 is VP, the potential of the transfer gate 19 is TG,
The potential under the electrodes of the horizontal charge transfer element 13 is indicated by H1, and the horizontal blanking pulse is indicated by HBL.

The potentials of the vertical charge transfer device 12 shown in FIG. 3 are the transfer stages (1, 2, ... N ...) of the vertical charge transfer device 12 of a certain column at the pulse timings t _{1 to} t ₇ in FIG. ,Four
5), the transfer gate 19 (TG), and the potential under the first transfer stage electrode (H1) of the horizontal charge transfer device 13 are shown. The black portion in the figure is a signal charge (the same applies hereinafter).

Now, at a certain time of horizontal scanning including the horizontal blanking period, the vertical shift register 18 moves the vertical gate line 50 (V
When a voltage is applied to P) and the photogate 15 is turned on, the signal charge accumulated in the photodiode 11 is transferred to the vertical charge transfer element 12 side. At this time, the vertical pulse line 51
Since a high voltage is applied to all of them, the signal charge is accumulated over a plurality of transfer stages of the vertical charge transfer element 12 in the vicinity of the selected vertical gate line 50 according to the amount of the charge (third stage). (T = t _{1 in the} figure).

After that, the vertical transfer shift register 16 operates to lower the voltage of the vertical pulse line 51 in each transfer stage in order from the 485th line farthest from the horizontal charge transfer element, and the potential barrier generated thereby becomes vertical charge transfer. The element 12 is moved so as to approach the first row (t = t ₂ , t _{3 in} FIG. ₃ ).

When the potential barrier reaches the transfer stage near the n-th row where the signal charges are accumulated, the signal charges are transferred to the next stage. If the storage area 20V of the next stage is full of signal charges at this time, the signal charges are transferred to (the storage area 20V of) the empty transfer stage after the next stage (t = in FIG. 3).
t ₄ ).

Each time the operation of t = t ₄ is repeated, the vertical charge transfer device 12
The signal charges therein are sequentially sent toward the horizontal charge transfer element 13. In parallel with these operations, the signal charges in the horizontal charge transfer element 13 that have been transferred from the (n-1) th row are transferred in the direction of the output section 14 and output, and at the time of the horizontal blanking period. Then, there is no signal charge inside the horizontal charge transfer element 13.

In the horizontal blanking period, transfer gate 19 (TG)
At the same time as applying a voltage to the ON state by applying a voltage to the electrode (H1) of the horizontal charge transfer element 13 so that the signal charge can move from the vertical charge transfer element 12 to the horizontal charge transfer element 13 side. (T = t _{5 in} FIG. ₃ ). When the signal charge starts to be transferred to the horizontal charge transfer device 13, and the vertical pulse line 51 having a low voltage is in the m-th row, the signal charge is transferred to each transfer stage between 1-m-1 rows. It has been accumulated.

After that, by the operation at t = t ₄ in FIG. 3, the signal charge is further sent to the side of the horizontal charge transfer element 13, and when the potential V1 of the vertical pulse line 51 of the first row becomes a low voltage. , The vertical charge transfer is completed, and the signal charges of the nth row are transferred below the electrode H1 of the horizontal charge transfer element 13 (t = t ₆ , in FIG. 3).
t ₇ ). Next, the voltage of the transfer gate 19 is lowered to be “off”, the horizontal charge transfer element 13 is ready to transfer and output again, and the signal charge reading operation of the (n + 1) th row is performed.
It starts in the same way as t _{1 to} t ₇ .

As described above, the signal charge is m− of the vertical charge transfer element 12.
It suffices to disperse and store the data in one transfer stage before transferring. As a result, the storage capacity required for each transfer stage of the vertical charge transfer device 12 can be reduced to 1 / (m-1) as compared with the conventional method, and the area of the vertical charge transfer device 12 region can be greatly reduced. The ratio of the openings can be dramatically increased. Note that the above effect is obtained regardless of the electrode structure of the horizontal charge transfer element 13.
You can get enough. Similarly, the vertical transfer shift register 1
6, the buffer circuit 17 and the vertical shift register 18 can be sufficiently obtained without depending on their specific circuit configurations.
Further, in the embodiment, the case where the storage area 20V and the transfer area 21V are provided in one transfer stage has been described, but the transfer area 21V may not be provided.

Next, a second reference example related to the present invention is shown in FIGS.
This will be described with reference to the figure.

FIG. 5 is a timing diagram of drive pulses similar to FIG. 2, and FIG. 6 is a potential diagram of the vertical charge transfer device 12 similar to FIG. In both figures, only timings t _{1 to} t ₃ are shown for convenience of explanation.

In the circuit operation of FIG. 1, with the storage region 20 of each transfer stage in the vertical charge transfer device 12 being filled with the signal charges, the voltage of each transfer stage changes from high to low, and the signal charges are transferred. It At this time, if the potential under the electrode of the previous stage is low, the potential barrier under the transfer region 21 of the transfer stage is modulated by the electrolysis of the previous stage, and charges flow in the direction opposite to the transfer direction, resulting in a decrease in transfer efficiency. Occurs.

In this case, as shown in FIGS. 5 and 6, first, n
The transfer of the signal charges starts from the transfer stage of the + 1th row, and the signal charges are accumulated in the plurality of transfer stages including the nth row (t = t _{1 in} FIG. 6). Next, the under-electrode potential of the nth row becomes high, and the signal charges are transferred from the transfer stage of the nth row (t = t _{2 in} FIG. 6). At this time, since the under-electrode potential of the n + 1th row remains high, the n + 1th row to the n + 1th row
Prevents backflow of charge into the rows. After the charge transfer from the nth row is completed, the potential on the n + 1th row is lowered to
The signal charges are accumulated for the next transfer (t = t _{3 in} FIG. 6).

In this way, by repeatedly performing the operation of changing the potential of each transfer stage from high to low in the state where the potential under the electrode of the preceding stage is high (the potential is low), the charge flows in the opposite direction. It is possible to prevent the vertical charge transfer with good transfer efficiency.

Next, a third reference example relating to the present invention is shown in FIGS.
This will be described with reference to the figure.

FIG. 7 is a timing diagram of drive pulses similar to FIG. 2, and FIG. 8 is a potential diagram of the vertical charge transfer element 12 and the like similar to FIG.

In the circuit operation shown in FIG. 1, the channel width of the vertical charge transfer element 12 may become extremely narrow, which may reduce the efficiency of charge transfer.

In this case, as shown in FIG. 7 and FIG.
When the signal charge is transferred from the transfer stage of the row, a small portion of the signal charge is left in the transfer stage of the fourth row (eighth).
(T = t _{1 in the} figure). Next, the signal charges are transferred from the transfer stage of the third row. Also at this time, a slight signal charge is left in the transfer stage of the third row (t = t _{2 in} FIG. 8). Furthermore, the transfer is performed from the transfer stage of the second row. From this time, the potential of the transfer stage of the 4th row is increased again, and at time t ₁ , the charges remaining in the transfer stage of the 4th row are transferred to the transfer stage of the 3rd row (t = t _{3 in} FIG. 8). ). After that, the signal charges in the first row are transferred to the horizontal charge transfer element 13, and the charges remaining in the third row by the previous transfer are transferred in the second row (t = t _{4 in} FIG. 8).

After that, the same two-stage transfer is performed in all transfer stages, and at the end of the vertical charge transfer, all the signal charges are sent to the horizontal charge transfer element 13 with a low transfer loss (see FIG. 8). t = t ₅ ).

As described above, the transfer efficiency is improved by outputting a plurality of pulse trains from the vertical transfer shift register 16 in one horizontal scanning period and performing the vertical charge transfer operation in FIG. 2 and FIG. 3 a plurality of times. You can If the number of pulse trains is 2 or more, the effect of this method can be sufficiently obtained.
The time interval of the pulse train may be any value as long as it is at least twice the shift cycle of the pulse train output from the vertical shift register 18.

Next, a fourth reference example relating to the present invention will be described with reference to FIG.

FIG. 9 is a circuit configuration diagram of a solid-state image pickup device in which one transfer stage of the vertical charge transfer device 12 is provided for each of the two photodiodes 11.

In the circuit of FIG. 1, the horizontal scanning repetition period T _V must be ensured so that the signal charges in the nth row and the n + 1th row are not mixed.
It is necessary to finish the vertical charge transfer within. Now, assuming that the number of transfer stages of the vertical charge transfer device 12 is N _V , the scanning frequency f _V of the vertical transfer shift register 16 needs to satisfy the following expression (1).

f _V ≧ N _V / T _V (1) Since one transfer stage in the vertical charge transfer element 12 is provided for each photodiode 11, the photodiode 11
N _V of pixels in the vertical direction and the number of transfer stages of the vertical charge transfer device 12
Although it is equal to N _V , if the number of vertical pixels n _V increases as in a high-resolution solid-state image sensor, the number of transfer stages N _V also increases and the horizontal scanning repetition period T _V becomes shorter, resulting in vertical transfer. The scanning frequency f _V of the shift register 16 becomes high, and the efficiency of vertical charge transfer is reduced.

In this case, as shown in FIG. 9, one for each of the plurality of photodiodes 11 is provided in one transfer stage in the vertical charge transfer device 12.
By providing one, the scanning frequency f _V of the vertical transfer shift register 16 is reduced. That is, one transfer stage is provided for each of the two photodiodes 11 inside the vertical charge transfer element 12-1, and the buffer circuit 1 is provided from the vertical transfer shift register 16.
7, through the vertical pulse line 51, one output is sent to one transfer means corresponding to the two photodiodes 11. The operation of the circuit is similar to that shown in FIG.

As a result, the number of transfer stages of the vertical charge transfer element 12-1 is halved as compared with the case of FIG. 4 and the scanning frequency f _V is reduced to ½, so that the efficiency of vertical charge transfer can be improved. it can. Even if one transfer stage is provided for two or more photodiodes 11, the effect of this method can be sufficiently obtained.

Next, a first embodiment of the present invention will be described with reference to FIGS.

FIG. 10 is a timing chart of the drive pulse shown in FIG.
FIG. 11 is a vertical charge transfer device at the timing shown in FIG.
12 transfer stages (1,2,3, ... m, ..., 485), transfer gate 19 (T
G) is a potential diagram of the horizontal charge transfer device 13 (H1).

The smear phenomenon in the CCD solid-state image sensor is caused by the charges generated in the device substrate during the process of vertical charge transfer.
Since smears occur because they are collected in the potential well of the vertical charge transfer device 12, smear does not occur unless the potential well is present. Therefore, as shown in FIGS. 10 and 11, the potential well is formed only in a plurality of transfer stages that store and transfer charges, and the potential well is moved to reduce the amount of smear mixed in. Transfer charge.

First, at t ₁ in FIGS. 10 and 11, the potentials of all the vertical pulse lines 51 from the 3rd row to the m + 1th row are made high, and one potential well is formed under the electrodes of the corresponding transfer stages. It is formed and signal charges are accumulated in it. Note that m-1 is a value obtained by dividing the time during which the potential of the vertical pulse line 51 is at a high level by the shift cycle of the vertical transfer shift register 16, and determines the length of the potential well to be formed. At this time, the potential well is not formed by applying a low voltage to the vertical pulse lines 51 of the rows other than the above so that the potential under each electrode becomes equal to the substrate potential (t _{1 in} FIG. 11).

After that, the potential of the vertical pulse line 51 in the (m + 1) th row is increased to transfer the signal charge, and the transfer stage in the second row is newly set to the range of the potential well (t _{2 in} FIG. 11).

By moving the potential well by repeating the above operation,
The signal charge is transferred from the vertical charge transfer element 12 to the horizontal charge transfer element 13
It is transferred in (t ₃ , t _{4 in} Fig. 11).

As a result, the storage capacity required for each transfer stage of the vertical charge transfer element 12 can be reduced to 1 / (m-1) of the conventional method in this embodiment as well, and the area of the vertical charge transfer element 12 region can be reduced. Can be significantly reduced, and the ratio of openings can be dramatically increased.

Further, the number of potential well smear charge accumulates by you conventional _{(m-1) / N V} , smear can be greatly reduced. For example, when the above ratio is 1/50, it is possible to improve about 34 dB.

In this embodiment, since the signal charge of the photodiode 11 is transferred to the vertical charge transfer element 12 when the potential well is formed in the vertical charge transfer element 12, the time to turn on the photogate 15 is set for each row. You have to choose. This selection can be easily realized by providing a synchronizing circuit outside the element. In addition, a plurality of vertical transfer shift registers 16 (m-
A pulse train over one shift cycle is disclosed in
The shift register described in Japanese Patent No. 53-69793 may be used to select the feedback period as m and omit the buffer circuit 17 to output directly to the vertical pulse line 51.

Next, a second embodiment of the present invention will be described with reference to FIGS. 12 to 14 (a) and (b).

FIG. 12 is a circuit configuration diagram of a solid-state image sensor when the two-pixel simultaneous reading method and the smear differential method are used, and FIG.
FIG. 12 is a timing chart of the drive pulse, and FIG.
The potential diagram of the vertical charge transfer element 12 at the timings t ₁ and t ₂ in the figure, and FIG. 13B shows the timings t _{3 to} t _{8 in} FIG.
Sweep gate (SG) and drain (SD), under the horizontal charge transfer element 13 electrode (H1), transfer gates (TG1 to T)
It is a potential diagram of G3).

In FIG. 12, 31 and 32 are sweep gates and their drains for sweeping smear charges to the outside of the element, and 33 is synchronized with an output pulse from the vertical shift register 18 and performs row selection necessary for simultaneous reading of two pixels. Interlace circuit, 13-1
13-13 are first to third horizontal charge transfer elements for reading a first signal, a second signal and a smear signal, respectively, and 14-1 to 14-3 are first to first Output units 19-1 to 19-3 of the third horizontal charge transfer device are first to third transfer gates, respectively, between the vertical charge transfer device 12 and the first horizontal charge transfer device 13-1, and 1st and 2nd horizontal charge transfer device
13-1, 13-2, the second and third horizontal charge transfer elements 13-2,
Gate between 3 and 3. As the interlace circuit 33, for example, the circuits described in Japanese Patent Application No. 57-144042 and Japanese Patent Application No. 55-54158 are used. In addition, horizontal charge transfer device
For 13-1 to 13-3, since two signal charges and one smear charge are read simultaneously, parallel horizontal charge transfer elements are used.

In FIG. 13, HBL, V1 to V485, H1 are the same signals as in FIG. 2, VP1 is the potential of one vertical gate line 50, and VP2 is the potential of the other vertical gate line 50, and the signals are read out. Timing varies depending on the line. TG1 to TG3 are first to third
Transfer gates 19-1 to 19-3, SG is a sweep gate
31 potential.

In FIGS. 14A and 14B, 41 is a smear charge swept to the outside of the device, and 42 is a third horizontal charge transfer device 13-3.
Smear electric charge read out at, 43 is the second horizontal charge transfer element 13-
2 is the signal charge of the n-th row read by 2 and 44 is the signal charge of the n + 1-th row read by the first horizontal charge transfer element 13-1. Further, m _S in FIG. 13A is a value obtained by dividing the time interval tm _S between the smear sweep pulse train and the smear read pulse train shown in FIG. 13 by the shift cycle of the vertical transfer system register 16, and m ₁ is the smear. A value obtained by dividing the time interval tm ₁ between the read pulse train and the first signal read pulse train by the shift cycle of the vertical transfer shift register 16, and m ₂ is the first signal read pulse train and the second
It is a value obtained by dividing the time interval tm ₂ of the signal reading pulse train by the shift cycle of the vertical transfer shift register 16.

The operation of this circuit is that the vertical transfer shift register 16 sequentially lowers the potential of the vertical pulse line 51 for each transfer stage from the 485th line at a certain time of horizontal scanning including the horizontal blanking period, and the vertical charge transfer device is operated. Move the first potential barrier into 12. Then, after tm _S time, the second electric potential barrier, the third electric potential barrier after tm ₁ and the fourth electric potential barrier after tm ₂ are sequentially arranged in order from the 485th line to the vertical charge transfer device 12 Start moving inside. As a result, at a certain time of vertical charge transfer, the first potential well across the m _S −1 transfer stages of the vertical charge transfer element 12 and the second potential well including the m ₁ −1 transfer stages. If, so that the third potential well consisting of transfer stages of m ₂ -1 stage is it formed.

The signal charge of each photodiode 11 has a voltage applied to the corresponding photogate 15 by the timing of an external synchronization circuit when each potential well passes near the row selected by the vertical shift register 18 and the interlace circuit 33. It is applied and transferred to the potential well in the vertical charge transfer device 12. It should be noted that the selection of each row is performed after the shift of the fourth potential barrier in the previous scanning period is completed and the vertical transfer shift register 16
Just before the next operation.

After the signal charge is transferred from the photogate 15, the smear charge 41 to be swept from the first potential barrier during the transfer stage of the first row is read out to the horizontal charge transfer element 13 in the first potential well. Smear charge 42, the signal charge 43 of the nth row in the second potential well, and the signal charge of the n + 1th row in the third potential well.
44 will be accumulated respectively. (T = t _{1 in} FIG. 14 (a)).

After that, when the pulse train from the vertical transfer shift register 16 moves one transfer stage, each potential well also moves one transfer stage (t = t _{2 in} FIG. 14A). By repeating this operation, the smear charge 41 to be swept, the smear charge 42 to be read,
The first signal charges 43 and the second signal charges 44 are transferred to the horizontal charge transfer elements 13-1 to 13-3 without being mixed.

When the first potential barrier approaches the first row, the smear charge 41 is sequentially swept from the sweep gate 31 (t = in FIG. 14 (b)).
t ₃ ).

After this, in the horizontal blanking period, the sweep gate
31 is turned off, and the charges are sent from the vertical charge transfer device 12 to the parallel horizontal charge transfer devices 13-1 to 13-3. First, the first transfer gate 19-1 is turned on, a voltage is applied to the electrodes of the horizontal charge transfer devices 13-1 to 13-3 to lower the potential, and the smear charge 42 is transferred to the first horizontal charge. Transfer to the transfer element 13-1 (t = t _{4 in} FIG. 14B). Note that the transfer is continued until the second potential barrier reaches the first row.

After this, the first transfer gate 19-1 is turned off,
The electrode potentials of the horizontal charge transfer devices 13-1 to 13-3 are increased, a voltage is applied to the second transfer gate 19-2 to decrease the potential, and the smear charge in the first horizontal charge transfer device 13-1 is reduced. 42 is transferred below the electrode of the second transfer gate 19-2 (t = t _{5 in} FIG. 14 (b)). Next, 1 transfer gate 19
-1 is turned on again and the horizontal charge transfer elements 13-1 to 13-13
-3 voltage is applied to the electrode to lower the potential,
Of the first charge transfer element 12 is transferred from the vertical charge transfer element 12 into the first horizontal charge transfer element 13-1 and the smear charge 42 is transferred to the second transfer gate. Transfer from 19-2 to the second horizontal charge transfer device 13-2 (t = t _{6 in} FIG. 14 (b)). When this operation is repeated and the fourth pulse train of the vertical transfer shift register 16 reaches the first row, the smear charge 42 and the second horizontal charge transfer to the third horizontal charge transfer element 13-3. The signal charge 43 of the nth row is applied to the element 13-2 by the first horizontal charge transfer element 13-1.
The signal charges 44 in the (n + 1) th row are transferred to the
14 (b) t = t ₇ , t ₈ ).

In the horizontal scanning period, three horizontal charge transfer elements 13
−1 to 13-3 operate at the same time to output smear charge 42, signal charge of the nth row, signal charge 44 of the n + 1th row to output sections 14-1 to 14−
Output from 3 at the same time.

After that, by subtracting the smear charges 42 from the signal charges 43, 44, it is possible to generate only the signal charges of the nth row and the n + 1th row in which the smear charges are not mixed. In the next field, interlaced scanning is possible by reading out the signal charges of the n-1th row and the nth row.

Thus, by forming a plurality of potential wells in the vertical charge transfer device 12 and moving them to simultaneously transfer a plurality of charge packets, the area of the vertical charge transfer device 12 region is increased. Without it, both two-pixel simultaneous reading and smear differential can be realized. Moreover, since the signals are transferred by the potential wells extending over a plurality of transfer stages of the vertical charge transfer device 12, the storage capacity required for each transfer stage can be reduced as in the first embodiment, and the area of the vertical charge transfer device can be reduced. Can be significantly reduced. In this embodiment, three horizontal charge transfer elements 13-1 to 13-3 are arranged in parallel to read the smear signal and the first and second signals.
If the above three signal charges can be read, any number of one or more may be used. The interlace circuit 33 can be used without depending on the specific circuit configuration. It can be realized without performing the sweeping operation of the smear charges by the sweeping gate and drains 31 and 32. The vertical transfer shift register 16 may start the pulse train transmission operation during the scanning period.

In the smear differential method used also in this embodiment, the random noise is generally increased by the arithmetic processing, and the S / N ratio is lowered. In the conventional method in which the amount of smear mixed in the signal charge and the amount of smear when reading only the smear are the same,
The total random noise Nt can be expressed as Nt ² = Sn ₁ ² + Sn ₂ ² (2). However, Sn ₁ and Sn ₂ are the amounts of random noise mixed in the signal charge and smear charge, respectively.

When Sn ₁ ² = Sn ₂ ² , noise is 3dB due to smear differential
In Although this embodiment will increase, m ₁ for smear mixed at a potential barrier that precedes the smear amount and smear amount of differential mixed in the signal is also mixed into the potential well: m _S or m, ₂ : m _S. Now, assuming that m ₁ = m ₂ = mm, the total random noise N't ² after smear differential isN't ² = Sn ₁ ² + mm ² · Sn ₂ ² / m _S ² ... (3) can be represented. That is, the number of transfer stages ms-1 of the potential well formed to store and transfer smear is made larger than the number of transfer stages mm-1 of the potential well formed to store and transfer signal charge (ms> mm), By increasing the amount of smear when extracting only the smear signal to be larger than the amount of smear mixed in the signal, it is possible to prevent an increase in random noise due to smear differential and obtain a high S / N ratio. Note that m ₁ , m ₂ , m
The value of _S is an arbitrary value of 2 or more. Also in the present embodiment, as in the case of FIG. 11, the vertical charge transfer element other than the region where the smear charge and the two signal charges are accumulated and transferred.
It can be carried out by a driving method in which the under-electrode potential of 12 is made equal to the substrate potential. Further, in this embodiment, the sweeping operation of the smear charge can be made unnecessary, so that the sweeping gate 31 and the sweeping drain 32 shown in FIG. 12 are unnecessary.

Next, a third embodiment of the present invention will be described with reference to FIGS.

FIG. 15 is a circuit configuration diagram of the solid-state imaging device when the vertical shift register 18 is omitted, FIG. 16 is a circuit configuration diagram of one stage of the row selection circuit, and FIG. 17 is an operation timing diagram of FIG. .

In FIG. 15, 34 is the vertical shift register 18 of FIG.
Is a row selection circuit that plays a role of, and a row selection pulse signal synchronized with a pulse train output from the vertical transfer shift register 16 is input from the outside of the element to perform row selection of the element. Other numbers and operations are the same as those in FIG.

In FIGS. 16 and 17, V _PD is a row selection pulse for selecting a row, and V _SR is a vertical transfer shift register 1 for a certain row.
6 outputs, V ₁ and V ₂ are each one of two phase clocks for driving the vertical transfer shift register 16, V _R is a reset clock for resetting the row selection circuit, and V _OUT is sent to the interlace circuit 33. Output of row selection circuit, T1 to T9 are MOS
Transistors'a ',' a ', and'c' are node voltages.

The row selection circuit 34 selects only the first pulse in the pulse train of a certain row output from the vertical transfer shift register 16 (V _SR ), and ANDs the pulse with the row selection pulse V _PD applied from the outside. By selecting, the row of the photodiodes 11 is selected. First, when the first pulse synchronized with the clock V ₂ is input from the vertical transfer shift register 16, the MOS transistor T1 becomes conductive, and the node “a” becomes a high voltage, and the MOS transistor T2 also becomes conductive.

After that, when the clock V ₁ is input, the MOS transistor T
2 → node “a” goes high → MOS transistor T3 → node “c” goes high → MOS transistor T4 becomes conductive. Then, when V ₁ becomes 0V, the node'a 'becomes 0V, but the node'c' remains at a high potential, and the conduction state of T4 continues thereafter. In this state, when the second pulse synchronized with the clock V ₂ delayed by one clock from the first pulse is input from the vertical transfer shift register 16, the MOS transistor T5 becomes conductive and the voltage of the node'a 'becomes low. As a result, MOS
The transistor T2 does not become conductive thereafter, and the voltage of the node'a 'is kept low. That is, the voltage of the node'a 'becomes high for 0.5 clock time after the input of the first output pulse from the vertical transfer shift register 16, and at this time, the row selection pulse V _PD from the outside is input to the gate of the MOS transistor T6. The output V _{OUT then} goes to a high voltage and selects a row of devices. After this, the blanking period starts, and the reset clock is set immediately before the operation of the vertical transfer shift register 16.
V _R is input to reset the row selection circuit 34.

As described above, by using the row selection circuit 34 and inputting the row selection pulse synchronized with the pulse train of the vertical transfer shift register 16 from the outside, the row selection can be performed without using the vertical shift register 18, and the connection pin or the component can be selected. The number can be reduced to simplify the device circuit.

Next, a fifth reference example related to the present invention is shown in FIGS.
This will be described with reference to the figure.

FIG. 18 is a circuit configuration diagram of the solid-state image pickup device when the blooming phenomenon is suppressed, and FIG. 19 is a timing diagram of the drive pulse of FIG.

In FIG. 18, 35 and 36 are RABs for suppressing blooming.
Circuit gates and their drains
It is similar to the figure.

When the solid-state image sensor is exposed to strong light, the photodiode
11 is saturated, excess charge overflows into the vertical charge transfer element 12, that is, a blooming phenomenon occurs, and similar to the case of smear, white strip-shaped pseudo-overlaps are formed above and below the portion on the screen where strong light is applied. A signal appears, degrading image quality. In this embodiment, the RAB circuit method described in Japanese Patent Application No. 55-130240 is used to provide a photodiode just before the signal charge is read out.
A part of the signal charge accumulated in 11 is swept out of the element and the signal charge in the non-saturated state is read out to suppress the blooming phenomenon.

In this circuit, a series of pulse train transmission by the vertical transfer shift register 16 is completed and immediately before starting the next transmission operation, as shown in FIG.
Apply a high voltage to the gate 35 of the circuit, then from the RD end to RAB
A small voltage is applied to the drain 36 of the circuit to slightly open the photogates 15 of all the pixels (photodiodes 11), and a part of the saturated charges of the photodiodes 11 are vertically transferred.
Pour to 12. After that, the drain 36 of the RAB circuit → gate 35
The voltage is lowered in the order of and the photogate 15 is'closed '.
As a result, at the time of reading the smear charge and the two signals, the photodiode 11 is in the state before the saturation, so that the blooming phenomenon does not occur. The vertical charge transfer device 12
The charges that have flowed in are swept out of the device along with the smear charges. The subsequent operation is exactly the same as that shown in FIG.

In this way, just before reading a signal from the photodiode 11, only the saturated charges are swept out of the element to bring the photodiode 11 into a non-saturated state, so that the blooming phenomenon can be suppressed.

〔The invention's effect〕

As described above, according to the present invention, in the interline CCD, a plurality of (m-
Since the area of the vertical charge transfer element region is reduced by being dispersed in the transfer stage of 1), the ratio of the opening can be greatly increased and the sensitivity is improved. In addition, the simultaneous readout of two pixels and the smear differential method can be realized without reducing the ratio of the openings or making the planar structure of the pixel section complicated and overcrowded, and the solid-state image sensor has high sensitivity, high resolution, low smear, High yield.

[Brief description of drawings]

1, FIG. 9, FIG. 12, FIG. 15, and FIG. 18 are reference circuit diagrams relating to the present invention and a circuit configuration diagram of a solid-state imaging device showing an embodiment of the present invention, FIG. 2, FIG. , Fig. 7, Fig. 10, Fig. 13
Fig. 19 and Fig. 19 are timing diagrams of drive pulses, Fig. 3 and Fig. 8 respectively.
Figures and 11 are potential diagrams of vertical charge transfer elements, transfer gates, and horizontal charge transfer elements. Figure 4 is a circuit diagram of a conventional solid-state image sensor. Figures 6 and 14 (a) are vertical charge transfer elements. Fig. 14 (b) is a potential diagram of the device, Fig. 14 (b) is a potential diagram of the sweep gate and drain, the horizontal charge transfer device, and the transfer gate. Fig. 16 is a circuit configuration diagram of one stage of the row selection circuit,
FIG. 17 is an operation timing chart of FIG. 1, 11: photodiode, 2, 12, 12-1: vertical charge transfer device,
3,13,13-1 to 13-3: Horizontal charge transfer device, 4,14,14-1
14-3: Output part, 5, 15: Photogate, 16: Vertical transfer shift register, 17: Buffer circuit, 18: Vertical shift register, 1
9,19-1 to 19-3: Transfer gate, 20: Storage area, 21: Transfer area, 31: Smear sweep gate, 32: Smear sweep drain, 33: Interlace circuit, 34: Row selection circuit, 35: RAB circuit , 36: Drain of RAB circuit, 41: Smear charge to be swept out, 42: Smear charge to be read out, 43: nth signal charge, 44: n + 1th signal charge, 50: Vertical gate line, 51:
Vertical pulse line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinya Oba 1-280, Higashi Koigakubo, Kokubunji City, Central Research Laboratory, Hitachi, Ltd. (56) References JP 59-68970 (JP, A) JP 58-156272 (JP, A)

Claims (7)

(57) [Claims] 1. A photoelectric conversion element arranged two-dimensionally, a vertical charge transfer element having a plurality of electrodes for vertically transferring a signal charge from the photoelectric conversion element, and a signal charge of the photoelectric conversion element. Row selection means for selectively transferring to the vertical charge transfer element in horizontal rows, a shift register for sending a drive pulse to each electrode of the vertical charge transfer element, and a signal charge from the vertical charge transfer element In the solid-state image pickup device having a horizontal scanning means for outputting, a potential well across a plurality of electrodes for transferring signal charges in the vertical charge transfer device is formed and moved by the drive pulse. Solid-state image sensor. 2. The drive pulse forms a potential barrier under the electrode of the vertical charge transfer element at intervals of n times (n: an integer of 3 or more) the data shift cycle of the shift register. The solid-state image sensor according to claim 1. 3. The shift register ends data shift at a predetermined time within horizontal blanking, and signal charges are transferred from the photoelectric conversion element to the potential well formed in the vertical charge transfer element. The solid-state imaging device according to claim 1, wherein the application time of the signal transfer pulse applied to the row selected by the row selecting means is different for each row. 4. The shift register completes a data shift within one horizontal scanning period including one horizontal blanking period, and the row selecting means sets a first row for each horizontal scanning period of the shift register. The solid-state imaging device according to claim 1, wherein row selection is performed by taking a logical product of the output of 1 and a row selection pulse applied from the outside. 5. A photoelectric conversion element arranged two-dimensionally, a vertical charge transfer element having a plurality of electrodes for vertically transferring a signal charge from the photoelectric conversion element, and a signal charge of the photoelectric conversion element Row selection means for selectively transferring to the vertical charge transfer element in horizontal rows, a shift register for sending out a pulse train for driving the vertical charge transfer element, and outputting a signal charge from the vertical charge transfer element In the solid-state imaging device having the horizontal scanning means for performing the above, a plurality of potential wells for independently transferring a plurality of signal charges are formed and moved in the vertical charge transfer device by the pulse train transmitted by the shift register. A solid-state image sensor characterized by the above. 6. A photoelectric conversion element arranged two-dimensionally, a vertical charge transfer element having a plurality of electrodes for vertically transferring a signal charge from the photoelectric conversion element, and a signal charge of the photoelectric conversion element. Row selection means for selectively transferring to the vertical charge transfer element in horizontal rows, a shift register for sending out a pulse train for driving the vertical charge transfer element, and outputting a signal charge from the vertical charge transfer element In the solid-state imaging device including the horizontal scanning means for performing the operation, the pulse train transmitted by the shift register mixes the potential well for transferring at least one signal charge to the vertical charge transfer device and the vertical charge transfer device. A potential well for transferring smear charges is formed and moved, and signal charges and smear charges independently read from the vertical charge transfer element are subtracted to transfer signals of pure signal charges. Solid-state imaging device characterized in that it comprises a smear differential means for obtaining. 7. The number of electrodes of the vertical charge transfer element forming the potential well for transferring the smear charge is larger than that of the vertical charge transfer element forming the potential well for transferring the signal charge. The solid-state image sensor according to claim 6.