JPS60167579A - Charge transfer type solid-state image pickup element - Google Patents

Abstract

PURPOSE:To improve a smear suppression factor and to reduce the power consumption by providing a CCD shift register which stores the smear charge as well as the optical signal charge and obtaining the difference between stored optical and smear signals in order to delete the smear component. CONSTITUTION:The optical signal charge stored to a photodiode for a field period is read out within a vertical CCD shift register 2 via a transfer gate 7 at a time point t1 and sent to a CCD shift register 15-1 for storage of signals. Then the register 2 is driven again in its idle state at a time point t2 and sends the leakage smear charge to a shift register 15-2 for storage of smear. Then the optical signal charge and then the smear charge are sent into the horizontal CCD shift registers 3-2 and 3-1 respectively at a time point t3 when the transfer is through with both optical signal and smear charges. Then these CCD shift registers are driven at a time point t4, and the optical and smear signals are extracted successively to outputs 4-2 and 4-1 respectively to undergo the subtraction.

Description

Detailed Description of the Invention [Field of Application of the Invention] (2) The present invention provides a photoelectric conversion element on a semiconductor substrate and a charge transfer element for extracting optical information of each element.
Pled Device, hereinafter abbreviated as CCD. ) is related to a solid-state image sensor using

[Background of the invention]

Solid-state image sensors need to have resolving power comparable to the imaging electron tubes used in current television broadcasting.
Therefore, there are 500 pieces in the vertical direction and 800 to 10 pieces in the horizontal direction.
A matrix of 00 picture elements (photoelectric conversion elements) and a corresponding scanning element are required. Therefore, the solid-state imaging device is manufactured using MO8 large-scale circuit technology that requires high integration, and generally uses COD or MOS transistors as constituent elements. FIG. 1 shows the basic configuration of a CCD-type solid-state image sensor, which is characterized by low noise. l is a photoelectric conversion element consisting of, for example, a photodiode, 2
and 3 are a vertical COD shift register and a horizontal shift register for taking out the optical signals accumulated in the photoelectric conversion element group to the output terminal 4. 5 and 6 are clock pulse generators for producing clock pulses for driving the vertical shift registers and the horizontal shift register (3). Although a two-phase clock pulse generator is illustrated here, either a four-phase or three-phase clock format may be adopted. Further, numeral 7 indicates a transfer gate that sends the charges accumulated in the photodiode to the vertical shift register 2. If this element is left in its current form, it will not be able to capture a monochrome image, but if a color filter is stacked on the negative side, each photodiode will be provided with color information, resulting in a color image.

As is well known, solid-state imaging devices have many advantages over electron tubes, such as being small, lightweight, maintenance-free, and low power consumption, and are expected to have a promising future as the next imaging device.

However, when an image is captured using the current device and a reproduced image is displayed on a monitor, vertical patterns appear above and below a high-luminance optical information pattern (ie, a bright pattern), significantly degrading the image quality. This phenomenon is unique to solid-state devices and is called lithomere.

(4) As a means to remove this smear, a frame interline transfer type COD solid-state image sensor as shown in Fig.
11 is the imaging area, which is composed of a vertical CCD shift register and a photodiode.1
Reference numeral 2 denotes an accumulation region for temporarily accumulating signal charges stored in the photodiode, and is composed of a selection gate 8, a COD shift register 9 for accumulation, and an output gate 1O. Inter L
By /-space scanning (interlace scanning), the signals of the photodiodes in the odd columns are read out in the first field, and the signals of the photodiodes in the even columns are read out in the second field. In the device with this configuration, in the first field, the signal charges 1, 3, 5, 7, . ...is transfer gate 7-IL.

The signal is read into the vertical CCD shift register through 7-IR, and then transferred to the storage COD shift register by high-speed driving of the vertical COD shift register. Here, the signal (5) (1,5,...) outputted via 7-IL is the signal outputted via 7-IR to the storage CCD 9-I on the left side by opening and closing of the selection gate 8. (
3, 7, . . . ) are transferred to the storage CCD 9-H on the right side by opening and closing the selection gate 8. Next, the storage COD is driven at the standard TV drive frequency (15.7kHz), and the regular arrangement order (
1, 3, 5, 7, . . . ), the photodiodes in each column are sent column by column into the horizontal CCD shift register 3, and an optical signal is taken out at the output terminal 4. On the other hand, a similar signal read operation is performed in the second field (description of the operation will be omitted).

In the image pickup device of this configuration, compared to the conventional device shown in FIG. 1, the time for the optical signal charge to pass through the image pickup section is shorter, so the time required for accumulating smear charges is shorter, and as a result, The amount of smear charge decreases. For example, if the vertical CCD shift register is driven at 785 kHz (50 times the standard speed), the amount of smear charge will be reduced to 115°.

Although this configuration has made it possible to considerably improve smear (6)9, the device with this configuration has severe problems as described below.

(1) In order to increase the smear suppression rate, it is necessary to increase the speed at which optical signals are sent from the vertical COD shift register to the storage area. In order to increase the transfer speed, it is necessary to increase the driving frequency of the vertical CCD shift register and the storage COD shift register, which increases power consumption. Although the power depends on the drive frequency, in the case of the 785 kHz drive described above, the power increases by about 20 times compared to the conventional element (FIG. 1).

Furthermore, high performance is required of the electronic components that make up the drive circuit, raising the price of the video camera.

(2) When the transfer speed is increased, the transfer loss of the vertical COD shift register and storage COD shift register (CCD
As a result, the vertical resolution deteriorates and color mixture (in the case of a color element) occurs, resulting in deterioration of image quality.

(7) (3) When trying to achieve a smear suppression rate comparable to that of imaging electron tubes (in other words, when trying to suppress smear to a level that does not bother the human eye), the smear is about 1/1000 of that of conventional elements. must be suppressed. In the element with the above configuration, the driving frequency is 1.57 MHz (78 MHz).
Even if the frequency is increased to twice that of 5kHz, the suppression rate is 1/1.
00, and it must be improved by one order of magnitude (in reality, driving at 1.57 MHz is not practicable because it increases power consumption and transfer loss).

[Purpose of the invention]

The purpose of the present invention is to solve the problems described in "-", that is, to drastically improve the frame interline transformer type COD solid-state image sensor shown in FIG. The goal is to reduce

[Summary of the invention]

In order to achieve the above object, the present invention provides an accumulation CCD shift register (8) that is provided below the imaging area and stores smear charges at the same time as the optical signal charges in the charge accumulation area, and collects the optical signals from the photodiodes. After transferring the charges to the COD shift register for signal accumulation, the smear charges accumulated in the vertical COD shift register during this transfer period are transferred to the COD shift register for smear charge accumulation, and the light obtained through the horizontal COD shift register is transferred to the COD shift register for smear charge accumulation. The smear component contained in the optical signal is removed by taking the difference between the signal and the smear signal. here,
The transfer of the smear charge to the CCD shift register for smear accumulation may be performed before the transfer of the optical signal charge to the COD shift register for signal accumulation, by changing the order of the above case.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using examples.

The improved element configuration, which is the gist of the present invention, is shown in FIG. 1.
3 is a selection gate that opens and closes in synchronization with the optical signal or smear signal sent from the vertical CCD shift register 2; 3-
1 and 3-2 are horizontal CCD shift registers, for example, 3-1 directs the smear signal to output 4-1, and 3-2
transfers the optical signal towards output (9) 4-2. Reference numeral 14 denotes a sweep gate that sweeps out unnecessary charges accumulated in the vertical CCD shift register and takes them out to the drain 14d. The storage area 12 is 15-1
．． It is composed of two parts, 15-2, and 15-2.
1 is a signal accumulation COD shift register for temporarily accumulating optical signal charges, and 15-2 is a smear accumulation COD shift register for temporarily accumulating smear signals.

The operation of the COD solid-state image sensor of the present invention will be explained.

Transfer of optical signal charge and smear charge to the storage region is carried out by the fourth
This is done during the vertical blanking period as shown in the figure.

(1) When reading the optical signal charge from the photodiode to the vertical COD shift register, first shift the vertical COD at time t0.
By driving the vertical COD shift register in the opposite direction (arrow 16 in FIG. 3), unnecessary charges such as dark current components and smear charges accumulated in the shift register during one field period are swept out through the gate 14 and drained to the drain 14d. swept away.

(10) (2) At time 11, the optical signal charge accumulated in the photodiode during the field period is transferred to the vertical COD via the transfer gate 7.
Read into shift register.

Here, it is assumed that optical signal charges accumulated in photodiodes in odd-numbered columns in the first field and in even-numbered columns in the second field are read out. Therefore, in the first field, the transfer gate 7-1 is placed in a conductive state, and in the second field, the transfer gate 7-1 is placed in a conductive state.
In the field, transfer gate 7-2 is placed in a conductive state.

Subsequently (from time t2), by driving the vertical COD shift register in the positive direction (arrow 17 in FIG. 3), the data is sent to the storage COD shift register. Here, vertical CO
The driving frequency of the D shift register is 115 to 1/10 of the frame interline transfer type shown in Figure 2.
A low frequency (for example, about 150 kHz) may be sufficient.

The optical signal charge of the vertical CCD shift register is transferred to the signal storage CC by applying an l'' level voltage (high voltage) to the selection gate 13-1 and making the selection gate 13-1 conductive.
T') is sent to shift register (11) 15-1. On the other hand, the selection gate 13-2 is kept in a non-conducting state (a ``0'' level voltage is applied to the selection gate 13-2) while the gate 13-1 is in a conducting state, so that the optical signal charge is transferred to the smear accumulation CCD. Here, the optical signal charge is sent to the COD shift register for signal accumulation, so the electrodes constituting the COD shift register for signal accumulation have 1" g, z
Although it is necessary to apply a clock pulse of ron, the same clock pulse as that for the signal accumulation COD shift register may or may not be applied to the electrodes constituting the smear accumulation CCD shift register. If the voltage is applied, the smear accumulation CCD shift register simply operates in an empty state with no charge, and no harm is caused.

(3) When the transfer of the optical signal charge is completed, at time t2, the vertical COD shift register is driven again in the empty state (state with no optical signal charge). Generally, the driving frequency is preferably the same as that when transferring optical signal charges. in this case,
The amount of smear charge that leaks during the driving of the vertical CCD shift register (12) is the same as the amount of smear charge that leaks when the optical signal charge is transferred previously. Here, the selection gate 13-2 is in a conductive state (1
11# level voltage is applied), and the selection gate 13-1 is in a non-conducting state (CrtOn level voltage is applied), so the smear charge leaked to the vertical COD shift register mentioned above is transferred to the selection gate 13. -2 to the smear storage 15-2.

If the driving frequency of the vertical COD shift register is made lower or higher than that during optical signal transfer, the amount of smear leakage will also increase or decrease. (Explained in Figure 5), the smear signal is amplified and the amplification factor is set to less than 1 or more than 1)
Just enter it into the subtracter. Here, C for smear accumulation
Since the smear charge is sent to the CD shift register, a clock pulse must be applied to the electrodes constituting the CCD shift register for smear accumulation. On the other hand, it is preferable to stop the operation of the CCD shift register (13) for signal accumulation (because the signal charge moves when it is operated), and for this purpose, clock pulses may not be applied.

(4) When the transfer of the smear charge is completed, transfer of the optical signal and the smear signal to the horizontal COD shift register starts at time t3. Therefore time t.

The operation from t3 to t3 is performed during the vertical blanking period, and after time t4, it becomes a video period. At time t3, the optical signal charge and smear charge stored in the location closest to the horizontal COD shift register are sent column by column to the horizontal CCD shift register. The period of feeding each column is 15.7kHz, which corresponds to the standard television frequency, and at the same time the charges in the front row are sent to the horizontal COD shift register, the charges accumulated in the storage COD shift register are transferred to the horizontal CCD shift register. Shift one row forward. In this embodiment, since two rows of horizontal CCD shift registers are provided, at time t3-1, the optical signal type (14) load once passes through the horizontal CCD shift register 3-1 and is shifted to the horizontal CCD shift registers 1 to 1. The smear charge is then pumped into the horizontal CCD shift 1 register 3-1 at time t3-2.

(5) When the charge transfer to the horizontal CCD shift 1-register is completed, driving of the horizontal CCD shift register starts at time t4, and the optical signal is taken out at the output 4-2 and the smear signal is taken out at the output 4-1 in time order. It will be done. In this embodiment, a horizontal COD shift register for optical signal transfer is placed on the outside, and a horizontal CCD shift register for smear signal is placed on the inside.
Even if a horizontal COD shift register for smear signals is placed on the outside and a horizontal COD shift register for optical signals is placed on the inside, there is no problem at all.

Output 4-2.4-1 with 2 rows of horizontal CCD shift registers
The optical signal and smear signal sent to the subtracter are subtracted by a simple circuit as shown in FIG.

(1) In the case of FIG. 5(a) (15) 4' is a charge detection circuit integrated within the CCD image sensor;
4 is an output, and 18' is a subtracter. The subtracter 18' may be integrated within the CCD image sensor or may be provided externally. Although various circuits can be used as the subtracter, it is generally preferable to use a differential amplifier that also has an amplification function. In this case, the two rows of horizontal COD shift registers output the optical signal (S□) and the smear signal (S8) at the same time.
The shift register is a horizontal CC whose corresponding COD electrodes are in phase.
The two signal outputs SA and S8 are input to a subtracter, and the output 18 of the subtracter is a true optical signal from which the smear signal has been subtracted (s-r
) can be obtained.

(2) In the case of FIG. 5(C), 19 is a delay circuit in which the smear signal is set for a predetermined time (t, for example, one pixel scanning period or 1/2 pixel scanning period) with respect to the optical signal. will only be delayed. Since the delay time is usually about several 10 n5ec to 100 (16) nsec, a commercially available delay line can be used as the delay circuit, or a sample and hold circuit can be used to integrate it into the same element. good.

In this case, the smear signal appears at the output 4-1 faster by one pixel or 1/2 pixel than the optical signal. Therefore, in the two rows of horizontal CCDs, the electrodes of the smear horizontal CCD are driven by clock pulses whose phase is earlier by 1 pixel or 172 pixels.

The smear signal (S8) appearing at the output 4-1 is sent to the delay circuit 1.
9 and is delayed by a predetermined time (So.) and input to the subtracter. As a result, a true optical signal (8 signals) from which the smear signal has been subtracted can be obtained at the output 18 of the subtracter.

In the above explanation, we considered extracting the smear signal earlier than the optical signal, but conversely, it is also possible to extract the optical signal earlier than the smear signal (which one is output earlier depends on the drive of the two horizontal CCDs). (can be decided depending on the person)
. If the optical signal is extracted quickly, a delay circuit will be provided on the optical signal side.

(17) The circuit configurations shown in FIGS. 5(a) and 5(c) are extremely simple, and there is no problem since the increase in camera price or power consumption is extremely small.

FIG. 6 shows an element configuration in which the area of the smear accumulation angle cco shift register is reduced and the area of the spectral signal accumulation CCD shift register is enlarged. 15'-2 is a CCD shift register for smear accumulation, 15'-1 is a CCD shift register for optical signal accumulation, 3'-1 is a CCD shift register for smear transfer, and 3'-2 is CCD for optical signal transfer.
This is an OD shift register. Generally, the amount of charge of a smear signal is about two times smaller than the amount of charge of an optical signal, so the size (electrode capacitance) of a COD shift register for smear storage or transfer can be reduced.

The advantages of the CCD element with this configuration are: (1) CO for optical signal storage;
Since the horizontal electrode dimension WH of the D shift register can be increased, the vertical dimension Wv can be reduced accordingly. In other words, the area of the storage region can be effectively reduced, and the chip size of the CCD element can be reduced (18) (the yield can be improved); (2) the optical signal charge can be horizontally reduced; When feeding into the COD shift register 3'-2, it is necessary to pass through the smear transfer CCD shift register 3'-1 located inside the hole, but the electrode size of the horizontal COD shift register 3'-1 is short. Therefore, the optical signal can be sent to the outer horizontal COD shift register at high speed and without transfer loss. The operation of the element of this configuration is the same as that of the previous embodiment (FIGS. 3, 4, and 5), so a description thereof will be omitted.

In the embodiments of FIGS. 3 and 6, two rows of horizontal CO
Although a D shift register is provided, an optical signal and a smear signal can also be transferred by one column of horizontal COD shift registers. In this case, it is sufficient to operate the horizontal COD shift register 3' in dual transfer mode (2
Double transfer mode means an operation in which two signals are sent by one stage of CCD, and when using three-phase clock pulses, [signal].

[Signal], [Empty bit] [Signal], [Signal].

[Empty bit] The transfer operation is performed as follows.

(19) Generally, if N-phase clock pulses are used, (N-1)
Although various types of signals can be transferred, in this case there are two types of signals, an optical signal and a smear signal, so it is desirable to use three-phase clock pulses to drive the horizontal COD shift register). The operation of the element with this configuration is the same as that described in FIG. 4 except for the time of transfer to the horizontal COD shift register. When transferring the charges in the storage COD shift register to the horizontal COD shift register, the optical signal charges and smear charges are transferred to the lower part of the adjacent COD electrode 20-1 at time t3.
20-2 at the same time. In this configuration, the COD shift register for optical signal accumulation is on the left side, and the CC for smear accumulation is on the left side.
Since the D shift register is located on the right side, the horizontal CO
After time t4, the charge on the D shift register circle is transferred toward output 4# in the order of optical signal, smear signal, empty, optical signal, smear signal, empty, . . . .

Subtraction of the two signals S, , S, in the element of this configuration can be performed by a circuit as shown in FIG.

21-1.21-2 is a switch that alternately samples two types of signals appearing at the output II 4 #j (20), and the opening and closing of this switch is 180' in synchronization with the clock pulse of the horizontal CCD shift register. Amount of sampling pulses φ with different phases.

This is done by φ2. In the device of this configuration, the optical signal appears first, so the switch 21-1 is made conductive, and the signal (Sl) appearing at the output 114gg is further passed through the delay circuit 22 for a predetermined time (tl). Delay (St-8
). Subsequently, the switch 21-2 becomes conductive and the smear signal S,
appears on output 4#. When the outputs 23-1 and 23-2 of the delay circuit are input to the subtracter 18', the true signal (ST
) can be obtained.

The drain drain does not have to be placed on the upper side as shown in FIGS. 3, 6, and 7, but may be provided in a portion of the storage area with sufficient space as shown in FIG. 9. In this case, the unnecessary charge transfer 16 in the vertical COD shift register before reading out the optical signal is in the same direction as the optical signal and the smear signal (17).
(21) It is swept out to the drain 14d'.

Furthermore, unnecessary charges are sent to the horizontal COD shift register via the CCD shift L nozzle for storage, and the horizontal COD
If the shift register is used to perform the sweep, the sweep input/in can be omitted.

Finally, we will provide some additional information about sweeping out unnecessary charges accumulated in the vertical COD shift 1 register. In the above embodiment, it was considered that the unnecessary charge is swept out once every 1° before the optical signal charge is read out from inside the vertical CCD shift register. Good too. The signal charge and smear charge of the previous field are already stored in the storage C.
Since these charges are being sent into the OD shift register, even if the vertical COD shift register is driven while these charges are being transferred through the horizontal COD shift register, unnecessary charges will be continuously swept out to the drain. I do not care. In this case, it becomes possible to suppress blooming (development in which a bright pattern spreads to the surroundings more than the true image). Blooming (22) A part of the charge leaks into the vertical CCD shift register through the transfer gate 7, so during the blooming period, the transfer gate 1
By increasing the voltage applied to - during the period when the optical signal or smear signal is transferred to the storage COD shift register and lowering the potential wall under the transfer gate, blooming charges can easily leak into the vertical COD shift register. If this is done, an even higher blooming suppression effect can be obtained. (If some of the electrodes forming the vertical CCD shift register also serve as transfer gate electrodes,
The above purpose is achieved by making the it i u level voltage of the clock pulse applied to the vertical CCD shift 1 register during the sweep period higher than the II 1 ' level voltage of the clock pulse applied during the optical signal or smear charge transfer period. It can be realized. ) In the embodiments shown in FIGS. 3, 6, 7, and 9, the selection gate 13 is provided between the vertical ClCD shift 1~register and the storage CCD shift I/register, but the selection gate is omitted. It is also possible. In the case of (23), for example, when sending the signal charge of the vertical COD shift register to the signal accumulation CCr shift register, only the signal accumulation COD is driven and the smear accumulation CCD shift register is not driven. On the other hand, when feeding the smear charge, the CCD shift register for smear accumulation is driven and the CCD shift register for signal accumulation is shifted! - All you have to do is not drive the register.

In the embodiments shown in FIGS. 3, 6, 7, and 9, the optical signal charges of the odd-numbered columns are read out in the first field, and the optical signal charges of the even-numbered columns are read out in the second field.
We considered transferring the optical signal charge to the storage COD shift register via the D shift register. On the other hand, optical signals from two adjacent rows of photodiodes can also be read out. In this case, the transfer gates 7-1 and 7-2 in two adjacent columns are made conductive at the same time, and in the first field (1, 2) (3° 4
)(5,6),..., in the second field, the signals of the photodiodes of (2.3)(4,5)(6,7) are shifted by one column.
), . Charges obtained by mixing signals from two adjacent columns of photodiodes are temporarily stored in the storage COD shift register in any field.

〔Effect of the invention〕

As described above using Examples, the solid-state imaging device of the present invention has extremely great practical value, and has the following advantages.

(1) The smear component can be significantly reduced by providing a region for accumulating the smear component at the same time as the signal component, reading out the signal and the smear signal simultaneously to the horizontal CCD shift register, and taking the difference between the two signals. Experiments conducted by the inventors have shown that it can be reduced to about 1/100. Vertical CCr
) to the storage CCr) at the standard frequency of 10
If the frequency is 1.57 kHz, which is twice as high, the lithium smear component will be reduced to 1/10 by this driving. Therefore, the above two effects make it possible to reduce the smear to /1000(25) (=1/100XI/10). As a result, the amount of smear can be suppressed to a level where there is no interlayer in practical use, and it has become possible to obtain image quality equivalent to that of an operating electron tube even in a solid-state image sensor.

(2) In the solid-state imaging device of the present invention, since the reduction of smear is performed by the above-mentioned differential force formula, the transfer of charge from the imaging region to the storage region is about one order of magnitude better than that of the device shown in FIG. It becomes possible to drive at a slow speed, that is, at a clock frequency about one order of magnitude lower. As a result, the power consumption of the drive circuit required for the solid-state image sensor of the present invention can be reduced to about 1/7 to 1/14. Transfer loss is significantly reduced, and resolution deterioration and color mixture can be prevented. Furthermore, since the number of electronic components constituting the drive circuit can be reduced, the price of a video camera using the solid-state image sensor of the present invention can be significantly reduced.

(3) Since the dark current is also swept out at the same time as the smear is swept out, the problem of dark current, which is one of the weaknesses (26) of the CCr') type solid-state imaging device, can be solved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional CCD solid-state imaging device, FIG. 2 is a diagram showing the configuration of a frame inter-line type CCD solid-state imaging device, and FIG. 3 is a diagram showing the configuration of a frame inter-line type CCD solid-state imaging device. A diagram showing the configuration of an interline type CCD solid-state image sensor, Figure 4 is a diagram explaining the operation of the frame interline type CCD solid-state image sensor shown in Figure 3, and Figure 5 is a diagram showing the structure of the frame interline type CCD solid-state image sensor shown in Figure 3. Frame interline type CC of invention
A diagram showing the configuration of a signal processing circuit used in the D solid-state image sensor,
6 and 7 are diagrams showing the configuration of the frame interline CCD solid-state image sensor of the present invention, which is different from FIG. 3, and FIG. 8 is the frame interline CCD solid state image sensor of the present invention shown in FIG. FIG. 9 is a diagram showing the configuration of a signal processing circuit used in an image sensor, and is a diagram showing a structure of a frame interline type CCD solid-state image sensor of the present invention, which is different from FIGS. 3, 6, and 7. . (27) 1... Photoelectric conversion element, 2... Vertical CCD shift register, 3-1.3-2... Horizontal CCD shift register, 13-1.13-2... Selection gate, 14.・・Sweep out gate, 14d... Sweep out do l twin, 1
5-1... CCD shift 1 register for signal accumulation, 15
-2...(28) ￥ 1 Country IZ Map Figure 6 Tomi 7 Tsuzuki g Figure 1-1 '￥3 9 Figure-2

Claims (1)

[Claims] 1. A group of photoelectric conversion elements and a vertical C on a conductor substrate.
An imaging area consisting of a group of OD shift registers, an accumulation area for temporarily accumulating optical signal charges detected in the imaging area, and a horizontal COD shift register for reading out the optical signal charges taken out from the accumulation area as output are integrated. In a charge transfer type solid-state image sensor, a smear signal accumulation CCD shift register for temporarily accumulating smear signals (false signals) is provided separately from a signal accumulation CCD shift register for accumulating optical signals in the accumulation region; 1. A charge transport type solid-state image sensor, characterized in that an optical signal and a smear signal are read out as output, and the smear signal is removed by taking the difference between the two signals. 2. In the charge transfer solid-state imaging device according to claim 1, by operating the horizontal COD shift register in a dual transfer mode, one stage of the shift register can transfer an optical signal and a smear signal (1). 1. A charge transfer type solid-state image sensor, which transfers two signals, and temporally alternately extracts an optical signal and a smear signal as outputs. 3. In the charge transfer type solid-state imaging device according to claim 1, two or more horizontal CCD shift registers are provided, and one horizontal COD shift register transfers an optical signal, and the other horizontal CCD shift register transfers an optical signal. A charge transfer type solid-state imaging device characterized in that a smear signal 1 is transferred by a register. 4. In the charge transfer solid-state imaging device according to claim 1, a drain for sweeping out unnecessary signals is provided in a part of the storage region or in a portion adjacent to the imaging region corresponding to the opposite side of the storage region, A charge transfer solid-state imaging device characterized in that after unnecessary signals accumulated in the vertical COD are swept out to the drain, the optical signal and the smear signal are transferred to the signal accumulation COD shift register and the smear signal accumulation CCD shift register, respectively. element.