JP2614263B2 - Solid-state imaging device camera - Google Patents

Description

The present invention relates to a camera using a solid-state imaging device such as a charge-coupled device (CCD), and particularly to a solid-state imaging device having a high-speed shutter function. About the camera.

(Prior Art) Recently, solid-state imaging devices such as CCDs have been developed, and color video cameras using the same have been put to practical use. In this color video camera, the charge storage time of the photosensitive section is equivalent to the shutter time of the camera. Usually this time
1/60 second is standard. However, recently, a frame interline transfer (FIT) type CCD has been developed, and a shutter speed can be freely selected.

The FIT type CCD has a photosensitive section as an image section, a vertical high-speed transfer section, a feed memory as a storage section, and a horizontal transfer section, and performs the following operations.

(A) First, the charges accumulated in the photosensitive section are simultaneously transferred to the high-speed transfer section by a sweeping field shift pulse supplied from the drive circuit. The high-speed transfer unit is supplied with a high-speed clock pulse from a driving circuit, and the electric charges there are discharged at a high speed.

(B) Next, the electric charges accumulated in the photosensitive section are simultaneously transferred to the high-speed transfer section by the signal readout field shift pulse supplied from the drive circuit. This charge is then transferred at high speed to the field memory line by line. Here, the electric charges in the field memory are transferred to the horizontal transfer unit at a normal television frequency line by line. The charges of the horizontal transfer section are read out in one horizontal period.

As described above, in the FIT type CCD, the charge accumulated in the photosensitive portion is first emptied by the field shift pulse for sweeping out, and then the charge read out by the field shift pulse for signal reading is held in the accumulation portion. Therefore, the interval between the field shift pulse for sweeping out and the field shift pulse for signal reading is the shutter speed, and an arbitrary shutter speed can be set by selecting this interval.

With a conventional video camera using the above-described FIT type CCD, an image obtained by a high-speed shutter can be obtained for an image of one field. However, when trying to obtain an image for two fields (that is, one frame) of an odd field and an even field in order to improve the vertical resolution, 2
Times of shutter operation is required. However, if the video camera is operated twice for the shutter operation, the interval between the first and second operations is 1/60 second. As a result, although the image of one field is obtained by the high-speed shutter operation, the result of one frame of image is the same as that of releasing the high-speed shutter twice at 1/60 second intervals. Therefore, when the movement of the subject is fast, there is a problem that flicker occurs and the image becomes unsightly.

(Problems to be Solved by the Invention) As described above, the conventional solid-state imaging device camera has a problem that when trying to improve the resolution, two shutter time shifts occur between fields, resulting in an unsightly image. .

Therefore, the present invention obtains a captured image for one frame in one shutter time and, when reading this captured image, reads the captured image by a reading method in which noise is hardly mixed, so that a high-quality image signal can be obtained. It is an object of the present invention to provide a solid-state imaging device having the above configuration.

[Constitution of the Invention] (Means for Solving the Problems) The present invention provides a photosensitive unit that accumulates electric charges according to a light receiving amount and a light receiving time,
A vertical transfer unit that simultaneously transfers the accumulated charges of the photosensitive unit, and transfers the charges in a line unit and in a vertical direction at a high speed;
A first field memory having a storage capacity for one field for storing the transfer charge from the vertical transfer section, and a second field memory having a storage capacity for one field for storing the transfer charge from the vertical transfer section. A field memory, transfer means for alternately transferring the transfer charge in run-in units from the vertical transfer unit to the first and second field memories, and reading the charge stored in the first field memory; Reading means for reading the charge stored in the second field memory; and a horizontal transfer unit for transferring the charge read by the reading means in a horizontal direction in line units. Transferring the charge to the first field memory, and if the first field memory is full, then transferring the charge to the second field memory; First transfer means for transferring charges to the first and second field memories alternately;
And transfer control means for selectively operating the second transfer means.

(Operation) According to the above configuration, when the transfer charge from the vertical transfer unit is stored in the first and second field memories, the charge is transferred to the first field memory, and the first field memory is filled. Then, next, there is provided a means for transferring electric charges to the second field memory. Because of this means, the number of times of switching when transferring the electric charge from the vertical transfer unit to the storage unit is one, so that there is little chance of generating switching noise and noise is not mixed into the image signal.

(Embodiment) FIG. 1 is a diagram for explaining the basic principle of the present invention, and is a timing chart for explaining the operation of FIGS. 2 (A) to 2 (G). Now, when the shutter button 12 for photographing is operated, the drive circuit 14 is turned on as shown in FIG.
As shown in (1), a field shift pulse Ps for sweeping out and a field shift pulse P1 for signal reading are continuously generated for one photographing, and supplied to the CCD 16 as a solid-state imaging device. CCD16, for example, 500 vertical, 4 horizontal
A photosensitive section 18 composed of 00 pixels (photodiodes);
There is a high-speed transfer unit 20 vertically arranged adjacent to each of the vertical columns of the photosensitive units 18, and these constitute an image unit. The number of stages of the high-speed transfer unit 20 is four times the number of pixels in the vertical direction, that is, 500 × 4 stages are arranged so that signals of 500 pixels can be transferred without color mixing.

Field time interval field shift pulse P ₁ for shift pulse Ps and the signal read for the sweep is the so-called electronic shutter operation time (exposure time). The CCD 16 is an interline transfer type CCD, and is periodically driven in a standard operation mode by a vertical blanking pulse. CCD16
Is, in addition to the photosensitive section 18 and the high-speed transfer section 20 as an image section, a frame memory 22 as a storage section, a horizontal transfer section 24,
It has an output circuit 26 and gate sections 28 and 30.

In the CCD 16, a gate (not shown) formed between the photosensitive section 18 and the high-speed transfer section 20 is opened by the first sweeping field shift pulse Ps, and the accumulated charges in the photosensitive section 18 are simultaneously transferred to the high-speed transfer section 20. Is forwarded to The charge of the high-speed transfer unit 20 is swept up at high speed by a clock supplied from the drive circuit 14 during a period t1, as indicated by an arrow α in FIG. In this period, image charges are accumulated in the photosensitive section 18.

Thereafter, field shift pulses P ₁ for signal reading is output from the drive circuit 14. The charges transferred to the high-speed transfer section 20 by the signal read field shift pulse P1 are transferred to the frame memory 22 as a storage section at a high speed in a downward direction as indicated by an arrow β in FIG. . In this case, addition reading is not performed on a pair of two adjacent pixels in the vertical direction.

In this case, the electric charge of the high-speed transfer unit 20 is transferred to the frame memory 22 line by line, which is characterized by this transfer means. That is, if explaining one high-speed electrical transmission column 20 ₁ to the column,
The charges of the high-speed transfer train 201 are alternately distributed to the two memory trains 221 and 222 by a high-speed transfer pulse (FIG. 2 (D)) and a gate pulse (φGA, φGB). . Therefore, the electric charges corresponding to the two fields are stored in the high-speed transfer column 201 and the memory columns 221, 222. Further, for the distribution, a gate unit 28 for performing the distribution is formed between the high-speed transfer column 201 and the memory columns 221 and 222. The gate unit 28 is controlled by gate pulses (φGA, φGB) from the drive circuit 14.

This operation will be described with reference to the timing chart of each clock in FIG. To the high-speed transfer section 20 of the image section, a four-phase pulse (φV1, φV2, φV3, φV4) waveform having a repetition of 1.58 MHz as shown in FIG. The signal charges are successively transferred under the electrode to which +5 V is applied, and move downward (indicated by an arrow β) in FIG.

Here, two sets of pulses (.phi.GA, .phi.GB) as shown in FIG. 3 (B) are applied from the drive circuit 14 to the gate section 28, and the gate section 28 switches alternately in accordance with the phase of the clock pulse .phi.V4. That is, the signal charge is distributed when the gate pulse φGA + 5V is applied to the memory column 22 _1, a gate pulse φG
When +5 V is applied to B, signal charges are distributed to the memory columns 222.

The signal charges sent to the memory columns 221 and 222 are 1/2 of the high-speed transfer unit 20 as shown in FIGS. 3 (C) and 3 (D).
, That is, a four-phase pulse with a frequency of 0.79 MHz (φFA1
φFA2 φFA3 φFA4 and φFB1 φFB2 φFB3 φFB4) are transferred downward in FIG. 1 (indicated by arrow β).

In this way, the signal charges for 500 pixels once stored in the high-speed transfer unit 20 are stored in the memory columns 221 and 222 of the storage unit in 250 pixels each.

Note that, as shown in FIGS. 3 (C) and (D),
The pulse waveforms applied to 22 1,22 2 are φFA1, φFB3, φFA2
ΦFB4, φFA3 and φFB1, and φFA4 and φFB2 have the same shape. Therefore, even if signals are not separately applied to φFA and φFB from the outside, the number of wirings can be reduced by arranging the wirings inside the CCD 16 in this way.

The above description is only for one high-speed transfer column 201, but the other columns have the same relationship between the high-speed transfer column and the memory column.

By operating as described above, one frame of image signal is stored in the frame memory 22 by one shutter operation. The image signal is read out for one field via the gate unit 30, the horizontal transfer unit 24, and the output circuit 26. FIGS. 2E and 2F show a period during which the signals of the first and second fields are transferred.
FIG. 7G shows a signal waveform output from the output circuit 26.

The image formed in this manner is composed of a signal of the first (odd) field and a signal of the second (even) field, and the shutter period is the same for all the field signals. As a result, according to the video camera using the CCD16, the vertical resolution can be increased,
In addition, flicker due to a time difference between fields does not occur. When the shutter time is set, the shutter speed can be set arbitrarily by adjusting the interval (exposure time) between the field shift pulses P _S and P ₁ .

FIG. 4 is a structural diagram of a color video camera using the solid-state imaging device of the present invention. That is, the light that has passed through the triple zoom lens 32 is converted into a color temperature conversion filter 34 and a color correction filter 3.
6. CCD1 as a solid-state image sensor with a color filter array 40 via an optical low-pass filter (LPF) 38
The image is formed on the image section 6.

The drive circuit 14 includes a synchronization signal generator 42, a vertical logic circuit,
44, and a horizontal logic circuit 46. Synchronous signal generator 42
The vertical and horizontal logic circuits 44 and 46 generate various pulse signals necessary for the operation of the CCD 16 using the various pulse signals from the CPU 16 and apply them to the CCD 16.

After the output signal of CCD16 is amplified by preamplifier 48,
The color separation circuit 50 separates the three primary color signals of red (R), green (G), and blue (B). These primary color signals are subjected to signal processing required for an ordinary color camera, such as gamma correction and white clipping, by a signal processing circuit 52, and are applied to an encoder 54. The encoder 54 creates a luminance signal and a chroma signal from the input signal, combines them, and
Create and output SC signal.

Next, a driving method of the CCD 16 will be described with reference to FIG. From the synchronization signal generator 42, timing pulses (F SS, F S1, F V1, F V2, F V3, F V4,
HP, VP) is generated and input to the vertical and horizontal logic circuits 46 and 48. The vertical logic circuit 46 is a part of the image section 5 of the CCD 16.
6 and pulse waveforms (φV1,
φV2, φV3, φV4, φG, φF1, φF2, φF3, φF4). On the other hand, the horizontal logic circuit 48 generates pulse waveforms (φH1, φH2, φRS) necessary for horizontal transfer. The waveforms required for horizontal transfer are two-phase drive waveforms (φH1, φH2) as shown in FIGS. 6 (A) and 6 (B), and an output circuit 26 as shown in FIG. 6 (C). This is a reset pulse waveform (φRS). These pulse waveforms are transferred to the horizontal transfer unit 24 and output circuit.
By adding the signal to the signal 26, the signal falling from the storage unit 58 line by line is transferred horizontally, and a signal waveform as shown in FIG. 6 (D) is obtained from the output circuit 26.

In the image section 56, there are a period for sweeping out unnecessary charges and a period for transferring signals. In the pulse waveforms in these periods, the phases of the four-phase waveforms are changed, and the upward and downward directions as shown by arrows α and β in FIG. 1 are determined. That is, in the unnecessary charge sweeping period, the timing at which 5 V is applied from the vertical logic circuit 46 is φV4 → φV3
→ V2 → αV1. Therefore, the unnecessary charges also move in the same direction, move upward, and are swept out. Normally, a drain portion is provided at the uppermost end of the image portion 56, and the charge that has moved there disappears. On the other hand, as shown in FIG. 3 (A), during the signal transfer period, the timing at which 5V is applied is φV1 → φV2 → φ
It moves in the order of V3 → φV4. Accordingly, the signal charge also moves in the same direction in accordance with this, and the signal is moved from the image unit 56 to the storage unit 58.

In the image section 56, the field shift pulses P _S and P ₁ as described above are required to move a signal from the photosensitive section 18 to the high-speed transfer section 20, but without providing a gate, These field shift pulses are applied from the vertical logic circuit 46 to the image section 56 so as to be superimposed on the pulse waveforms φV1 and φV3.

As described above, according to the present invention, a high-speed shutter operation can be performed, and an image with good vertical resolution of one frame can be obtained. With a normal video camera, if the subject moves to obtain a still image signal, flickering occurs because the shutter is released at 1/60 second intervals in odd and even fields, and a complete image of one frame is generated. Although it could not be obtained, the present invention can obtain a still image with good vertical resolution even when the subject moves fast. Even with a variable shutter, a still image for one frame can be obtained at an arbitrary speed. Moreover, the exposure time is
It is the same between the fields, so that there is no difference in the signal level between the feeds, and a high-quality image signal can be obtained.

FIG. 7 is a diagram for explaining the gist of the present invention.

In the present invention, in particular, a captured image for one frame is obtained in one shutter time, and when the captured image is read, a high-quality image is obtained by reading the captured image using a reading method in which noise is less likely to be mixed. I have. For this purpose, the means for transferring the electric charge from the vertical transfer unit to the storage unit transfers the electric charge to the first field memory, and transfers the electric charge to the first field memory.
When the field memory is filled, the charge is transferred to the next second field memory.

In this case, as shown in FIG. 7, first, the line signals of the odd field and the even field are written into the first field memory 60 in a non-interlaced form, and if the first field memory 60 is filled, Line signals of the odd field and the even field are sequentially written to the second field memory 62.

When transferring charges from the vertical transfer unit to the storage unit, the transfer unit must be switched for each line if the distribution method is line by line, and switching noise or the like is likely to be mixed into the image signal each time. However, as in the method of the present invention, the first
When the charge is transferred to the second field memory after the field memory is filled, the generation and mixing of the switching noise as described above is eliminated, and the optimal configuration for obtaining a high-quality and clear image is achieved. Become.

[Effects of the Invention] As described above, according to the present invention, a captured image for one frame is obtained with one shutter time, and when the captured image is read, the read method is used in which noise is less likely to be mixed. Thus, a high-quality and clear image signal can be obtained.

[Brief description of the drawings]

FIG. 1 is a structural explanatory view showing one embodiment of the present invention, FIG. 2 is a timing chart shown for explaining the operation of the solid-state imaging device of FIG. 1 and its driving circuit, and FIG. )
3 to 3D are timing charts of various pulses output by the drive circuit of FIG. 1, FIG. 4 is an explanatory diagram of a color video camera to which an embodiment of the present invention is applied, and FIG. FIG. 6 is a block diagram of the driving circuit of FIG. 1, FIG. 6 is a timing chart for explaining the operation of the horizontal logic circuit of the driving circuit of FIG. 5, and FIG. FIG. 4 is an explanatory diagram showing an example of signal writing in a storage unit for explaining the operation of FIG. 12 ... Shutter button, 14 ... Drive circuit, 16 ... CC
D, 18: photosensitive section, 20: high-speed transfer section, 22: frame memory, 24: horizontal transfer section, 26: output circuit, 28, 30 ...
... gate circuit.

Claims (1)

(57) [Claims] 1. A photosensitive section for accumulating electric charge according to a light receiving amount and a light receiving time; A vertical transfer unit for transferring in the vertical direction, a first field memory having a storage capacity for one field for storing the transfer charge from the vertical transfer unit, and storing a transfer charge from the vertical transfer unit. A second field memory having a storage capacity for one field, transfer means for alternately transferring the transfer charges in run-in units from the vertical transfer unit to the first and second field memories, Reading means for reading the charge stored in the field memory and then reading the charge stored in the second field memory; Was and a horizontal transfer section for transferring in the horizontal direction on a line basis, the transfer means transfers the charges in the first field memory, said first
If the field memory of
A first transfer unit for transferring charges to the field memory of the first embodiment, a second transfer unit for alternately transferring charges to the first and second field memories, and selectively selecting the first and second transfer units. A solid-state imaging device camera comprising: