JPH05219441A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To provide the solid-state image pickup device in which the S/N equal to the case with 2-line mixed interlace scanning is obtained and non- interlace scanning is attained. CONSTITUTION:The solid-state image pickup device provided with a picture element matrix A in which solid-state image pickup elements such as CMD able to read a signal non-destructively while the charge generated by light radiation and stored is maintained are arranged in a matrix is provided with a scanning means which selectively scans adjacent two-line while deviating one by one line each sequentially at all times for the picture element matrix A for one vertical scanning period. Thus, the same signal quantity as the 2-line mixed interlace scanning is obtained even in the non-interlace scanning.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a CMD (Charge Mod
ulation device) and SIT (Static Induction Transis)
The present invention relates to a solid-state imaging device configured to perform non-interlaced scanning by using a non-destructive read-out solid-state imaging element such as tor) as pixels.

[0002]

2. Description of the Related Art Conventionally, various methods have been known as a method of reading pixel signals in an image pickup apparatus, and one of them is a non-interlaced scanning method. This scanning method obtains an image of one frame by one vertical scanning. After capturing an image of a moving object and recording it on some medium, slow reproduction or still reproduction is performed, and interlaced scanning is performed. Compared to the system, there are features that there is less blurring and flicker-free images can be obtained.

For example, as shown in FIG. 9, this scanning system is a system in which the pixel matrix A is sequentially scanned row by row in the order of row numbers and signals are read out. In addition, in FIG.
Circled numbers indicate the scanning order. A configuration example in the case where this non-interlaced scanning method is applied to a solid-state imaging device using a CMD imaging device proposed by the applicant of the present application will be described. The CMD image pickup device is a kind of phototransistor that modulates the source / drain current by the amount of charges generated by light irradiation and accumulated under the gate electrode, and is held in JP-A-61-84059 or 1986. Intern
“A NEW MOS IMAGESENSOR OPERAT” on pages 353 to 356 of the proceedings of the ational ElectronDevice Meeting (IEDM).
The content is detailed in a paper entitled "ING IN A NON-DESTRUCTIVE READOUT MODE".

Next, a conventional solid-state image pickup device using such a CMD image pickup device will be described with reference to the circuit configuration diagram of FIG. First, CMD 1-11, 1-12, ...
1-mn are arranged in a matrix, and a video bias V _DD (> 0) is commonly applied to each drain thereof. The gate terminals of the CMDs arranged in the X direction are row lines 2
-1, 2-2, ... 2-m, respectively, and the source terminals of the CMD group arranged in the Y direction are column lines 3-1, 3-2, ...
・ Connect to 3-n respectively. The column lines 3-1, 3-2,
... 3-n are column selecting transistors 4-1 and 4-, respectively.
2, ... 4-n and anti-selection transistors 5-1, 5-2, ...
The signal line 6 and the reference line 7 grounded to GND are commonly connected via 5-n. The signal line 6 is connected to a current-voltage conversion type preamplifier 12 whose input is virtually grounded, and a negative video signal is read out in time series from the output terminal 9 of the preamplifier 12.

Further, the row lines 2-1, 2-2, ... 2-m are connected to the vertical scanning circuit 10, and signals φ _G1 , φ _G2 , ...
· Applying φ _Gm , column select transistors 4-1, 4-2, ...
.. 4-n and anti-selection transistors 5-1, 5-2, ... 5-n
The gate terminal of is connected to the horizontal scanning circuit 11 and applies signals φ _S1 , φ _S2 , ... φ _Sn and their inverted signals, respectively. Although not shown, each CMD is formed on the same substrate, and the substrate voltage V _SUB is applied to the substrate.

FIG. 11 is a signal waveform diagram for explaining the operation of the solid-state image pickup device using the CMD image pickup device shown in FIG. Signal φ applied to row lines 2-1, 2-2, ... 2-m
_G1 , φ _G2 , ... φ _Gm are read voltage V _RD and reset voltage V _RST , overflow voltage V _OF , and storage voltage V
_In the non-selected row, the accumulated voltage V _INT is applied during the horizontal effective period of the video signal, and the overflow voltage V _OF is applied during the horizontal blanking period, and the read voltage V _RD is applied during the horizontal effective period of the video signal in the selected row. During the horizontal blanking period, the reset voltage is V _RST . The overflow voltage V
_{The OF} is described in detail in JP-A-61-136388. Then, when performing non-interlaced scanning, the rows to which the read voltage V _RD and the reset voltage V _RST are applied are sequentially shifted row by row in the scanning direction, as shown in FIG. ..

On the other hand, the column selecting transistors 4-1, 4-2,
・ ・ ・ Signals φ _S1 , φ _S2 , applied to 4-n gate terminal
φ _Sn is a signal for selecting the column lines 3-1, 3-2, ... 3-n, and the low level is the column selecting transistors 4-1 and 4-.
2, ... 4-n off, anti-selection transistors 5-1 and 5-
2, ... 5-n is on, high level is column selection transistors 4-1, 4-2, ... 4-n is on, anti-selection transistor 5
-1, 5-2, ... 5-n is set to a voltage value for turning off, and the column selection transistors 4-1 and 4- are set while the read voltage V _RD is applied to the selected row. 2, ... 4-n are sequentially turned on, the optical signal of each CMD pixel is sequentially read out by the signal line 6, amplified by the preamplifier 12, and output.

Note that φ _HST , φ _H1 , and φ _{H2 in} FIG. 10 indicate a start signal and a clock signal for driving the horizontal scanning circuit 11. Further, φ _VST , φ _V1 , and φ _V2 indicate a start signal and a clock signal for driving the vertical scanning circuit 10, and V ₁ , V ₂ , and V ₃ are the read voltages V applied to the gates of the pixels, respectively. _RD , reset voltage V
_The input voltage that gives _RST and the overflow voltage V _OF is shown.

[0009]

By the way, in the solid-state imaging device shown in FIG. 10, when interlaced scanning is performed, the vertical scanning signal and the vertical scanning signal in the A field scanning of FIG.
As shown in the vertical scanning signal at the time of B field scanning of 13,
It is general to apply the row selection signals φ _G1 , φ _G2 , ... φ _Gm to perform two-row mixed reading. In this case, since the read voltage V _RD is always applied to the two rows of the pixel matrix, when the column selection transistors 4-1, 4-2, ... Will be obtained.

Compared to the case of performing the interlaced scanning, the case of the non-interlaced scanning described above has an advantage that the vertical resolution is improved, but since the signal current can always obtain only one pixel, the S / N ratio is increased. Is inevitable.

The present invention has been made to solve the above-mentioned problems in the conventional solid-state image pickup device for performing non-interlaced scanning. Even if non-interlaced scanning is performed, the same S / N as in interlaced scanning can be obtained. It is an object of the present invention to provide a solid-state image pickup device according to the above.

[0012]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a solid-state image sensor capable of non-destructive signal readout while retaining the charges generated and accumulated by light irradiation. In a solid-state imaging device having a pixel matrix in which the pixels are arranged in a matrix,
A scanning means is provided in which the pixel matrix is sequentially shifted and selected and read one by one in a unit of a plurality of consecutive rows of the pixel matrix in one vertical scanning period.

In the solid-state image pickup device having such a structure, for example, assuming that the read-out row unit is two rows, as shown by the scanning order in FIG. Thus, selective scanning is performed while shifting each row by one row, and even in non-interlaced scanning in which all pixels are sequentially scanned in one vertical scanning, the resolution and the signal amount equivalent to those in the two-row mixed interlaced scanning can be obtained. A video signal with a good / N can be obtained.

[0014]

EXAMPLES Next, examples will be described. FIG. 2 is a circuit configuration diagram showing only a vertical scanning circuit section of an embodiment in which the present invention is applied to a solid-state image pickup device using the CMD image pickup device shown in FIG. Vertical scanning circuit unit 100 in this embodiment
Is a vertical scanning shift register 101 and a plurality of 2-input NAs.
ND gates 103-1, 103-2, ... 103-m, and a level mix circuit 104. The vertical scanning shift register 101 includes unit circuits 102-1, 102-2, ... 1
Each of the shift register unit circuits, which is composed of 02-m, is disclosed in, for example, Japanese Patent Publication No. 54-35472.
It is composed of a clocked CMOS circuit as shown in FIG. 2 and receives clock pulses φ _V1 and φ _V2 , respectively, and outputs output pulses φ _P1 , φ _P2 , ... φ _Pm , respectively.

Output pulses φ _P1 , φ _P2 , ... φ _Pm of the vertical scanning shift register 101 are _generated by the NAND gates.
103-1, 103-2, ... 103-m are connected so as to be applied to one input, and clock pulses φ _V11 and φ _V12 are input to the other input of each NAND circuit. The unit circuits are connected so as to be applied alternately.
The NAND gates 103-1, 103-2, ... 103-
The output signals φ _N1 , φ _N2 , ... φ _Nm of m are respectively the unit circuits 105-1, 105-2, ... 105 of the level mix circuit 104.
Connected to be applied to the input of -m. Each unit circuit of the level mix circuit 104 has a read voltage V _RD and a reset voltage V _RST when the input is at a low level.
Is output in synchronization with the vertical scanning clock pulse, and the input is Hi
At the gh level, the circuit is configured to output the overflow voltage V _OF and the accumulated voltage V _INT in synchronization with the vertical scanning clock pulse. In this embodiment, each unit circuit 105-1, 105-2,・ ・ ・ 105-m is clock pulse φ _V1
Outputs the accumulated voltage V _INT or the read voltage V _RD during the Low level period, the overflow voltage V _OF during the High level period of the clock pulse φ _V1 and the reset voltage V _RST during the Low level period of the clock pulse φ _V2. Has been done.

FIG. 4 shows the vertical scanning circuit unit 100 of the above embodiment.
FIG. 6 is a timing diagram showing clock pulses applied to the circuit and signals of respective parts. The periods of the clock pulse φ _V1 and the clock pulse φ _V2 match the horizontal scanning period, the clock pulse φ _V1 is at High level during the horizontal blanking period, and the clock pulse φ _V2 is at Lo level during the High level period of the clock pulse φ _V1.
w level. The vertical scanning start pulse φ _VST is a pulse which becomes high level by including the low level period of the clock pulse φ _V2 twice in succession. The period of the clock pulse φ _V11 and the clock pulse φ _V12 is twice the period of the clock pulse φ _V1 and the clock pulse φ _V2 , and its Low level period corresponds to the High level period of the clock pulse φ _V1. φ _V11 and clock pulse φ _V12 have a relationship in which the phases are shifted by a half cycle.

Next, the operation of the vertical scanning circuit section of this embodiment shown in FIG. 2 will be described with reference to FIG. When a vertical scanning start pulse φ _VST is applied to the vertical scanning shift register 101,
Unit circuits 102-1 and 102- of the vertical scanning shift register 101
2, ... 102-m output pulses φ _P1 , φ _P2 , ... φ _Pm appearing at High level in synchronization with the falling edge of the clock pulse φ _V1 for twice the clock period. The phases of the clock pulse φ _V11 and the clock pulse φ _V12 are determined so that the Low level periods are positioned in the middle of the output pulses φ _P1 , φ _P2 , ... φ _Pm .
Alternatively, by determining the position of the vertical scanning start pulse φ _VST, the output pulses φ _N1 , as shown in FIG. 4, are output from the NAND gates 103-1, 103-2, ... 103-m, respectively.
φ _N2 , ... φ _Nm is output. This output pulse φ _N1 , φ
_{When N2} , ... φ _Nm is input to the level mixing circuit 104,
Vertical scan pulses φ _G1 , φ _G2 , ... φ _Gm as shown in FIG.
Is output. That is, these vertical scanning pulse signals are output pulses φ _P1 of the vertical scanning shift register 101,
While φ _P2 , ... φ _Pm is at the high level, the read voltage V _RD becomes in synchronization with the low level of the clock pulse φ _V1 ,
The overflow voltage V _OF is in the first High level period of the same clock pulse φ _{V1, and} the reset voltage V is in the Low level period of the clock pulse φ _V2 after the second read voltage period.
Become _RST . In addition, the output pulses φ _P1 , φ _P2 , ... φ _Pm are
Period of Low level, the clock pulse phi High level period of _V1 overflow voltage V _OF, the clock pulses phi _V1
During the low level period, the storage voltage becomes V _INT .

By scanning the pixel rows with the vertical scanning pulses φ _G1 , φ _G2 , ... φ _Gm formed in this way, the two adjacent rows are the first row, the second row, and the second row. And 3rd row, 3rd row and 4th row ..., and simultaneously select sequentially while shifting by 1 row, and obtain the signal output for 2 pixels as in the case of 2 row mixed interlaced scanning. You can The vertical resolution is also the same as in the case of two-row mixed interlaced scanning. Further, if the clock pulse φ _V11 and the clock pulse φ _V12 are always high level DC voltage signals, the conventional non-interlaced scanning in which the scanning is performed row by row is also possible.

FIG. 5 is a diagram showing a circuit configuration of a vertical scanning circuit section according to a second embodiment of the present invention. The same or equivalent members as those in the first embodiment shown in FIG. 2 are designated by the same reference numerals. Is shown. The difference between this embodiment and the first embodiment is that
Instead of applying clock pulses φ _V11 and φ _V12 to the input terminals of the first NAND gates 103-1, 103-2, ... 103-m, the second NAND gates 106-1, 106-2 ,. ·· Ten
The point is that the output signal of 6-m is applied. The second NAND gates 106-1, 106-2, ... 106-m
The clock pulse φ _V1 is applied to one input, and the output signal of the unit circuit one stage before the corresponding unit circuit of the vertical scanning shift register 101 is applied to the other input.

FIG. 6 shows a vertical scanning circuit section 100 of the second embodiment.
FIG. 6 is a timing diagram showing clock pulses applied to the circuit and signals of respective parts. The input clock pulses φ _V1 , φ _V2 and the vertical scanning start pulse φ _VST are the same as those in the first embodiment, and therefore, the output pulses φ _P1 , φ _P2 , ... φ of the vertical scanning shift register 101. _{Since Pm is} also the same as that of the first embodiment, its explanation is omitted. Second NAND gate 106-
1, 106-2, ... 106-m are outputs of the unit circuit of the shift register one stage before, and function to gate and invert the clock pulse φ _V1 . First NAND gates 103-1 and 103-2
, 103-m are the second NAND gates 106-1 and 106-2
The output pulse of 106-m is further gated and inverted by the output pulse of the corresponding unit circuit of the vertical scanning shift register 101, resulting in the first NAND gate 103-1.
103-2, ... 103-m output pulse φ _N1 , φ _N2 , ... φ _Nm
Is the same as that shown in FIG. 4, and therefore the unit circuits 105-1, 105-2, ... 105-m of the level mix circuit 104.
The vertical scanning pulses φ _G1 , φ _G2 , ... φ _Gm which are the outputs of
It is the same as that shown in FIG.

Therefore, also in this embodiment, the same operational effects as those in the first embodiment can be obtained. Further, in this embodiment, the first NAND gates 103-1 and 10-3
3-2, ... 103-m output pulse signal φ _N1 , φ _N2 , ... φ
_Since the inversion of the clock pulse φ _V1 appears in _Nm except for the last one cycle thereof regardless of the output pulse width of the vertical scanning shift register 101, for example, as shown in FIG. 7, the vertical scanning start pulse φ _VST , The vertical scanning pulses φ _G1 , φ _G2 , ... φ _Gm having three read pulses and one reset pulse can be obtained from the output of the level mix circuit 104. .. In this case, as shown in FIG. 8, three rows are simultaneously selected, and 1 row is selected.
3 compared to conventional non-interlaced scanning that scans line by line
A double large signal current can be obtained. Since this is also an integration operation, a vertical image filtering effect can also be obtained. Of course, vertical scan start pulse φ
_If the pulse width of _VST is set to 3 cycles or more, the effect is further enhanced. Further, if the pulse width of the vertical scanning start pulse φ _VST is set to one cycle, conventional non-interlaced scanning in which scanning is performed row by row is also possible.

In each of the above embodiments, the present invention is applied to the solid-state image pickup device using the CMD as the pixel.
It goes without saying that the present invention can also be applied to a solid-state image pickup device using another solid-state image pickup element capable of nondestructive readout such as SIT.

[0023]

As described above on the basis of the embodiments,
According to the present invention, non-interlaced scanning is performed by sequentially shifting one row at a time in units of a plurality of consecutive rows to perform non-interlaced scanning. Therefore, even in non-interlaced scanning, it is equivalent to performing two-row mixed interlaced scanning. It is possible to realize a solid-state image pickup device in which the signal current of 1 is obtained and a video signal with good S / N is obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a concept of a solid-state imaging device according to the present invention.

FIG. 2 is a circuit configuration diagram showing a vertical scanning circuit unit according to the first embodiment of the present invention.

3 is a circuit configuration diagram showing a configuration example of a unit circuit of a vertical scanning shift register in the embodiment shown in FIG.

FIG. 4 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 5 is a circuit configuration diagram showing a vertical scanning circuit unit according to a second embodiment of the present invention.

6 is a timing chart of each signal for explaining an example of the operation of the embodiment shown in FIG.

FIG. 7 is a timing chart of each signal for explaining another operation example of the embodiment shown in FIG.

8 is a diagram showing a selective scanning mode of a pixel matrix when operated at the operation timing shown in FIG.

FIG. 9 is a diagram showing a scanning mode of a pixel matrix by a conventional non-interlaced scanning method.

FIG. 10 is a circuit configuration diagram showing a configuration example of a conventional CMD solid-state imaging device.

11 is a timing chart of each signal for explaining a non-interlaced scanning operation of the CMD solid-state imaging device shown in FIG.

12 is a diagram showing a vertical scanning signal during A field scanning when the CMD solid-state imaging device shown in FIG. 10 is scanned by an interlaced scanning system.

FIG. 13 is a diagram similarly showing a vertical scanning signal during B field scanning.

[Explanation of symbols]

100 vertical scanning circuit unit 101 vertical scanning shift register 102-1, 102-2, ... 102-m vertical scanning shift register unit circuit 103-1, 103-2, ... 103-m 2-input NAND Gate 104 Level mix circuit 105-1, 105-2, ... 105-m Unit circuit of level mix circuit 106-1, 106-2, ... 106- (m-1) Second 2-input NAN
D gate

Claims (3)

[Claims] 1. A solid-state image pickup having a pixel matrix in which pixels are solid-state image pickup elements capable of nondestructive signal readout while holding charges accumulated and generated by light irradiation, and the pixels are arranged in a matrix. A solid-state imaging device, comprising: a scanning means for sequentially selecting and reading out a pixel matrix in units of a plurality of consecutive rows in one vertical scanning period. 2. A transistor, the source / drain current of which is modulated by the amount of charge generated and accumulated by light irradiation, is included as a constituent element of one pixel, the pixels are arranged in a matrix, and the pixels are arranged in a peripheral portion thereof. A read signal for reading the source / drain current corresponding to the accumulated charges, and a reset signal for discharging all accumulated charges of the pixel,
In the solid-state imaging device including a driving unit that selectively applies, to the gate of the pixel, an overflow signal for discharging a part of the accumulated charge after the pixel is reset and before the next reading is performed, the driving unit includes: A vertical scanning shift register including a plurality of unit circuits to which a first clock pulse and a scan start pulse are input, and an output of each unit circuit of the vertical scanning shift register and two clock pulses shifted by a second half cycle. A plurality of 2-input NAND gates alternately inputting, and a read signal level and a reset signal level when the output of each 2-input NAND gate is a Low level, and an accumulation signal level and an overflow signal level when the output is a High level, A register composed of a plurality of unit circuits for outputting in synchronization with the first clock pulse input to the vertical scanning shift register. A solid-state imaging apparatus characterized by being composed of a LUMIX circuit. 3. A pixel includes a transistor whose source / drain current is modulated by the amount of charge generated and accumulated by light irradiation, as a constituent element of one pixel, and the pixels are arranged in a matrix and peripheral portions of the pixel are arranged. A read signal for reading the source / drain current corresponding to the accumulated charges, and a reset signal for discharging all accumulated charges of the pixel,
In the solid-state imaging device including a driving unit that selectively applies, to the gate of the pixel, an overflow signal for discharging a part of the accumulated charge after the pixel is reset and before the next reading is performed, the driving unit includes: A vertical scanning shift register which is composed of a plurality of unit circuits and which receives a clock pulse and a scanning start pulse, and an output of the unit circuit in the preceding stage of the corresponding unit circuit of the vertical scanning shift register and the first clock pulse are inputted. A plurality of first 2-input NAND gates, a plurality of outputs of the first 2-input NAND gates, and a plurality of second 2-input NAND gates to which outputs of the corresponding unit circuits of the vertical scanning shift register are input And when the output of the second 2-input NAND gate is at the low level, the read signal level and the reset signal level are set to the high level.
And a level mix circuit including a plurality of unit circuits that outputs the accumulated signal level and the overflow signal level in synchronization with the clock pulse input to the vertical scanning shift register when the level is set. Solid-state imaging device.