JPH0265380A - Image-pick up device - Google Patents

Abstract

PURPOSE:To obtain a frame still picture to be a little blurred even to a moving subject by once housing all the photo-electric converting signals of a photo-electric converting part to a frame memory. CONSTITUTION:At first, clear scanning is started beforehand to clear the charge of a photo-electric converting cell 10C. In the photo-electric converting cell 10C of a row, to which the clearing is finished, the accumulation of the charge based on incident light quantity is started. When a prescribed accumulating time passes, memory scanning is started. In this memory scanning, the accumulating charges of all the photo-electric converting cells 10C are transferred to a frame memory 15. Then, the reading scanning of an odd-number field is executed from a frame memory 16 and continuously the reading scanning of the even- number field is executed. Since the accumulating time of each row is continuously changed in such an operation mode, even concerning the moving subject, the still picture not be blurred can be obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an imaging device having an electronic shutter function.

[Conventional technology]

In recent years, FGA (floating gate array) type area sensors have been proposed. FIG. 2 shows its configuration block diagram, 10 is a large number of photoelectric conversion cells IOC
are photoelectric conversion units located in a matrix, 10.sub.2 is a vertical address line that specifies a vertical address, and IO3 is a signal line that reads out the signals of the photoelectric conversion cells in the row specified by the vertical address line 10V. 12 is a photoelectric conversion unit 1
I4 is a clamp circuit, 16 is a line memory, 18 is an output signal line for sequentially reading out the stored values of the line memory 16 in the horizontal direction, 20 is a line memory. 22 is a switch that is opened and closed by the output of the shift register 20; 24 is a high input impedance output buffer; and 26 is an output terminal.

28 is an address decoder that selectively activates the vertical address line 10 of the photoelectric conversion unit 10; 30 is a decoder drive circuit that specifies the vertical address line to be activated by the address decoder 28 according to the vertical address data DVA; be. The address decoder 28 applies φi to the vertical address line 10v of the row to be continued or reset, and applies φ to the other vertical address lines 10v. 32 is a coupling capacitor.

12T is reset FET, 14T is clamp PET
, 16T transfers the output of the clamp circuit 14 to the line memory 1
6 is a switching FET for reading data, and 16M is a memory capacitor. φ. A reset pulse that controls the reset FET 12T of the beam set circuit 12, ■
e is the clamp voltage, φ is the clamp pulse, φ and H are the sample and hold clocks that control the opening and closing of FET 16T, 5TATH is the starting pulse that starts the shift register 20, and φ is the shift pulse for the shift register 20. It's a pulse.

The line memory 16 and clamp circuit 14 portions are shielded from external light.

The configuration of the photoelectric conversion cell 10C is shown in FIG. 3, and its operating timing is shown in FIG. 34 is a pulse source of clock φ8°φL, which corresponds to address decoder 28 in FIG. , 36 is an N-channel junction FET as a light receiving element, the gate G of which is floating, and connected to the vertical address line 10 via a capacitor 38.
Connect to V.

The drain D of the FET 36 is connected to the DC power supply VDD, and its source S is connected to the reset FET 1 of the reset circuit 12.
Connect to 2T. Source S of FET36 is signal readout line 1
Connect to 0S. Time LI shown in FIG.

12, the vertical address line 10■ becomes H by the pulse source 34.
, the gate-drain junction of PE 736 becomes forward biased and capacitor 38 is precharged. After that, if no light is incident on the gate region of the FET 36, FF! The gate of T36 remains fully reverse biased (point wA in Figure 4). When light is incident on the gate region, the capacitor 38 gradually discharges due to the photo-excited charges, and the gate potential increases (solid line in FIG. 4).
Since the source potential of the PE 736 changes in accordance with the gate potential, a voltage corresponding to the intensity of the incident light is obtained in the signal output line 10S.

FIG. 5 shows the imaging drive timing of the imaging device shown in FIG. A horizontal blanking period starts with the horizontal blanking signal HBLK, and at time 1. A vertical address DVA is applied to the decoder drive circuit 30.

As a result, φ8 is sequentially applied to the designated vertical address line 10■, and φ is applied to the other vertical address line 10V. When φ becomes L level at time t1, all PE736 of the associated photoelectric conversion cell IOC are turned off, so only the signal of the photoelectric conversion cell IOC connected to the specified vertical address line 10■ is read out to the signal succession line 10S. It will be done. (During the period between , and t2, the clamp pulse φ, is H, and the sample-and-hold pulse φ, H is H, so the capacitor 16M of the line memory 16 is reset to the reference potential ■, clamp. The FBT 14T is opened at t.

When clock φ becomes H between L4 and L3, capacitor 3
8 is precharged, but at that time, the coupling capacitor 3
The voltage appearing at 2 is proportional to the amount of charge caused by the photoexcitation voltage in the photoelectric conversion cell IOC. This voltage on the coupling capacitor 32 is from t6 to t.

By setting φSH to H, the signal is transferred to the capacitor 16M and stored.

At t, to L, a reset operation for storage time control is performed. The vertical line address to be reset is t,
Specify t, . ~tl+ resets the charge of the designated line. The time from the reset operation until the next signal on that line is read is the charge accumulation time. By driving the horizontal shift register 20 with a shift pulse φ after time t13, the signals stored in the capacitor 16M are sequentially transferred onto the output signal line 18 and output to the output terminal 26 via the buffer 24. .

[Problem to be solved by the invention]

On the other hand, recently, as electronic still cameras have been commercialized, imaging devices such as the above-mentioned FGA type area sensor have come to be used in the camera section as well. Electronic still cameras are capable of frame recording of image signals in order to improve the quality of recorded images; Since the photoelectric conversion time point of a field and the photoelectric conversion time point of an even field are shifted by 1/60 seconds, in the case of a moving subject, the image will be blurred from field to field, and a good frame image cannot be obtained after all.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an imaging device that can obtain frame still images with less blur even for moving subjects.

[Means to solve the problem]

An imaging device according to the present invention is an imaging device that once transfers a photoelectric conversion signal of a photoelectric conversion section to a memory means line by line, and sequentially transfers the stored signal of the memory means to an output signal line, the memory means is characterized in that it is a frame memory capable of storing all photoelectric conversion signals of the photoelectric conversion section.

[Effect]

The memory means is a frame memory, and by storing all the photoelectric conversion signals of the photoelectric conversion section in the frame memory, the odd field and even field are
It is possible to substantially prevent the shadow time difference from occurring. Therefore, even for a moving subject, a still frame image with less blur can be obtained.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. The same components as in FIG. 2 are given the same reference numerals. Reference numeral 15 denotes a frame memory having a storage capacity for one frame, which replaces the line memory 16 in FIG. 1
5T stores the output of the clamp circuit 14 in the frame memory 15.
15M is a memory capacitor, and 15N is a FET for writing and continuous output of the memory capacitor 15M. Memory capacitor 15
M is provided corresponding to the photoelectric conversion cell of the photoelectric conversion unit 10, and designates the capacitor 15M to which the vertical shift register 15S performs writing or reading.

5TATV is a starting pulse for starting the vertical shift register 15S, and φ7 is a shift pulse for the vertical shift register 15V. The frame memory 16 and clamp circuit 14 portions are shielded from external light.

In the image pickup device shown in FIG. 1, 5 TATV pulses are applied to the vertical shift register 15S at power-up, and then,
If clock φ9 is not applied, frame memory 15
Only the first line of is in a state where it is effective. In other words, frame memory 15 functions as line memory 16. In this state, the photoelectric conversion signal in units of rows from the photoelectric conversion unit 10 is stored in the frame memory 16 (memory cell of the first row) via the clamp circuit 14, and is stored in the horizontal shift register 20. Under the action, horizontal continuous line 1
8 are sequentially read out. This operation is referred to herein as movie mode.

FIG. 6 shows the sequence of operations for obtaining odd field signals and even field signals when performing the above-described frame still image recording. First, a clear scan for clearing the charge of the photoelectric conversion cell 10C is started in advance. In the photoelectric conversion cell IOC of the cleared line, charge accumulation based on the amount of incident light is started, and when a predetermined accumulation time has elapsed, memory scanning is started. In this memory scanning, the accumulated charges of all the photoelectric conversion cells 10C are transferred to the frame memory 15, and from the frame memory 16- successive scanning of odd fields is performed, followed by successive scanning of even fields. In this operation mode, the accumulation time of each row changes continuously, and there is no accumulation time difference of 1760 seconds between rows as in the conventional example, so it is possible to obtain still images without blur even for moving subjects. Can be done. This operating mode is called still mode.

FIG. 7A shows the drive timing of the image sensor of FIG. 1 during clear scanning. By setting the clear pulse φC to H, setting the address of the line to be cleared to the vertical address DvA, and setting φH to H, the charges in all photoelectric conversion cells IOC on the designated line are cleared.

FIG. 7B shows the driving timing of the image sensor of FIG. 1 near the start of memory scanning. Note that at the time shown in the figure, the clear scan has not yet been completed, so the clear scan and memory scan are performed alternately. When a STATV pulse is applied to tt, the vertical shift register 15S resets the frame memory 15 to the value pointing to the first row and sets the vertical address.
Line 15A closes the first row of switch transistors 15N. As a result, between t4 and t3, the accumulated charge in the photoelectric conversion cell IOC in the first row of the photoelectric conversion unit 10 is transferred to the capacitor 1 in the first row in the frame memory 15.
Transferred to 5M. t, hereafter a7. ! While clearing the line, a driving clock φ9 is applied to the vertical shift register 15S, and the vertical shift register 15S
shift. As a result, the switch transistor 15N in the second row of the frame memory 15 is turned on, and the signal from the cell 10C in the second row of the photoelectric conversion section 10 is transferred to the capacitor 15M in the second row of the frame memory 15. be transferred. By sequentially performing such operations, clear scanning and memory scanning are performed alternately.

FIG. 7C shows the driving timing in a state where only memory scanning is performed after clear scanning has been completed. In order to keep the accumulation time of each line constant, the scan speed of the memory scan is equal to the scan speed of the clear scan. The memory scan ends at t.

FIG. 7D shows successive scan timing for odd (ODD) fields. Application of the 5TATV pulse resets the vertical shift register 15S, and the frame memory 1
The signal from the capacitor 15M in the first row of 5 can be output one after another, and by applying the 5TATH pulse and the drive pulse φ to the horizontal readout shift register 20, the signal from the capacitor 15M in the first row of the output terminal 2
It is output sequentially from 6 onwards. Next, vertical shift register 15
Apply two driving pulses φ to S, frame memory 1
The stored value in the third row of No. 5 can be successively read out by the horizontal successive shift register 20. In this way,
The values stored in the odd rows of the frame memory 15 are read out and output from the output terminal 26.

FIG. 7E shows the scan timing for successive even fields. After resetting the vertical shift register 15S with 5TATV pulses, one φ9 is applied to address the stored value in the second row of the frame memory 15. In this state, 5TATI (pulse and drive pulse φ) are applied to the horizontal readout shift register 20, sequentially scanned in the horizontal direction, and sequentially outputted from the output terminal 26. Next, the drive pulse is applied to the vertical shift register 153. Two φ9 pulses are applied to make it possible to successively read out the stored value in the fourth row of the frame memory 15, and the horizontal successive shift register 20 sequentially reads it out.
The stored values in even-numbered rows of the memory 15 are read out and output from the output terminal 26.

During this successive scanning of odd and even fields, φ
, H are set to L, the photoelectric conversion unit lO and the frame memory 15 are separated in terms of signals, so that the stored signal in the frame memory 15 is not affected by the light incident on the photoelectric conversion unit 10. Also, since the buffer 24 has a high input impedance, it can be read from the frame memory 15 any number of times in a non-destructive manner.

FIG. 8 shows a configuration block diagram of an image recording device using a solid-state image sensor having the functions shown in FIG.
The solid-state image sensor shown in the figure, 116 is a video signal processing circuit for converting the output of the image sensor 114 into a video signal, 118
is a monitor circuit, 120 is a video monitor device, 122 is a PM
A modulation circuit, 124 a recording amplifier, 126 an odd field switch 126A and an even field switch 126B.
128 is a magnetic head for recording signals on odd field recording tracks; 130 is a magnetic head for recording signals on even field recording trunks; 132 is a magnetic head for recording signals as an image recording medium; a magnetic sheet; 134 is a motor that rotates the magnetic sheet 132;
136 is a motor drive circuit that controls the motor 134;
8 is a system control circuit that controls the entire system; 140
142 is a switch that also serves as a power switch; 142 is a recording switch that instructs recording; 144 is a power supply circuit; 146 is a clock generation circuit that is necessary for each part of the system and supplies a lock signal; 148 is a drive circuit that drives the image sensor 124;
150 is an aperture drive circuit that drives the aperture 112. The first stroke of the shirt release closes the switch 140, and the second stroke closes the switch 142. 152 is a motor servo lock signal indicating that the rotation of the motor 134 has become stable.

FIG. 9 shows the operation timing of FIG. 8. In this embodiment, the shutter can be released (more specifically, the switch 142 can be closed) without waiting for the rotation of the motor 134 to stabilize. The time is determined by the shutter release. and switch 1
When switch 40 is closed, power is supplied to the system and switch 1 is turned off at time t, at which point the image sensor 114 starts to be driven.
Until 42 is closed, the image sensor 114 is
mode, a photographed image is displayed on the video monitor 120, and the photometry sensor 113 performs photometry. When the switch 142 is closed at time t, the aperture value and the charge accumulation time of the image sensor 114 are fixed based on the photometric value at that time, and the drive of the image sensor 114 is switched to still mode. If the rotation of the motor 136 is not stable when the clear scan and memory scan are completed, φ
, H remain at L, read scanning of the frame memory 16 is not performed, and the frame memory 16 enters a standby state. When the rotation of the motor 136 becomes stable and the motor servo lock signal 152 becomes H (time t), the gate switch 126A is closed and a signal is sent to the magnetic sheet 132 at the same time as successive odd field scanning is performed. is recorded. Subsequently, consecutive even field scanning is performed from t4 to t, and at the same time, the gate
Switch 126B is closed and a signal is recorded on magnetic sheet 132.

In this embodiment, since clear scanning and memory scanning are performed in an interlaced manner, a time lag of 1/60 seconds does not occur even between adjacent lines in odd and even fields. That is, the charge accumulation time in the image sensor 114 is continuously shifted slightly in the vertical direction, resulting in a still image.
It can achieve the same operation as a vertically running focal brain shutter in a camera. Therefore, it is possible to obtain a frame still image without any blur even for a moving subject. In addition, the photographed still image is stored in the light-shielded frame memory 15 and is signal-insulated from the photoelectric converter 10, so you can capture the image you want without waiting for the rotation of the motor 134 to stabilize. This reduces the release time lag. Furthermore, unlike the conventional example, the speed of clear scanning and memory scanning of the photoelectric conversion unit 10 is 1 per water period.
No need to shift lines, 5μs per line
The focal plane
The time equivalent to the running time of the shafter is 5μ5×500
The line time is approximately 2.5 ms, which is equivalent to or less than that of a mechanical shutter. Therefore, the deformation of a moving subject can be reduced to the same degree or less than in the case of a mechanical shutter.

FIG. 10 shows a block diagram of an embodiment of the present invention in color. In this example, each photoelectric conversion cell IO
C has a so-called interpolation arrangement in which the phase is spatially shifted by 1800 for each horizontal line, and a color filter is arranged in each photoelectric conversion cell IOC as shown in FIG. R is a red filter, G is a green filter, and B is a blue filter. The memory capacitor 15M of the frame memory 15 is also arranged corresponding to the interpolated arrangement of the photoelectric conversion cells IOC. 15B is an interlace circuit for switching the output of the vertical shift register 15S according to odd field (0) or even field (E) scanning. When selecting an odd field, L is input to the control terminal E10 of the interlacing circuit 15B, and when selecting an even field, H is input. In this embodiment, the vertical shift register 153 may have half the number of stages as compared to the case of FIG.

In addition, in order to read out the photoelectric conversion signals of each color, it is equipped with three circuits, 18R, 18G, and 18B are frame
These are output signal lines for sequentially reading out the stored values of designated rows of the memory 150, and are for R, G, and B signals, respectively. 2OR, 20G.

20B are horizontal successive shift registers that specify stored values to be read from the frame memory 15;
23 is the eight shift registers 20R, 20G, 20
Swifts opened and closed by the output of B, 24R, 24G,
24B is an output vanofer, and 26A, 26B, and 26C are output terminals. 5TATH is shift register 20R,2
Starting pulse to start 0G, 20B, φSA, φs
a, φsc are shift registers 20R, 20G,
Shift pulse for 20B.

29 is an address decoder that simultaneously activates two adjacent vertical address lines 10■ of the photoelectric conversion unit 10, and 31 is a vertical address line that is activated by the address decoder 29 according to the vertical address data Dv^. This is a decoder drive circuit. The vertical address data I) va is, for example, 9 bits, the first bit of which specifies whether it is an odd field or an even field, and the remaining 8 bits specify the vertical address. The address decoder 29 applies a read clock φi to the two vertical address lines 10V determined by the even/odd signal from the decoder drive circuit 30 and the vertical address, and the other Clock φ1 is applied to the vertical address line 10V. For example, in an odd field, the first and second rows, the third and fourth rows,
And so on, in even fields, the second and third rows
row, 4th row, 5th row, and so on, each with 2
At the same time, successive clocks are applied to the 10V vertical address lines.

Note that the interlacing circuit 15B has two
The book's vertical address lines 15A are activated at the same time.

FIG. 12 shows a sequence when driving the image sensor shown in FIG. 10 in still mode. As described above, since two adjacent rows of the photoelectric conversion cells IOC are addressed at the same time, clear scanning and memory scanning are also performed two rows at a time. In the example shown in FIG. 12, clear scanning and memory scanning are performed in odd field mode. Clear scan and memory scan are 2
Since the process is performed line by line, it can be completed in 1/2 the time compared to the case shown in FIG. After the memory scan is completed, the frame memory 15 is read out and scanned, and the odd field and even field are read out in this order.

FIG. 13A shows the drive timing near the start of clear scanning. Except that two adjacent lines are cleared at the same time.
It is similar to FIG. 7A. The (0) added to the line number of address DMA indicates odd field mode.

FIG. 13B shows drive timing near the start of memory scanning and near the end of clear scanning. Frame memory 15
In order to perform scanning in odd mode, interlacing circuit 1
Set L to the control terminal E10 of 5B. Memory scanning is also performed two rows at a time. FIG. 13C shows the driving timing near the end of memory scanning, and FIG. 13D shows the driving timing in reading scanning of the frame memory 15 in an odd field. In Figure 13D, frame memory 15
Two lines each, such as the first and second lines, the third and fourth lines, are distributed to three outputs corresponding to R, G, and B and output. This differs from FIG. 7D in that φ9 is applied once per horizontal scanning period. Furthermore, L is set to the control terminal E10 of the interlace circuit 15B.

FIG. 13E shows the drive timing in read scanning of the frame memory 15 for even fields. Control of interlace circuit 15B? 11 terminal E10 is set to H,
Two rows of signals are read out, such as the second and third rows, the fourth and fifth rows, and so on.

FIG. 14 is a timing diagram near the start of horizontal scanning timing. After the starting pulse 5TATH is applied to the shift registers 2OR, 20G, and 20B, shift pulses φ, φ8M, φ, and C are applied to each of the shift registers 20R, 20G, and 20B with a 1206 phase shift. This causes FET 23 to be closed at 1/3 duty cycle. Assuming that the n-th and (r++1) rows are being read now, and the output of the n-th row and m-column is expressed as (n, m), the signals for two lines will be generated at the timing shown in Figure 14. Output terminal 26A.

It is divided into 26B and 26C (voltage Vo+, Voz, VO3). In addition, voi ■. By adding 2 and V(11), it is possible to extract a wideband luminance signal with twice the horizontal resolution of the I-line due to the interpolation pixel arrangement.

FIG. 15 shows the scanning order in the luminance signal. Taking advantage of the fact that the stored information in the frame memory 15 is non-destructive, a wide band luminance signal is generated using all pixel information in both the odd field and even field. Can be formed.

Furthermore, when recording still images, field recording, in which only one field is recorded, is often recorded by adding the signals of two adjacent lines within the image sensor, whereas frame recording, in which both fields are recorded, is were different. Therefore, in the past, it was necessary to change the gain during photometry between field recording and frame recording, but in this example, the sensitivity is the same for both, so such a change operation is not necessary. .

Next, a case will be described in which the image sensor shown in FIG. 10 is driven in movie mode. After power is turned on, a starting pulse 5TATV is applied to the vertical shift register 153 to reset it. This causes the first and second rows of frame memory 15 to be addressed. In order to make the frame memory 15 function as a line memory, the drive clock φ7 is not applied. In addition, the control unit E1 of the interlace circuit 15B
If L is set to 0, the first and second lines will form a line memory, and if H is set, the second and third lines will form a line memory. The operation is the same either way. By operating in the same manner as shown in FIG. 5 in this state, the operation becomes movie mode. However, by switching the setting of the successive line address DVA on a field-by-field basis, two lines of signals shifted by one line are simultaneously read out on a field-by-field basis, making it possible to obtain an interlaced image.

According to this embodiment, the number of pixels is relatively small, for example, 6 horizontally.
00, an image sensor with about 500 pixels vertically and 480 pixels horizontally
It is possible to obtain high-resolution frame still images of about 350 vertical TV lines. Furthermore, since the same sensitivity is sufficient for field recording and frame recording, there is no need to switch the gain of the photometric system, and the circuit configuration can be simplified. Furthermore, since clear scanning and memory scanning are performed two lines at a time, the first
Compared to the embodiment shown in the figure, the time corresponding to the travel time of the focal brain shifter can be further shortened to 1/2, and the deformation of a fast-moving subject can be further reduced.

〔Effect of the invention〕

As can be easily understood from the above explanation, according to the present invention, it is possible to obtain a frame still image without blur even for a moving subject. Furthermore, when applied to an electronic still camera, it is possible to take a picture and save the photographed image in the frame memory of the imaging means without waiting for the rotation of the recording medium rotation motor to stabilize, thereby reducing the release time lag. can be significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of the configuration of a conventional example, FIG. 3 is a detailed diagram of the photoelectric conversion cell IOc in FIG. 2, and FIG. 4 is a block diagram of the photoelectric conversion cell IOC. 5 is a drive timing diagram of FIG. 2, FIG. 6 is an operation timing diagram of the image sensor in still mode of FIG. 1, FIGS. 7A, 7B, 7C, and Figure 7D and 7th
Figure E is a more detailed timing diagram of Figure 6, Figure 8 is a block diagram of the configuration of the electronic still camera, Figure 9 is an operation timing diagram of Figure 8, and Figure 10 is a second embodiment of the present invention. 11 is a layout diagram of the color filter in FIG. 10, FIG. 12 is an operation timing diagram of the image sensor in FIG. 10, FIG. 13A, FIG. 13B, FIG. 13C, FIG. 13D, and Fig. 13E is a more detailed drive timing diagram of Fig. 12, Fig. 14 is a horizontal scanning timing diagram of Fig. 10, and Fig. 15 is a more detailed drive timing diagram of Fig. 12.
The figure is a scanning order chart of luminance signals in the image sensor of FIG. 10. 10-Photoelectric conversion section 10C・-Photoelectric conversion cell 10■・
-・Vertical address! la 1os-・Signal readout line 12
...Reset circuit, 14--clamp circuit 15-
・Frame memory 15S-Vertical shift register 1
8.18R, 18G, 18B --- Output signal line 20.2
OR, 20G, 20B-・Horizontal shift register 24
,24R,24G,24B--output buffer 26,
26A, 26B, 26C --- Output terminal 32 --- Coupling capacitor Figure 11 Figure Figure τI rim uu Curl Rrap takr (
r3 Figure 7B shoes η1 leaning) Shizu[ ~:, JJL (ODD) oop) MLL (ooo) fd, LL (opo) Elephant acupuncture-1 (
ε claw) Fig. 13A f Fig. 138 (1) 5TArv s,] Fig. 13E (1) 5TAry H (1) STATH Fig. 14

Claims (1)

[Claims] An imaging device that once transfers a photoelectric conversion signal of a photoelectric conversion section to a memory means line by line, and sequentially transfers the stored signals of the memory means to an output signal line, the memory means comprising:
An imaging device characterized in that it is a frame memory capable of storing all photoelectric conversion signals of the photoelectric conversion section.