JP2007267431A - Solid-state image pickup device and method of driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output a high-definition digital image signal by simultaneous AD translation by performing the AD translation quickly with low load without increasing the scale of a pixel array part and an optical system. <P>SOLUTION: The pixel array part 110 has a photoelectric converter and a pixel transistor for each pixel 111 and outputs an analog pixel signal. An AD memory part 130 is constituted by arranging a unit memory 131 in two-dimensional arrangement corresponding to each pixel arrangement of the pixel array part 110, sequentially accumulates the analog pixel signals read through a perpendicular signal line and performs various kinds of processings (for example, solid-state pattern noise removal and gain adjustment, etc., by CDS) including the AD conversion. AD conversion circuits 132 are provided to each unit memory 131 of the AD memory part 130 and the analog pixel signal read from each pixel by the AD conversion circuit 132 is converted to a digital pixel signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device such as a CMOS image sensor, which has a pixel array section in which a plurality of pixels are provided in a two-dimensional array and performs signal processing by extracting signals from each pixel of the pixel array section.

Since a CMOS image sensor is generally manufactured using a MOS process, unlike a CCD image sensor, an AD conversion circuit can be mounted on-chip on the same chip provided with a pixel array portion.
As a form of mounting this AD conversion circuit on-chip, three types described later are known.
FIG. 4 is an explanatory diagram showing a configuration example of a CMOS image sensor on which such an AD conversion circuit is mounted on-chip. However, the hatched blocks 200A, 200B, and 200C in the figure show three arrangement examples of the AD conversion circuit, and any one arrangement example is adopted in the actual circuit.

First, the configuration of a conventional CMOS image sensor will be described with reference to FIG.
As shown in the figure, this CMOS image sensor has a pixel array unit 210, a V selection circuit 220, a column signal processing unit 230, an H selection circuit 240, and an output unit 250 mounted on one chip.
The pixel array unit 210 is provided with a large number of pixels in a two-dimensional array (matrix).
The V selection circuit 220 is a circuit that drives each pixel of the pixel array unit 210 while sequentially selecting each pixel in the vertical direction (column direction).
The column signal processing unit 230 is a circuit that is provided corresponding to each pixel column of the pixel array unit 210, and that sequentially receives signals from each pixel 211 and performs processing such as fixed pattern noise removal and gain adjustment.
The H selection circuit 240 sequentially selects the column signal processing unit 230 in the row direction, and outputs a signal of each pixel processed by the column signal processing unit 230 to the output line 241.
The output unit 250 receives the pixel signal from the output line 241, performs final signal processing, and outputs it as an image signal.

In such a CMOS image sensor, the AD conversion circuit is arranged on-chip in the following three ways.
First, in the arrangement example indicated by the hatched block 200A shown in FIG. 4, each pixel 211 is provided with an AD conversion circuit, and AD conversion is performed for each pixel, and a digitized pixel signal is output from each pixel 211. (Hereinafter referred to as pixel level AD). (For example, patent document 1).
Further, in the arrangement example indicated by the hatched block 200B shown in FIG. 4, each column signal processing circuit 230 is provided with an AD conversion circuit, and AD conversion is performed for each column and digitized from each column signal processing circuit 230. A pixel signal is output (hereinafter referred to as column level AD). (For example, patent document 2).
Further, in the arrangement example indicated by the hatched block 200 </ b> C shown in FIG. 4, an AD conversion circuit is provided in the output unit 250, AD conversion is sequentially performed on a signal guided to the output line 241, and the output unit 250. Output a pixel signal digitized outside the chip (hereinafter referred to as chip level AD). This is equivalent to a simple analog output device connected to an AD conversion circuit.
US Pat. No. 5,461,425 Japanese Patent No. 253234

However, the above three AD conversions have the following problems.
(1) Since the pixel level AD can be AD-converted simultaneously for all the pixels, high-speed processing is possible. However, since the AD conversion circuit is arranged in each pixel, the scale of each pixel increases, and the pixel array unit However, there is a drawback that the aperture ratio (area ratio of the photodiode in the pixel) is lowered and the sensitivity is lowered.

(2) The column level AD is simpler and smaller in size as compared with the pixel level AD, but the number of times (for example, several hundred to several) is output to output an image for one frame. Since AD conversion has to be performed thousands of times, there is a disadvantage that the speed is low.
Further, since AD conversion is performed in a short time, it is necessary to increase the circuit band, and noise increases.
In addition, since AD conversion processes the rows in sequence for one frame, the time for AD conversion between the first row and the last row is shifted by one frame time. It is not suitable for reducing the size (for example, when shooting a moving subject).

(3) The chip level AD has the same properties as the column level AD. In other words, although the pixels are simplified, in order to output one frame, AD conversion must be performed a number of times corresponding to the number of pixels (for example, several hundred thousand to several million times), and therefore, more than column level AD. There is a drawback of being slow.
In addition, since AD conversion is performed in a short time, it is necessary to increase the bandwidth of the circuit, and the noise becomes larger than the column level AD. In addition, since AD conversion sequentially processes pixel signals for one frame, a time difference of one frame occurs in the time of AD conversion between the first pixel and the last pixel, and the time difference of the entire screen is made as small as possible. Not suitable if you want to.

  Accordingly, an object of the present invention is to perform AD conversion quickly and with low burden without increasing the size of the pixel array unit and the optical system, and to output a high-quality digital image signal by simultaneous AD conversion. An object of the present invention is to provide a solid-state imaging device capable of performing

  In order to achieve the above object, the present invention provides a pixel array section in which a plurality of pixels are provided in a two-dimensional array, and a plurality of unit memories in a two-dimensional array corresponding to the pixel array in the pixel array section. An AD memory unit provided with an AD conversion circuit, a pixel array scanning circuit that scans the pixel array unit and reads an analog signal of each pixel to the AD memory unit, and scans the AD memory unit to store each unit memory. And a memory scanning circuit for outputting a digital signal.

In the solid-state imaging device of the present invention, an AD conversion circuit is provided for each unit memory of the AD memory unit corresponding to the two-dimensional array of pixel arrays, and signals read from each pixel are AD converted by the AD memory unit.
Accordingly, AD conversion can be performed in a distributed manner by a two-dimensional array of AD conversion circuits, and high-speed AD conversion can be performed as compared with the above-described column level AD conversion and chip level AD conversion. In addition, the bandwidth of the AD conversion circuit can be reduced, and a signal with less noise can be obtained.
Further, since no AD conversion circuit is provided in the pixel, the configuration of the pixel circuit can be simplified, the aperture ratio of the pixel can be increased, and a highly sensitive pixel array portion can be configured. In addition, since the pixel signal can be read from the pixel array unit to the AD memory unit in a short time, the processing time difference within one screen can be reduced, and even if a moving subject is taken, there is little distortion and a good quality image can be obtained. Obtainable.

Embodiments of the solid-state imaging device according to the present invention will be described below.
FIG. 1 is an explanatory diagram showing a configuration example of a CMOS image sensor on which an AD conversion circuit according to an embodiment of the present invention is mounted on-chip.
As shown in the figure, this CMOS image sensor includes a pixel array unit 110, a V selection circuit 120, an AD memory unit (memory block) 130, a memory V selection circuit 140, an H selection circuit 150, and an output unit 160 on one chip. It is mounted on.

The pixel array unit 110 is provided with a large number of pixels 111 in a two-dimensional array (matrix), and an analog signal detected in each pixel is an output signal line (vertical signal) provided for each pixel column. Line).
Note that various configurations can be used for the circuit configuration of each pixel 111. For example, a photoelectric conversion element (e.g., a photodiode), a transfer transistor that reads the generated charge to a floating diffusion (FD) unit, and An amplifying transistor that converts the potential fluctuation caused by the signal charge transferred to the FD unit into an electric signal and outputs the signal, a selection transistor that connects the output of the amplifying transistor and an output signal line (vertical signal line), and a potential of the FD unit And a reset transistor for resetting.
The V selection circuit 120 drives each pixel of the pixel array unit 110 while sequentially selecting the pixels in the vertical direction (column direction) in units of rows, and constitutes a pixel array scanning circuit.

The AD memory unit 130 is configured by disposing unit memories 131 in a two-dimensional array corresponding to each pixel array of the pixel array unit 110, and sequentially stores analog pixel signals read through the vertical signal lines to perform AD conversion. Various types of processing (for example, solid pattern noise removal and gain adjustment by CDS) are performed. Each unit memory 131 is constituted by a DRAM.
Each unit memory 131 of the AD memory unit 130 is provided with an AD conversion circuit 132. The AD conversion circuit 132 converts an analog pixel signal read from each pixel into a digital pixel signal.
1 shows an example in which each pixel 111 of the pixel array unit 110 and each unit memory 131 of the AD memory unit 130 correspond to each other on a one-to-one basis, but a plurality (N ≧ 2) The pixel may correspond to one unit memory in an N to 1 correspondence. In this case, a plurality of (N) pixels are sequentially processed by one unit memory.
In this example, each unit memory array of the AD memory unit 130 directly corresponds to one image frame, and AD conversion is performed in units of this frame. Therefore, the AD conversion method of this example is called a frame memory level AD. Shall.

The memory V selection circuit 140 is a circuit that scans and drives each unit memory 131 of the AD memory unit 130 and outputs a digital pixel signal processed by each unit memory 131.
The H selection circuit 150 sequentially selects the AD memory unit 130 in the row direction, and outputs the digital pixel signal processed by the AD memory unit 130 to the output line 151. The memory V selection circuit 140 and the H selection circuit 150 constitute a memory scanning circuit.
The output unit 160 receives the digital pixel signal from the output line 151, performs final signal processing, and outputs it as a digital image signal outside the chip.

  In the frame memory level AD of this example, the pixel signals of the pixel array unit 110 can be transferred to the AD memory unit 130 in a short time, and then the signals of all the pixels can be AD converted simultaneously. Therefore, unlike the conventional pixel level AD, the pixel does not become large due to the AD conversion circuit and the aperture ratio does not decrease. Unlike the column level AD and the chip level AD, AD conversion is performed in one frame. Since it only needs to be performed once, processing can be performed at high speed. In addition, since individual AD conversion processing can be performed slowly, the band of the AD conversion circuit can be reduced and noise can be reduced.

FIG. 2 is a circuit diagram showing a circuit example of the unit memory 131 in the AD memory unit 130 of this example, and FIG. 3 is a timing chart showing an example of driving in the AD memory unit 130 of this example.
First, the configuration of the unit memory 131 will be described with reference to FIG.
The unit memory 131 of this example takes the difference between the reset level voltage and the signal level voltage read from each pixel through the vertical signal line 133, and removes fixed pattern noise generated for each pixel by CDS (correlated double sampling). A circuit 170 and an AD conversion circuit 180 that compares the difference signal generated by the CDS circuit 170 with a ramp wave and outputs a digital signal value (that is, the AD conversion circuit 132 shown in FIG. 1). Is done. Here, it is assumed that a pixel circuit of a type in which the reset level voltage is a voltage corresponding to a 0 level signal and a signal level voltage that is negatively changed with respect to the reset level voltage is sequentially output.
As shown in FIG. 2, the CDS circuit 170 includes switches (SW1, SW2) 171, 172, capacitors (C1, C2) 173, 174, and a differential amplifier 175.
Further, the AD conversion circuit 180 is a configuration example in the case of having a data width of 10 bits in the illustrated example. For each bit, a conversion transistor (Tr0 to Tr9) 181, a sampling capacitor 182, and an output Transistor 183.

Hereinafter, the operation of the AD memory unit 130 of this example will be described with reference to FIG. Since the ramp voltage is an analog voltage signal, the waveform diagram in FIG. 3 shows a scale different from other signals.
(1) Reading period from the pixel array unit 110 to the AD memory unit (memory block) 130 Here, signals are read from the pixel array unit 110 row by row and written to the unit memory 131 of the AD memory unit 130 corresponding to each pixel. It becomes operation.
The operation for one line is as follows.
(1-1) First, the switches 171 and 172 are turned ON during a period in which the reset level is read from the pixel 111 to the vertical signal line 133.
Here, the potential on the switch 171 side of the capacitor 173 is at the reset level, but on the opposite side, the ramp voltage supplied by the ramp signal supply line (ramp wiring) 191 is applied to the + input terminal of the differential amplifier 175. Therefore, when the switch 172 is turned on, the negative input terminal and the output terminal of the differential amplifier 175 are clamped to the ramp voltage.

(1-2) Next, after the switch 172 is turned OFF, the signal level of the pixel is read out to the vertical signal line 133. At this time, the negative input potential variation proportional to the difference between the reset level and the signal level occurs through the capacitor 173 to the negative input terminal of the differential amplifier 175, and the signal voltage from which the fixed pattern variation of the pixel is removed is input. become.
As a result, the output of the differential amplifier 175 becomes High level, and the transistor 181 is turned on.
(1-3) Next, when the switch 171 is turned OFF, it is disconnected from the vertical signal line 133, and this state is maintained.
During this period, the ramp signal is at a high level. Further, the driving clock wiring (ck wiring) 192 of the transistor 181 and the driving clock wiring (word wiring) 193 of the transistor 183 are both at the low level.
This operation is repeated for each row, and one frame signal is taken into the AD memory unit.

(2) AD conversion period Next, while driving the ramp voltage from High to Low, the driving clocks ck [0] to ck [9] of the transistor 181 are driven to count up by 10 bits. When the ramp voltage becomes lower than the minus input terminal voltage of the differential amplifier 175 held in (1), the output of the differential amplifier 175 is inverted, and the ck [0] to ck [9] at that time are inverted. A value (High / Low) is held in each capacitor 182, that is, a 10-bit AD conversion result is stored.
Note that the ramp voltage and ck [0] to ck [9] are common throughout the entire AD memory unit, so that signals for one frame are AD-converted simultaneously. In addition, since High / Low is written to the capacitor 182, this is in principle a DRAM.

(3) Memory Access Period Next, a pixel signal to be read from the AD memory unit is read from the bit wiring 194 which is a data output line by driving the word wiring 193 of the transistor 183. Note that both the reading method and the reading circuit configuration may be the same as those of a normal DRAM. Further, it may be read out line by line, or only one part may be read out. Alternatively, complete random access is possible.

  Further, in order to obtain information of the next frame, the same operation is performed from the reading operation (1). Since this is an operation for each row, even in the reading period to the AD memory unit, a memory access is possible for a row that has not yet been read out. Thereafter, these operations are repeated.

By the way, in a CMOS image sensor without a conventional frame memory, even if one row is simultaneously read out to the column signal processing unit, the column signal processing circuit of each column is selected in order and the signal is guided to the horizontal signal line. The period for outputting one by one is required several times to several tens of times, and after that, it is finally possible to move to the next line.
On the other hand, in the method of this example, reading to the AD memory unit 130 is completed only by reading one row at a time. Therefore, the time required for the reading ends in a short time of 1 to several tens of minutes. . This means that the time lag when each row is read is shortened, so that the time difference of the entire screen is reduced several times to several tens of times. If there is this time difference, the subject is distorted due to the time difference when the moving subject is photographed. However, according to the method of this example, this distortion has the effect of reducing several times to several tens of times. Of course, since reading from the pixel is the same as in the conventional CMOS image sensor, a known method of eliminating the distortion by synchronizing the exposure time with the conventional CMOS image sensor can be applied to this example.

Further, in the method of this example, signals for one frame are AD converted at the same time, so AD conversion is completed in a short time.
Further, since reading from the AD memory unit 130 is access to the frame memory, there is no need for the order for each row, and the reading order is completely free. Of course, another signal can be written from the outside using the word line and the bit line, as in a normal DRAM.
Similarly to the conventional CMOS image sensor, the pixel is reset and the electronic shutter can be applied at an appropriate time before reading the signal of each pixel.

In the above example, it is assumed that the pixel circuit is of a type that sequentially outputs a reset level voltage (voltage corresponding to the signal 0) and a signal level voltage that is negatively swinged with respect to the reset level voltage. Of course, it is also possible to apply to.
In addition to the above, the AD memory unit can be variously modified. For example, as described above, it is possible to assign one AD conversion circuit corresponding to a plurality of pixels.
Further, the AD conversion circuit can use a chopper type comparator or a ΔΣ type. Further, an SRAM type or the like can be used as the memory instead of the DRAM type.

As described above, according to the solid-state imaging device of the present invention, an AD conversion circuit is provided for each unit memory of the AD memory unit corresponding to the two-dimensional array of pixel arrays, and signals read from the pixels are stored in the AD memory unit. Since the AD conversion is performed with the AD conversion circuit of the two-dimensional array, the AD conversion can be distributed, and the AD conversion can be performed at a higher speed than the above-described column level AD conversion and chip level AD conversion. The bandwidth of the conversion circuit can be reduced, and a signal with less noise can be obtained.
In addition, since no AD conversion circuit is provided in the pixel, the configuration of the pixel circuit can be simplified, the aperture ratio of the pixel can be increased, a highly sensitive pixel array unit can be configured, and the pixel array unit can be shortened to the AD memory unit. Since the pixel signal can be read in time, the time difference in processing within one screen can be reduced, and even when a moving subject is taken, there is little distortion and an image with good image quality can be obtained.
Further, since reading from the AD memory unit is access to the frame memory, there is no need for the order for each row, and the reading order is completely free. Further, similarly to a normal DRAM, another signal can be written from the outside using the word line and the bit line.

It is explanatory drawing which shows the structural example of the CMOS image sensor which mounts the AD converter circuit by the embodiment of this invention on-chip. FIG. 2 is a circuit diagram illustrating a circuit example of a unit memory in the AD memory unit illustrated in FIG. 1. 2 is a timing chart illustrating an example of driving in the AD memory unit illustrated in FIG. 1. It is explanatory drawing which shows the structural example of the CMOS image sensor which mounts the conventional AD conversion circuit on-chip.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 110 ... Pixel array part, 111 ... Pixel, 120 ... V selection circuit, 130 ... AD memory part, 131 ... Unit memory, 132, 180 ... AD conversion circuit, 133 ... Vertical signal line, 140 ... ... Memory V selection circuit, 150 ... H selection circuit, 160 ... Output section, 170 ... CDS circuit, 171, 172 ... Switch, 173, 174, 182 ... Capacitor, 175 ... Differential amplifier, 181, 183: Transistor.

Claims (8)

A pixel array section in which a plurality of pixels are provided in a two-dimensional array;
A plurality of unit memories corresponding to the pixel array of the pixel array unit are provided in a two-dimensional array, and an AD memory unit provided with an AD conversion circuit in each unit memory;
A pixel array scanning circuit that scans the pixel array unit and reads an analog signal of each pixel to the AD memory unit;
A memory scanning circuit that scans the AD memory unit and outputs a digital signal of each unit memory;
A solid-state imaging device.   The solid-state imaging device according to claim 1, further comprising: an output unit that processes a digital signal output from the AD memory unit and outputs the signal to the outside of the device.   2. The solid-state imaging device according to claim 1, wherein each pixel of the pixel array section and each unit memory of the AD memory section correspond one-to-one.   2. The solid-state imaging device according to claim 1, wherein each pixel of the pixel array unit and each unit memory of the AD memory unit correspond N to 1 (N ≧ 2).   A signal is read from the pixel array unit to the AD memory unit by the pixel array scanning circuit, then AD conversion is performed in the AD memory unit, and then a signal is output from the AD memory unit by the memory scanning circuit. Item 2. The solid-state imaging device according to Item 1.   2. The solid-state imaging device according to claim 1, wherein AD conversion in the AD memory unit is simultaneously performed in all unit memories.   2. The solid-state imaging device according to claim 1, wherein reading of signals from the pixel array unit to the AD memory unit is performed in units of pixel rows, and AD conversion in the AD memory unit is performed simultaneously in all unit memories.   The solid-state imaging device according to claim 1, wherein the unit memory is a DRAM.

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