JPS58125982A - Solid state image pickup device - Google Patents

Abstract

PURPOSE:To realize the high density of an electrostatic induction type phototransistor, by combining said phototransistor and a frame memory. CONSTITUTION:A phototransistor TR201 receives the incident light and performs a photoelectric conversion with an electronic depleting action. If a vertical flyback time starts under such conditions, phiG1 is set at a high level to turn on an MOS switch 208. Furthermore a vertical scanning circuit 203 has a high-speed operation, and the signal information of a TR201 set vertically is transmitted to a corresponding memory capacitor 212 via signal transmission lines 207 and 209. In a vertical scan period, an MOS switch 205 is turned off. Thus the pulse given from the circuit 203 is transmitted only to a pulse transmission line 204 at a memory capacitor part to turn on a vertical MOS switch 213. Then in a vertical scan period, the pulse given from a horizontal scanning circuit 211 is applied to the gate of a horizontal MOS switch 210. Thus the switch 210 is turned on. Then a signal is read out of the capacitor 212, and the signal voltage emerges at an output load resistance RL.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an SIT (static induction transistor, 8tat
The present invention relates to a solid-state imaging device having a photoelectric conversion section having a structure (abbreviation for io induction transistor) and a corresponding frame storage section.

A typical photoelectric conversion unit of a solid-state imaging device is a pn photodiode or an MO8 photodiode, which accumulates carriers excited by incident light in a floating region and converts the accumulated carriers into a floating region. Since it is only for reading, the photosensitivity depends on the aperture ratio of the photodetector.

For this reason, if the chip size of the image sensor is reduced and the number of pixels is increased to increase the density, the light sensitivity inevitably decreases in proportion to the decrease in the aperture ratio of the photodetector.

Page 3 Furthermore, it becomes impossible to provide a general overflow drain or the like near the photodiode as a countermeasure against pluming, considering the aperture ratio that accompanies higher density.

Under these circumstances, as an element structure that increases the aperture ratio and enables countermeasures against pluming, a pixel area (such as a photodiode) that does not perform photoelectric conversion, a pixel selection means (such as a scanning circuit), and a signal readout means (such as a scanning circuit) are required. A solid-state imaging device has been proposed in which a photoconductive film for photoelectric conversion function, known as a laminated film, is formed on the surface of a semiconductor substrate on which a scanning circuit, analog shift register, etc.) are formed.
For example, JP-A-49-91116. @ Kaisho 6l-1
0715j Japanese Patent Publication No. 51-95720. Japanese Unexamined Patent Publication 1986-1995
721 etc.). However, since photoconductive films are mainly composed of amorphous or polycrystalline semiconductors, material integrity (purity,
It is inferior to single crystals in terms of accuracy of stoichiometric ratio and crystal perfection, and it is extremely difficult to control properties and improve reproducibility.

On the other hand, the aperture ratio is also improved by providing an amplification function inside the element (1).Sho 58-125982 (2) The sensitivity is improved by increasing the aperture ratio, and the photoelectric conversion operation is performed by majority carrier depletion operation in the pixel region. There are also proposals to take measures against pluming (for example, Japanese Patent Laid-Open No. 55
-124259). This uses an SIT as a phototransistor, but since it is essentially a three-terminal element, it is extremely difficult to increase the density compared to one using a photodiode.

Therefore, the present invention solves the above-mentioned conventional problems, provides high sensitivity, measures against plumping, enables high density (high integration), and at the same time, provides easy characteristic control and high reproducibility. The purpose is to provide a good solid-state image sensor.

Therefore, in the present invention, a phototransistor with an SIT structure is used in the photoelectric conversion section, and its internal amplification function and majority carrier depletion operation realize high sensitivity and prevent pluming, and the phototransistor is laminated on the surface of the substrate. & A three-dimensional structure using a single crystal, and a frame memory that temporarily stores the signal charge from the phototransistor. This realizes higher density transistors.

Hereinafter, one embodiment of the present invention will be described in detail using the drawings. Figure 1 shows the photoelectric conversion section of this device, and Figure 1 (IL) uses an nzpn type phototransistor. It is formed in a grown single crystal portion (therefore, hereinafter also referred to as a stacked structure n+ipn+ type phototransistor).

As shown in FIG. 1 (IL), on the surface of the P substrate 101,
n+ area '+02 which is a pixel area and signal transmission 1i11
n+ region 104 connected to 03 and gate electrode 1o6
constitutes the M08 switch 106, and the P region 10 contacts the surface of the insulator region 107 from the n+ region 102 to the surface of the insulator region 107
8. High resistance region (represented by 1) for photoelectric conversion 10
99 n+ class area 11o, transparent electrode 111 are stacked, and n
A +ipn+ type phototransistor is configured.

The equivalent circuit of FIG. 1(a) is shown in FIG. 1(b-1). The n lpn type phototransistor including the transparent electrode 111 can be further simplified as shown in the diagram on the left, and is also called an SIT type phototransistor 112.

Below, the operation of the SIT type phototransistor 112 is shown in FIG. 1 (b-2)t(b-3), which shows an energy band diagram.
Explain using. (Here, FIG. 1(b-2) shows the case where an intrinsic semiconductor is used as the high resistance region 109, and the voltage Vs of the transparent electrode is equal to the voltage vO of the signal transmission line and 0.
corresponds to the state of being a master. FIG. 1 (b-s) shows that vS>
This corresponds to the operating state when o is set. ) In FIG. 1(b-1), if the impurity density in the high and low antibiotic regions 109 is zero or extremely low, if a small voltage is applied to Vs, the high and low antibiotic regions 109 are completely covered with a depletion layer, resulting in pinch-off. The state is n+, which is the pixel area.
A saddle point-shaped potential barrier 113 appears in front of the floating region 102, and the height of this potential barrier 113 is mainly determined by ? The flow rate of electrons flowing from the floating region 102 to the transparent electrode 7 vane electrode 111 is controlled.

In FIGS. 1(b-1) and (1)-3), when light enters the high-low antibiotic region 109, electron-hole pairs excited by the incident light are generated within the high-low antibiotic region 109. Among these electrons, the n+ region 110 absorbs them immediately. The holes are accelerated by the strong electric field applied to the high resistance i region 109, flow into the p floating region 108, and positively charge the p floating region 10B. Therefore, p floating region 1
With 0B? The junction of floating region 102 is forward biased.

This is the potential barrier 11 for electrons in the cod floating region 102.
As a result, electrons from the n+ floating region 102 pass through the p floating region (crossing over the stain level barrier 113), drift through the high resistance region 109, and become n+ It is absorbed into region 110.

As a result,? The floating region 102 is in an electron depletion state (in other words, electrons flow out and become insufficient), which indicates that the floating region 102 is positively charged, and the potential barrier 113
Sensitivity multiplication effect occurs by appropriate setting of
, Dig, of1980 IICDMpp350
-354). At this time, the smaller the capacitance cr of the p floating region 108 shown in FIG. 1(b, -1), the greater the voltage change with a small inflow of holes, and the better the sensitivity. On the other hand, the capacitance Os of the floating region 102 does not affect the voltage value of this region in any significant way. This is because electrons flow from the nx floating region 102 to the high-low antibiotic region 109 until the n.

Further, the read voltage hardly depends on the capacitance CIl of the signal transmission line 103. This is because when electrons flow into the n+ floating region 102 from the signal transmission line 103 during signal readout,
At that moment, the positive voltage of the floating region 102 decreases, and as a result, the forward bias of the junction between the p floating region 10B and the n floating region 102 becomes deeper.
Since the electrons flowing into the region 2 are immediately injected into the high resistance region 1o9, there is an e vane.

Although the contact between the transparent electrode 111 and the n+ region 11o may be an ohmic contact, as can be seen from FIG. 1(b-3), it is found that a blocking type contact for holes is more desirable for reducing dark current.

Further, in FIG. 1(b-3), the holes trapped near the potential barrier 113 are in an accumulated state.

Therefore, even if a signal is read out using the MOS switch 102, the potential of the n+# free region 102 is determined by the height of the potential barrier 113 corresponding to the accumulation of holes in the p floating region 1o8. As long as the holes are not lost due to recombination or the like, the potential of the floating region 102 does not change. In other words, non-destructive reading becomes possible. On the contrary, n
In order to set the potential of the ten region 1o2 to the initial setting value vo, holes in the p region 108 must be removed. In this device, as described later, vll is set to 0? A method is used in which a negative voltage is applied for I5 and the holes in the p floating region 108 are discharged to the transparent electrode 111 side.

In addition, in order to realize the above operation, the high and low antibiotic regions 109 from the floating regions 10 to 102 to the transparent electrodes 111 must be
high resistance i region 10 controlled by series resistance r8 and light incidence
If the virtual conductance of the photoelectric conversion region including 9 is Gm, it is necessary that rsGm<1. In order to realize this condition, it is possible to use not only an intrinsic semiconductor but also a ``type'' or PL type semiconductor having an impurity density of about 1,012 to 10150111-5 as the high-low antibiotic region 109. As the area 108,
101s to 1018C "An impurity density of about 3 may be used.

FIG. 2 shows an embodiment of the solid-state imaging device of the present invention using the SIT type phototransistor shown in FIG. 1 as a light receiving element.

The configuration of this embodiment includes two-dimensionally arranged SIT type phototransistors 201 and 214, and a vertical MO for pixel selection.
S switch 2o2. Vertical shift register 203 for sequentially scanning the vertical MOS switches row by row. A pulse transmission line 204 for transmitting scanning pulses from the vertical shift register 203, and a pulse transmission line 206 . A signal transmission line 207 for transmitting the potential of the phototransistor 201 when each vertical MOi9 switch 202 is turned on and a signal transmission line 2 via a MOS switch 208 controlled by φ・1
o9. Horizontal MO8 switch 210 for setting the potential of each signal transmission line 209 with an external power supply To (OV may also be used)
．． Horizontal scanning circuit 211 for sequentially scanning the horizontal MOS switch 210 Capacitors 212 and 21 for temporarily storing signal information of the SIT phototransistor 201
6. Vertical MO8 switch 213 for transmitting signal information of the capacitor 212 to the signal transmission line 209. Signal transmission line 2
φ to refresh the potentials of 07 and 209.
It consists of a MOS switch 216 controlled by G2. Note that the phototransistor 201 is set to Vs so that photoelectric conversion is performed by the depletion operation of majority carriers in the pixel region (this corresponds to the n+gj4 region 102 in FIG. 1 (IL)).
is applied.

The operation of the solid-state image sensor shown in the embodiment shown in FIG. 2 is explained by the drive pulse timing chart shown in FIG.
25982(4) will be explained below using the potential model shown in the figure (below, in addition to being applied to the signal output terminal So in Fig. 2, the voltage from the city power supply is Ov).

The phototransistor 201 in FIG. 2 receives the incident light and performs photoelectric conversion by electron depletion operation, as shown in FIG. 4 (a-1).
(7) n+ floating region 401 (Assume that as a result of ejecting D electrons to the n″I″lJ region 402, the potential of the n+ region 401 changes by ΔV (see FIG. 4 (a-3))
.

When the vertical retrace period (hereinafter abbreviated as V-BLK period) is entered in this state, φG1 becomes the no-y level and the MOI9 switch 208 is turned on. Furthermore, start pulse S
Pv and Clock Tsukurusuφma1. A vertical scanning circuit 203 operating in the φ machine 2 operates at high speed and sequentially transmits signal information from the phototransistors 201 arranged in the vertical direction to the corresponding memory capacitors 212.

Specifically, during the V- and BLK periods, all MOS switches 205 controlled by φG3 are turned on, so the pulses from the vertical scanning circuit 203 are transmitted to the pulse transmission 13 page one-node lines 204 and 206. applied simultaneously.

As a result, vertical MO8 switches 202 and 213 are turned on simultaneously. At this time, the n floating region 401 that constitutes the phototransistor is lowered by ΔV due to electron depletion, and since this is determined by the potential barrier 404 controlled by the holes accumulated in the p floating region 403, the signal The electrons on the transmission lines 207 and 209 are ejected to the n+ region 402 across the potential barrier 404, and the vertical signal line 20? and the potential of 209 and memory capacitor 2
The potential of the 120 needle region 406 is the potential of the phototransistor 2
It corresponds to the potential of n0 floating region 401 of o1 (Fig. 4 (
IL-4)).

After this, at the next timing of φ ma 1, it is necessary to refresh the signal transmission lines 207 and 209, which remain depleted, before transmitting the signal information of another phototransistor 214 to the corresponding memory capacitor 216. be. To do this, vertical MO8 switches 202 and 213
is turned off (FIG. 4 (a-5)'), %φG2 is set to high level, the MOS switch 216 is turned on, and electrons are injected into the signal transmission lines 207 and 209 (the fourth
Figure (!L-6)).

In this way, the signal information of the phototransistors is transmitted to the corresponding memory capacitors one after another during the V-BLK period.

After that, by temporarily setting the voltage Vs applied to the transparent electrode 406 to zero voltage (or negative voltage), the potential of the floating region 401 of all the phototransistors 201 can be returned to the initial setting, and the phototransistor The refresh of 201 is completed (FIG. 4 (IL-7)).

Next, when entering the vertical scanning period, φ also becomes Ov, and MO
Since the S switch 205 is turned off, the vertical scanning circuit 20
The pulse from 3 is not transmitted to the pulse transmission line 206 on the light receiving part side, but is transmitted to the pulse transmission line 20 of the memory capacitor part.
4 only.

Therefore, signal information can be read out from the memory capacitor within the vertical scanning period. The specific operation is as follows: start pulse SPma, clock pulse 16, etc.→・Sφma1. The vertical MO8 switch 213 is turned on by applying a pulse (generated, for example, during the horizontal retrace period of the NT8G signal) to the pulse transmission line 204 from the vertical scanning circuit 203 operating at low speed in the φ motor 2. The depletion voltage ΔV (pin-edge signal voltage) of the depleted capacitor 212 becomes 7vI due to the capacitance distribution between the vertical signal line 209 and the capacitor 212 (FIG. 4 (IL-8)').
. However, since the number of depleted electrons IQ remains unchanged, there is no need to take such changes into consideration when reading out charges.

During the horizontal scanning period, the pulse of the vertical scanning circuit 203 is maintained at pulse transmission M2O4t-high level, and at the same time, the start pulse ISP! +, clock pulse φ! 11. High speed operation with φH2 (if the number of horizontal pixels is about 400, the clock pulse φI11.φ■2 is approximately y
Pulses are sequentially applied to the gates of the horizontal MOS switches 210 from a horizontal scanning circuit 211 (which uses MHz).

At this time, the horizontal MO8 switch 21o is turned on, and the number of electrons NQ=IQ corresponding to the number of depletion electrons IQ distributed in the capacitor 212 and the signal transmission line 209 is injected into the signal transmission line 209 and the capacitor 212 through Rt. Then, a signal voltage based on the number of electrons IQ flowing across the output load resistor 9 appears, and at the same time, the capacitor 212 and the signal transmission line 209
The potential returns to the initial setting value (Fig. 4 (a-2)).

By repeating this operating state, signal information is read from all memory capacitors during the vertical scanning period.

As described above, according to the present invention, by using the SIT type phototransistor as the light receiving part and providing the frame memory part, (1) Refreshing of all the 81 type phototransistors is controlled by the applied voltage v8 of the transparent electrode. can.

(2) Furthermore, by adopting a three-dimensional configuration of the SIT type phototransistor and further introducing a frame memory section, it is extremely advantageous to increase the density of pixels in the light receiving section.

■ The operation of SIT type phototransistor is electron 17.-
7. Since photoelectric conversion is performed using the depletion state, the capacitance connecting the phototransistor and the memory capacitor may be large (it is also possible to provide the frame memory IJ' in the image sensor section).

Moreover, such a combination can be realized for the first time with the present invention.

(2) If a field selection circuit is inserted in the dotted line frame in FIG. 2, interlaced readout, simultaneous two-line readout, etc. can be arbitrarily controlled.

■ Vertical scanning circuit 203 and horizontal scanning circuit 211 in Figure 2
If these are replaced with a vertical selection circuit and a horizontal selection circuit, respectively, random access reading can be realized.

■ Non-destructive readout can be performed many times while the above refresh is stopped, so if you combine it with the random access readout in O above, it becomes an input imaging device for advanced information processing. , various features that could never be obtained with conventional image sensors can be obtained.

In addition, in the present invention, only the photoelectric conversion section has a three-dimensional structure of SI.
Although T-type phototransistors are used, in order to further improve the above-mentioned performance, it is desirable to configure everything with SITs. In particular, if the memory section is an SIT memory, the area required for the memory section can be reduced due to the vertical structure.

Here, it is also possible to change the photoelectric conversion section shown in FIG. 1 to a more optimal structure.

FIG. 6(IL) is a modification of FIG. 1(a), in which the p region 10B is formed on the surface of the n1 region 102 in FIG. 1(a), but in FIG. 6(IL) A p region 10B is formed below the surface of the n+ region 102. This makes it easier to form the high resistance i region.

Furthermore, the potential barrier of the phototransistor is
Since it can also be formed in the p-region 601 inside the phototransistor 2, the effect of the interface with the high-low resistance region 109 of the phototransistor is included in the drift travel region of electrons, and the operation of the potential barrier becomes more stable.

FIG. 6(b) shows another embodiment (hereinafter also referred to as an n+-1-n+ type phototransistor) which is effective as a phototransistor of the present invention.

This method does not use the p region to form the potential barrier of the phototransistor, but insulator regions 503 and 5 with different dielectric constants.
04 (or by implanting impurity ions into the insulator region 604) to form a potential barrier in the insulator region 504.
(This is a means to make the potential barrier that originally occurs even if the dielectric constants of the insulator regions 503 and 504 are equal in FIG. 6(b) more reliable and stable. )°.

Here, Fig. 6>) is the simplest structure of the photoelectric conversion section of the present invention, but the performance of the present invention is that the high resistance region 109 of the photoelectric conversion section is made of an 8i single crystal and a perfect crystal with no defects. It depends largely on whether or not it can be formed smoothly on the surface of the n+ region 102.

In this sense, FIG. 6 shows a typical process for manufacturing the photoelectric conversion section of this device.

That is, as shown in FIG. 6 (IL-1), the p-substrate 10
An n1 region 102 and an n1 region 104 are formed on one surface by diffusion or ion implantation. After this, the table JP-A-58-12
5982(a) surface was thermally oxidized (~1000 μm) to form the first
An insulator region 503 is formed. Subsequently, the gate electrode 10
5 is formed of polysilicon, the surface is thermally oxidized again to form a second insulator region 504, and p is formed by ion implantation or the like.
Shall be type 10.

Next, drill a hole and use aluminum etc. for the signal transmission line 10.
3 and makes contact with the n+ region 104. Thereafter, thermal oxidation is performed again to form a third insulator region 603. On top of this, deposit CVD polysilicon 01 (~10
oOm) and make a hole on the n10 area 102.

Next, as shown in FIG. 6(&-2), when an epitaxial layer is grown, single crystal silicon 602 grows on the n0 region 102, and polysilicon layer 03 grows on the cvn polysilicon layer 01. grows uniformly (this is called silicon-
(referred to as simultaneous polysilicon growth).

Subsequently, as shown in FIG. 6(a, -3,), a laser beam or an energy beam is irradiated from above to turn the polygon 21 base silicon regions 601 and 603 into single crystal silicon using the single crystal silicon region 602 as a core. On the other hand, a high resistance region 604 of single crystal silicon is formed over the entire surface of the insulator region 603.

After this, if n0 regions and transparent electrodes are formed on the surface in order,
A phototransistor structure shown in FIG. 6(b) is completed.

As described above, the photoelectric conversion section used in the first embodiment of the solid-state image sensor of the present invention can have a three-dimensional structure with high density. However, with the circuit configuration shown in FIG. It has the disadvantage of being large.

This occupied area can be significantly reduced in size by using a vertically structured SIT, that is, a circuit configuration that fully utilizes a three-dimensional structure. Such an embodiment will be explained using FIGS. 7 and 8.

The fundamental difference in configuration compared to the first embodiment shown in FIG. 2 is that the SIT phototransistor 2
The vertical MO8 switch for selecting the signal information of 01 is no longer required, and the vertical scanning circuit 203 does not need to operate at high speed during the V-BLK period. The MOS switch 216 controlled by φG2 for resetting is no longer necessary.

Furthermore, since all elements are configured with SIT, a MOS switch 213 for reading signal information of the capacitor 212 is provided.
is now an SIT switch 213', and the MOS switch 210, which is controlled by a pulse from the horizontal scanning circuit 211 to reset the capacitor 212 and signal transmission line 209, is now an SIT switch 210'.

Furthermore, when the MOS switch 208 controlled by φG1 changes to a 191T switch 208' for directly transmitting signal information from the phototransistor 2o1 to the capacitor 212, and as a result, -1 becomes high level during the V-BLK period. , SIT switches 208' are all turned on, and the transmission of signal information is completed while the electron depletion state of all phototransistors 201 turns the corresponding capacitor 212 into an electron depletion state. Thereafter, the manner in which the signal is read out from capacitor 212 is similar to that of FIG.

As described above, in the second embodiment shown in FIG. 7, not only the configuration of the circuit 23 but also the operation itself is simplified.

The cross-sectional structure of the 1-bit pixel portion of this second embodiment is shown in the eighth example.
As shown in the figure.

FIG. 8(IL) shows a cross-sectional structure, and FIG. 8(b) shows a top view.

According to FIG. 8 (IL), transparent electrode 801. n ten area 8o2. An insulator region 80 that forms a high-low antibiotic region 803 and insulates and isolates each pixel on the high-resistance i region 803
4 is surrounded by p region 805. An n+ region 806 is formed (the above is a photoelectric conversion portion corresponding to the structure shown in FIG. 1, and is also a p, n+ pin type phototransistor 201).

Above this, that is, on the insulator region 804, a "region 808" is formed on the p region 807゜n÷area aoe which becomes the gate of the SIT switch 213', and further on this is surrounded by an insulator region 809. Needle area 810・'Area 8
11 is formed, and an n+ region 813 surrounded by a p region 812 serving as a gate is formed on the surface of the region 811. Among these, n0 area 806 to n- area 8o8 to n0 area 810
~p region 80a is SIT switch 2 controlled by Kay 1
08', n10 areas 810 to n- areas 811 to n
The ten area 813 to the p area 812 are the SIT switch 213'
Configure.

According to the embodiment of the cylinder 2 described above, in addition to the features of the first embodiment, (1) a thorough adoption of a three-dimensional structure makes it possible to achieve even higher density and to simplify the drive system.

■ Since the signal information of all phototransistors can be simultaneously transmitted to the corresponding memory, it can also function as an ideal electronic shutter (in this case,
vs)・The time to level out corresponds to the shutter opening time).

As described above, according to the present invention, by combining an SIT phototransistor with a stacked structure and a frame memory, it is possible to realize high density SIT phototransistors, which was previously considered impossible. By adopting a thorough three-dimensional structure, an ideal electronic shutter function can be achieved.

In addition, by using SXT, blue 25 and high sensitivity can be achieved.
Of course, it is ensured that nomink occurs (this is essentially non-occurrence in the case of electron depletion operation), and furthermore, non-destructive readout and random access are easy, so the information processing function of the image can be improved. It is also possible to prepare.

Therefore, according to the present invention, a television camera, an electronic still camera, 2. A wide range of applications can be considered, such as optical sensors for information processing.

In the above embodiment, an n-channel 4-channel MOS and an n-channel 8IT are used, but the same applies to a p-channel MO8 and a p-channel SIT.

Furthermore, it goes without saying that the substrate material is not limited to Si, but also CaAs or the like.

[Brief explanation of drawings]

Figure 1' r (b-1) y (b-2) t
(b 3) is a cross-sectional structural diagram and an equivalent circuit diagram of the photoelectric conversion section of the solid-state imaging device in the first embodiment of the present invention, 'l5
2 is a circuit diagram of the solid-state imaging device, FIG. 3 is a timing chart of drive pulses used in the device, and FIG. -1) to (a-8) are equivalent circuit diagrams and potential model diagrams showing the operation of the device, Figure 6 a, b
6(z1))(a-2L(L-3) is a sectional view showing the manufacturing process of the photoelectric conversion unit, and FIG. is an equivalent circuit diagram of a solid-state imaging device according to a second embodiment of the present invention,
Figure 8a. b is a cross-sectional structural diagram and a top view of the solid-state image sensor. 1o1...p substrate, 1o2...-n10 area, 103...signal transmission line, 1o4...
・n+a region, 106...gate electrode, 106・
...MOS switch, 107 insulator area, 1o8
...p region, 109...high resistance region,
110...n10 area, 111...transparent electrode, 201...SIT type phototransistor, 202...vertical MOS switch, 2o3...
...Vertical shift register, 2o4...Pulse transmission line, 205...MOS switch, 206
...Pulse transmission line, 207...Signal transmission line, 2o8...MOS switch, 209...
...Signal transmission line, 210...Horizontal MOS switch 27 base switch, 211...Horizontal scanning circuit, 212,2
15... Capacitor, 213... Vertical MOS switch, 216... MOS switch. Name of agent: Patent attorney Toshio Nakao and one other person JP-A-58-125982 (8) f/s 1 Figure 4! ! I 5 Figure

Claims (1)

[Claims] (1) Phototransistors that are arranged in two dimensions and perform photoelectric conversion by working through the depletion operation of majority carriers, and capacitors that are arranged in two dimensions corresponding to the phototransistors to temporarily store signal changes of the phototransistors. A solid-state imaging device comprising: a signal transmission means for connecting the phototransistor and the capacitor; and a signal readout means for outputting a signal change temporarily stored in the capacitor to the outside. @) The first method in which the signal transmission means selects a phototransistor
the first switch means and the second switch means, a second switch means for selecting a capacitor, and a signal transmission line connecting the first switch means and the second switch means. Claim No. 3, characterized in that the switch means is opened and closed for each horizontal line.
1) The solid-state imaging device described in section 1). ('4) The transmission means is a third switch means provided between a phototransistor and a capacitor, and the third switch means is opened and closed at the same time. The solid-state imaging device described in (1).