JP2556885B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device in which a volatile semiconductor memory device, a nonvolatile semiconductor memory device and a photodiode are combined.

<Prior Art> A CCD element is a semiconductor device that converts an optical signal into an electrical signal.

In a CCD element, a photodiode matrix is irradiated with an optical signal, and the charges collected in the diode matrix are transmitted by a register using a charge-coupled device and appear as a current or voltage pulse at an output terminal.

<Problems to be Solved by the Invention> However, the above-mentioned CCD device has a problem in that it cannot store data.

<Means and Actions for Solving the Problems> In the present invention, in order to solve the above-mentioned problems, a volatile semiconductor memory device, a non-volatile semiconductor memory device, and a photodiode are combined, and the photodiode is irradiated. By converting the optical signal into an electric signal and transferring and storing the data in the non-volatile semiconductor memory device, the data is stored and held without a battery backup.

<Example> A DRAM is used as an example of a volatile semiconductor memory device, an EEPROM is used as an example of a nonvolatile semiconductor memory device, and a PN junction formed on a P-type Si substrate is used as an example of a photodiode. A circuit diagram is shown in FIG. 1 and a sectional view thereof is shown in FIG.

Since the EEPROM, DRAM, and photodiode are all manufactured by MOS technology, they are easy to manufacture, and DRAM has the advantage that the number of elements required for one memory cell is the smallest.

In FIG. 1, three MOS transistors MT ₁ , MT ₂ and
MT ₃ is formed in series on a semiconductor substrate. In the actual memory, many combinations are arranged, but for convenience, the part that operates as one unit is taken out. At the intermediate point 4 between the MOS transistor MT ₁ and the MOS transistor MT ₂ ,
The capacitive element C is connected and a predetermined voltage is applied from the terminal 5. The terminal 1 of the MOS transistor MT ₁ is usually the n-layer of the semiconductor substrate and is connected to the column line of the memory, and its gate G ₁
3 is connected to the row line of the memory. The MOS transistor MT ₂ constitutes an EEPROM by providing a floating gate 6 below the normal control gate G ₂ . MOS transistor MT
Reference numeral ₃ is a mode switching transistor for whether this memory operates as an EEPROM or a DRAM, and a voltage is applied from a terminal 7 to its gate G ₃ and the gate G ₂ of the MOS transistor MT _2. It is supposed to be done. MO
The terminal 2 of the S-transistor MT ₃ becomes the n-layer of the semiconductor substrate.
One of the terminals 1 and 2 is on the drain side and the other is on the source side. In the capacitive element C, the diffusion layer 4 of the semiconductor substrate can be used as one electrode, and the polysilicon film provided through the oxide film can be used as the other electrode CG. Diffusion layer (n layer)
A PN junction photodiode PD is formed between 4 and the P-type Si substrate 8.

 Such a device operates as follows.

(1) Initialization Before starting the operation, a positive voltage is applied to the terminal 7 to accumulate charges in the floating gate 6 of the MOS transistor MT ₂ (the charge at this time is defined as Q _F ).

Before irradiating the photodiode PD with light, positive charges are accumulated in the n-type diffusion layer 4 of the photodiode PD (DRAM
Data “1” state). This is because the terminals 5 and 7 are grounded, the MOS transistor MT ₃ is turned off, and then the voltage V _CC is applied to the terminal 1 of the drain portion of the MOS transistor MT ₁ to turn this transistor on. By doing. The charge Q _C accumulated in the capacitive element C (referred to as the capacitance C _C ) is Q _C = C _C V _CC .

(2) Light irradiation to the photodiode When the photodiode PD is irradiated with light, the P-type Si substrate 8
Minority carrier electrons generated at the n-type diffusion layer 4 gather,
The holes accumulated in the initial setting are recombined, and the n-type diffusion layer 4
Has no positive charge (DRAM data “0” state).

By irradiating the photodiode with light by the above method, the DRAM data is converted from "1" to "0", so that an optical signal can be converted into an electrical signal.

FIG. 3 is an equivalent circuit diagram when the optical signal of the photodiode is converted into an electric signal by the DRAM.

(3) Data transfer from DRAM to EEPROM Figure 4 shows the equivalent circuit for transferring the data stored in the DRAM to the EEPROM.

Charge in the capacitor C Q _C, the charge in the floating gate 6
When voltage V ₅ is applied to terminal 5 while Q _F is accumulated, C _L (V _F −V ₄ ) + C _H V _F = Q _F …… (1) C _C (V ₄ −V ₅ ) + C _L (V ₄ −V _F ) = Q _C (2) where C _C : capacitance of capacitive element C _L : capacitance between floating gate 6 and substrate C _H : floating gate 6 and control gate G ₂ Capacitance V ₄ : Potential of terminal 4 V ₅ : Voltage of terminal 5 V _F : Potential of floating gate 6 Q _C : Charge stored in capacitive element C Q _F : Charge stored in floating gate 6 (1 ), (2) From the floating gate 6,
The voltage V applied between the capacitive element and the diffusion layer forming one electrode of the capacitive element is expressed by the following equation.

By the way, in the above initial setting, the electric charge of Q _F = −C _H · ΔV _TH (4) is accumulated.

ΔV _TH : Shift value of the threshold value of the MOS transistor MT ₂ due to the charge accumulated in the floating gate in the initial setting. Also, by applying V _CC to the capacitive element C, Q _C = C _C V _CC ...... (5 ) Charges are accumulated.

From equations (3), (4) and (5) The current density J _F injected into the floating gate 6 is
Determined by the electric field E _OX applied between the floating gate 6 and the diffusion region of the semiconductor substrate, J _F = AE _OX ² e × p (−B / E _OX ) (7). A and B are constants.

Is represented by Here, t _OX is the thickness of the thin oxide film between the floating gate 6 and the diffusion region.

E _OX of the state in which the charge Q _C = C _C V _CC is accumulated and the state in which the charge C _C V _CC is not accumulated (Q _C = 0) are respectively E
_{If OX1} , E _OX0 , Is represented by

When holes are injected into the floating gate 6 by applying the voltage V ₅ to the terminal 5 of the electrode CG of the capacitor C, and when the charge Q _C = C _C V _CC is accumulated in the capacitor C, ΔE shown in Eq. (9) is better than that in the non-accumulated state
Holes will be injected by an electric field that is strong only by _OX .

When the thickness of the thin oxide film for the hole injection between the floating gate 6 and the diffusion layer 4 and t _OX, t _OX in Example _{= 80Å C C = 50fF C H} = 158fF C L = It is assumed that 9.2fF V _CC = 5V.

At this time, each numerical value is put into the equation (9), and ΔE _OX
ΔE _OX = 3.54 (MV / cm), and J _F1 is the current density flowing in the floating gate 6 when the electric field applied between the floating gate 6 and the diffusion layer 4 is E _OX1 and E _OX0. , J _F0 , J _F1 / J _F0 ≈10 ⁷ and the electric charge is accumulated in the capacitive element C (Q _C =
In the C _C V _CC ) state, no charge is accumulated (Q _C = 0)
It can be seen that a large amount of positive charges are accumulated in the floating gate 6 as compared with the state.

In this embodiment, the control gate G ₂ of the MOS transistor MT ₂ is grounded and the voltage V ₅ is applied to one electrode CG of the capacitive element C. However, one electrode CG of the capacitive element C is grounded and the terminal 7 is connected to the terminal 7. The same can be done by applying a voltage.

As described above, by applying the voltage to the terminal 5 or the terminal 7 with respect to the data accumulated in the capacitive element C,
The data stored in the floating gate 6 can be transferred as data. That is, the optical signal given to the photodiode can be stored in the EEPROM.

Even if a large number of storage elements with the above-mentioned configuration are connected, by applying a voltage to the common terminal 5 or 7, all the large-capacity data accumulated as DRAM is transferred at once to the EEPROM at a high speed. can do. The EEPROM data is discriminated by the magnitude of the channel current of the MOS transistor MT ₂ or the change of the gate threshold voltage seen from the control gate G.

<Effects of the Invention> As described in detail above, according to the present invention, storing and holding an optical signal as an electrical signal without a battery backup is a semiconductor device of a smaller size than a conventional semiconductor device. Can be done at.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a sectional view of an embodiment of the present invention, and FIG. 3 is an equivalent circuit when an optical signal of a photodiode is converted into an electric signal by a DRAM. Figure, 4th
The figure is an equivalent circuit diagram when transferring data from DRAM to EEPROM. Explanation of symbols MT ₁ , MT ₂ , MT ₃ ... MOS transistors, G ₁ , G ₂ , G ₃ ... control gate, C ... capacitive element, PD ... photodiode, 4 ...
... n-type diffusion layer, 6 ... floating gate, 8 ... P
Type Si substrate.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792 31/10

Claims (1)

(57) [Claims] 1. A photodiode, a volatile memory element for storing an electrical signal corresponding to an optical signal applied to the photodiode, the volatile memory element including a capacitive element and a first MOS transistor, and a floating state on a semiconductor substrate. A non-volatile memory element having a gate and a control gate formed on the floating gate, a second MOS type transistor for switching the mode of the semiconductor device, and data for transferring the data of the volatile memory element to the non-volatile memory element. A voltage applying unit, the photodiode comprises the semiconductor substrate and a diffusion layer formed on the semiconductor substrate, and the volatile memory element includes the nonvolatile memory element in the diffusion layer. Is electrically connected, one electrode of the capacitive element is formed of the diffusion layer, and Memory element, semiconductor device, characterized in that said floating gate is formed so as to face each other with a tunnel insulating film on the diffusion layer.