JPS6378567A - Image sensor - Google Patents

Abstract

PURPOSE:To assure the simultaneousness with incident light and the reduction in production cost by a method wherein outputs from respective photodiodes are once transmitted to respective memory capacitors to be read out successively later. CONSTITUTION:When a precharging power supply terminal 5 is held at specified charging voltage; respective switching MOS transistors 6, 9 are turned on; and after charging respective junction capacitors 8 and respective memory capacitors 10, said transistors 6, 9 are turned off; and after exposure for specified time, the transistors 9 are turned on; the junction capacitors 8 discharged corresponding to the incident light quantity from memory capacitors 10 are charged up to equivalent potential. Later when the transistors 9 are turned off, respective outputs from respective photodiodes 12 are to be transferred to respective memory capacitors 10. Finally, switching MOS transistors 11 are successively turned on by a shift register 1 to read out the outputs by charging current etc. from an output terminal 2 to the memory capacitors 10.

Description

[Detailed description of the invention] [Industrial use! 7] The present invention relates to a MOS image sensor capable of achieving simultaneity with respect to incident light.

[Prior Art] As a conventional MOS image sensor, one shown in FIG. 3, for example, is known.

In FIG. 3, 12 is a photodiode, and this photodiode 12 has a junction diode 7 and a junction capacitance 8.
is equivalently shown as a parallel circuit.

The photodiode 12 constitutes a part of the switching MOS transistor 11, and the switching MOS transistor 11 is connected in parallel to the shift register l. Further, 2 in the figure indicates an output terminal of the switching MOS transistor 11.

The conventional example configured in this manner operates as follows.

First, by holding the output terminal 2 at a predetermined voltage VP and turning on the switching MO5)-transistor 11, the junction capacitance 8 of the photodiode 12 is set to a predetermined voltage VP.
Charge up to. After charging is completed, when the switching MOS transistor 11 is turned off, the electric charge charged in the junction capacitor 8 starts discharging according to the amount of incident light. In this state, after allowing the head to open for a certain period of time, the switching MOS)
The transistor 11 is turned on and the junction capacitance 8 is charged again to the predetermined voltage VP. At this time, the amount of charge supplied from the output terminal 2 becomes the output signal.

By sequentially repeating the above operations for each pixel using the shift register 1, the output of each pixel can be obtained as a time-series signal.

[Problem that this invention attempts to solve] However,
In such a conventional image sensor, since each output of a photodiode corresponding to each pixel is read out sequentially, synchronization with respect to incident light cannot be obtained.

On the other hand, in a CCD image sensor, the output of each pixel is simultaneously transmitted to the CCD shift register and then read out, so it is important to know whether synchronization with respect to incident light can be achieved or not.
Compared to iCCD type image sensor image sensor,
There are problems in that the manufacturing process is complicated, the manufacturing cost is high, and the peripheral circuitry of the image sensor is also complicated.

As described above, using a MOS image sensor has the disadvantage that the output of each pixel cannot be synchronized with the incident light, and using a CCD image sensor to achieve synchronization increases the cost. However, the drawback was that the peripheral circuitry became complicated.

[Means for Solving the Problems] The present invention has been made in view of the above-mentioned problems in the prior art. The purpose is to provide an image sensor with

In order to achieve this object, the present invention includes a plurality of photodiodes having a junction capacitance formed of a diffusion layer on a semiconductor substrate, and a plurality of memories each having a diffusion layer provided adjacent to each of the junction capacitances. A memory capacitor can be connected in parallel to a junction capacitor provided between both capacitors, and each output of the photodiode is transmitted to the memory capacitor.Therefore, a plurality of switching elements and each output transmitted to the memory capacitor are connected. It includes a plurality of switching elements for sequential reading and a shift register for driving the switching elements.

[Function] In the present invention having such a configuration, each output of each photodiode is connected to - through a switching element.
transmitted to the carrier memory capacity. After that, the transmitted output turns on the switching element by the shift register,
The 111th order is read from the output terminal. therefore,
MOS without using an expensive CCD image sensor
Simultaneity with respect to incident light can be obtained using a type image sensor.

[Example] Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 and FIG. 2 are diagrams showing one embodiment of the present invention.

First, to explain the structure, in FIG. 2, reference numeral 13 denotes a P-type substrate, and an N'''' diffusion layer 12A is formed on this P-type substrate 13 to constitute the photodiode 12.
A diffusion layer 6A is formed to constitute a source of a switching MOS transistor (switching element) 6. Further, an oxide film 15 made of 5ift is formed on the surface of the P multi-layer substrate 8, and a source electrode 6 is further formed on the oxide film 15.
B to the source, and the diffusion layer 12A and the diffusion layer 6
A gate electrode 6C of a switching MOS transistor is formed between the transistor A and the gate electrode 6C. 5 is a power supply terminal (source terminal) for precharging connected to the source electrode 6B, and 4 is a gate terminal connected to the gate electrode 6C.

On the other hand, an N'' diffusion layer 10 of the same size is placed adjacent to the diffusion layer 12A constituting the diode 12 on the P multilayer substrate 13.
A is formed to constitute the memory capacitor 10, and a gate TL pole 9A of the switching MO5)-transistor (switching element) 9 is formed between the inner diffusion layers 10A and 12A. 3 is a gate terminal connected to the gate electrode 9A. In addition, the diffusion layer 1 constituting the memory capacity 10
An N9 diffusion layer 11A is formed on the P-multilayer substrate 13 adjacent to 0A to constitute a source of a switching MOS)-transistor (switching element) 11, and is connected to this source to take out a signal connected to the output terminal 2. Source electrode 1 between
1B is formed. A gate electrode 11G of the switching MO3) transistor 11 is formed between the diffusion layer 11A and the diffusion layer 10A, and the gate terminal 11A is connected to the gate electrode 11C. Also, 14.

This is a light-shielding film formed to cover the oxidized lA15, gate electrodes IIC, 9A, 6C, and source electrodes 11B, 6B, and an opening 14A is formed in this light-shielding W214. The incident light enters only the photodiode 12 through the aperture 14A, and the diffusion layer 1 constituting the memory capacitor 10
It is made so that it does not enter 0A.

Figure 1 shows an equivalent circuit of the cross-sectional structure of one pixel shown in Figure 2, and also shows the circuit configuration of all pixels.
The diode 12 composed of 2A is shown as a parallel circuit of a junction diode 7 and a junction capacitance 8, and the diffusion layer 10A
are each shown as a memory capacity of 10. Here,
The junction capacitance 8 and the memory capacitance lO are configured to have the same capacitance, or they do not necessarily have to be the same capacitance of 5B.
A switching MOS transistor 9 is connected to the switching MOS transistor 9, and all outputs of the diode 2 are transmitted to the memory capacitor 110 via this switching MOS transistor 9. Furthermore, a switching MOS transistor 11 is connected between the memory capacity l 10 and the shift register l, and by turning on the switching MOS transistor 11 by the shift register 2, the memory capacity 10 is transferred from the output terminal 2. The transmitted outputs are read out sequentially. (Switching MOS)
- A switching MOS) - transistor is connected to the transistor 9 via a tie auto 12, and both transistors 6 and 9 are turned on from the power supply terminal 5 of the switching MO 3) - transistor to increase the junction capacitance 8 and the memory capacity 10. and is charged to a predetermined voltage VP.

Next, the operation will be explained.

First, connect the power supply terminal 5 for charging to a predetermined charging voltage vP.
, each switching MOS)-transistor and each switching MOS transistor 9 are turned on, and each junction capacitor 8 and each memory capacitor 10 are charged to a predetermined voltage vP. When charging is completed, each switching MO3) transistor and each switching MOS transistor 9 are turned off.

After the precharging is completed, the charge charged in each junction capacitor 8 is discharged according to the amount of incident light, and either the charging voltage decreases from the predetermined voltage vP, or the charging voltage of the memory capacitor IO is maintained at the predetermined voltage vP. Ru.

After exposure for a certain period of time, each switching MO3)
- When the transistor 9 is turned on 71, the memory capacity is 10
The junction table &8 is charged with electric charge, and becomes stable when the potentials of both become equal. For example, assume that the capacitance of the memory capacitor 10 and the junction capacitor 8 are equal, and that the charging voltage of the junction capacitor 8 or the incident light changes it from a predetermined value -HfJEvp to a certain voltage V.

It becomes stable when the potential reaches (VP+V)/2. After the potential is stabilized in this way, each switching MO3)-
When the transistor 9 is turned off, all outputs from each photodiode are transmitted to each memory capacity 10.

When the transmission to memory capacity jl 10 is completed, switching MO3)-transistor 11 is performed by shift register l.
are sequentially turned on, and the memory capacity i1 from output terminal 2 is
Charging to 0 1 (Reading the output using i-stream, etc.)

After reading out all pixels, repeating the process from precharging again operates as an image sensor.

As mentioned above, this image sensor is manufactured using exactly the same process as a normal MO3 type image sensor, so even though the manufacturing cost is low, it is possible to simultaneously send each output to each odd diode to each memory capacity lO Since each transmitted output is read out one term at a time, simultaneity with respect to the incident light can be obtained.

[Effects of the Invention] As explained above, according to the present invention, the output of each photodiode is transmitted to each memory capacity, and then the transmitted outputs are sequentially read out, so that the CCD
Even without using a CCD type image sensor, the MO3 type image sensor can provide uniformity with respect to incident light, and the manufacturing cost can be reduced compared to a CCD type image sensor.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a cross-sectional structure of one pixel, and FIG. 3 is a circuit diagram showing a conventional example. l...Shift register, 2...Output terminal, 3゜4, IIA...Gate terminal, 5...Precharge power supply terminal, 6. ．． 9.11...Switching M
OS transistor, 6B, IIB...source electrode,
6C, 9A, I IC...Gate electrode, 7...
Junction diode, 8... Junction capacitance, 6A. 10A, IIA, 12A...diffusion layer, 13...middle silicon substrate, 14...light shielding film, 14A...opening portion, 15...silicon oxide film.

Claims (1)

[Claims] A plurality of photodiodes each having a junction capacitor formed of a diffusion layer on a semiconductor substrate, a plurality of memory capacitors each having a diffusion layer provided adjacent to each of the junction capacitors, and a junction provided between the two capacitors. a plurality of switching elements capable of connecting memory capacitors in parallel to the capacitors and transmitting each output of the photodiode to the memory capacitor; and a plurality of switching elements for sequentially reading each output transmitted to the memory capacitor; An image sensor comprising: a shift register for driving a switching element.