JPS63128666A - Photoelectric converter - Google Patents

Abstract

PURPOSE:To increase a current amplification factor, to obtain a high output as well as to significantly improve a driving power by means of a Darlington connection of a transistor A and a transistor B, which are photoelectric conversion parts. CONSTITUTION:A p<-> base region 9 is formed in an n<-> region 4, a capacitor electrode 14 and an n<+> emitter region 15 are formed and a bipolar transistor A which performs photoelectric conversion is constituted. Moreover, a p<-> base region 22, which is formed along with the p<-> base region 9 in the same process, is electrically connected to the n<+> emitter region 15 through a wiring 24 for ohmic-contacting. An n<+> emitter region 25 is formed in the p<-> base region 22 and an emitter electrode 19 is connected to the n<+> emitter region 25. In such a way, a bipolar transistor B having a darlington connection with the transistor A is constituted. Moreover, a transistor Qrh for refresh is constituted using a p<+> region 28 formed at the end part of the p<-> base region 22 and a p<+> region 29 formed in the n<-> region 4 as its source and drain regions and using an electrode 32 as its gate electrode.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a photoelectric conversion device that accumulates carriers excited by light in the control electrode region of a transistor, and particularly relates to a photoelectric conversion device that has high output and high speed operation. The present invention relates to a contemplated photoelectric conversion device.

[Prior Art] FIG. 8(A) is a schematic plan view of a conventional photoelectric conversion device;
Figure 8 CB) shows one of the σ photoelectric conversion cells A-A'
The line sectional view, FIG. 8(C), is an equivalent circuit diagram thereof.

In FIGS. 8(A) and (B), n silicon substrate l
An n-epitaxial layer 4 is formed thereon, and photoelectric conversion cells electrically insulated from each other by element isolation regions 6 are arranged therein.

First, the p base region 9 of the bipolar transistor is placed on the n-epitaxial layer 4. Therein n ten emitter regions 15
is formed. Further, a capacitor electrode 14 for controlling the potential of the p base region 9 is provided on both sides of the oxide film 12.
, n0 emitter electrode 1 connected to emitter region l5
9 are formed respectively.

An electrode 17 connected to the capacitor electrode 14, an n''i region 2 for ohmic contact, and a collector electrode 21 of a bipolar transistor are formed on the back surface of the substrate 1, thereby forming a photoelectric conversion cell.

The basic operation of the photoelectric conversion cell is to first put the p base region 9 biased to a negative potential into a floating state, and accumulate holes in the p base region 9 among electron self-hole pairs generated by photoexcitation (accumulation operation).

Subsequently, a positive voltage is applied to the capacitor electrode 14 to forward bias between the emitter and the base, and the accumulated voltage generated by the accumulated holes is read out to the floating emitter side (read operation).

Subsequently, the emitter side is grounded and a positive voltage pulse is applied to the capacitor electrode 14 to eliminate the holes accumulated in the p base region 9. As a result, p base region 9 returns to its initial state at the time when the positive voltage pulse for refreshing falls (refresh operation).

This type of photoelectric conversion device has a current amplification function using bipolar transistors, so it has a high driving tFa power, and since it is structurally simple, it is also advantageous for future high resolution. be.

[Problem to be Solved by the Invention 1] Incidentally, as the number of cells increases due to high integration, the wiring capacitance increases, and a photoelectric conversion device is required to have an even higher ability to drive a capacitive load.

FIG. 9(A) is an explanatory diagram of the driving capacity of the conventional example, FIG.
B) is a voltage waveform diagram showing driving ability.

First, it is assumed that carriers due to photoexcitation are accumulated in the p base region 9 of the photoelectric conversion cell. When a positive voltage Vr is applied to the capacitor electrode 17 in this state and a read operation is performed, a current i flows between the collector and emitter and charges the capacitor C. As a result, the output voltage Vout increases, and an output voltage corresponding to the accumulated potential of the base is obtained.

However, when the capacitive load C increases due to an increase in wiring capacitance, etc., the output voltage Vout
rises slowly, making high-speed operation impossible.

To solve this problem, it is possible to improve the drive capability of the photoelectric conversion device, but in conventional photoelectric conversion devices, the drive capability decreases due to the reduction in the emitter area due to high integration, so high-speed operation is required. The problem was that it could not be achieved.

[Means for Solving the Problems] A photoelectric conversion device according to the present invention is comprised of first and second main electrode regions Al and A2 of one conductivity type semiconductor and a control electrode region A3 of an opposite conductivity type semiconductor. A transistor A accumulates carriers generated by photoexcitation in the control electrode region A3 by controlling the potential of the electrode region A3, and third and fourth main electrode regions Bl and B2 of one conductivity type semiconductor are of the opposite conductivity type. The main electrode region B2 is connected to the main electrode region A2, and the control electrode region B3 is connected to the main electrode region AI.

[Operation] By connecting the transistors A and B in a Darlington manner as described above, the current amplification factor becomes extremely large, and the driving capability can be significantly improved compared to the conventional one. As a result, even if capacitive loads such as wiring capacitance increase due to high integration, an output with good rise characteristics can be obtained, and high-speed operation is possible even with high integration.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1(A) shows the 17th photoelectric conversion device according to the present invention!
FIG. 1B, which is a schematic cross-sectional configuration diagram of the embodiment, is an equivalent circuit diagram of one of the cells. However, parts having the same functions as those of the conventional example are given the same numbers to simplify the explanation.

In the figure (A), a p base region 9 is formed in the n- region 4 and faces a capacitor electrode 14 with an oxide film 12 in between. Further, an n+ emitter region 15 is formed in the p base region 9, and constitutes a bipolar transistor A that performs photoelectric conversion as described above.

Furthermore, p base region 22 is formed in the same process as p base region 9.
is formed, and the p space region 22 is electrically connected to the n0 emitter region 15 by a wiring 24 with a P0 region 23 for ohmic contact interposed therebetween. Further, an n10 em-2 emitter region 25 is formed in the p base region 22,
An emitter electrode 19 is connected. In this way, bipolar transistor B is connected to transistor A by Darlington.
is configured.

In addition, p + region 2 formed at the end of p base region 22
A refresh transistor Qrh is constructed by using the transistor 8 and the p+ region 29 formed in the n- region 4 as a source/drain region, and using the electrode 32 formed with the oxide film 12 in between as a gate electrode. Note that a constant voltage is applied to the electrode 33 formed in connection with the p+ region 29.

Such a Darlington-connected photoelectric conversion cell has an amplification factor approximately equal to the product of the current amplification factors of transistors A and B, and its ability to drive a capacitive load is improved several hundred to several thousand times compared to the conventional one.

FIG. 2(A) is a basic drive circuit diagram of this embodiment.
Figure (B) is a timing chart for explaining the operation.

In FIG. 2A, a positive voltage control pulse Vr is applied to the capacitor electrode 17 of the photoelectric conversion cell S, and the emitter electrode 19 is grounded via the transistor Qvc. A constant voltage V is applied to the electrode 33 of the transistor Qrh.
rh is applied, and a pulse φrh is applied to the gate electrode 32. Further, a pulse φVC is applied to the gate electrode of the transistor QVC.

A storage capacitor C is further connected to the emitter electrode 19, and the capacitor C is connected to the output amplifier A.

In such a configuration, refresh, storage, and read operations can be performed by applying pulses at the timing shown in FIG. 4B.

First, the transistor Qrh is turned ON by the pulse φrh, the p base region 22 is set to the voltage Vrh, and the pulse φrh is set to the voltage Vrh.
The transistor Q VC is turned on by VC, and the emitter electrode 19 of the photoelectric conversion cell S is grounded. Then, by applying a refresh pulse φrc to the capacitor electrode 17, a refresh operation of the transistor A is performed. When this refresh operation is completed, the transistor Qrh is turned off.
Then, the p base region 22 of the transistor Qrh is at a constant voltage Vrh. In this state, the emitter electrode 19 is continued to be grounded, and the refresh operation of the transistor B is performed.

Subsequently, after performing an accumulation operation, a read pulse φr is applied to perform a read operation. During the read operation, the transistor Q
rh is OFF.

As already mentioned, since this embodiment uses the Darlington connection, a large output can be obtained, and even a capacitor C having a large capacity can be charged in a short time. Therefore, it is possible to obtain the output signal Vout with good rise characteristics as shown in FIG. 2B, and to achieve high-speed readout by shortening the pulse width of the readout pulse φr.

FIG. 3 is a schematic circuit diagram of a line sensor using this embodiment.

In the figure, a constant positive voltage Vcc is applied to each collector electrode 21 of the photoelectric conversion cells S1 to Sn shown in FIG. A control pulse Vr for performing a read operation and a refresh operation is applied to each capacitor electrode 17.

Further, each emitter electrode 19 is connected to the vertical lines L1 to Ln, respectively, and the vertical lines L1 to Ln are connected to the capacitors 01 to Cn via transfer transistors Tal to Tan, respectively. A pulse φa is applied to the gate electrodes of the transistors T a 1 to Tan.

Further, the gate electrodes 32 of the refresh transistors Qrh of each cell 31 to Sn are connected in common and the pulse φrh
is applied, and a constant voltage Vrh is applied to each 'IM and pole 33.

Furthermore, capacitors 01 to Cn are each transistor T1
~Tn to the output line 103. The gate electrodes of the transistors T1 to Tn are respectively connected to parallel output terminals of the shift register, and pulses φh1 to φhn are sequentially outputted from the parallel output terminals.

The output line 103 is grounded via a transistor Tr for refreshing the output line 103.

A pulse φr2 is applied to the gate electrode of the transistor Tr.

Further, the vertical lines L1 to Ln are grounded via refresh transistors QVt to Qvn, respectively. A pulse φVC is applied to the gate electrodes of the transistors QV1 to Qvn.

Next, the operation of the above line sensor will be explained.

FIG. 4 is a timing chart for explaining the operation of the line sensor.

First, it is assumed that carriers corresponding to the illuminance of incident light are accumulated in each photoelectric conversion cell S1"Sn. In this state, the transistor Qrh of each cell is turned off,
Turn on transistors Tal to Tan by pulse φa
, transistors Qvr to Qvn are turned off by a small pulse VC, the emitter electrode 19 is placed in a floating state, and a positive voltage pulse φr for reading IEL is applied to the capacitor electrode 17. By this, as already mentioned, the vertical line L
High output signals of each cell are read out from 1 to Ln, and each signal is stored in capacitors 01 to Cn.

Next, transistors Ta1 to Tan are turned off, and pulses φh1 to φhn are output from the shift register.
Transistors T1 to Tn are turned ON one after another. As a result, each signal stored in the capacitors 01 to Cn is sequentially read out to the output line 103 and outputted to the outside through the amplifier 104 as an output signal Vout. that time,
Every time each signal is output, the transistor Tr is turned on by the pulse φr2, and the previous residual carriers on the output line 103 are removed.

In parallel with such an output operation, the transistor Qrh of each cell is turned on by the pulse φrh, and the pulse φrh is turned on by the pulse φrh.
Transistors Qv1 to Qvn are turned on by VC, and the emitter electrode 19 is grounded. Then, as described above, the refresh pulse φrc performs the refresh operation of the transistor A, and then the transistor Q r
Transistor A performs a refresh operation by turning OFF h, and when transistor A finishes its refresh operation, it starts an accumulation operation, and the read, refresh, and accumulation operations are repeated in the same manner.

If such a line sensor is constructed with a long length.

The output line 103 becomes longer and the wiring capacitance increases.

For this reason, in conventional photoelectric conversion cells, the output rise time is long, but with this example, high output can be obtained, so even if the wiring capacitance becomes large, the output signal rises in a short time. High-speed reading becomes possible.

Further, in the case of an area sensor in which cells S1 to Sn are arranged in multiple rows, the wiring capacitance of the vertical lines L1 to Ln itself becomes large, but even in such a case, according to the present embodiment, High-speed operation can be achieved.

FIG. 5 is a schematic configuration diagram of an example of an imaging device using the above line sensor or area sensor.

In the figure, an image sensor 301 corresponds to the line sensor shown in FIG. 3. Output signal Vout of ma' element 301
The signal processing circuit 302 performs processing such as gain adjustment, and outputs it as a video signal.

Further, each of the above pulses for driving the image sensor 301 is supplied by a driver 303, and the driver 303 operates under the control of a control unit 304. In addition, the control unit 30
4 is a signal processing circuit 302 based on the output of the image sensor 301.
At the same time, the exposure control means 305 is controlled to adjust the amount of light incident on the image sensor 301.

By using the imager child 301 according to the present invention.

It is possible to provide an imaging device that has high output and operates at high speed.

FIG. 6 is a schematic cross-sectional configuration diagram of a second embodiment of the present invention. However, the same parts as those in the first embodiment are given the same numbers and their explanations are omitted.

Darlington connected transistors A and B are the first
The structure is similar to that of the embodiment, but in this embodiment, transistors Q1 and Q2 are further provided as switching means for refreshing.

First, a p medium region 26 is formed at the end of the p base region 9 of transistor A, and a p medium region 27 is formed at a predetermined distance from the p''71 region 26.Similarly, in transistor B, The p base region 22, the p ten region 28 and the p
A medium region 29 is formed. The p medium regions 26 and 27 are used as source/drain regions,
The gate electrode 30 formed with the oxide film 12 in between and the electrode 31 connected to the P region 27 constitute a switching transistor Q1.

In addition, a gate electrode 32 is formed using the p+ regions 28 and 29 as source/drain regions, with the oxide film 12 sandwiched therebetween;
The electrode 33 connected to the p-type region 29 constitutes a switching transistor Q2.

By providing such transistors Q1 and Q2, both transistors can be rendered conductive by applying a constant voltage to the electrodes 31 and 33, respectively, and applying a negative voltage to the gate electrodes 30 and 32. Each base potential of transistors A and B can be set to a constant value.

Even if such transistors Ql and Q2 are provided, p
The ten regions 26 to 29 can be formed in the same process as the p ten region 23, and the gate electrodes 30, 32, etc. can also be formed by the capacitor electrode 1.
4, the wiring electrode 24, etc., in the same process, so the process does not become complicated.

FIG. 7(A) is a basic drive circuit diagram of the second embodiment, i
Figure 57 (B) is a timing chart for explaining the operation.

A photoelectric conversion cell S in FIG. 2A is an equivalent circuit of this example. Further, it is assumed that a constant voltage is applied to each of the electrodes 31 and 33.

In the same figure (A), a positive voltage control pulse Vr is applied to the capacitor electrode 17 of the photoelectric conversion cell S, and a transistor Qvc and a storage capacitor C are connected to the emitter electrode 19, respectively. Also, transistors Q1 and Q
Pulse φrh is applied to both gate electrodes 30 and 32 of No. 2 to control the 0N10FF operation.

In such a configuration, refresh, storage, and read operations can be performed by applying pulses at the timing shown in FIG. 4B.

First, the transistor Qvc is turned on by a pulse φvC, the emitter electrode 19 of the photoelectric conversion cell S is grounded, and the pulse φrh is applied to the electrode 30.32. Pulse φ
Due to rh, transistors Q1 and Q2 are turned on, and the potentials of p base regions 9 and 22 of transistors A and B are respectively set to constant values regardless of the level of the accumulated potential. Then transistors Q1 and Q2 are turned off.
In the F state, a refresh pulse φrc is applied to the capacitor electrode 17, and the above-mentioned refresh operation is performed.
In this way, since the refresh operation is performed after the base potential is set to a constant value, the base potential can be returned to the complete initial state in a short time, and faster operation is possible.

Subsequently, after an accumulation operation is performed, a read pulse φr is applied to perform a read operation, but these operations are similar to those in the first embodiment.

[Effects of the Invention] As explained above in detail, the photoelectric conversion device according to the present invention has a configuration in which transistor A and transistor B, which are photoelectric conversion sections, are connected in Darlington, so that the current amplification factor is extremely large. In addition to obtaining high output, it is possible to significantly improve the drive capability compared to conventional products.As a result, even if capacitive loads such as wiring capacitance increase due to high integration, it is possible to obtain output with good rise characteristics. This enables high-speed operation.

[Brief explanation of the drawing]

FIG. 1(A) is a schematic cross-sectional configuration diagram of the first embodiment of the photoelectric conversion device according to the present invention, FIG. 1(B) is an equivalent circuit diagram of one cell, and FIG. 2(A) is , Basic drive circuit diagram of this embodiment, 2nd
Figure (B) is a timing chart for explaining its operation, Figure 3 is a schematic circuit diagram of the line sensor using this embodiment, and Figure 4 is a timing chart for explaining the operation of the line sensor. Timing chart. FIG. 5 is a schematic configuration diagram of an example of an imaging device using the above-mentioned line sensor or area sensor. FIG. 6 is a schematic cross-sectional configuration diagram of a second embodiment of the present invention. FIG. 7(A) is a basic drive circuit diagram of the second embodiment, FIG. 7(8) is a timing chart for explaining its operation, and FIG. 8(A) is a conventional photoelectric conversion a schematic plan view of the device;
FIG. 8(B) is a sectional view taken along line AA' of one of the photoelectric conversion cells, and FIG. 8(C) is an equivalent circuit diagram thereof. FIG. 9(A) is an explanatory diagram of the driving m force of the conventional example, FIG.
B) is a voltage waveform diagram showing driving ability. l...n silicon substrate 4...n-epitaxial region 6--element isolation region 9-P base region 12 of Φφ transistor A...oxide film 14.1711...capacitor electrode 15...-transistor A n0 emitter region 19・Φ
・Emitter electrode 21...Reference collector electrode 22・Φ・P base region 25 of transistor B...N10 emitter region 30 of transistor B・Fist・Gate electrode 32 of transistor Q1...φ Gate electrode agent of transistor Q2 Patent Attorney Jo Taira Yamashita Figure 1 (A) I (B) Figure 2 (A) CC (B) Figure 5 Figure 8 (A) @ Figure 8 (B)

Claims (2)

[Claims] (1) First and second main electrode regions A of one conductivity type semiconductor
1 and A2, and a control electrode region A3 of a semiconductor of the opposite conductivity type, and a transistor A that stores carriers generated by photoexcitation in the control electrode region A3 by controlling the potential of the control electrode region A3, and a transistor A of one conductivity type. Transistor B consisting of third and fourth main electrode regions B1 and B2 of semiconductor and a control electrode region B3 of opposite conductivity type semiconductor
and connecting the main electrode area B2 to the main electrode area A2,
A photoelectric conversion device characterized in that a control electrode region B3 is connected to a main electrode region A1. (2) The photoelectric conversion device according to claim 1, further comprising a switch means for setting at least one of the control electrode regions A3 and B3 to either a constant potential or a floating state.