JPS584460B2 - handmade takiokusouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device having a MOS structure.

Conventional semiconductor random access memory (RAM) is
Generally, 6 transistors, 4 transistors, or 8 transistors are used per cell, and because the number of transistors per cell is large, a large area is required and it is difficult to increase the degree of integration.

Recently, 1-transistor, 1-cell type semiconductor RAM
has also been proposed, but this involves creating a region for storing charge on the substrate surface near the source region of the MOS transistor, which requires extra area outside the transistor region, so it cannot be expected to achieve a sufficient increase in integration density. Moreover, the signal pulse arrangement during operation becomes complicated and the noise margin is low.

This invention was made in view of the above points, and allows random access with a one-transistor, one-cell system.
The present invention provides a semiconductor memory device that can achieve a sufficient degree of integration.

The semiconductor memory device according to the present invention basically has a MOS transistor structure, and a conductive charge trapping region is provided in the substrate directly under the channel region between the source region and the drain region, and the charge in the trapping region is The present invention is characterized in that the conductivity of the channel region is changed by controlling the amount, and different states of the conductivity correspond to information "1" and "0".

Embodiments of the invention will be described below with reference to the drawings.

FIG. 1 is a structural diagram of the memory transistor.

This is an example of an n-channel case, in which a P-type silicon substrate 1 is used, an n+ source region 2 and a drain region 3 are provided at positions separated from each other within the substrate 1, and the substrate 1 is formed so as to straddle these regions. In the structure in which a gate electrode 5 is disposed on the surface via a gate insulating film 4 such as an oxide film, an n+ layer 6 is provided in the substrate 1 between the source region 2 and the drain region 3 and directly under the channel region.

The n+ layer 6 is a region that traps charges, and the conductivity of the channel region is controlled by the amount of captured charges.

Operations such as writing and reading information in this memory transistor are as follows.

Assuming that the amount of charge in the n+ layer 6 is now in an equilibrium state, the drain current ID of this memory transistor - the gate voltage ■
In the G characteristic, for example, as shown by the solid line in FIG. 2, the gate threshold voltage is ■to.

That is, it is turned on when VG>Vto, and turned off when ■G<to.

This state corresponds to, for example, binary information "0".

Considering a state in which the number of electrons, which are the majority carriers, in the n+ layer 6 is smaller than in the equilibrium state, this n+ layer 6 has equivalently captured positive charges, that is, holes, and therefore, the apparent This is equivalent to applying an upper back gate bias (substrate bias), and the gate threshold voltage becomes Vt (<Vto) as shown by the broken line in FIG.

This state corresponds to information "1". A specific numerical example will be given.

For example, phosphorus ions are accelerated at 300 kev and implanted into the channel region of the silicon substrate 1 at a dose of 1015 cm-2 to form the n+ layer 6.

At this time, the distribution of phosphorus within the substrate has a peak at 0.38 μm from the surface, and the effective depth of the channel is 0.28 μm.

The P-type impurity concentration in this channel region is set to 7×1016 cm.
-3, the threshold voltage is approximately 0.5■.

When positive charges are accumulated in this n+ layer 6, the channel region becomes depleted, and the threshold voltage drops by about 0.5V.

To write information "1", a predetermined positive voltage is applied to the gate G to form a channel, and at the same time, predetermined positive voltages are also applied to the source S and drain D, and the source region 2 and n+ This is done by passing a displacement current through the layers 6 or between the drain region 3 and the n+ layer 6 to accumulate positive charges in the n+ layer 6.

For example, this write operation between the drain region 3 and the n+ layer 6 will be explained in detail.

When a positive voltage is applied to the drain region 3 and the potential difference between the drain region 3 and the N+ layer 6 becomes VB, the drain region 3
The width d of the depletion layer extending from the N+ layer 6 to the N+ layer 6 side is given by:

Here, εS is the dielectric constant of silicon, NCH is the impurity concentration of the substrate, and q is the elementary charge of electrons.

Therefore, if the distance between the drain region 3 and the N+ layer 6 is less than or equal to d, punch-through occurs between the drain region 3 and the N+ layer 6 when a positive voltage as described above is applied between the drain region 3 and the substrate. occurs, and the n+ layer 6 is charged to a certain positive potential.

That is, positive charges are injected into the n+ layer 6.

Note that applying a positive voltage to the gate at the same time forms a channel and utilizes the spread of the depletion layer from the channel region to the n+ layer 6 side, compared to the case where no positive voltage is applied to the gate. This is to facilitate the occurrence of pan-through between the drain region 3 and the n+ layer 6, thereby enabling bit selection for writing, which will be described later.

This accumulated positive charge will eventually disappear due to the reverse diffusion current flowing through the Pn junction between the n+ layer 6 and the substrate 1, but this state of positive charge accumulation will be maintained for about several seconds.

Information reading is performed by selecting the gate voltage VG to be an intermediate value VR between ■to and ■t1, and determining conduction or non-conduction between the source and drain.

That is, assuming VG=■R, if the source and drain are conductive, the value is "1", and if the source and drain are non-conductive, the value is "0".

Note that the gate voltage VG=VR for reading must be selected to a value such that the channel formed between the source and drain is not electrically connected to the n+ layer 6.

To erase information "1", apply a sufficiently larger positive voltage to the gate G than in the case of writing to form an inversion layer, and then
This is done by bringing the barrier between the layer 6 and the inversion layer into a sufficiently small state, that is, making it virtually conductive, and by grounding the source S and drain D to return the amount of charge in the n+ layer 6 to an equilibrium state. .

FIG. 3 shows a 2×2 bit memory array using the above-mentioned memory transistors.

M11, Ml2, M21, M22 arranged in matrix
are memory transistors, whose gates are commonly connected to bit lines B1 and B2 for each row, and whose drains are commonly connected to word lines W1 and W2 for each column.

Further, the sources of each column are commonly connected to terminals S1 and S2 via MOS switching transistors Q1 and Q2.

FIG. 4 shows the relationship of applied pulses when writing, reading, etc. are performed by selecting the memory transistor M11.

First, write information “1” to transistor M11? teeth,
For example, 10V is applied as a sufficiently large positive write voltage VW to the bit line B1, and at the same time, a positive voltage is applied to the gate terminal (R/E) 1 of the switching transistor Q1 to turn it on, and a positive voltage is applied to the word line W1. (2) Apply a positive voltage VS (VS<VD) to the terminal S1.

As a result, n directly below the channel region of transistor M1
Positive charges are accumulated in the + layer, the gate threshold voltage moves in the direction of decreasing, and "1" is stored.

At this time, the gate of the transistor M21, that is, the bit line B
2 is grounded, punch-through does not occur between the drain region and the n+ layer with only the positive voltage VD of the word line W1, and therefore no writing is performed.

By grounding the word line W2 and the terminal S2 of the transistors M11 and M22, writing is not performed.

In this way, bit selective writing is performed.

Next, for reading from the transistor M11, a terminal (R/E
)1 to turn on transistor Q1,
At the same time, the gate threshold voltage ■t in the “0” state is applied to the bit line B1.
An intermediate value ■R between the gate threshold voltage Vt1 in the 0 and "1" states is applied, and a positive voltage is applied to the word line W1.

As a result, the conduction level of the transistor M11 becomes "1",
If it is non-conducting, it will be "0".

Next, to erase the information of the transistor MH, the terminal (
Apply a positive voltage to R/E) 1, turn on the transistor Q1, and apply a sufficiently large positive erase voltage VE of, for example, 20 V to the bit line B1 to transfer the positive charge stored in the n+ layer from the channel region to the source region. , discharge through the drain region.

That is,.

Electrons, which are majority carriers, flow into the + layer, returning to a thermal equilibrium state, and the information becomes "0".

As described above, according to the present invention, a RAM memory array having one memory transistor and one cell can be constructed.

Moreover, since the area of the memory transistor is the same as that of a normal MOS transistor, high integration is possible.

In the embodiment, an n+ layer was provided directly under the channel region as a charge trapping region of the memory transistor, but instead of the n+ layer, conductivity was provided at a position corresponding to the n+ layer by means such as ion implantation. A layer having an electron trapping level may also be provided.

To give a specific example, oxygen at 1014 to 1016 cm-2
When ions are implanted into a Si substrate at a moderate dose and heat treated, a layer in which minute SiO2 grains are dispersed is obtained within the substrate.

This layer has an electron capture level in the SiO2 grains, but the electron capture state is not stable as is known for example in non-volatile memory, and electrons can easily move due to tunneling, so it should not be left alone. The captured electrons disappear naturally.

That is, like the n+ layer in the previous embodiment, it functions as a region for temporarily accumulating charges.

In this case, the gate threshold voltage is higher in the state where electrons are captured than in the state where no electrons are captured, and therefore the principle of writing and erasing is different from the above embodiment in which positive charges are equivalently accumulated by extracting electrons. It will be the opposite.

1. Brief Description of the Drawings FIG. 1 is a diagram showing the structure of a memory transistor according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating its memory operation.
FIG. 3 is a diagram showing the configuration of a RAM memory array using four memory transistors shown in FIG. 1, and FIG. 4 is a diagram showing an applied pulse train to explain its operation. be.

1...P-type silicon substrate, 2...n+
Source region, 3...n+ drain region, 4...
...Insulating film, 5...Gate electrode, 6...
...n+ layer (charge trapping region).

Claims (1)

[Claims] 1. A semiconductor substrate is provided with source and drain regions, a gate electrode is provided on the surface of the substrate via an insulating film so as to span these source and drain regions, and the inside of the substrate is directly below the channel region between the source and drain regions. 1. A semiconductor memory device characterized in that a conductive charge trapping region is provided in the channel region, and the conductivity of the channel region is changed by controlling the amount of charge in the trapping region.