JPH07106553A - Solid state image pickup element - Google Patents

Abstract

PURPOSE:To provide a high speed and high sensitive charge detecting device to realize high density of a solid state image pickup element by improving sensitivity through small capacitance of a floating diffusion layer. CONSTITUTION:A P type semiconductor region 14A in the width of 1 to 2mum is provided between a floating diffusion layer 10A and a reset drain region 13A. A reset operation of signal charges of the floating diffusion layer 10A discharges the charges by giving directly a pulse voltage to the reset drain region 13A to generate punch-through on the P type semiconductor region 14A. Therefore, the reset gate electrode can be ruled out, the floating diffusion capacity can be reduced because parasitic capacitance against the floating diffusion layer can be eliminated and thereby sensitivity can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a charge transfer type solid-state image pickup device (hereinafter referred to as CCD).

[0002]

2. Description of the Related Art The structure of a conventional CCD from the final stage of a charge transfer register to a charge detecting portion will be described with reference to FIGS. 3 is a plan view and FIG. 4 is a sectional view taken along line XX of FIG. P well 2 is formed on the surface of N type silicon substrate 1.
(P-type region) is provided, and an embedded CCD is provided in this P-well 2.
Forming an N well 3 to be a transfer channel of the transfer electrode (barrier gate electrode 6b) through the insulating film (gate oxide film 5).
And a set of storage gate electrodes 6s), an output gate electrode 8,
9 and the reset gate electrode 12 are formed. The signal charges transferred by applying transfer pulses φ1 and φ2 to the transfer electrodes in the N well 3 pass under the output gate electrodes 8 and 9 and are converted into a voltage in the floating diffusion layer 10,
When a high level pulse is applied to the reset gate electrode 12 (Vrg becomes a high level), it is discharged to the reset drain region 13. In addition, the floating diffusion layer 10
Potential change V is V = Q / C _FJ (Q: signal charge, C _FJ :
Floating diffusion capacitance), and MOS transistors M1, M
It is output as the output voltage Vout of the CCD through a two-stage source follower amplifier circuit AMP composed of 2, M3 and M4. Therefore, the smaller this C _FJ , the better the conversion efficiency from charge to voltage, which is desirable. C _FJ is a parasitic capacitance C between the floating diffusion layer 10 and the reset gate electrode 12.
a, parasitic capacitance Cb between floating diffusion layer 10 and output gate electrode 9, junction capacitance C between floating diffusion layer 10 and P well 2
c, the wiring capacitance Cd that the wiring 11 connecting the floating diffusion layer 10 and the MOS transistor M1 for the first stage drive has with the silicon substrate, and the parasitic between the gate electrode and the drain region and the source region of the MOS transistor M1 for the first stage drive It is represented by the sum of the capacitances Ce and Cf. Conventionally, in order to make this C _FJ as small as possible, the area of the floating diffusion layer is reduced and the concentration thereof is reduced for Cc, the length of the wiring 11 is shortened for Cd, and the drive MOS for Ce and Cf. Measures such as reducing the size of the gate electrode of the transistor have been taken.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Higher sensitivity by reducing the floating diffusion capacitance in the CD has reached its limit, and there is a problem that it is becoming difficult to further improve the sensitivity. In addition, when the high-level pulse is applied to the reset gate electrode and the signal charge is discharged to the reset drain by decreasing the concentration of the floating diffusion layer to improve the sensitivity, the resistance of this part becomes high, and the charge is discharged. Problems such as time consuming and inability to cope with high speed are also derived.

[0004]

A solid-state imaging device according to the present invention fills a second conductivity type region provided on a surface portion of the first conductivity type region of a semiconductor substrate having a first conductivity type region on the surface portion. A charge transfer register having an embedded transfer channel,
A second conductive type floating diffusion layer provided adjacent to the charge transfer register and connected to the second conductive type region to receive a signal charge from the charge transfer register; and the first diffusion layer separated from the floating diffusion layer by a predetermined dimension. A reset drain region of the second conductivity type formed in the conductivity type region, and a pulse voltage is applied to the reset drain region to establish a pulse-through state between the reset drain region and the signal charge of the floating diffusion layer. I tried to sweep out.

[0005]

The present invention will be described below with reference to the drawings. FIG. 1A is a plan view showing a signal output portion of an embodiment of the present invention, and FIG. 1B is a sectional view taken along line XX of FIG.

In this embodiment, the P well 2 of the N type silicon substrate 1 having a P type region (P well 2) on the surface is used.
N-type region (depth 2 to 4 μm, concentration 1 × 10 ¹⁵ to 1) provided on the surface of (concentration 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻³ ).
A charge transfer register having a × 10 ¹⁶ cm ⁻³ N well 3) as an embedded transfer channel, and a signal charge from the above charge transfer register provided in proximity to the charge transfer register and connected to the N well 2. N-type floating diffusion layer 1 to receive
0A, and the floating diffusion layer 10A is separated from the floating diffusion layer 10A by a predetermined dimension (2 μm) to form an N-type reset drain region 13 in the P well.
A (having an N ⁺ type diffusion layer 13Aa on the surface portion) and applying a pulse voltage to the reset drain region 13A to make a punch-through state with the floating diffusion layer 10A. It is said that the signal charge of was swept out.

Reference numeral 4 denotes an N ⁻ formed on the surface of the N well 3.
Type barrier layer, 5 is a gate oxide film provided on the surface of the silicon substrate, 6s is a storage gate electrode, 6b is a barrier gate electrode,
Reference numerals 8 and 9 are output gate electrodes. The wiring 11 connected to the floating diffusion layer 10A through the contact hole C is connected to the same one as the source follower amplifier circuit AMP shown in FIG.

Next, the operation of this embodiment will be described with reference to FIG.

At time t0, it is assumed that the signal charge Q is transferred below the storage electrode 6s at the final stage of the transfer register. That is, the transfer pulse φ1 is set to the “H” level and φ2 is set to the “L” level. Next, when φ1 becomes “L” level and φ2 becomes “H” level at the time t1, the signal charge Q is injected into the floating diffusion layer 10A through below the output gate electrodes 8 and 9. Next, at time t2, the voltage Vrda applied to the reset drain region 13A is at a low level (for example, 0 V).
From the high level (for example, 15 V), the space between the floating diffusion layer 10A and the reset drain region becomes a punch-through state, the potential barrier of the P-type semiconductor region 14A disappears, and the signal charge Q is transferred to the reset drain region 13A.
Swept to. It is assumed that the N-type silicon substrate is biased at Vs (for example, 5 V) and the input end of the transfer channel is biased at, for example, 15 V.

In the conventional example, the parasitic capacitance Ca (2 to 3 fF between the reset gate electrode and the floating diffusion layer, which is about 2 of C _FJ ).
To win) is gone. A junction capacitance (about 0.8 fF) between the floating diffusion layer 10A and the P-type semiconductor region 14A is newly added, which is about 1/3 of Ca. Therefore, the sensitivity can be improved.

If the concentration of the P-type semiconductor region 14A is made thinner than that of the portion where the N well 3 is present by utilizing the ion implantation of arsenic or boron, the sensitivity can be further improved, but the charge is not swept out. Since it depends on the punch-through current, it can be carried out promptly without adverse effects.

[0012]

As described above, according to the present invention, a reset drain region is provided with a predetermined distance from the floating diffusion layer, and a pulse voltage is directly applied to the reset drain region to bring the floating diffusion layer into a punch-through state. As a result, the signal charges are discharged, so that it is not necessary to provide a reset gate electrode, and the floating diffusion capacitance can be reduced and the sensitivity can be increased.

[Brief description of drawings]

FIG. 1 is a plan view (FIG. 1A) and a sectional view (FIG. 1B) of a semiconductor chip showing an embodiment of the present invention.

FIG. 2 is a potential diagram for explaining the sweeping out of signal charges in an example.

FIG. 3 is a plan view of a semiconductor chip showing a conventional example.

4 is a sectional view taken along line XX of FIG.

[Explanation of symbols]

1 N-type silicon substrate 2 P-well 3 N-well 4 N ^- type barrier layer 5 Gate oxide film 6b Barrier gate electrode 6s Storage gate electrode 7 Insulating film 8,9 Output gate electrode 10, 10A Floating diffusion layer 11 Wiring 12 Reset gate electrode 13, 13A Reset drain region 13Aa N ⁺ type diffusion layer 14A P type semiconductor region

Claims (2)

[Claims] 1. A charge transfer register having, as a buried transfer channel, a second conductivity type region provided on the surface of the first conductivity type region of a semiconductor substrate having a first conductivity type region on the surface thereof, and A second conductivity type floating diffusion layer provided adjacent to the charge transfer register and connected to the second conductivity type region and receiving signal charges from the charge transfer register; and the first conductivity type separated from the floating diffusion layer by a predetermined dimension. A reset drain region of the second conductivity type formed in the drain region, and a pulse voltage is applied to the reset drain region to establish a pulse-through state between the reset drain region and the reset diffusion region, and a signal charge of the floating diffusion layer is generated. A solid-state imaging device characterized by being swept out. 2. The solid-state image sensor according to claim 1, wherein the first conductivity type is P-type.