JPH04373136A - Charge coupled device - Google Patents

Abstract

PURPOSE:To reduce the parasitic capacitance of a floating diffusion layer for signal charge detection. CONSTITUTION:A (p) well 12 is formed on an n-type semiconductor substrate 11, an (n) well 15 is formed on the main surface of the (p) well 12, and a floating diffusion layer 13 for electric charge detection is formed in the (n) well 15. A reset drain 14 for electric charge absorption is formed in the (p) well 12 in the vicinity of the floating diffusion layer 13 for electric charge detection. In order to reset the electric potential of the floating diffusion layer 13, a high voltage pulse is applied to the reset drain 14 for electric charge absorption, and signal charge is discharged toward the reset drain 14.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention relates to a charge-coupled device.
In particular, the present invention relates to a charge-coupled device that uses a floating diffusion layer to detect transferred signal charges.

0002

2. Description of the Related Art FIG. 3A is a cross-sectional view of a charge detection section of a conventional charge-coupled device of the buried channel type.
FIG. 3(b) is a diagram showing the potential of each part. Figure 3
As shown in (a), p is formed on the n-type semiconductor substrate 31.
A well 32 is provided in the surface area of the p-well 32, an n-well 35 serving as a charge transfer region of a charge-coupled device, an n+ type floating diffusion layer 33 for detecting charges, and a reference potential applied to the floating diffusion layer 33. is applied to n+
A type reset drain 34 is provided.

A charge transfer clock φ1 is provided on the n-well.
is applied to the final transfer electrode 37, the output gate 38, and the reset gate 36 to which the reset pulse φR is applied.
Further, the floating diffusion layer 33 is connected to the input gate of the preamplifier 39.

This charge-coupled device applies charge transfer clocks φ1, . . . shown in FIG. 4 to the transfer electrodes, and a reset pulse φR synchronized with the clock φ1 to the reset gate 36.
The preamplifier 39 is driven by applying constant output gate voltage VOG and reset drain voltage VRD to the output gate 38 and reset drain 34, respectively, and from the output terminal of the preamplifier 39, as shown in FIG.
The signal output VOUT is output at the same period as the reset pulse.

By applying charge transfer clocks φ1, . . . to the transfer electrodes, signal charges are transferred within the n-well 35 and sent directly below the final transfer electrode 37 at the same cycle as the charge transfer clock φ1. This final transfer electrode 37
When the charge transfer clock φ1 applied to is at high level, the signal charge is held directly below the final transfer electrode 37 (the potential at this time is indicated by φ1 = “H” in FIG. 3(b)).
. At this time, the reset pulse φR becomes high level, and the potential of the floating diffusion layer 33 changes to the reset drain potential (V
RD), and then a reset pulse φR
becomes low level.

Next, when the charge transfer clock φ1 becomes low level (at this time, the potential directly below the electrode 37 is shown in FIG. 3).
b), the signal charge is transferred to the floating diffusion layer 33 through the bottom of the output gate 38 (indicated by φ1 = “L”). The potential change ΔV of the floating diffusion layer 33 at this time is determined by assuming that the transfer signal charge is Q and the total capacitance of the floating diffusion layer is CFJ.
ΔV=Q/CFJ

...It is given by ■. This potential change ΔV is amplified by a preamplifier 39 and taken out as a signal output VOUT.

Thereafter, the charge transfer pulse φ1 applied to the final transfer electrode 37 becomes high level, and at the same time, the reset pulse φR applied to the gate electrode 36 of the reset transistor becomes high level, and the signal charge is transferred to the floating diffusion layer 3.
3 to the reset drain 34.

Here, CFJ is the sum of the junction capacitance of the floating diffusion layer 33, the reset gate 36, the capacitance between the final electrode 37 and the floating diffusion layer 33, the input gate capacitance of the preamplifier 39, etc. As can be seen from equation (2), the smaller the total capacitance CFJ of the floating diffusion layer 33, the greater the signal charge voltage conversion efficiency, and the higher the sensitivity of the element. Conventionally, in order to reduce this total capacitance CFJ, measures such as reducing the area of the floating diffusion layer 33 and reducing the wiring length have been taken.

[0009]

[Problems to be Solved by the Invention] In the conventional charge-coupled device described above, the area and wiring length have been reduced in order to reduce the parasitic capacitance of the floating diffusion layer that detects charges, but this measure has already reached its limit. It has reached that point. Since the floating diffusion layer always has a certain capacitance between each electrode, it is difficult to further reduce the total capacitance CFJ, and therefore it has been impossible to sufficiently increase the voltage conversion efficiency of signal charges.

0010

[Means for Solving the Problems] The charge-coupled device of the present invention is characterized in that it does not use a reset gate, and includes a charge transfer region provided in a surface region of a semiconductor substrate and an insulating region on the charge transfer region. a charge transfer electrode provided through a film; a floating diffusion layer provided downstream of the charge transfer region and adjacent to the region and receiving signal charges transferred within the region; A reset drain diffusion provided near the diffusion layer and capable of drawing out signal charges accumulated in the floating diffusion layer by setting the region between the floating diffusion layer and the floating diffusion layer into a punch-through state by applying a voltage. A layer.

[0011]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1(a) is a cross-sectional view of a charge detection section according to a first embodiment of the present invention, and FIG. 1(b) is a potential diagram in the cross-section.

As shown in FIG. 1A, a p-well 12 is provided on an n-type semiconductor substrate 11, and the surface area of the p-well 12 serves as a charge transfer region of a charge-coupled device. An n-well 15 is provided. Although a large number of transfer electrodes are actually provided on the n-well 15, the final transfer electrode 1 to which the charge transfer clock φ1 is applied is shown in the figure.
Only 7 are shown.

An output gate 18 to which a constant output gate voltage VOG is applied is provided adjacent to the final transfer electrode, and in the surface region of the n-well 15 after the output gate 18,
A floating diffusion layer 13 is provided to receive signal charges transferred within the charge transfer region. Also, n well 1
5, another n-well 16 is provided at a slight interval, and inside this n-well 16 is an n+ well for charge absorption.
A mold reset drain 14 is provided. A reset drain pulse φRD synchronized with the charge transfer clock φ1 is applied to this reset drain. The input gate of a preamplifier 19 is connected to the floating diffusion layer 13 as in the conventional example.

Next, the operation of this embodiment will be explained. First, before the signal charge is transferred to the floating diffusion layer, the reset drain pulse φRD applied to the reset drain 14 is set to a high level to create a punch-through state between the floating diffusion layer 13 and the reset drain 14. The charges accumulated in the reset drain 14 are drawn out to the reset drain 14. At that time, the potential of the floating diffusion layer 13 is (
As shown in b), the potential is reset to the punch-through potential.

Here, when the charge transfer clock φ1 applied to the final transfer electrode 17 changes from high level to low level, the signal charge accumulated under this electrode passes under the output gate 18 and flows into the floating diffusion layer. Transferred to 13. The potential change ΔV of the floating diffusion layer 13 at this time is given by the above equation (2).

Here, since the conventional reset gate is removed, the parasitic capacitance of the total capacitance CFJ associated with the floating diffusion layer 13 is reduced accordingly. Therefore, the voltage conversion efficiency of signal charges is increased, and the sensitivity of the element is improved.

Furthermore, since there is no gate electrode, there is no feed-through noise in the signal output.
S/N improves. Furthermore, the circuit scale is reduced by the amount of the reset transistor, and the degree of integration within the wafer can be increased.

FIG. 2 is a sectional view showing a second embodiment of the invention. In this figure, parts that are common to those in FIG. 1 are given reference numbers with the same last digit, and therefore redundant explanation will be omitted. In this embodiment, the floating diffusion layer 2
3 uses a part of the n-well 25 as it is, and the reset drain 24 is provided in the p-well 22 directly under the floating diffusion layer 23.

Next, the operation of the charge detection section in this embodiment will be explained. By setting the reset drain pulse φRD applied to the reset drain 24 directly under the floating diffusion layer 23 to a high level, a punch-through state is created between the floating diffusion layer 23 and the reset drain 24, and the signal charge in the floating diffusion layer is transferred to the reset drain 24. release to.

Next, as the charge transfer clock φ1 applied to the final transfer electrode 27 changes from high level to low level, the signal charges are transferred to the floating diffusion layer 23, changing the potential of this diffusion layer. Also in this embodiment, since the reset gate is eliminated, the total capacitance CF of the floating diffusion layer
J is reduced, so that the potential change ΔV can be increased.

Furthermore, in this embodiment, the reset drain 2
4 is formed directly under the floating diffusion layer 23, the area used on the wafer can be further reduced and the degree of integration can be increased.

Although the preferred embodiments have been described above, the present invention is not limited thereto, and various modifications are possible. For example, the conductivity type of the semiconductor layer can be reversed so that the signal charge is a hole, and the charge coupled device can also be a surface channel type.

[0023]

[Effects of the Invention] As explained above, the present invention extracts accumulated charges in the floating diffusion layer by causing punch-through between the floating diffusion layer and the reset drain, thereby resetting the potential of this region. , the following effects can be achieved. (2) By removing the reset gate, the capacitance of the floating diffusion layer can be reduced and charge detection sensitivity can be improved.

(2) Since the reset gate is eliminated and the wiring for it is no longer necessary, the area used by the charge detection section can be reduced, and the degree of integration can be improved.

(2) Since the reset pulse feed-through noise generated due to the capacitance between the reset drain and the floating diffusion layer is eliminated, the S/N ratio is improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a first embodiment of the present invention and its potential diagram.

FIG. 2 is a sectional view of a second embodiment of the invention.

FIG. 3 is a cross-sectional view of a conventional example and its potential diagram.

FIG. 4 is an explanatory diagram of the operation of the conventional example.

[Explanation of symbols]

11, 21, 31...n-type semiconductor substrate, 12
, 22, 32...p well, 13, 23, 33... floating diffusion layer, 14, 24, 34... reset drain, 15, 16, 25, 35... n well, 3
6... Reset gate, 17, 27, 37... Final transfer electrode, 18, 28, 38... Output gate, 19, 29, 39... Preamplifier,
φ1...charge transfer clock, φR...reset pulse, φRD...reset drain pulse, VOG...output gate voltage, VRD...reset drain voltage, VOUT...signal output.

Claims (1)

[Claims] 1. A charge transfer region provided in a surface region of a semiconductor substrate, a charge transfer electrode provided on the charge transfer region with an insulating film interposed therebetween, and a charge transfer electrode provided downstream of the charge transfer region adjacent to the region. A floating diffusion layer provided in the vicinity of the floating diffusion layer receives the transfer of signal charges transferred through the region, and a voltage is applied to the floating diffusion layer provided near the floating diffusion layer. a reset drain diffusion layer capable of pulling out signal charges accumulated in the floating diffusion layer by punching a region into a punch-through state.