JP3173806B2 - Driving method of charge detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a charge detecting circuit used as an output circuit of a semiconductor integrated circuit, particularly a charge coupled device (CCD).

[0002]

2. Description of the Related Art Conventionally, a charge detection circuit called a floating diffusion amplifier as shown in FIG. 3 has been used as an output circuit of a CCD. In FIG. 1A, reference numeral 1 denotes a semiconductor substrate of the first conductivity type. 2 is CC
The last gate electrode 3 of D is a gate electrode for forming a potential barrier. The gate electrode 2 is applied with one of the drive clocks φH for charge transfer, and the gate electrode 3 is applied with the DC voltage VG ₀ . In a region adjacent to the gate electrode 3, a MOS transistor including a gate electrode 4 and high-concentration impurity regions 5 and 6 of the second conductivity type is formed. It is insulated from the electrode by an insulating film). Reset power supply voltage VR is applied to impurity region 6.

The impurity region 5 is called a floating diffusion and is connected to the gate of an output source follower transistor 7 formed on the same semiconductor substrate 1. A source follower power supply V ₀ is applied to the drain of the transistor 7. The source is grounded via the load resistor 8, and an output D ₀ is derived from a connection point between the source and the resistor 8.

Next, the operation will be described. FIG.
(D) respectively show t ₁ to t _{3 in} the timing chart of FIG.
FIG. 3A shows the potential of each part at the time. First, the driving clock φH is at t ₁ is at a high level (H), the signal charge Q potential well is formed to under the gate electrode 2 shown in FIG. 3 (b) is accumulated. At the same time, the reset clock φR applied to the gate electrode 4 is at a high level, and the MOS transistor composed of the gate electrode and the impurity regions 5 and 6 is turned on to turn on each of the impurity region 5 and the gate of the transistor 7 connected thereto. The voltage has been reset to the level of the reset power supply voltage VR.

At t ₂ , the reset clock φR becomes low level (L), and the gate electrode and the impurity region 5
The MOS transistor 6 is turned off. When the reset clock φR changes from high to low level,
The potential of the impurity region 5 decreases due to the capacitive coupling between the gate electrode 4 and the impurity region 5. While the reset clock φR is at the low level, the node connected to the impurity region 5 is floating.

When drive clock φH attains a low level at t ₃ , signal charge Q stored in a potential well below gate electrode 2 is read out to impurity region 5, and a change in this potential is output through a source follower circuit. Is done. When the capacitance of the floating diffusion node is C _FD and the gain of the source follower circuit is G, the magnitude ΔV is ΔV = (G · Q) / (C _FD ). Since the gain G is usually about 0.7 to 0.9 and hardly changes, it is necessary to reduce C _FD in order to increase ΔV for the same signal charge. The larger the ΔV with respect to the same Q, the larger the charge-to-voltage conversion gain, which is advantageous from the viewpoint of S / N.

On the other hand, the maximum amount of charge that can be detected by the charge detection circuit is the maximum when the charge is accumulated in the impurity region 5 and the potential of the region 5 does not exceed the channel potential below the gate electrode 3. The amount of charge. The value increases as the capacitance _CFD increases.

[0008]

As described above, in the conventional charge detection circuit, the dynamic range is determined by the difference between the reset voltage of the floating diffusion portion and the channel potential under the gate electrode 3, and the maximum charge that can be detected. the amount decreases the detection sensitivity by increasing C _FD to a large, there is a problem that the dynamic range is narrowed by the maximum charge amount is decreased to be detected and to reduce the C _FD to detect minute charge reversed Was. SUMMARY OF THE INVENTION It is an object of the present invention to provide a floating diffusion charge detection circuit capable of obtaining high detection sensitivity at the time of a small signal and realizing a wide dynamic range.

[0009]

The present invention drives a floating diffusion charge detection circuit used in an output circuit of a CCD.
The potential under the final storage gate of D is the final storage gate.
Deeper than and adjacent to the potential below the gate immediately before
Deeper than the potential under the adjacent potential barrier forming gate
Gate to be applied to the final storage gate
When the signal charge amount is equal to or less than a predetermined amount, signal detection is performed using only the capacitance of the charge detection capacitance portion. When the signal charge amount is equal to or more than the predetermined amount, the charge detection capacitance portion and the potential barrier are formed. in the gate portion and the final accumulation gate portion is obtained to perform the signal detection.

[0010]

When the signal charge is small, the detection is performed only by the capacitance of the floating diffusion portion. However, when the signal charge amount exceeds a certain value and becomes large, a part of the CCD channel adjacent to the capacitance, that is, the final accumulation. Detection is performed at the gate portion. As a result, the charge detection circuit has a knee (kn
ee) Characteristics can be provided, and a wide dynamic range can be obtained with high sensitivity at the time of a small signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1A is a cross-sectional view showing a configuration of a floating diffusion charge detection circuit used in an output circuit of a CCD, and the configuration itself is exactly the same as that of a conventional one.

FIGS. 1B and 1C show signal charges Q, respectively.
FIG. 6 shows potential states at the time of signal readout when the number is small and when the number is large. In this case, the level of the clock applied to the gate electrode is adjusted so that the potential under the final gate electrode 2 of the CCD at the time of signal reading is the same as the potential under the potential barrier forming gate electrode 3. At this time, the potential under the gate electrodes 2 and 3 is set deeper than the potential under the gate electrode 11 immediately before the gate electrode 2.

[0013] When the signal charge Q is small, the detection of the signal electric load as shown in FIG. 1 (b) is carried out in the node impurity region 5 called floating diffusion.
Therefore, if the capacitance _CFD is reduced, the circuit operates as a highly sensitive charge detection circuit. When the signal charge increases and the potential of the floating diffusion node becomes shallower than the potential under the gate electrodes 2 and 3, the signal charge also spreads under the gate electrodes 2 and 3 and the capacitance C _FD
And the detection sensitivity decreases. As a result, the circuit has a knee characteristic as shown in FIG. 2, and a wide dynamic range can be obtained. The point at which the characteristics change can be adjusted by changing the voltage applied to the gate electrodes 2 and 3. The sensitivity on the high output side can be adjusted by the size of the gate electrodes 2 and 3.

In this embodiment, the driving is performed so that the potentials under the gate electrodes 2 and 3 are the same. However, this is not always necessary, and the potential under the gate electrode 2 is changed to the potential of the immediately preceding portion. It just needs to be deeper. In addition, although the gate electrode 3 is provided separately from the gate electrode 2, they may be shared by the same gate electrode, and the effectiveness of the present invention does not change in such a case.

[0015]

As described above, according to the present invention, at the time of signal charge detection, the potential under the final storage gate of the CCD is deeper than the potential under the immediately preceding gate , and
Deeper than the potential below the adjacent potential barrier forming gate
The gate applied to the final storage gate should be
When the signal charge amount is equal to or less than a predetermined amount, signal detection is performed only with the capacitance of the charge detection capacitance portion, and when the signal charge amount is equal to or more than the predetermined amount, the charge detection capacitance portion and the potential barrier are set. by to perform signal detection in the form gate portion and the final accumulation gate portion, the floating diffusion charge detection circuit of the conventional and the same configuration, while obtaining a high charge detection sensitivity at the time of a small signal, charge detection at the time of high signal There is an effect that a wide dynamic range can be realized by suppressing the sensitivity. Further, there is an effect that the signal charge amount for changing the sensitivity can be controlled.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a charge detection circuit and a potential diagram illustrating an operation thereof.

FIG. 2 is a characteristic diagram illustrating input / output characteristics of a charge detection circuit.

FIG. 3 is a sectional view showing a configuration of a conventional charge detection circuit not using the present invention, and a potential diagram showing its operation.

FIG. 4 is a clock timing diagram corresponding to the potential diagram of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 CCD last gate electrode 3 Potential barrier forming gate electrode 4 Reset gate electrode 5, 6 Impurity region 11 CCD gate electrode

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-53-33588 (JP, A) JP-A-59-217367 (JP, A) JP-A-61-201577 (JP, A) JP-A-61-201577 292363 (JP, A) JP-A-2-5475 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/335 H01L 29/76

Claims (1)

(57) [Claims] 1. A potential barrier in a final storage gate of a charge-coupled device.
In a driving method for driving a floating diffusion charge detection circuit including a charge detection capacitor provided adjacently via a wall forming gate and a reset circuit for resetting a charge of the capacitor portion , the signal charge detection means may detect The potential under the last storage gate of the charge-coupled device is deeper than the potential under the gate immediately before the last storage gate , and the potential under the potential barrier forming gate is higher.
Mark the final storage gate above so that it is not deeper than
The low level of the gate potential to be applied is set, and when the signal charge amount is equal to or less than a predetermined amount, signal detection is performed only with the capacitance of the charge detection capacitance portion. When the signal charge amount is equal to or more than the predetermined amount, the charge detection capacitance portion is set. And the potential barrier forming gate portion
And to perform the signal detection in the above final accumulation gate portion
A method for driving a charge detection circuit, comprising: